# HG changeset patch
# User Robert Mustacchi <rm@fingolfin.org>
# Date 1609896572 28800
# Node ID 65462c7d0b001b123ed33192ab54a4d352d32c5e
# Parent  e3fed54935246c4647cc78be2e8d69bf884f53d0
13440 ppin disablement path missing state transition
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

diff -r e3fed5493524 -r 65462c7d0b00 usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c
--- a/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c	Tue May 12 09:05:18 2020 +0300
+++ b/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c	Tue Jan 05 17:29:32 2021 -0800
@@ -150,7 +150,10 @@
 	 * failure of this part, as we will have gotten everything that we need.
 	 * It is possible that it locked open, for example.
 	 */
-	(void) cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_LOCKED);
+	if (cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_DISABLED) ==
+	    CMI_SUCCESS) {
+		(void) cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_LOCKED);
+	}
 
 	return (kmem_asprintf("iv0-%s-%x-%llx", vendor, cmi_hdl_chipsig(hdl),
 	    value));
diff -r e3fed5493524 -r 65462c7d0b00 usr/src/uts/intel/sys/x86_archext.h
--- a/usr/src/uts/intel/sys/x86_archext.h	Tue May 12 09:05:18 2020 +0300
+++ b/usr/src/uts/intel/sys/x86_archext.h	Tue Jan 05 17:29:32 2021 -0800
@@ -472,6 +472,7 @@
  * These values are currently the same between Intel and AMD.
  */
 #define	MSR_PPIN_CTL_MASK	0x03
+#define	MSR_PPIN_CTL_DISABLED	0x00
 #define	MSR_PPIN_CTL_LOCKED	0x01
 #define	MSR_PPIN_CTL_ENABLED	0x02