illumos/illumos-gate: usr/src/uts/common/io/ixgbe/ixgbe

comparison usr/src/uts/common/io/ixgbe/ixgbe_82599.c @ 13448:f03238cace0b

1390 ixgbe update from FreeBSD via Joyent Reviewed by: Richard Lowe <richlowe@richlowe.net> Reviewed by: Garrett D'Amore <garrett@nexenta.com> Reviewed by: Gordon Ross <gwr@nexenta.com> Approved by: Richard Lowe <richlowe@richlowe.net>

author	Jerry Jelinek <jerry.jelinek@joyent.com>
date	Fri, 09 Sep 2011 10:48:44 -0400
parents	22e6d3edaab5
children	7b5944437191

comparison

equal deleted inserted replaced

-:99622235dae0
+:f03238cace0b
-/*
+/******************************************************************************
-* CDDL HEADER START
-*
+Copyright (c) 2001-2010, Intel Corporation
-* The contents of this file are subject to the terms of the
+All rights reserved.
-* Common Development and Distribution License (the "License").
-* You may not use this file except in compliance with the License.
+Redistribution and use in source and binary forms, with or without
-*
+modification, are permitted provided that the following conditions are met:
-* You can obtain a copy of the license at:
-*      http://www.opensolaris.org/os/licensing.
+1. Redistributions of source code must retain the above copyright notice,
-* See the License for the specific language governing permissions
+this list of conditions and the following disclaimer.
-* and limitations under the License.
-*
+2. Redistributions in binary form must reproduce the above copyright
-* When using or redistributing this file, you may do so under the
+notice, this list of conditions and the following disclaimer in the
-* License only. No other modification of this header is permitted.
+documentation and/or other materials provided with the distribution.
-*
-* If applicable, add the following below this CDDL HEADER, with the
+3. Neither the name of the Intel Corporation nor the names of its
-* fields enclosed by brackets "[]" replaced with your own identifying
+contributors may be used to endorse or promote products derived from
-* information: Portions Copyright [yyyy] [name of copyright owner]
+this software without specific prior written permission.
-*
-* CDDL HEADER END
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-*/
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-/*
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-* Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-*/
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-/*
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-*/
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
-/* IntelVersion: 1.217 scm_061610_003709 */
+******************************************************************************/
+/*$FreeBSD$*/
 #include "ixgbe_type.h"
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
-ixgbe_link_speed *speed, bool *autoneg);
+ixgbe_link_speed *speed,
+bool *autoneg);
 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+ixgbe_link_speed speed, bool autoneg,
+bool autoneg_wait_to_complete);
 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+				     ixgbe_link_speed speed, bool autoneg,
+				     bool autoneg_wait_to_complete);
 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
-bool autoneg_wait_to_complete);
+				bool autoneg_wait_to_complete);
 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
-ixgbe_link_speed speed, bool autoneg,
+ixgbe_link_speed speed,
-bool autoneg_wait_to_complete);
+bool autoneg,
+bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
-ixgbe_link_speed speed, bool autoneg,
+ixgbe_link_speed speed,
-bool autoneg_wait_to_complete);
+bool autoneg,
+bool autoneg_wait_to_complete);
 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw);
-void ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw);
 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
-s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps);
 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
+bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
-void
-ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
+void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
-	if (hw->phy.multispeed_fiber) {
+	/* enable the laser control functions for SFP+ fiber */
-		/* Set up dual speed SFP+ support */
+	if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
-		mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
 		mac->ops.disable_tx_laser =
-		    &ixgbe_disable_tx_laser_multispeed_fiber;
+		                       &ixgbe_disable_tx_laser_multispeed_fiber;
 		mac->ops.enable_tx_laser =
-		    &ixgbe_enable_tx_laser_multispeed_fiber;
+		                        &ixgbe_enable_tx_laser_multispeed_fiber;
 		mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
 	} else {
 		mac->ops.disable_tx_laser = NULL;
 		mac->ops.enable_tx_laser = NULL;
 		mac->ops.flap_tx_laser = NULL;
+	}
+	if (hw->phy.multispeed_fiber) {
+		/* Set up dual speed SFP+ support */
+		mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
+	} else {
 		if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
-		    (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
+		     (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
-		    hw->phy.smart_speed == ixgbe_smart_speed_on))
+		      hw->phy.smart_speed == ixgbe_smart_speed_on) &&
+		      !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
-		else
+		} else {
 			mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
-	}
+		}
-}
+	}
+}
-/*
-* ixgbe_init_phy_ops_82599 - PHY/SFP specific init
+/**
-* @hw: pointer to hardware structure
+*  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
-*
+*  @hw: pointer to hardware structure
-* Initialize any function pointers that were not able to be
+*
-* set during init_shared_code because the PHY/SFP type was
+*  Initialize any function pointers that were not able to be
-* not known.  Perform the SFP init if necessary.
+*  set during init_shared_code because the PHY/SFP type was
-*
+*  not known.  Perform the SFP init if necessary.
-*/
+*
-s32
+**/
-ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
+s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
 	s32 ret_val = IXGBE_SUCCESS;
 	/* If copper media, overwrite with copper function pointers */
 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 		mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 		mac->ops.get_link_capabilities =
-		    &ixgbe_get_copper_link_capabilities_generic;
+		                  &ixgbe_get_copper_link_capabilities_generic;
 	}
 	/* Set necessary function pointers based on phy type */
 	switch (hw->phy.type) {
 	case ixgbe_phy_tn:
 		phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
 		phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_tnx;
+		             &ixgbe_get_phy_firmware_version_tnx;
 		break;
 	case ixgbe_phy_aq:
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_generic;
+		             &ixgbe_get_phy_firmware_version_generic;
 		break;
 	default:
 		break;
 	}
 init_phy_ops_out:
-	return (ret_val);
+	return ret_val;
 }
-s32
+s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
-ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
 {
 	s32 ret_val = IXGBE_SUCCESS;
+	u32 reg_anlp1 = 0;
+	u32 i = 0;
 	u16 list_offset, data_offset, data_value;
 	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
 	if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 		ixgbe_init_mac_link_ops_82599(hw);
 		hw->phy.ops.reset = NULL;
 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
-		    &data_offset);
+		                                              &data_offset);
 		if (ret_val != IXGBE_SUCCESS)
 			goto setup_sfp_out;
 		/* PHY config will finish before releasing the semaphore */
 		ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 		while (data_value != 0xffff) {
 			IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 			IXGBE_WRITE_FLUSH(hw);
 			hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		}
-		/* Now restart DSP by setting Restart_AN */
-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
-		    (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
 		/* Release the semaphore */
 		ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 		/* Delay obtaining semaphore again to allow FW access */
 		msec_delay(hw->eeprom.semaphore_delay);
+		/* Now restart DSP by setting Restart_AN and clearing LMS */
+		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
+		                IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
+		                IXGBE_AUTOC_AN_RESTART));
+		/* Wait for AN to leave state 0 */
+		for (i = 0; i < 10; i++) {
+			msec_delay(4);
+			reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
+			if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
+				break;
+		}
+		if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
+			DEBUGOUT("sfp module setup not complete\n");
+			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
+			goto setup_sfp_out;
+		}
+		/* Restart DSP by setting Restart_AN and return to SFI mode */
+		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
+		                IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
+		                IXGBE_AUTOC_AN_RESTART));
 	}
 setup_sfp_out:
-	return (ret_val);
+	return ret_val;
 }
-/*
+/**
-* ixgbe_init_ops_82599 - Inits func ptrs and MAC type
+*  ixgbe_init_ops_82599 - Inits func ptrs and MAC type
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* Initialize the function pointers and assign the MAC type for 82599.
+*  Initialize the function pointers and assign the MAC type for 82599.
-* Does not touch the hardware.
+*  Does not touch the hardware.
-*/
+**/
-s32
+s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
-ixgbe_init_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
 	s32 ret_val;
 	phy->ops.identify = &ixgbe_identify_phy_82599;
 	phy->ops.init = &ixgbe_init_phy_ops_82599;
 	/* MAC */
 	mac->ops.reset_hw = &ixgbe_reset_hw_82599;
-	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82599;
+	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
 	mac->ops.get_media_type = &ixgbe_get_media_type_82599;
 	mac->ops.get_supported_physical_layer =
-	    &ixgbe_get_supported_physical_layer_82599;
+	                            &ixgbe_get_supported_physical_layer_82599;
 	mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
 	mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
 	mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
 	mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599;
-	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82599;
 	mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
 	mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
-	mac->ops.get_device_caps = &ixgbe_get_device_caps_82599;
+	mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
 	mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
 	mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 	/* RAR, Multicast, VLAN */
 	mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 	mac->rar_highwater = 1;
 	mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 	mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 	mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 	mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
+	mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
+	mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 	/* Link */
 	mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
-	mac->ops.check_link = &ixgbe_check_mac_link_generic;
+	mac->ops.check_link            = &ixgbe_check_mac_link_generic;
 	ixgbe_init_mac_link_ops_82599(hw);
-	mac->mcft_size = 128;
+	mac->mcft_size        = 128;
-	mac->vft_size = 128;
+	mac->vft_size         = 128;
-	mac->num_rar_entries = 128;
+	mac->num_rar_entries  = 128;
-	mac->max_tx_queues = 128;
+	mac->rx_pb_size       = 512;
-	mac->max_rx_queues = 128;
+	mac->max_tx_queues    = 128;
+	mac->max_rx_queues    = 128;
 	mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
-	return (ret_val);
+	return ret_val;
 }
-/*
+/**
-* ixgbe_get_link_capabilities_82599 - Determines link capabilities
+*  ixgbe_get_link_capabilities_82599 - Determines link capabilities
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @speed: pointer to link speed
+*  @speed: pointer to link speed
-* @negotiation: true when autoneg or autotry is enabled
+*  @negotiation: TRUE when autoneg or autotry is enabled
 *
-* Determines the link capabilities by reading the AUTOC register.
+*  Determines the link capabilities by reading the AUTOC register.
-*/
+**/
-s32
+s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
-ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
+ixgbe_link_speed *speed,
-ixgbe_link_speed *speed, bool *negotiation)
+bool *negotiation)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = 0;
 	DEBUGFUNC("ixgbe_get_link_capabilities_82599");
 	/* Check if 1G SFP module. */
 	if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		goto out;
 	}
 	/*
 	 * Determine link capabilities based on the stored value of AUTOC,
 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 	case IXGBE_AUTOC_LMS_1G_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 	case IXGBE_AUTOC_LMS_10G_SERIAL:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 		*speed = IXGBE_LINK_SPEED_100_FULL;
 		if (autoc & IXGBE_AUTOC_KR_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 	case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 	default:
 		status = IXGBE_ERR_LINK_SETUP;
 		goto out;
 	}
 	if (hw->phy.multispeed_fiber) {
 		*speed |= IXGBE_LINK_SPEED_10GB_FULL |
-		    IXGBE_LINK_SPEED_1GB_FULL;
+		          IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 	}
 out:
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_get_media_type_82599 - Get media type
+*  ixgbe_get_media_type_82599 - Get media type
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* Returns the media type (fiber, copper, backplane)
+*  Returns the media type (fiber, copper, backplane)
-*/
+**/
-enum ixgbe_media_type
+enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
-ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 {
 	enum ixgbe_media_type media_type;
 	DEBUGFUNC("ixgbe_get_media_type_82599");
 	/* Detect if there is a copper PHY attached. */
-	if (hw->phy.type == ixgbe_phy_cu_unknown ||
+	switch (hw->phy.type) {
-	    hw->phy.type == ixgbe_phy_tn ||
+	case ixgbe_phy_cu_unknown:
-	    hw->phy.type == ixgbe_phy_aq) {
+	case ixgbe_phy_tn:
+	case ixgbe_phy_aq:
 		media_type = ixgbe_media_type_copper;
 		goto out;
+	default:
+		break;
 	}
 	switch (hw->device_id) {
 	case IXGBE_DEV_ID_82599_KX4:
 	case IXGBE_DEV_ID_82599_KX4_MEZZ:
 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
-	case IXGBE_DEV_ID_82599_KR:
+	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
 	case IXGBE_DEV_ID_82599_XAUI_LOM:
 		/* Default device ID is mezzanine card KX/KX4 */
 		media_type = ixgbe_media_type_backplane;
 		break;
 	case IXGBE_DEV_ID_82599_SFP:
-	case IXGBE_DEV_ID_82599_SFP_EM:
+	case IXGBE_DEV_ID_82599_SFP_FCOE:
 		media_type = ixgbe_media_type_fiber;
 		break;
 	case IXGBE_DEV_ID_82599_CX4:
 		media_type = ixgbe_media_type_cx4;
 		break;
 	default:
 		media_type = ixgbe_media_type_unknown;
 		break;
 	}
 out:
-	return (media_type);
+	return media_type;
 }
-/*
+/**
-* ixgbe_start_mac_link_82599 - Setup MAC link settings
+*  ixgbe_start_mac_link_82599 - Setup MAC link settings
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-*
+*  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
-* Configures link settings based on values in the ixgbe_hw struct.
+*
-* Restarts the link.  Performs autonegotiation if needed.
+*  Configures link settings based on values in the ixgbe_hw struct.
-*/
+*  Restarts the link.  Performs autonegotiation if needed.
-s32
+**/
-ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
+s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
+bool autoneg_wait_to_complete)
 {
 	u32 autoc_reg;
 	u32 links_reg;
 	u32 i;
 	s32 status = IXGBE_SUCCESS;
 	DEBUGFUNC("ixgbe_start_mac_link_82599");
 	/* Restart link */
 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 	/* Only poll for autoneg to complete if specified to do so */
 	if (autoneg_wait_to_complete) {
 		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR ||
+		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
+		     IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
+		     IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 			links_reg = 0; /* Just in case Autoneg time = 0 */
 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 				if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 					break;
 	}
 	/* Add delay to filter out noises during initial link setup */
 	msec_delay(50);
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
+*  ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* The base drivers may require better control over SFP+ module
+*  The base drivers may require better control over SFP+ module
-* PHY states.  This includes selectively shutting down the Tx
+*  PHY states.  This includes selectively shutting down the Tx
-* laser on the PHY, effectively halting physical link.
+*  laser on the PHY, effectively halting physical link.
-*/
+**/
-void
+void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
-	/*
+	/* Disable tx laser; allow 100us to go dark per spec */
-	 * Disable tx laser; allow 100us to go dark per spec
-	 */
 	esdp_reg |= IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(100);
 }
-/*
+/**
-* ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
+*  ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* The base drivers may require better control over SFP+ module
+*  The base drivers may require better control over SFP+ module
-* PHY states.  This includes selectively turning on the Tx
+*  PHY states.  This includes selectively turning on the Tx
-* laser on the PHY, effectively starting physical link.
+*  laser on the PHY, effectively starting physical link.
-*/
+**/
-void
+void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
-	/*
+	/* Enable tx laser; allow 100ms to light up */
-	 * Enable tx laser; allow 100ms to light up
-	 */
 	esdp_reg &= ~IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	msec_delay(100);
 }
-/*
+/**
-* ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
+*  ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* When the driver changes the link speeds that it can support,
+*  When the driver changes the link speeds that it can support,
-* it sets autotry_restart to true to indicate that we need to
+*  it sets autotry_restart to TRUE to indicate that we need to
-* initiate a new autotry session with the link partner.  To do
+*  initiate a new autotry session with the link partner.  To do
-* so, we set the speed then disable and re-enable the tx laser, to
+*  so, we set the speed then disable and re-enable the tx laser, to
-* alert the link partner that it also needs to restart autotry on its
+*  alert the link partner that it also needs to restart autotry on its
-* end.  This is consistent with true clause 37 autoneg, which also
+*  end.  This is consistent with TRUE clause 37 autoneg, which also
-* involves a loss of signal.
+*  involves a loss of signal.
-*/
+**/
-void
+void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
 	if (hw->mac.autotry_restart) {
 		ixgbe_disable_tx_laser_multispeed_fiber(hw);
 		ixgbe_enable_tx_laser_multispeed_fiber(hw);
-		hw->mac.autotry_restart = false;
+		hw->mac.autotry_restart = FALSE;
 	}
 }
-/*
+/**
-* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
+*  ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @speed: new link speed
+*  @speed: new link speed
-* @autoneg: true if autonegotiation enabled
+*  @autoneg: TRUE if autonegotiation enabled
-* @autoneg_wait_to_complete: true when waiting for completion is needed
+*  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
 *
-* Set the link speed in the AUTOC register and restarts link.
+*  Set the link speed in the AUTOC register and restarts link.
-*/
+**/
-s32
+s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
-ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
+ixgbe_link_speed speed, bool autoneg,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
-	ixgbe_link_speed link_speed;
+	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	u32 speedcnt = 0;
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 	u32 i = 0;
-	bool link_up = false;
+	bool link_up = FALSE;
 	bool negotiation;
 	DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
 	/* Mask off requested but non-supported speeds */
 	status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
 	if (status != IXGBE_SUCCESS)
-		return (status);
+		return status;
 	speed &= link_speed;
 	/*
 	 * Try each speed one by one, highest priority first.  We do this in
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 		speedcnt++;
 		highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 		/* If we already have link at this speed, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 		if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
 			goto out;
 		/* Set the module link speed */
 		IXGBE_WRITE_FLUSH(hw);
 		/* Allow module to change analog characteristics (1G->10G) */
 		msec_delay(40);
-		status = ixgbe_setup_mac_link_82599(
+		status = ixgbe_setup_mac_link_82599(hw,
-		    hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg,
+						IXGBE_LINK_SPEED_10GB_FULL,
-		    autoneg_wait_to_complete);
+						autoneg,
+						autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 		/* Flap the tx laser if it has not already been done */
 		ixgbe_flap_tx_laser(hw);
 		/*
 			/* Wait for the link partner to also set speed */
 			msec_delay(100);
 			/* If we have link, just jump out */
 			status = ixgbe_check_link(hw, &link_speed,
-			    &link_up, false);
+			                          &link_up, FALSE);
 			if (status != IXGBE_SUCCESS)
-				return (status);
+				return status;
 			if (link_up)
 				goto out;
 		}
 	}
 		speedcnt++;
 		if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 			highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 		/* If we already have link at this speed, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 		if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
 			goto out;
 		/* Set the module link speed */
 		IXGBE_WRITE_FLUSH(hw);
 		/* Allow module to change analog characteristics (10G->1G) */
 		msec_delay(40);
-		status = ixgbe_setup_mac_link_82599(
+		status = ixgbe_setup_mac_link_82599(hw,
-		    hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
+						    IXGBE_LINK_SPEED_1GB_FULL,
-		    autoneg_wait_to_complete);
+						    autoneg,
+						    autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 		/* Flap the tx laser if it has not already been done */
 		ixgbe_flap_tx_laser(hw);
 		/* Wait for the link partner to also set speed */
 		msec_delay(100);
 		/* If we have link, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 		if (link_up)
 			goto out;
 	}
 	 * (if there was more than one).  We call ourselves back with just the
 	 * single highest speed that the user requested.
 	 */
 	if (speedcnt > 1)
 		status = ixgbe_setup_mac_link_multispeed_fiber(hw,
-		    highest_link_speed, autoneg, autoneg_wait_to_complete);
+		        highest_link_speed, autoneg, autoneg_wait_to_complete);
 out:
 	/* Set autoneg_advertised value based on input link speed */
 	hw->phy.autoneg_advertised = 0;
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
+*  ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @speed: new link speed
+*  @speed: new link speed
-* @autoneg: true if autonegotiation enabled
+*  @autoneg: TRUE if autonegotiation enabled
-* @autoneg_wait_to_complete: true when waiting for completion is needed
+*  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
 *
-* Implements the Intel SmartSpeed algorithm.
+*  Implements the Intel SmartSpeed algorithm.
-*/
+**/
-s32
+s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
-ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
+				     ixgbe_link_speed speed, bool autoneg,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+				     bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
 	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	s32 i, j;
-	bool link_up = false;
+	bool link_up = FALSE;
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
-	/* Set autoneg_advertised value based on input link speed */
+	 /* Set autoneg_advertised value based on input link speed */
 	hw->phy.autoneg_advertised = 0;
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 	 * highest negotiated rate.  This can sometimes happen due to integrity
 	 * issues with the physical media connection.
 	 */
 	/* First, try to get link with full advertisement */
-	hw->phy.smart_speed_active = false;
+	hw->phy.smart_speed_active = FALSE;
 	for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
 		status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-		    autoneg_wait_to_complete);
+						    autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
 			goto out;
 		/*
 		 * Wait for the controller to acquire link.  Per IEEE 802.3ap,
 		for (i = 0; i < 5; i++) {
 			msec_delay(100);
 			/* If we have link, just jump out */
 			status = ixgbe_check_link(hw, &link_speed, &link_up,
-			    false);
+						  FALSE);
 			if (status != IXGBE_SUCCESS)
 				goto out;
 			if (link_up)
 				goto out;
 	if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
 	    ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
 		goto out;
 	/* Turn SmartSpeed on to disable KR support */
-	hw->phy.smart_speed_active = true;
+	hw->phy.smart_speed_active = TRUE;
 	status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+					    autoneg_wait_to_complete);
 	if (status != IXGBE_SUCCESS)
 		goto out;
 	/*
 	 * Wait for the controller to acquire link.  600ms will allow for
 	 */
 	for (i = 0; i < 6; i++) {
 		msec_delay(100);
 		/* If we have link, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
 			goto out;
 		if (link_up)
 			goto out;
 	}
 	/* We didn't get link.  Turn SmartSpeed back off. */
-	hw->phy.smart_speed_active = false;
+	hw->phy.smart_speed_active = FALSE;
 	status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+					    autoneg_wait_to_complete);
 out:
 	if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
 		DEBUGOUT("Smartspeed has downgraded the link speed "
 		"from the maximum advertised\n");
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_setup_mac_link_82599 - Set MAC link speed
+*  ixgbe_setup_mac_link_82599 - Set MAC link speed
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @speed: new link speed
+*  @speed: new link speed
-* @autoneg: true if autonegotiation enabled
+*  @autoneg: TRUE if autonegotiation enabled
-* @autoneg_wait_to_complete: true when waiting for completion is needed
+*  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
 *
-* Set the link speed in the AUTOC register and restarts link.
+*  Set the link speed in the AUTOC register and restarts link.
-*/
+**/
-s32
+s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
-ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
+ixgbe_link_speed speed, bool autoneg,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	u32 start_autoc = autoc;
 	if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 		status = IXGBE_ERR_LINK_SETUP;
 		goto out;
 	}
-	/*
+	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
-	 * Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support
-	 */
 	if (hw->mac.orig_link_settings_stored)
 		orig_autoc = hw->mac.orig_autoc;
 	else
 		orig_autoc = autoc;
 		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 		if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 				autoc |= IXGBE_AUTOC_KX4_SUPP;
 			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
-			    (hw->phy.smart_speed_active == false))
+			    (hw->phy.smart_speed_active == FALSE))
 				autoc |= IXGBE_AUTOC_KR_SUPP;
 		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 			autoc |= IXGBE_AUTOC_KX_SUPP;
 	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
-	    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
+	           (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
-	    link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
+	            link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 		/* Switch from 1G SFI to 10G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 		    (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
 			autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 		}
 	} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
-	    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
+	           (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 		/* Switch from 10G SFI to 1G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 		    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
 			if (autoneg)
 				autoc |= IXGBE_AUTOC_LMS_1G_AN;
 			else
 				autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
-			}
+		}
 	}
 	if (autoc != start_autoc) {
 		/* Restart link */
 		autoc |= IXGBE_AUTOC_AN_RESTART;
 		/* Only poll for autoneg to complete if specified to do so */
 		if (autoneg_wait_to_complete) {
 			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
-				links_reg = 0; /* Just in case Autoneg time=0 */
+				links_reg = 0; /*Just in case Autoneg time=0*/
 				for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 					links_reg =
-					    IXGBE_READ_REG(hw, IXGBE_LINKS);
+					       IXGBE_READ_REG(hw, IXGBE_LINKS);
 					if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 						break;
 					msec_delay(100);
 				}
 				if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 					status =
-					    IXGBE_ERR_AUTONEG_NOT_COMPLETE;
+						IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 					DEBUGOUT("Autoneg did not complete.\n");
 				}
 			}
 		}
 		/* Add delay to filter out noises during initial link setup */
 		msec_delay(50);
 	}
 out:
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
+*  ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @speed: new link speed
+*  @speed: new link speed
-* @autoneg: true if autonegotiation enabled
+*  @autoneg: TRUE if autonegotiation enabled
-* @autoneg_wait_to_complete: true if waiting is needed to complete
+*  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
 *
-* Restarts link on PHY and MAC based on settings passed in.
+*  Restarts link on PHY and MAC based on settings passed in.
-*/
+**/
-static s32
+static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
-ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
+ixgbe_link_speed speed,
-ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+bool autoneg,
+bool autoneg_wait_to_complete)
 {
 	s32 status;
 	DEBUGFUNC("ixgbe_setup_copper_link_82599");
 	/* Setup the PHY according to input speed */
 	status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+	                                      autoneg_wait_to_complete);
 	/* Set up MAC */
 	(void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
-	return (status);
+	return status;
 }
-/*
-* ixgbe_reset_hw_82599 - Perform hardware reset
+/**
-* @hw: pointer to hardware structure
+*  ixgbe_reset_hw_82599 - Perform hardware reset
-*
+*  @hw: pointer to hardware structure
-* Resets the hardware by resetting the transmit and receive units, masks
+*
-* and clears all interrupts, perform a PHY reset, and perform a link (MAC)
+*  Resets the hardware by resetting the transmit and receive units, masks
-* reset.
+*  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
-*/
+*  reset.
-s32
+**/
-ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
+s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 ctrl;
 	u32 i;
 	u32 autoc;
 		goto reset_hw_out;
 	/* Setup SFP module if there is one present. */
 	if (hw->phy.sfp_setup_needed) {
 		status = hw->mac.ops.setup_sfp(hw);
-		hw->phy.sfp_setup_needed = false;
+		hw->phy.sfp_setup_needed = FALSE;
 	}
 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 		goto reset_hw_out;
 	/* Reset PHY */
-	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
+	if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
 		hw->phy.ops.reset(hw);
 	/*
 	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 	 * access and verify no pending requests before reset
 	/* Poll for reset bit to self-clear indicating reset is complete */
 	for (i = 0; i < 10; i++) {
 		usec_delay(1);
 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
-		if (!(ctrl & IXGBE_CTRL_RST)) {
+		if (!(ctrl & IXGBE_CTRL_RST))
 			break;
-		}
 	}
 	if (ctrl & IXGBE_CTRL_RST) {
 		status = IXGBE_ERR_RESET_FAILED;
 		DEBUGOUT("Reset polling failed to complete.\n");
 	}
 	 * stored off yet.  Otherwise restore the stored original
 	 * values since the reset operation sets back to defaults.
 	 */
 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
-	if (hw->mac.orig_link_settings_stored == false) {
+	if (hw->mac.orig_link_settings_stored == FALSE) {
 		hw->mac.orig_autoc = autoc;
 		hw->mac.orig_autoc2 = autoc2;
-		hw->mac.orig_link_settings_stored = true;
+		hw->mac.orig_link_settings_stored = TRUE;
 	} else {
-		if (autoc != hw->mac.orig_autoc) {
+		if (autoc != hw->mac.orig_autoc)
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
-			    IXGBE_AUTOC_AN_RESTART));
+					IXGBE_AUTOC_AN_RESTART));
-		}
 		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 			autoc2 |= (hw->mac.orig_autoc2 &
-			    IXGBE_AUTOC2_UPPER_MASK);
+			           IXGBE_AUTOC2_UPPER_MASK);
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 		}
 	}
 	/* Store the permanent mac address */
 	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 	/* Add the SAN MAC address to the RAR only if it's a valid address */
 	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 		hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
-		    hw->mac.san_addr, 0, IXGBE_RAH_AV);
+		                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 		/* Reserve the last RAR for the SAN MAC address */
 		hw->mac.num_rar_entries--;
 	}
 	/* Store the alternative WWNN/WWPN prefix */
 	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
-	    &hw->mac.wwpn_prefix);
+	                               &hw->mac.wwpn_prefix);
 reset_hw_out:
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
+*  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-*/
+**/
-s32
+s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
-ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
 {
 	int i;
 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
 	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
 	 * Before starting reinitialization process,
 	 * FDIRCMD.CMD must be zero.
 	 */
 	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
-		    IXGBE_FDIRCMD_CMD_MASK))
+		      IXGBE_FDIRCMD_CMD_MASK))
 			break;
 		usec_delay(10);
 	}
 	if (i >= IXGBE_FDIRCMD_CMD_POLL) {
 		DEBUGOUT("Flow Director previous command isn't complete, "
-		    "aborting table re-initialization. \n");
+		         "aborting table re-initialization. \n");
-		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
 	IXGBE_WRITE_FLUSH(hw);
 	/*
 	 * before re-writing the FDIRCTRL control register with the same value.
 	 * - write 1 to bit 8 of FDIRCMD register &
 	 * - write 0 to bit 8 of FDIRCMD register
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
-	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
+	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
-	    IXGBE_FDIRCMD_CLEARHT));
+	                 IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
-	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
+	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
-	    ~IXGBE_FDIRCMD_CLEARHT));
+	                 ~IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	/*
 	 * Clear FDIR Hash register to clear any leftover hashes
 	 * waiting to be programmed.
 	 */
 	IXGBE_WRITE_FLUSH(hw);
 	/* Poll init-done after we write FDIRCTRL register */
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		usec_delay(10);
 	}
 	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
-		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 	/* Clear FDIR statistics registers (read to clear) */
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
-/*
+/**
-* ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
+*  ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @pballoc: which mode to allocate filters with
+*  @pballoc: which mode to allocate filters with
-*/
+**/
-s32
+s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
-ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
 	u32 pbsize;
 	int i;
 	 * must be reduced.  The new value is the current size minus
 	 * flow director memory usage size.
 	 */
 	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
 	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize);
+	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 	/*
 	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
 	 * intialized to zero for non DCB mode otherwise actual total RX PB
 	 * would be bigger than programmed and filter space would run into
 		/* 32k - 1 signature filters */
 		fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 		break;
 	default:
 		/* bad value */
-		return (IXGBE_ERR_CONFIG);
+		return IXGBE_ERR_CONFIG;
 	};
 	/* Move the flexible bytes to use the ethertype - shift 6 words */
 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 	/* Prime the keys for hashing */
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
-	    IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY));
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-	    IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY));
 	/*
 	 * Poll init-done after we write the register.  Estimated times:
-	 *   10G: PBALLOC = 11b, timing is 60us
+	 *      10G: PBALLOC = 11b, timing is 60us
-	 *    1G: PBALLOC = 11b, timing is 600us
+	 *       1G: PBALLOC = 11b, timing is 600us
-	 *  100M: PBALLOC = 11b, timing is 6ms
+	 *     100M: PBALLOC = 11b, timing is 6ms
 	 *
-	 *   Multiple these timings by 4 if under full Rx load
+	 *     Multiple these timings by 4 if under full Rx load
 	 *
 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 	 * this might not finish in our poll time, but we can live with that
 	 * for now.
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 	IXGBE_WRITE_FLUSH(hw);
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		msec_delay(1);
 	}
-	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
 		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
-	}
+	return IXGBE_SUCCESS;
-	return (IXGBE_SUCCESS);
+}
-}
+/**
-/*
+*  ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
-* ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
+*  @hw: pointer to hardware structure
-* @hw: pointer to hardware structure
+*  @pballoc: which mode to allocate filters with
-* @pballoc: which mode to allocate filters with
+**/
-*/
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
-s32
-ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
 	u32 pbsize;
 	int i;
 	/*
 	 * Before enabling Flow Director, the Rx Packet Buffer size
 	 * must be reduced.  The new value is the current size minus
 	 * flow director memory usage size.
 	 */
 	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
 	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize);
+	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 	/*
 	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
 	 * intialized to zero for non DCB mode otherwise actual total RX PB
 	 * would be bigger than programmed and filter space would run into
 		/* 8k - 1 perfect filters */
 		fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 		break;
 	default:
 		/* bad value */
-		return (IXGBE_ERR_CONFIG);
+		return IXGBE_ERR_CONFIG;
 	};
 	/* Turn perfect match filtering on */
 	fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 	fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 	/* Move the flexible bytes to use the ethertype - shift 6 words */
 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 	/* Prime the keys for hashing */
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
-	    IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY));
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY);
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-	    IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY));
 	/*
 	 * Poll init-done after we write the register.  Estimated times:
-	 *   10G: PBALLOC = 11b, timing is 60us
+	 *      10G: PBALLOC = 11b, timing is 60us
-	 *    1G: PBALLOC = 11b, timing is 600us
+	 *       1G: PBALLOC = 11b, timing is 600us
-	 *  100M: PBALLOC = 11b, timing is 6ms
+	 *     100M: PBALLOC = 11b, timing is 6ms
 	 *
-	 *  Multiple these timings by 4 if under full Rx load
+	 *     Multiple these timings by 4 if under full Rx load
 	 *
 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 	 * this might not finish in our poll time, but we can live with that
 	 * for now.
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 	IXGBE_WRITE_FLUSH(hw);
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		msec_delay(1);
 	}
-	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
 		DEBUGOUT("Flow Director Perfect poll time exceeded!\n");
-	}
+	return IXGBE_SUCCESS;
-	return (IXGBE_SUCCESS);
+}
-}
+/**
-/*
+*  ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
-* ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
+*  @stream: input bitstream to compute the hash on
-* @stream: input bitstream to compute the hash on
+*  @key: 32-bit hash key
-* @key: 32-bit hash key
+**/
-*/
+u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
-u16
+				 u32 key)
-ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
 {
 	/*
 	 * The algorithm is as follows:
 	 *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
 	 *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
 	 *    and A[n] x B[n] is bitwise AND between same length strings
 	 *
 	 *    K[n] is 16 bits, defined as:
-	 *	for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
+	 *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
-	 *	for n modulo 32 < 15, K[n] =
+	 *       for n modulo 32 < 15, K[n] =
-	 *		K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
+	 *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 	 *
 	 *    S[n] is 16 bits, defined as:
-	 *	for n >= 15, S[n] = S[n:n - 15]
+	 *       for n >= 15, S[n] = S[n:n - 15]
-	 *	for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
+	 *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 	 *
 	 *    To simplify for programming, the algorithm is implemented
 	 *    in software this way:
 	 *
-	 *    Key[31:0], Stream[335:0]
+	 *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 	 *
-	 *    tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
+	 *    for (i = 0; i < 352; i+=32)
-	 *    int_key[350:0] = tmp_key[351:1]
+	 *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
-	 *    int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
 	 *
-	 *    hash[15:0] = 0;
+	 *    lo_hash_dword[15:0]  ^= Stream[15:0];
-	 *    for (i = 0; i < 351; i++) {
+	 *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
-	 *	if (int_key[i])
+	 *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
-	 *		hash ^= int_stream[(i + 15):i];
+	 *
+	 *    hi_hash_dword[31:0]  ^= Stream[351:320];
+	 *
+	 *    if(key[0])
+	 *        hash[15:0] ^= Stream[15:0];
+	 *
+	 *    for (i = 0; i < 16; i++) {
+	 *        if (key[i])
+	 *            hash[15:0] ^= lo_hash_dword[(i+15):i];
+	 *        if (key[i + 16])
+	 *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 	 *    }
-	 */
+	 *
+	 */
-	union {
+	__be32 common_hash_dword = 0;
-		u64 fill[6];
+	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
-		u32 key[11];
+	u32 hash_result = 0;
-		u8 key_stream[44];
+	u8 i;
-	} tmp_key;
+	/* record the flow_vm_vlan bits as they are a key part to the hash */
-	u8 *stream = (u8 *)atr_input;
+	flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
-	u8 int_key[44];		/* upper-most bit unused */
-	u8 hash_str[46];	/* upper-most 2 bits unused */
+	/* generate common hash dword */
-	u16 hash_result = 0;
+	for (i = 10; i; i -= 2)
-	int i, j, k, h;
+		common_hash_dword ^= atr_input->dword_stream[i] ^
+				     atr_input->dword_stream[i - 1];
-	DEBUGFUNC("ixgbe_atr_compute_hash_82599");
+	hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
-	/*
-	 * Initialize the fill member to prevent warnings
+	/* low dword is word swapped version of common */
-	 * on some compilers
+	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
-	 */
-	tmp_key.fill[0] = 0;
+	/* apply flow ID/VM pool/VLAN ID bits to hash words */
+	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
-	/* First load the temporary key stream */
-	for (i = 0; i < 6; i++) {
+	/* Process bits 0 and 16 */
-		u64 fillkey = ((u64)key << 32) | key;
+	if (key & 0x0001) hash_result ^= lo_hash_dword;
-		tmp_key.fill[i] = fillkey;
+	if (key & 0x00010000) hash_result ^= hi_hash_dword;
-	}
+	/*
-	/*
+	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
-	 * Set the interim key for the hashing.  Bit 352 is unused, so we must
+	 * delay this because bit 0 of the stream should not be processed
-	 * shift and compensate when building the key.
+	 * so we do not add the vlan until after bit 0 was processed
 	 */
-	int_key[0] = tmp_key.key_stream[0] >> 1;
+	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
-	for (i = 1, j = 0; i < 44; i++) {
-		unsigned int this_key = tmp_key.key_stream[j] << 7;
-		j++;
+	/* process the remaining 30 bits in the key 2 bits at a time */
-		int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
+	for (i = 15; i; i-- ) {
-	}
+		if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
+		if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
-	/*
+	}
-	 * Set the interim bit string for the hashing.  Bits 368 and 367 are
-	 * unused, so shift and compensate when building the string.
+	return hash_result & IXGBE_ATR_HASH_MASK;
-	 */
-	hash_str[0] = (stream[40] & 0x7f) >> 1;
-	for (i = 1, j = 40; i < 46; i++) {
-		unsigned int this_str = stream[j] << 7;
-		j++;
-		if (j > 41)
-			j = 0;
-		hash_str[i] = (u8)(this_str | (stream[j] >> 1));
-	}
-	/*
-	 * Now compute the hash.  i is the index into hash_str, j is into our
-	 * key stream, k is counting the number of bits, and h interates within
-	 * each byte.
-	 */
-	for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
-		for (h = 0; h < 8 && k < 351; h++, k++) {
-			if (int_key[j] & (1 << h)) {
-				/*
-				 * Key bit is set, XOR in the current 16-bit
-				 * string.  Example of processing:
-				 *	h = 0,
-				 *	tmp = (hash_str[i - 2] & 0 << 16) |
-				 *		(hash_str[i - 1] & 0xff << 8) |
-				 *		(hash_str[i] & 0xff >> 0)
-				 *	So tmp = hash_str[15 + k:k], since the
-				 *	i + 2 clause rolls off the 16-bit value
-				 *	h = 7,
-				 *	tmp = (hash_str[i - 2] & 0x7f << 9) |
-				 *		(hash_str[i - 1] & 0xff << 1) |
-				 *		(hash_str[i] & 0x80 >> 7)
-				 */
-				int tmp = (hash_str[i] >> h);
-				tmp |= (hash_str[i - 1] << (8 - h));
-				tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
-				    << (16 - h);
-				hash_result ^= (u16)tmp;
-			}
-		}
-	}
-	return (hash_result);
 }
 /*
-* ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
+* These defines allow us to quickly generate all of the necessary instructions
-* @input: input stream to modify
+* in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
-* @vlan: the VLAN id to load
+* for values 0 through 15
 */
-s32
+#define IXGBE_ATR_COMMON_HASH_KEY \
-ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
+		(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
-{
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
-	DEBUGFUNC("ixgbe_atr_set_vlan_id_82599");
+{ \
+	u32 n = (_n); \
-	input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
+	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
-	input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
+		common_hash ^= lo_hash_dword >> n; \
+	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
-	return (IXGBE_SUCCESS);
+		bucket_hash ^= lo_hash_dword >> n; \
-}
+	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
+		sig_hash ^= lo_hash_dword << (16 - n); \
-/*
+	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
-* ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
+		common_hash ^= hi_hash_dword >> n; \
-* @input: input stream to modify
+	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
-* @src_addr: the IP address to load
+		bucket_hash ^= hi_hash_dword >> n; \
-*/
+	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
-s32
+		sig_hash ^= hi_hash_dword << (16 - n); \
-ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
+}
-{
-	DEBUGFUNC("ixgbe_atr_set_src_ipv4_82599");
+/**
+*  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
+*  @stream: input bitstream to compute the hash on
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
+*
-	    (src_addr >> 16) & 0xff;
+*  This function is almost identical to the function above but contains
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
+*  several optomizations such as unwinding all of the loops, letting the
-	    (src_addr >> 8) & 0xff;
+*  compiler work out all of the conditional ifs since the keys are static
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
+*  defines, and computing two keys at once since the hashed dword stream
+*  will be the same for both keys.
-	return (IXGBE_SUCCESS);
+**/
-}
+static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+					    union ixgbe_atr_hash_dword common)
-/*
+{
-* ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
+	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
-* @input: input stream to modify
+	u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
-* @dst_addr: the IP address to load
-*/
+	/* record the flow_vm_vlan bits as they are a key part to the hash */
-s32
+	flow_vm_vlan = IXGBE_NTOHL(input.dword);
-ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
-{
+	/* generate common hash dword */
-	DEBUGFUNC("ixgbe_atr_set_dst_ipv4_82599");
+	hi_hash_dword = IXGBE_NTOHL(common.dword);
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
+	/* low dword is word swapped version of common */
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
+	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
-	    (dst_addr >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
+	/* apply flow ID/VM pool/VLAN ID bits to hash words */
-	    (dst_addr >> 8) & 0xff;
+	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
+	/* Process bits 0 and 16 */
-	return (IXGBE_SUCCESS);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
-}
+	/*
-/*
+	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
-* ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
+	 * delay this because bit 0 of the stream should not be processed
-* @input: input stream to modify
+	 * so we do not add the vlan until after bit 0 was processed
-* @src_addr_1: the first 4 bytes of the IP address to load
+	 */
-* @src_addr_2: the second 4 bytes of the IP address to load
+	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
-* @src_addr_3: the third 4 bytes of the IP address to load
-* @src_addr_4: the fourth 4 bytes of the IP address to load
+	/* Process remaining 30 bit of the key */
-*/
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
-s32
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
-ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
-u32 src_addr_1, u32 src_addr_2, u32 src_addr_3, u32 src_addr_4)
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
-{
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
-	DEBUGFUNC("ixgbe_atr_set_src_ipv6_82599");
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
-	    (src_addr_4 >> 8) & 0xff;
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
-	    (src_addr_4 >> 16) & 0xff;
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
-	    (src_addr_3 >> 8) & 0xff;
+	/* combine common_hash result with signature and bucket hashes */
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
+	bucket_hash ^= common_hash;
-	    (src_addr_3 >> 16) & 0xff;
+	bucket_hash &= IXGBE_ATR_HASH_MASK;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
+	sig_hash ^= common_hash << 16;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
+	sig_hash &= IXGBE_ATR_HASH_MASK << 16;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
-	    (src_addr_2 >> 8) & 0xff;
+	/* return completed signature hash */
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
+	return sig_hash ^ bucket_hash;
-	    (src_addr_2 >> 16) & 0xff;
+}
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
+/**
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
+*  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
+*  @hw: pointer to hardware structure
-	    (src_addr_1 >> 8) & 0xff;
+*  @stream: input bitstream
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
+*  @queue: queue index to direct traffic to
-	    (src_addr_1 >> 16) & 0xff;
+**/
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
+s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
+union ixgbe_atr_hash_dword input,
-	return (IXGBE_SUCCESS);
+union ixgbe_atr_hash_dword common,
-}
+u8 queue)
-/*
-* ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
-* @input: input stream to modify
-* @dst_addr_1: the first 4 bytes of the IP address to load
-* @dst_addr_2: the second 4 bytes of the IP address to load
-* @dst_addr_3: the third 4 bytes of the IP address to load
-* @dst_addr_4: the fourth 4 bytes of the IP address to load
-*/
-s32
-ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
-u32 dst_addr_1, u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_set_dst_ipv6_82599");
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
-	    (dst_addr_4 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
-	    (dst_addr_4 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
-	    (dst_addr_3 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
-	    (dst_addr_3 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
-	    (dst_addr_2 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
-	    (dst_addr_2 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
-	    (dst_addr_1 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
-	    (dst_addr_1 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_set_src_port_82599 - Sets the source port
-* @input: input stream to modify
-* @src_port: the source port to load
-*/
-s32
-ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
-{
-	DEBUGFUNC("ixgbe_atr_set_src_port_82599");
-	input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
-	input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_set_dst_port_82599 - Sets the destination port
-* @input: input stream to modify
-* @dst_port: the destination port to load
-*/
-s32
-ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
-{
-	DEBUGFUNC("ixgbe_atr_set_dst_port_82599");
-	input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
-	input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
-* @input: input stream to modify
-* @flex_bytes: the flexible bytes to load
-*/
-s32
-ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
-{
-	DEBUGFUNC("ixgbe_atr_set_flex_byte_82599");
-	input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
-	input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
-* @input: input stream to modify
-* @vm_pool: the Virtual Machine pool to load
-*/
-s32
-ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool)
-{
-	DEBUGFUNC("ixgbe_atr_set_vm_pool_82599");
-	input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
-* @input: input stream to modify
-* @l4type: the layer 4 type value to load
-*/
-s32
-ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
-{
-	DEBUGFUNC("ixgbe_atr_set_l4type_82599");
-	input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
-* @input: input stream to search
-* @vlan: the VLAN id to load
-*/
-s32
-ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
-{
-	DEBUGFUNC("ixgbe_atr_get_vlan_id_82599");
-	*vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
-	*vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
-* @input: input stream to search
-* @src_addr: the IP address to load
-*/
-s32
-ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr)
-{
-	DEBUGFUNC("ixgbe_atr_get_src_ipv4_82599");
-	*src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
-* @input: input stream to search
-* @dst_addr: the IP address to load
-*/
-s32
-ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_ipv4_82599");
-	*dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
-* @input: input stream to search
-* @src_addr_1: the first 4 bytes of the IP address to load
-* @src_addr_2: the second 4 bytes of the IP address to load
-* @src_addr_3: the third 4 bytes of the IP address to load
-* @src_addr_4: the fourth 4 bytes of the IP address to load
-*/
-s32
-ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
-u32 *src_addr_1, u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_get_src_ipv6_82599");
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
-* @input: input stream to search
-* @dst_addr_1: the first 4 bytes of the IP address to load
-* @dst_addr_2: the second 4 bytes of the IP address to load
-* @dst_addr_3: the third 4 bytes of the IP address to load
-* @dst_addr_4: the fourth 4 bytes of the IP address to load
-*/
-s32
-ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
-u32 *dst_addr_1, u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_ipv6_82599");
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_src_port_82599 - Gets the source port
-* @input: input stream to modify
-* @src_port: the source port to load
-*
-* Even though the input is given in big-endian, the FDIRPORT registers
-* expect the ports to be programmed in little-endian.  Hence the need to swap
-* endianness when retrieving the data.  This can be confusing since the
-* internal hash engine expects it to be big-endian.
-*/
-s32
-ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port)
-{
-	DEBUGFUNC("ixgbe_atr_get_src_port_82599");
-	*src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
-	*src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_dst_port_82599 - Gets the destination port
-* @input: input stream to modify
-* @dst_port: the destination port to load
-*
-* Even though the input is given in big-endian, the FDIRPORT registers
-* expect the ports to be programmed in little-endian.  Hence the need to swap
-* endianness when retrieving the data.  This can be confusing since the
-* internal hash engine expects it to be big-endian.
-*/
-s32
-ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_port_82599");
-	*dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
-	*dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
-* @input: input stream to modify
-* @flex_bytes: the flexible bytes to load
-*/
-s32
-ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte)
-{
-	DEBUGFUNC("ixgbe_atr_get_flex_byte_82599");
-	*flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
-	*flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
-* @input: input stream to modify
-* @vm_pool: the Virtual Machine pool to load
-*/
-s32
-ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool)
-{
-	DEBUGFUNC("ixgbe_atr_get_vm_pool_82599");
-	*vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
-* @input: input stream to modify
-* @l4type: the layer 4 type value to load
-*/
-s32
-ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type)
-{
-	DEBUGFUNC("ixgbe_atr_get_l4type__82599");
-	*l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
-* @hw: pointer to hardware structure
-* @stream: input bitstream
-* @queue: queue index to direct traffic to
-*/
-s32
-ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-struct ixgbe_atr_input *input, u8 queue)
 {
 	u64  fdirhashcmd;
-	u64  fdircmd;
+	u32  fdircmd;
-	u32  fdirhash;
-	u16  bucket_hash, sig_hash;
-	u8   l4type;
 	DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
-	bucket_hash = ixgbe_atr_compute_hash_82599(input,
+	/*
-	    IXGBE_ATR_BUCKET_HASH_KEY);
+	 * Get the flow_type in order to program FDIRCMD properly
+	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
-	/* bucket_hash is only 15 bits */
+	 */
-	bucket_hash &= IXGBE_ATR_HASH_MASK;
+	switch (input.formatted.flow_type) {
+	case IXGBE_ATR_FLOW_TYPE_TCPV4:
-	sig_hash = ixgbe_atr_compute_hash_82599(input,
+	case IXGBE_ATR_FLOW_TYPE_UDPV4:
-	    IXGBE_ATR_SIGNATURE_HASH_KEY);
+	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+	case IXGBE_ATR_FLOW_TYPE_TCPV6:
-	/* Get the l4type in order to program FDIRCMD properly */
+	case IXGBE_ATR_FLOW_TYPE_UDPV6:
-	/* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
+	case IXGBE_ATR_FLOW_TYPE_SCTPV6:
-	(void) ixgbe_atr_get_l4type_82599(input, &l4type);
+		break;
+	default:
+		DEBUGOUT(" Error on flow type input\n");
+		return IXGBE_ERR_CONFIG;
+	}
+	/* configure FDIRCMD register */
+	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+	          IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+	fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 	/*
 	 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
 	 * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
 	 */
-	fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
+	fdirhashcmd = (u64)fdircmd << 32;
+	fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
-	fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
-	    IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
+	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-	case IXGBE_ATR_L4TYPE_TCP:
+	return IXGBE_SUCCESS;
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
+}
-		break;
-	case IXGBE_ATR_L4TYPE_UDP:
+/**
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
+*  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
-		break;
+*  @input_mask: mask to be bit swapped
-	case IXGBE_ATR_L4TYPE_SCTP:
+*
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+*  The source and destination port masks for flow director are bit swapped
+*  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
+*  generate a correctly swapped value we need to bit swap the mask and that
+*  is what is accomplished by this function.
+**/
+static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
+{
+	u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask);
+	mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
+	mask |= IXGBE_NTOHS(input_masks->src_port_mask);
+	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
+	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
+	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
+	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
+}
+/*
+* These two macros are meant to address the fact that we have registers
+* that are either all or in part big-endian.  As a result on big-endian
+* systems we will end up byte swapping the value to little-endian before
+* it is byte swapped again and written to the hardware in the original
+* big-endian format.
+*/
+#define IXGBE_STORE_AS_BE32(_value) \
+	(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
+	 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
+#define IXGBE_WRITE_REG_BE32(a, reg, value) \
+	IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
+#define IXGBE_STORE_AS_BE16(_value) \
+	(((u16)(_value) >> 8) | ((u16)(_value) << 8))
+/**
+*  ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
+*  @hw: pointer to hardware structure
+*  @input: input bitstream
+*  @input_masks: masks for the input bitstream
+*  @soft_id: software index for the filters
+*  @queue: queue index to direct traffic to
+*
+*  Note that the caller to this function must lock before calling, since the
+*  hardware writes must be protected from one another.
+**/
+s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
+union ixgbe_atr_input *input,
+struct ixgbe_atr_input_masks *input_masks,
+u16 soft_id, u8 queue)
+{
+	u32 fdirhash;
+	u32 fdircmd;
+	u32 fdirport, fdirtcpm;
+	u32 fdirvlan;
+	/* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
+	u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
+		    IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
+	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
+	/*
+	 * Check flow_type formatting, and bail out before we touch the hardware
+	 * if there's a configuration issue
+	 */
+	switch (input->formatted.flow_type) {
+	case IXGBE_ATR_FLOW_TYPE_IPV4:
+		/* use the L4 protocol mask for raw IPv4/IPv6 traffic */
+		fdirm |= IXGBE_FDIRM_L4P;
+		/* FALLTHRU */
+	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+		if (input_masks->dst_port_mask || input_masks->src_port_mask) {
+			DEBUGOUT(" Error on src/dst port mask\n");
+			return IXGBE_ERR_CONFIG;
+		}
+		break;
+	case IXGBE_ATR_FLOW_TYPE_TCPV4:
+		break;
+	case IXGBE_ATR_FLOW_TYPE_UDPV4:
 		break;
 	default:
-		DEBUGOUT(" Error on l4type input\n");
+		DEBUGOUT(" Error on flow type input\n");
-		return (IXGBE_ERR_CONFIG);
+		return IXGBE_ERR_CONFIG;
 	}
-	if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
-		fdircmd |= IXGBE_FDIRCMD_IPV6;
-	fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
-	fdirhashcmd = ((fdircmd << 32) | fdirhash);
-	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, fdirhash & 0x7FFF7FFF);
-	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
-* @hw: pointer to hardware structure
-* @input: input bitstream
-* @input_masks: masks for the input bitstream
-* @soft_id: software index for the filters
-* @queue: queue index to direct traffic to
-*
-* Note that the caller to this function must lock before calling, since the
-* hardware writes must be protected from one another.
-*/
-s32
-ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-struct ixgbe_atr_input *input, struct ixgbe_atr_input_masks *input_masks,
-u16 soft_id, u8 queue)
-{
-	u32 fdircmd = 0;
-	u32 fdirhash;
-	u32 src_ipv4 = 0, dst_ipv4 = 0;
-	u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
-	u16 src_port, dst_port, vlan_id, flex_bytes;
-	u16 bucket_hash;
-	u8  l4type;
-	u8  fdirm = 0;
-	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
-	/* Get our input values */
-	(void) ixgbe_atr_get_l4type_82599(input, &l4type);
-	/*
-	 * Check l4type formatting, and bail out before we touch the hardware
-	 * if there's a configuration issue
-	 */
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-	case IXGBE_ATR_L4TYPE_TCP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-		break;
-	case IXGBE_ATR_L4TYPE_UDP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-		break;
-	case IXGBE_ATR_L4TYPE_SCTP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
-		break;
-	default:
-		DEBUGOUT(" Error on l4type input\n");
-		return (IXGBE_ERR_CONFIG);
-	}
-	bucket_hash = ixgbe_atr_compute_hash_82599(input,
-	    IXGBE_ATR_BUCKET_HASH_KEY);
-	/* bucket_hash is only 15 bits */
-	bucket_hash &= IXGBE_ATR_HASH_MASK;
-	(void) ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
-	(void) ixgbe_atr_get_src_port_82599(input, &src_port);
-	(void) ixgbe_atr_get_dst_port_82599(input, &dst_port);
-	(void) ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
-	fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-	/* Now figure out if we're IPv4 or IPv6 */
-	if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
-		/* IPv6 */
-		(void) ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1,
-		    &src_ipv6_2, &src_ipv6_3, &src_ipv6_4);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
-		/* The last 4 bytes is the same register as IPv4 */
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
-		fdircmd |= IXGBE_FDIRCMD_IPV6;
-		fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
-	} else {
-		/* IPv4 */
-		(void) ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
-	}
-	(void) ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
-	    (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
-	    (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
 	/*
 	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 	 * are zero, then assume a full mask for that field.  Also assume that
 	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 	 * cannot be masked out in this implementation.
 	 *
 	 * This also assumes IPv4 only.  IPv6 masking isn't supported at this
 	 * point in time.
 	 */
-	if (src_ipv4 == 0)
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
+	/* Program FDIRM */
-	else
+	switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) {
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
+	case 0xEFFF:
+		/* Unmask VLAN ID - bit 0 and fall through to unmask prio */
-	if (dst_ipv4 == 0)
+		fdirm &= ~IXGBE_FDIRM_VLANID;
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
+		/* FALLTHRU */
-	else
+	case 0xE000:
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
+		/* Unmask VLAN prio - bit 1 */
+		fdirm &= ~IXGBE_FDIRM_VLANP;
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
+		break;
-	case IXGBE_ATR_L4TYPE_TCP:
+	case 0x0FFF:
-		if (src_port == 0)
+		/* Unmask VLAN ID - bit 0 */
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
+		fdirm &= ~IXGBE_FDIRM_VLANID;
-		else
+		break;
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
+	case 0x0000:
-			    input_masks->src_port_mask);
+		/* do nothing, vlans already masked */
-		if (dst_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-			    0xffff0000));
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-			    (input_masks->dst_port_mask << 16)));
-		break;
-	case IXGBE_ATR_L4TYPE_UDP:
-		if (src_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    input_masks->src_port_mask);
-		if (dst_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-			    0xffff0000));
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-			    (input_masks->src_port_mask << 16)));
 		break;
 	default:
-		/* this already would have failed above */
+		DEBUGOUT(" Error on VLAN mask\n");
-		break;
+		return IXGBE_ERR_CONFIG;
 	}
-	/* Program the last mask register, FDIRM */
+	if (input_masks->flex_mask & 0xFFFF) {
-	if (input_masks->vlan_id_mask || !vlan_id)
+		if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
-		/* Mask both VLAN and VLANP - bits 0 and 1 */
+			DEBUGOUT(" Error on flexible byte mask\n");
-		fdirm |= (IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP);
+			return IXGBE_ERR_CONFIG;
+		}
-	if (input_masks->data_mask || !flex_bytes)
+		/* Unmask Flex Bytes - bit 4 */
-		/* Flex bytes need masking, so mask the whole thing - bit 4 */
+		fdirm &= ~IXGBE_FDIRM_FLEX;
-		fdirm |= IXGBE_FDIRM_FLEX;
+	}
 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
-	fdirm |= (IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
-	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
+	/* store the TCP/UDP port masks, bit reversed from port layout */
-	fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
+	fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
-	fdircmd |= IXGBE_FDIRCMD_LAST;
-	fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
+	/* write both the same so that UDP and TCP use the same mask */
-	fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
+	/* store source and destination IP masks (big-enian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
+			     ~input_masks->src_ip_mask[0]);
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
+			     ~input_masks->dst_ip_mask[0]);
+	/* Apply masks to input data */
+	input->formatted.vlan_id &= input_masks->vlan_id_mask;
+	input->formatted.flex_bytes &= input_masks->flex_mask;
+	input->formatted.src_port &= input_masks->src_port_mask;
+	input->formatted.dst_port &= input_masks->dst_port_mask;
+	input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
+	input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
+	/* record vlan (little-endian) and flex_bytes(big-endian) */
+	fdirvlan =
+		IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes));
+	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
+	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
+	/* record source and destination port (little-endian)*/
+	fdirport = IXGBE_NTOHS(input->formatted.dst_port);
+	fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
+	fdirport |= IXGBE_NTOHS(input->formatted.src_port);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
+	/* record the first 32 bits of the destination address (big-endian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
+	/* record the source address (big-endian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+	/* configure FDIRCMD register */
+	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+	/* we only want the bucket hash so drop the upper 16 bits */
+	fdirhash = ixgbe_atr_compute_hash_82599(input,
+						IXGBE_ATR_BUCKET_HASH_KEY);
+	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
-/*
+/**
-* ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
+*  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @reg: analog register to read
+*  @reg: analog register to read
-* @val: read value
+*  @val: read value
 *
-* Performs read operation to Omer analog register specified.
+*  Performs read operation to Omer analog register specified.
-*/
+**/
-s32
+s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
-ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
 {
 	u32  core_ctl;
 	DEBUGFUNC("ixgbe_read_analog_reg8_82599");
 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
-	    (reg << 8));
+	                (reg << 8));
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 	core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
 	*val = (u8)core_ctl;
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
-/*
+/**
-* ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
+*  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @reg: atlas register to write
+*  @reg: atlas register to write
-* @val: value to write
+*  @val: value to write
 *
-* Performs write operation to Omer analog register specified.
+*  Performs write operation to Omer analog register specified.
-*/
+**/
-s32
+s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
-ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
 {
 	u32  core_ctl;
 	DEBUGFUNC("ixgbe_write_analog_reg8_82599");
 	core_ctl = (reg << 8) | val;
 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
-/*
+/**
-* ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
+*  ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* Starts the hardware using the generic start_hw function.
+*  Starts the hardware using the generic start_hw function
-* Then performs revision-specific operations:
+*  and the generation start_hw function.
-* Clears the rate limiter registers.
+*  Then performs revision-specific operations, if any.
-*/
+**/
-s32
+s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
-ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
+{
-{
-	u32 i;
-	u32 regval;
 	s32 ret_val = IXGBE_SUCCESS;
 	DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
 	ret_val = ixgbe_start_hw_generic(hw);
+	if (ret_val != IXGBE_SUCCESS)
-	/* Clear the rate limiters */
+		goto out;
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
-		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
+	ret_val = ixgbe_start_hw_gen2(hw);
-		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
+	if (ret_val != IXGBE_SUCCESS)
-	}
+		goto out;
-	IXGBE_WRITE_FLUSH(hw);
-	/* Disable relaxed ordering */
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
-	}
-	for (i = 0; i < hw->mac.max_rx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
-	}
 	/* We need to run link autotry after the driver loads */
-	hw->mac.autotry_restart = true;
+	hw->mac.autotry_restart = TRUE;
 	if (ret_val == IXGBE_SUCCESS)
 		ret_val = ixgbe_verify_fw_version_82599(hw);
+out:
-	return (ret_val);
+	return ret_val;
 }
-/*
+/**
-* ixgbe_identify_phy_82599 - Get physical layer module
+*  ixgbe_identify_phy_82599 - Get physical layer module
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
 *
-* Determines the physical layer module found on the current adapter.
+*  Determines the physical layer module found on the current adapter.
-* If PHY already detected, maintains current PHY type in hw struct,
+*  If PHY already detected, maintains current PHY type in hw struct,
-* otherwise executes the PHY detection routine.
+*  otherwise executes the PHY detection routine.
-*/
+**/
-s32
+s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
-ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 	DEBUGFUNC("ixgbe_identify_phy_82599");
 	/* Detect PHY if not unknown - returns success if already detected. */
 	status = ixgbe_identify_phy_generic(hw);
-	if (status != IXGBE_SUCCESS)
+	if (status != IXGBE_SUCCESS) {
-		status = ixgbe_identify_sfp_module_generic(hw);
+		/* 82599 10GBASE-T requires an external PHY */
+		if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
+			goto out;
+		else
+			status = ixgbe_identify_sfp_module_generic(hw);
+	}
 	/* Set PHY type none if no PHY detected */
 	if (hw->phy.type == ixgbe_phy_unknown) {
 		hw->phy.type = ixgbe_phy_none;
 		status = IXGBE_SUCCESS;
 	}
 	/* Return error if SFP module has been detected but is not supported */
 	if (hw->phy.type == ixgbe_phy_sfp_unsupported)
 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
-	return (status);
+out:
-}
+	return status;
+}
-/*
-* ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
+/**
-* @hw: pointer to hardware structure
+*  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
-*
+*  @hw: pointer to hardware structure
-* Determines physical layer capabilities of the current configuration.
+*
-*/
+*  Determines physical layer capabilities of the current configuration.
-u32
+**/
-ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
 	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 	DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
 	hw->phy.ops.identify(hw);
-	if (hw->phy.type == ixgbe_phy_tn ||
+	switch (hw->phy.type) {
-	    hw->phy.type == ixgbe_phy_aq ||
+	case ixgbe_phy_tn:
-	    hw->phy.type == ixgbe_phy_cu_unknown) {
+	case ixgbe_phy_aq:
+	case ixgbe_phy_cu_unknown:
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
+		IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 		if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 		if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 		if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 		goto out;
+	default:
+		break;
 	}
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_AN:
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
 			    IXGBE_PHYSICAL_LAYER_1000BASE_BX;
 			goto out;
-		} else {
-			/* SFI mode so read SFP module */
-			goto sfp_check;
 		}
+		/* SFI mode so read SFP module */
+		goto sfp_check;
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
 	default:
 		goto out;
 	}
 sfp_check:
-	/*
+	/* SFP check must be done last since DA modules are sometimes used to
-	 * SFP check must be done last since DA modules are sometimes used to
 	 * test KR mode -  we need to id KR mode correctly before SFP module.
-	 * Call identify_sfp because the pluggable module may have changed
+	 * Call identify_sfp because the pluggable module may have changed */
-	 */
 	hw->phy.ops.identify_sfp(hw);
 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 		goto out;
 	switch (hw->phy.type) {
 	case ixgbe_phy_sfp_avago:
 	case ixgbe_phy_sfp_ftl:
 	case ixgbe_phy_sfp_intel:
 	case ixgbe_phy_sfp_unknown:
 		hw->phy.ops.read_i2c_eeprom(hw,
-		    IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
+		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
 		hw->phy.ops.read_i2c_eeprom(hw,
-		    IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
+		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
 		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
 		else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
 	default:
 		break;
 	}
 out:
-	return (physical_layer);
+	return physical_layer;
 }
-/*
+/**
-* ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
+*  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @regval: register value to write to RXCTRL
+*  @regval: register value to write to RXCTRL
 *
-* Enables the Rx DMA unit for 82599
+*  Enables the Rx DMA unit for 82599
-*/
+**/
-s32
+s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
-ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
+{
-{
+#define IXGBE_MAX_SECRX_POLL 30
-#define	IXGBE_MAX_SECRX_POLL	30
 	int i;
 	int secrxreg;
 	DEBUGFUNC("ixgbe_enable_rx_dma_82599");
 	}
 	/* For informational purposes only */
 	if (i >= IXGBE_MAX_SECRX_POLL)
 		DEBUGOUT("Rx unit being enabled before security "
-		    "path fully disabled.	Continuing with init.\n");
+		         "path fully disabled.  Continuing with init.\n");
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 	secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
 	IXGBE_WRITE_FLUSH(hw);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
-/*
+/**
-* ixgbe_get_device_caps_82599 - Get additional device capabilities
+*  ixgbe_verify_fw_version_82599 - verify fw version for 82599
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-* @device_caps: the EEPROM word with the extra device capabilities
+*
-*
+*  Verifies that installed the firmware version is 0.6 or higher
-* This function will read the EEPROM location for the device capabilities,
+*  for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
-* and return the word through device_caps.
+*
-*/
+*  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
-s32
+*  if the FW version is not supported.
-ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
+**/
-{
+static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
-	DEBUGFUNC("ixgbe_get_device_caps_82599");
-	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
-	return (IXGBE_SUCCESS);
-}
-/*
-* ixgbe_verify_fw_version_82599 - verify fw version for 82599
-* @hw: pointer to hardware structure
-*
-* Verifies that installed the firmware version is 0.6 or higher
-* for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
-*
-* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
-* if the FW version is not supported.
-*/
-static s32
-ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM_VERSION;
 	u16 fw_offset, fw_ptp_cfg_offset;
 	u16 fw_version = 0;
 	if ((fw_offset == 0) || (fw_offset == 0xFFFF))
 		goto fw_version_out;
 	/* get the offset to the Pass Through Patch Configuration block */
 	hw->eeprom.ops.read(hw, (fw_offset +
-	    IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset);
+	                         IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
+	                         &fw_ptp_cfg_offset);
 	if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
 		goto fw_version_out;
 	/* get the firmware version */
-	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4),
+	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
-	    &fw_version);
+	                         IXGBE_FW_PATCH_VERSION_4),
+	                         &fw_version);
 	if (fw_version > 0x5)
 		status = IXGBE_SUCCESS;
 fw_version_out:
-	return (status);
+	return status;
 }
-/*
+/**
-* ixgbe_enable_relaxed_ordering_82599 - Enable relaxed ordering
+*  ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
-* @hw: pointer to hardware structure
+*  @hw: pointer to hardware structure
-*/
+*
-void
+*  Returns TRUE if the LESM FW module is present and enabled. Otherwise
-ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw)
+*  returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
-{
+**/
-	u32 regval;
+bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
-	u32 i;
+{
+	bool lesm_enabled = FALSE;
-	DEBUGFUNC("ixgbe_enable_relaxed_ordering_82599");
+	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
+	s32 status;
-	/* Enable relaxed ordering */
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
+	DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-		regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+	/* get the offset to the Firmware Module block */
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
+	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
-	}
+	if ((status != IXGBE_SUCCESS) ||
-	for (i = 0; i < hw->mac.max_rx_queues; i++) {
+	    (fw_offset == 0) || (fw_offset == 0xFFFF))
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
+		goto out;
-		regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+	/* get the offset to the LESM Parameters block */
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
+	status = hw->eeprom.ops.read(hw, (fw_offset +
-	}
+	                         IXGBE_FW_LESM_PARAMETERS_PTR),
-}
+	                         &fw_lesm_param_offset);
+	if ((status != IXGBE_SUCCESS) ||
+	    (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
+		goto out;
+	/* get the lesm state word */
+	status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
+	                             IXGBE_FW_LESM_STATE_1),
+	                             &fw_lesm_state);
+	if ((status == IXGBE_SUCCESS) &&
+	    (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
+		lesm_enabled = TRUE;
+out:
+	return lesm_enabled;
+}

Mercurial > illumos > illumos-gate

comparison usr/src/uts/common/io/ixgbe/ixgbe_82599.c @ 13448:f03238cace0b