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diff usr/src/uts/i86pc/os/cpuid.c @ 5269:395a95dbfd17

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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors 6563039 Need support for Intel's SSE4.1 and SSE4.2 instructions
author kk208521
date Mon, 15 Oct 2007 20:04:53 -0700
parents 38162db71c7d
children 2f7098179999
line wrap: on
line diff
--- a/usr/src/uts/i86pc/os/cpuid.c	Mon Oct 15 18:11:54 2007 -0700
+++ b/usr/src/uts/i86pc/os/cpuid.c	Mon Oct 15 20:04:53 2007 -0700
@@ -916,6 +916,14 @@
 			feature |= X86_SSE2;
 		if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
 			feature |= X86_SSE3;
+		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
+			if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3)
+				feature |= X86_SSSE3;
+			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1)
+				feature |= X86_SSE4_1;
+			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2)
+				feature |= X86_SSE4_2;
+		}
 	}
 	if (cp->cp_edx & CPUID_INTC_EDX_DE)
 		feature |= X86_DE;
@@ -2017,6 +2025,15 @@
 		if ((x86_feature & X86_SSE3) == 0)
 			*ecx &= ~CPUID_INTC_ECX_SSE3;
 
+		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
+			if ((x86_feature & X86_SSSE3) == 0)
+				*ecx &= ~CPUID_INTC_ECX_SSSE3;
+			if ((x86_feature & X86_SSE4_1) == 0)
+				*ecx &= ~CPUID_INTC_ECX_SSE4_1;
+			if ((x86_feature & X86_SSE4_2) == 0)
+				*ecx &= ~CPUID_INTC_ECX_SSE4_2;
+		}
+
 		/*
 		 * [no explicit support required beyond x87 fp context]
 		 */
@@ -2035,6 +2052,14 @@
 			hwcap_flags |= AV_386_SSE2;
 		if (*ecx & CPUID_INTC_ECX_SSE3)
 			hwcap_flags |= AV_386_SSE3;
+		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
+			if (*ecx & CPUID_INTC_ECX_SSSE3)
+				hwcap_flags |= AV_386_SSSE3;
+			if (*ecx & CPUID_INTC_ECX_SSE4_1)
+				hwcap_flags |= AV_386_SSE4_1;
+			if (*ecx & CPUID_INTC_ECX_SSE4_2)
+				hwcap_flags |= AV_386_SSE4_2;
+		}
 		if (*ecx & CPUID_INTC_ECX_POPCNT)
 			hwcap_flags |= AV_386_POPCNT;
 		if (*edx & CPUID_INTC_EDX_FPU)