# HG changeset patch
# User ml29623
# Date 1189215681 25200
# Node ID 29edb5b549e20ae8a4019b7dc7ff696f72c1ccb0
# Parent  119c4a9949a85fee33f3984bbafc44c114116abe
PSARC/2007/453 MSI-X interrupt limit override
6584901 nxge driver needs to use 8 MSI for 10GbE on SPARC by default for OOB performance

diff -r 119c4a9949a8 -r 29edb5b549e2 usr/src/uts/common/io/nxge/nxge_main.c
--- a/usr/src/uts/common/io/nxge/nxge_main.c	Fri Sep 07 15:05:42 2007 -0700
+++ b/usr/src/uts/common/io/nxge/nxge_main.c	Fri Sep 07 18:41:21 2007 -0700
@@ -35,9 +35,15 @@
 uint32_t 	nxge_dma_obp_props_only = 1;	/* use obp published props */
 uint32_t 	nxge_use_rdc_intr = 1;		/* debug to assign rdc intr */
 /*
- * until MSIX supported, assume msi, use 2 for msix
+ * PSARC/2007/453 MSI-X interrupt limit override
+ * (This PSARC case is limited to MSI-X vectors
+ *  and SPARC platforms only).
  */
-uint32_t	nxge_msi_enable = 1;		/* debug: turn msi off */
+#if defined(_BIG_ENDIAN)
+uint32_t	nxge_msi_enable = 2;
+#else
+uint32_t	nxge_msi_enable = 1;
+#endif
 
 /*
  * Globals: tunable parameters (/etc/system or adb)
@@ -216,6 +222,11 @@
 void
 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *);
 
+/* PSARC/2007/453 MSI-X interrupt limit override. */
+#define	NXGE_MSIX_REQUEST_10G	8
+#define	NXGE_MSIX_REQUEST_1G	2
+static int nxge_create_msi_property(p_nxge_t);
+
 /*
  * These global variables control the message
  * output.
@@ -4085,7 +4096,7 @@
 	uint_t			*inthandler;
 	void			*arg1, *arg2;
 	int			behavior;
-	int			nintrs, navail;
+	int			nintrs, navail, nrequest;
 	int			nactual, nrequired;
 	int			inum = 0;
 	int			x, y;
@@ -4116,6 +4127,18 @@
 		"ddi_intr_get_navail() returned: nintrs %d, navail %d",
 		    nintrs, navail));
 
+	/* PSARC/2007/453 MSI-X interrupt limit override */
+	if (int_type == DDI_INTR_TYPE_MSIX) {
+		nrequest = nxge_create_msi_property(nxgep);
+		if (nrequest < navail) {
+			navail = nrequest;
+			NXGE_DEBUG_MSG((nxgep, INT_CTL,
+			    "nxge_add_intrs_adv_type: nintrs %d "
+			    "navail %d (nrequest %d)",
+			    nintrs, navail, nrequest));
+		}
+	}
+
 	if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) {
 		/* MSI must be power of 2 */
 		if ((navail & 16) == 16) {
@@ -4460,6 +4483,9 @@
 
 	(void) nxge_ldgv_uninit(nxgep);
 
+	(void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
+	    "#msix-request");
+
 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs"));
 }
 
@@ -4873,3 +4899,49 @@
 
 	return (nports);
 }
+
+/*
+ * The following two functions are to support
+ * PSARC/2007/453 MSI-X interrupt limit override.
+ */
+static int
+nxge_create_msi_property(p_nxge_t nxgep)
+{
+	int	nmsi;
+	extern	int ncpus;
+
+	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property"));
+
+	switch (nxgep->mac.portmode) {
+	case PORT_10G_COPPER:
+	case PORT_10G_FIBER:
+		(void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip,
+		    DDI_PROP_CANSLEEP, "#msix-request", NULL, 0);
+		/*
+		 * The maximum MSI-X requested will be 8.
+		 * If the # of CPUs is less than 8, we will reqeust
+		 * # MSI-X based on the # of CPUs.
+		 */
+		if (ncpus >= NXGE_MSIX_REQUEST_10G) {
+			nmsi = NXGE_MSIX_REQUEST_10G;
+		} else {
+			nmsi = ncpus;
+		}
+		NXGE_DEBUG_MSG((nxgep, MOD_CTL,
+		    "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)",
+		    ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip,
+		    DDI_PROP_CANSLEEP, "#msix-request"), nmsi));
+		break;
+
+	default:
+		nmsi = NXGE_MSIX_REQUEST_1G;
+		NXGE_DEBUG_MSG((nxgep, MOD_CTL,
+		    "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)",
+		    ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip,
+		    DDI_PROP_CANSLEEP, "#msix-request"), nmsi));
+		break;
+	}
+
+	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property"));
+	return (nmsi);
+}