# HG changeset patch # User kz151634 # Date 1189650316 25200 # Node ID 4879e862fff880de43ac6a3779b5dd939ff4bc11 # Parent 8571b83c9ad0078390d5a5332405d8f8fcef3fda 6596174 AGP support for Intel 3 series 6596178 965GM/GME should have more graphics modes diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/pkgdefs/SUNWagp/postinstall --- a/usr/src/pkgdefs/SUNWagp/postinstall Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/pkgdefs/SUNWagp/postinstall Wed Sep 12 19:25:16 2007 -0700 @@ -47,6 +47,9 @@ \"pci8086,2980\" \ \"pci8086,2990\" \ \"pci8086,29a0\" \ + \"pci8086,29b0\" \ + \"pci8086,29c0\" \ + \"pci8086,29d0\" \ \"pci8086,2a00\" \ \"pci8086,2a10\" \ \"pci8086,1130\" \ diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/uts/common/sys/agp/agpdefs.h --- a/usr/src/uts/common/sys/agp/agpdefs.h Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/uts/common/sys/agp/agpdefs.h Wed Sep 12 19:25:16 2007 -0700 @@ -96,6 +96,9 @@ #define INTEL_BR_965G2 0x29a08086 #define INTEL_BR_965GM 0x2a008086 #define INTEL_BR_965GME 0x2a108086 +#define INTEL_BR_Q35 0x29b08086 +#define INTEL_BR_G33 0x29c08086 +#define INTEL_BR_Q33 0x29d08086 /* AGP common register offset in pci configuration space */ #define AGP_CONF_MISC 0x51 /* one byte */ @@ -156,18 +159,25 @@ #define INTEL_IGD_965G2 0x29a28086 #define INTEL_IGD_965GM 0x2a028086 #define INTEL_IGD_965GME 0x2a128086 -#define I8XX_CONF_GMADR 0x10 /* offset in PCI config space */ -#define I915_CONF_GMADR 0x18 /* offset in PCI config space */ -#define I8XX_CONF_GC 0x52 /* offset in PCI config space */ +#define INTEL_IGD_Q35 0x29b28086 +#define INTEL_IGD_G33 0x29c28086 +#define INTEL_IGD_Q33 0x29d28086 +/* register offsets in PCI config space */ +#define I8XX_CONF_GMADR 0x10 /* GMADR of i8xx series */ +#define I915_CONF_GMADR 0x18 /* GMADR of i915 series */ +#define IX33_CONF_GMADR 0x10 /* GMADR of x33 series */ +/* (Mirror) GMCH Graphics Control Register (GGC, MGGC) */ +#define I8XX_CONF_GC 0x52 /* Intel integrated video card graphics mode mask */ #define I8XX_GC_MODE_MASK 0x70 -#define I8XX_GC_MODE0 0x00 -#define I8XX_GC_MODE1 0x10 -#define I8XX_GC_MODE2 0x20 -#define I8XX_GC_MODE3 0x30 -#define I8XX_GC_MODE4 0x40 -#define I8XX_GC_MODE5 0x50 +#define IX33_GC_MODE_MASK 0xf0 +/* GTT Graphics Memory Size (9:8) in GMCH Graphics Control Register */ +#define IX33_GGMS_MASK 0x300 +/* No VT mode, 1MB allocated for GTT */ +#define IX33_GGMS_1M 0x100 +/* VT mode, 2MB allocated for GTT */ +#define IX33_GGMS_2M 0x200 /* Intel integrated video card GTT definition */ #define GTT_PAGE_SHIFT 12 diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/uts/common/sys/agp/agpmaster_io.h --- a/usr/src/uts/common/sys/agp/agpmaster_io.h Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/uts/common/sys/agp/agpmaster_io.h Wed Sep 12 19:25:16 2007 -0700 @@ -1,5 +1,26 @@ /* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE + * or http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at usr/src/OPENSOLARIS.LICENSE. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -46,6 +67,7 @@ typedef struct gtt_impl { ddi_acc_handle_t gtt_mmio_handle; /* mmaped graph registers */ caddr_t gtt_mmio_base; /* pointer to register base */ + ddi_acc_handle_t gtt_handle; /* GTT table */ caddr_t gtt_addr; /* pointer to gtt */ igd_info_t gtt_info; /* for I8XX_GET_INFO ioctl */ } gtt_impl_t; diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/uts/intel/io/agpgart/agpgart.c --- a/usr/src/uts/intel/io/agpgart/agpgart.c Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/uts/intel/io/agpgart/agpgart.c Wed Sep 12 19:25:16 2007 -0700 @@ -768,10 +768,17 @@ * - scratch page size * * scratch page size = 4 - * GTT size = aperture size (in MBs) + * GTT size (KB) = aperture size (MB) * this algorithm came from Xorg source code */ - prealloc_size = prealloc_size - info->agpki_apersize - 4; + if (prealloc_size > (info->agpki_apersize + 4)) + prealloc_size = + prealloc_size - info->agpki_apersize - 4; + else { + AGPDB_PRINT2((CE_WARN, "lyr_get_info: " + "pre-allocated memory too small, setting to zero")); + prealloc_size = 0; + } info->agpki_presize = prealloc_size; AGPDB_PRINT2((CE_NOTE, "lyr_get_info: prealloc_size = %ldKB, apersize = %dMB", diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/uts/intel/io/agpgart/agptarget.c --- a/usr/src/uts/intel/io/agpgart/agptarget.c Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/uts/intel/io/agpgart/agptarget.c Wed Sep 12 19:25:16 2007 -0700 @@ -54,6 +54,18 @@ kmutex_t tsoft_lock; }agp_target_softstate_t; +/* + * To get the pre-allocated graphics mem size using Graphics Mode Select + * (GMS) value. + */ +typedef struct gms_mode { + uint32_t gm_devid; /* bridge vendor + device id */ + off_t gm_regoff; /* mode selection register offset */ + uint32_t gm_mask; /* GMS mask */ + uint32_t gm_num; /* number of modes in gm_vec */ + int *gm_vec; /* modes array */ +} gms_mode_t; + static void *agptarget_glob_soft_handle; #define GETSOFTC(instance) ((agp_target_softstate_t *) \ @@ -269,114 +281,111 @@ gartaddr & AGP_ATTBASE_MASK); } +/* + * Pre-allocated graphics memory for every type of Intel north bridge, mem size + * are specified in kbytes. + */ +#define GMS_MB(n) ((n) * 1024) +#define GMS_SHIFT 4 +#define GMS_SIZE(a) (sizeof (a) / sizeof (int)) + +/* + * Since value zero always means "No memory pre-allocated", value of (GMS - 1) + * is used to index these arrays, i.e. gms_xxx[1] contains the mem size (in kb) + * that GMS value 0x1 corresponding to. + * + * Assuming all "reserved" GMS value as zero bytes of pre-allocated graphics + * memory, unless some special BIOS settings exist. + */ +static int gms_810[12] = {0, 0, 0, 0, 0, 0, 0, 512, 0, 0, 0, GMS_MB(1)}; +static int gms_830_845[4] = {0, 512, GMS_MB(1), GMS_MB(8)}; +static int gms_855GM[5] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), + GMS_MB(32)}; +/* There is no modes for 16M in datasheet, but some BIOS add it. */ +static int gms_865_915GM[4] = {GMS_MB(1), 0, GMS_MB(8), GMS_MB(16)}; +static int gms_915_945_965[3] = {GMS_MB(1), 0, GMS_MB(8)}; +static int gms_965GM[7] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), + GMS_MB(32), GMS_MB(48), GMS_MB(64)}; +static int gms_X33[9] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), + GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256)}; + +static gms_mode_t gms_modes[] = { + {INTEL_BR_810, I810_CONF_SMRAM, I810_GMS_MASK, + GMS_SIZE(gms_810), gms_810}, + {INTEL_BR_810DC, I810_CONF_SMRAM, I810_GMS_MASK, + GMS_SIZE(gms_810), gms_810}, + {INTEL_BR_810E, I810_CONF_SMRAM, I810_GMS_MASK, + GMS_SIZE(gms_810), gms_810}, + {INTEL_BR_830M, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_830_845), gms_830_845}, + {INTEL_BR_845, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_830_845), gms_830_845}, + {INTEL_BR_855GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_855GM), gms_855GM}, + {INTEL_BR_865, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_865_915GM), gms_865_915GM}, + {INTEL_BR_915GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_865_915GM), gms_865_915GM}, + {INTEL_BR_915, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_945, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_945GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_946GZ, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_965G1, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_965G2, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_965Q, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_915_945_965), gms_915_945_965}, + {INTEL_BR_965GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_965GM), gms_965GM}, + {INTEL_BR_965GME, I8XX_CONF_GC, I8XX_GC_MODE_MASK, + GMS_SIZE(gms_965GM), gms_965GM}, + {INTEL_BR_Q35, I8XX_CONF_GC, IX33_GC_MODE_MASK, + GMS_SIZE(gms_X33), gms_X33}, + {INTEL_BR_G33, I8XX_CONF_GC, IX33_GC_MODE_MASK, + GMS_SIZE(gms_X33), gms_X33}, + {INTEL_BR_Q33, I8XX_CONF_GC, IX33_GC_MODE_MASK, + GMS_SIZE(gms_X33), gms_X33} +}; + +/* Returns the size (kbytes) of pre-allocated graphics memory */ static size_t i8xx_biosmem_detect(agp_target_softstate_t *softstate) { uint8_t memval; size_t kbytes; + int i; + int num_modes; - switch (softstate->tsoft_devid) { - case INTEL_BR_810: - case INTEL_BR_810DC: - case INTEL_BR_810E: - memval = pci_config_get8(softstate->tsoft_pcihdl, - I810_CONF_SMRAM); - switch (memval & I810_GMS_MASK) { - case 0x80: - kbytes = 512; /* 512K preallocated memory */ - break; - case 0xc0: - kbytes = 1024; /* 1024K preallocated memory */ - break; - default: - kbytes = 0; /* an unexpected case */ - } - break; - case INTEL_BR_830M: - case INTEL_BR_845: - memval = pci_config_get8(softstate->tsoft_pcihdl, I8XX_CONF_GC); - switch (memval & I8XX_GC_MODE_MASK) { - case I8XX_GC_MODE2: - kbytes = 512; /* 512K preallocated memory */ - break; - case I8XX_GC_MODE3: - kbytes = 1024; /* 1M preallocated memory */ - break; - case I8XX_GC_MODE4: - kbytes = 8 * 1024; /* 8M preallocated memory */ - break; - default: - kbytes = 0; /* an unexpected case */ - } - break; - case INTEL_BR_855GM: - memval = pci_config_get8(softstate->tsoft_pcihdl, I8XX_CONF_GC); - switch (memval & I8XX_GC_MODE_MASK) { - case I8XX_GC_MODE1: - kbytes = 1024; /* 1M preallocated memory */ - break; - case I8XX_GC_MODE2: - kbytes = 4 * 1024; /* 4M preallocated memory */ - break; - case I8XX_GC_MODE3: - kbytes = 8 * 1024; /* 8M preallocated memory */ - break; - case I8XX_GC_MODE4: - kbytes = 16 * 1024; /* 16M preallocated memory */ + kbytes = 0; + /* get GMS modes list entry */ + num_modes = (sizeof (gms_modes) / sizeof (gms_mode_t)); + for (i = 0; i < num_modes; i++) { + if (gms_modes[i].gm_devid == softstate->tsoft_devid) break; - case I8XX_GC_MODE5: - kbytes = 32 * 1024; /* 32M preallocated memory */ - break; - default: - kbytes = 0; /* an unexpected case */ - } - break; - case INTEL_BR_865: - case INTEL_BR_915GM: - memval = pci_config_get8(softstate->tsoft_pcihdl, I8XX_CONF_GC); - switch (memval & I8XX_GC_MODE_MASK) { - case I8XX_GC_MODE1: - kbytes = 1024; /* 1M preallocated memory */ - break; - case I8XX_GC_MODE3: - kbytes = 8 * 1024; /* 8M preallocated memory */ - break; - /* - * There is no option for 16M in 915GM datasheet, - * but some BIOS add this option for 16M support. - */ - case I8XX_GC_MODE4: - kbytes = 16 * 1024; /* 16M preallocated memory */ - break; - default: - kbytes = 0; /* an unexpected case */ - } - break; - case INTEL_BR_915: - case INTEL_BR_945: - case INTEL_BR_945GM: - case INTEL_BR_946GZ: - case INTEL_BR_965G1: - case INTEL_BR_965G2: - case INTEL_BR_965Q: - case INTEL_BR_965GM: - case INTEL_BR_965GME: - memval = pci_config_get8(softstate->tsoft_pcihdl, I8XX_CONF_GC); - switch (memval & I8XX_GC_MODE_MASK) { - case I8XX_GC_MODE1: - kbytes = 1024; /* 1M preallocated memory */ - break; - case I8XX_GC_MODE3: - kbytes = 8 * 1024; /* 8M preallocated memory */ - break; - default: - kbytes = 0; /* an unexpected case */ - } - break; - default: - kbytes = 0; } + if (i == num_modes) + goto done; + /* fetch the GMS value from DRAM controller */ + memval = pci_config_get8(softstate->tsoft_pcihdl, + gms_modes[i].gm_regoff); + TARGETDB_PRINT2((CE_NOTE, "i8xx_biosmem_detect: memval = %x", memval)); + memval = (memval & gms_modes[i].gm_mask) >> GMS_SHIFT; + /* assuming zero byte for 0 or "reserved" GMS values */ + if (memval == 0 || memval > gms_modes[i].gm_num) { + TARGETDB_PRINT2((CE_WARN, "i8xx_biosmem_detect: " + "devid = %x, GMS = %x. assuming zero byte of " + "pre-allocated memory", gms_modes[i].gm_devid, memval)); + goto done; + } + memval--; /* use (GMS_value - 1) as index */ + kbytes = (gms_modes[i].gm_vec)[memval]; +done: TARGETDB_PRINT2((CE_NOTE, "i8xx_biosmem_detect: %ldKB BIOS pre-allocated memory detected", kbytes)); diff -r 8571b83c9ad0 -r 4879e862fff8 usr/src/uts/intel/io/agpmaster/agpmaster.c --- a/usr/src/uts/intel/io/agpmaster/agpmaster.c Wed Sep 12 16:14:19 2007 -0700 +++ b/usr/src/uts/intel/io/agpmaster/agpmaster.c Wed Sep 12 19:25:16 2007 -0700 @@ -59,7 +59,10 @@ #define MMIO_BASE(x) (x)->agpm_data.agpm_gtt.gtt_mmio_base #define MMIO_HANDLE(x) (x)->agpm_data.agpm_gtt.gtt_mmio_handle +#define GTT_HANDLE(x) (x)->agpm_data.agpm_gtt.gtt_handle +/* Base address of GTT */ #define GTT_ADDR(x) (x)->agpm_data.agpm_gtt.gtt_addr +/* Graphics memory base address */ #define APER_BASE(x) (x)->agpm_data.agpm_gtt.gtt_info.igd_aperbase #define AGPM_WRITE(x, off, val) \ @@ -98,6 +101,12 @@ (agpmaster->agpm_id == INTEL_IGD_965GM) || \ (agpmaster->agpm_id == INTEL_IGD_965GME)) +/* Intel G33 series */ +#define IS_INTEL_X33(agpmaster) ((agpmaster->agpm_id == INTEL_IGD_Q35) || \ + (agpmaster->agpm_id == INTEL_IGD_G33) || \ + (agpmaster->agpm_id == INTEL_IGD_Q33)) + + static struct modlmisc modlmisc = { &mod_miscops, "AGP master interfaces v%I%" }; @@ -159,10 +168,18 @@ master_softc = *master_softcp; /* intel integrated device */ - if (IS_IGD(master_softc)) { - if (MMIO_HANDLE(master_softc) != NULL) { + if (IS_IGD(master_softc) && + ((MMIO_HANDLE(master_softc) != NULL) || + (GTT_HANDLE(master_softc) != NULL))) { + /* + * for some chipsets, mmap handle is shared between both mmio + * and GTT table. + */ + if ((GTT_HANDLE(master_softc) != MMIO_HANDLE(master_softc)) && + (GTT_HANDLE(master_softc) != NULL)) + ddi_regs_map_free(>T_HANDLE(master_softc)); + if (MMIO_HANDLE(master_softc) != NULL) ddi_regs_map_free(&MMIO_HANDLE(master_softc)); - } } kmem_free(master_softc, sizeof (agp_master_softc_t)); @@ -194,10 +211,43 @@ apersize = 128; break; default: + apersize = 0; AGPM_DEBUG((CE_WARN, "i965_apersize: invalid GTT size in PGTBL_CTL")); } - apersize = MB2BYTES(apersize); + return (apersize); +} + +/* + * For Intel 3 series, we need to get GTT size from the GGMS field in GMCH + * Graphics Control Register. Return aperture size in MB. + */ +static off_t +i3XX_apersize(ddi_acc_handle_t pci_acc_hdl) +{ + uint16_t value; + off_t apersize; + + /* + * Get the value of configuration register MGGC "Mirror of Dev0 GMCH + * Graphics Control" from Internal Graphics #2 (Device2:Function0). + */ + value = pci_config_get16(pci_acc_hdl, I8XX_CONF_GC); + AGPM_DEBUG((CE_NOTE, "i3XX_apersize: MGGC = 0x%x", value)); + /* computing aperture size using the pre-allocated GTT size */ + switch (value & IX33_GGMS_MASK) { + case IX33_GGMS_1M: + apersize = 1024; + break; + case IX33_GGMS_2M: + apersize = 2048; + break; + default: + apersize = 0; /* no memory pre-allocated */ + AGPM_DEBUG((CE_WARN, + "i3XX_apersize: no memory allocated for GTT")); + } + AGPM_DEBUG((CE_NOTE, "i3xx_apersize: apersize = %ldM", apersize)); return (apersize); } @@ -212,30 +262,19 @@ * according to chipset. */ static int -set_gtt_mmio(dev_info_t *devi, agp_master_softc_t *agpmaster, ddi_acc_handle_t - pci_acc_hdl) +set_gtt_mmio(dev_info_t *devi, agp_master_softc_t *agpmaster, + ddi_acc_handle_t pci_acc_hdl) { - off_t apersize; + off_t apersize; /* size of graphics mem (MB) == GTT size (KB) */ uint32_t value; - off_t conf_off; /* offset in PCI conf space for aperture */ + off_t gmadr_off; /* GMADR offset in PCI config space */ int status; - if (IS_INTEL_965(agpmaster)) { - status = ddi_regs_map_setup(devi, I965_GTTMMADR, - &MMIO_BASE(agpmaster), 0, 0, &i8xx_dev_access, - &MMIO_HANDLE(agpmaster)); - CHECK_STATUS(status); - GTT_ADDR(agpmaster) = MMIO_BASE(agpmaster) + I965_GTT_OFFSET; - - conf_off = I915_CONF_GMADR; - apersize = i965_apersize(agpmaster); - /* make this the last line, to clear follow-up status check */ - status = DDI_SUCCESS; - - } else if (IS_INTEL_915(agpmaster)) { + if (IS_INTEL_X33(agpmaster)) { + /* Intel 3 series are similar with 915/945 series */ status = ddi_regs_map_setup(devi, I915_GTTADDR, >T_ADDR(agpmaster), 0, 0, &i8xx_dev_access, - &MMIO_HANDLE(agpmaster)); + >T_HANDLE(agpmaster)); CHECK_STATUS(status); status = ddi_regs_map_setup(devi, I915_MMADR, @@ -243,8 +282,37 @@ &MMIO_HANDLE(agpmaster)); CHECK_STATUS(status); - conf_off = I915_CONF_GMADR; + /* + * Different computing method used in getting the base of gmadr + * and aperture size. + */ + gmadr_off = IX33_CONF_GMADR; + apersize = i3XX_apersize(pci_acc_hdl); + } else if (IS_INTEL_965(agpmaster)) { + status = ddi_regs_map_setup(devi, I965_GTTMMADR, + &MMIO_BASE(agpmaster), 0, 0, &i8xx_dev_access, + &MMIO_HANDLE(agpmaster)); + CHECK_STATUS(status); + GTT_ADDR(agpmaster) = MMIO_BASE(agpmaster) + I965_GTT_OFFSET; + GTT_HANDLE(agpmaster) = MMIO_HANDLE(agpmaster); + + gmadr_off = I915_CONF_GMADR; + apersize = i965_apersize(agpmaster); + } else if (IS_INTEL_915(agpmaster)) { + /* I915/945 series */ + status = ddi_regs_map_setup(devi, I915_GTTADDR, + >T_ADDR(agpmaster), 0, 0, &i8xx_dev_access, + >T_HANDLE(agpmaster)); + CHECK_STATUS(status); + + status = ddi_regs_map_setup(devi, I915_MMADR, + &MMIO_BASE(agpmaster), 0, 0, &i8xx_dev_access, + &MMIO_HANDLE(agpmaster)); + CHECK_STATUS(status); + + gmadr_off = I915_CONF_GMADR; status = ddi_dev_regsize(devi, I915_GMADR, &apersize); + apersize = BYTES2MB(apersize); } else { /* I8XX series */ status = ddi_regs_map_setup(devi, I8XX_MMIO_BAR, @@ -253,32 +321,30 @@ CHECK_STATUS(status); GTT_ADDR(agpmaster) = MMIO_BASE(agpmaster) + I8XX_PTE_OFFSET; - conf_off = I8XX_CONF_GMADR; + GTT_HANDLE(agpmaster) = MMIO_HANDLE(agpmaster); + gmadr_off = I8XX_CONF_GMADR; status = ddi_dev_regsize(devi, I8XX_FB_BAR, &apersize); + apersize = BYTES2MB(apersize); CHECK_STATUS(status); } /* - * if memory size is smaller than a certain value, it means + * If memory size is smaller than a certain value, it means * the register set number for graphics memory range might * be wrong */ - if (status != DDI_SUCCESS || apersize < 0x400000) { + if (status != DDI_SUCCESS || apersize < 4) { AGPM_DEBUG((CE_WARN, - "set_gtt_mmio: ddi_dev_regsize error")); + "set_gtt_mmio: error in getting graphics memory")); return (-1); } - agpmaster->agpm_data.agpm_gtt.gtt_info.igd_apersize = - BYTES2MB(apersize); + agpmaster->agpm_data.agpm_gtt.gtt_info.igd_apersize = apersize; - /* get GTT base */ - value = pci_config_get32(pci_acc_hdl, conf_off); - + /* get graphics memory base address from GMADR */ + value = pci_config_get32(pci_acc_hdl, gmadr_off); APER_BASE(agpmaster) = value & GTT_BASE_MASK; - agpmaster->agpm_data.agpm_gtt.gtt_info.igd_devid = - agpmaster->agpm_id; - AGPM_DEBUG((CE_NOTE, "set_gtt_mmio: aperbase = %x, apersize = %lx, " + AGPM_DEBUG((CE_NOTE, "set_gtt_mmio: aperbase = 0x%x, apersize = %ldM, " "gtt_addr = %p, mmio_base = %p", APER_BASE(agpmaster), apersize, (void *)GTT_ADDR(agpmaster), (void *)MMIO_BASE(agpmaster))); return (0); @@ -321,6 +387,9 @@ return (0); } + agpmaster->agpm_data.agpm_gtt.gtt_info.igd_devid = + agpmaster->agpm_id; + /* create minor node for IGD or AGP device */ instance = ddi_get_instance(devi); @@ -551,6 +620,9 @@ case INTEL_IGD_965GM: case INTEL_IGD_965GME: case INTEL_IGD_965Q: + case INTEL_IGD_Q35: + case INTEL_IGD_G33: + case INTEL_IGD_Q33: master_softc->agpm_dev_type = DEVICE_IS_I830; break; default: /* unknown id */ @@ -626,7 +698,7 @@ i++, paddr++) { if (phys2entry(seg.igs_type, *paddr, &entry)) return (-1); - ddi_put32(gtt->gtt_mmio_handle, + ddi_put32(gtt->gtt_handle, (uint32_t *)(gtt->gtt_addr + i * sizeof (uint32_t)), entry); } @@ -648,7 +720,7 @@ return; for (i = seg.igs_pgstart; i < (seg.igs_pgstart + seg.igs_npage); i++) { - ddi_put32(gtt->gtt_mmio_handle, + ddi_put32(gtt->gtt_handle, (uint32_t *)(gtt->gtt_addr + i * sizeof (uint32_t)), 0); } }