# HG changeset patch
# User Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
# Date 1333016948 18000
# Node ID af464d8d3a312dbbcdc5b26202dbd5cb8aaad18b
# Parent  8f838b3f28d2b613ce75d6490194e9b392831d62
2449 Add workaround for AMD K10 CPU erratum 721
Reviewed by: Dan McDonald <danmcd@nexenta.com>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Albert Lee <trisk@nexenta.com>
Approved by: Richard Lowe <richlowe@richlowe.net>

diff -r 8f838b3f28d2 -r af464d8d3a31 usr/src/uts/i86pc/Makefile.workarounds
--- a/usr/src/uts/i86pc/Makefile.workarounds	Tue Mar 27 13:56:18 2012 -0500
+++ b/usr/src/uts/i86pc/Makefile.workarounds	Thu Mar 29 05:29:08 2012 -0500
@@ -21,8 +21,6 @@
 # Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
 #
-# ident	"%Z%%M%	%I%	%E% SMI"
-#
 # This makefile contains workaround defines to be shared
 # by Makefile.i86pc and the genunix Makefile.
 #
@@ -117,3 +115,8 @@
 # Accessed or Dirty Bit.
 #
 WORKAROUND_DEFS += -DOPTERON_ERRATUM_298
+
+#
+# Processor May Incorrectly Update Stack Pointer
+#
+WORKAROUND_DEFS += -DOPTERON_ERRATUM_721
diff -r 8f838b3f28d2 -r af464d8d3a31 usr/src/uts/i86pc/os/cpuid.c
--- a/usr/src/uts/i86pc/os/cpuid.c	Tue Mar 27 13:56:18 2012 -0500
+++ b/usr/src/uts/i86pc/os/cpuid.c	Thu Mar 29 05:29:08 2012 -0500
@@ -3336,6 +3336,13 @@
 		return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
 		    DR_B2(eax) || RB_C0(eax));
 
+	case 721:
+#if defined(__amd64)
+		return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
+#else
+		return (0);
+#endif
+
 	default:
 		return (-1);
 
diff -r 8f838b3f28d2 -r af464d8d3a31 usr/src/uts/i86pc/os/mp_startup.c
--- a/usr/src/uts/i86pc/os/mp_startup.c	Tue Mar 27 13:56:18 2012 -0500
+++ b/usr/src/uts/i86pc/os/mp_startup.c	Thu Mar 29 05:29:08 2012 -0500
@@ -649,6 +649,10 @@
 int opteron_erratum_298;
 #endif
 
+#if defined(OPTERON_ERRATUM_721)
+int opteron_erratum_721;
+#endif
+
 static void
 workaround_warning(cpu_t *cp, uint_t erratum)
 {
@@ -1177,6 +1181,16 @@
 
 	missing += do_erratum_298(cpu);
 
+	if (cpuid_opteron_erratum(cpu, 721) > 0) {
+#if defined(OPTERON_ERRATUM_721)
+		wrmsr(MSR_AMD_DE_CFG, rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
+		opteron_erratum_721++;
+#else
+		workaround_warning(cpu, 721);
+		missing++;
+#endif
+	}
+
 #ifdef __xpv
 	return (0);
 #else
@@ -1267,6 +1281,10 @@
 		    " system\noperation may occur.\n");
 	}
 #endif
+#if defined(OPTERON_ERRATUM_721)
+	if (opteron_erratum_721)
+		workaround_applied(721);
+#endif
 }
 
 /*
diff -r 8f838b3f28d2 -r af464d8d3a31 usr/src/uts/intel/sys/controlregs.h
--- a/usr/src/uts/intel/sys/controlregs.h	Tue Mar 27 13:56:18 2012 -0500
+++ b/usr/src/uts/intel/sys/controlregs.h	Thu Mar 29 05:29:08 2012 -0500
@@ -209,6 +209,10 @@
 
 #define	AMD_BU_CFG_E298			(UINT64_C(1) << 1)
 
+#define	MSR_AMD_DE_CFG	0xc0011029
+
+#define	AMD_DE_CFG_E721			(UINT64_C(1))
+
 /* AMD's osvw MSRs */
 #define	MSR_AMD_OSVW_ID_LEN		0xc0010140
 #define	MSR_AMD_OSVW_STATUS		0xc0010141