Mercurial > illumos > illumos-gate
changeset 3159:2750b6a8d8c0
PSARC/2006/646 Extension to ddi_fm_error_t
6193493 fail all handles for a device where we know the failing device but not the individual handle
6421886 should ignore header logs for ptlp/ecrc on switches
6422933 pci_bdg_error_report() should look up handle in either dma or acc handle cache - not both
6434201 fmd_eventq does not re-queue an event with lowest hrt to head of queue
6446828 io.pci.nr ereports shouldn't be generated during cautious accesses
6457970 fma code should stop masking advisory nonfatal support
6457992 sec-ude doesn't seem to work as expected on the PLX bridge card
6491762 bdf for completions originating from behind pciex-pci bridge not as expected by eversholt rules
6491773 need to relax some pciex eversholt rules for non-posted accesses
6492223 panic during ddi_peek on x86
6494431 mask bits in pcie-pci bridge sue mask register are not being cleared
6494939 itree create time should fully evaluate "and" and "or" constraints
| author | stephh |
|---|---|
| date | Wed, 22 Nov 2006 13:57:56 -0800 |
| parents | f30a3849aa23 |
| children | 8234795d0b5f |
| files | usr/src/cmd/fm/eversholt/files/common/pci.esc usr/src/cmd/fm/eversholt/files/common/pciex.esc usr/src/cmd/fm/fmd/common/fmd_eventq.c usr/src/cmd/fm/modules/common/eversholt/eval.c usr/src/uts/common/os/ddifm.c usr/src/uts/common/os/ndifm.c usr/src/uts/common/os/pcifm.c usr/src/uts/common/sys/ddifm.h usr/src/uts/common/sys/ndifm.h usr/src/uts/common/sys/pcifm.h usr/src/uts/i86pc/io/pciex/pcie_error.c usr/src/uts/i86pc/io/pciex/pcie_pci.c usr/src/uts/i86pc/os/ddi_impl.c usr/src/uts/sun4u/cpu/spitfire.c |
| diffstat | 14 files changed, 623 insertions(+), 406 deletions(-) [+] |
line wrap: on
line diff
--- a/usr/src/cmd/fm/eversholt/files/common/pci.esc Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/cmd/fm/eversholt/files/common/pci.esc Wed Nov 22 13:57:56 2006 -0800 @@ -844,9 +844,11 @@ error.io.pcix.spl-comp-ma-u@pcibus/pcidev/pcifn, error.io.pcix.spl-comp-ta-u@pcibus/pcidev/pcifn; -prop error.io.pcix.spl-comp-ma-u@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (3)-> +prop error.io.pcix.spl-comp-ma-u@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (2)-> ereport.io.pcix.sec-spl-dis@pcibus/pcidev/pcifn, - error.io.pci.serr-u@pcibus/pcidev/pcifn, + error.io.pci.serr-u@pcibus/pcidev/pcifn; + +prop error.io.pcix.spl-comp-ma-u@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (0)-> ereport.io.pci.sec-ma@pcibus/pcidev/pcifn; prop error.io.pcix.spl-comp-ta-u@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (3)->
--- a/usr/src/cmd/fm/eversholt/files/common/pciex.esc Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/cmd/fm/eversholt/files/common/pciex.esc Wed Nov 22 13:57:56 2006 -0800 @@ -76,17 +76,6 @@ (payloadprop("source-valid") == 0 || \ payloadprop("source-id") == ((b << 8) | (d << 3) | f)) -/* - * for request from device behind pci-express/pci bridge, source-id could be - * either the originator's bdf or the bus number of the secondary bus of the - * bridge with dev/fn both 0 (if for various reasons the bridge takes ownership - * of the transaction) - */ -#define SOURCE_ID_MATCHES_BDF_OR_B \ - (payloadprop("source-valid") == 0 || \ - payloadprop("source-id") == ((b << 8) | (d << 3) | f) || \ - payloadprop("source-id") == (b << 8)) - #define SOURCE_ID_MATCHES_OWN_BDF \ (payloadprop("source-valid") == 1 && \ payloadprop("source-id") == (confprop(asru(pciexrc), TOPO_PCI_BDF) + 0)) @@ -104,9 +93,6 @@ #define PCIBDF_IS_UNDER_RC \ is_under(pciexrc<>, pcibus[b]/pcidev[d]/pcifn[f]) -#define IMM_PCIBDF_IS_UNDER_RC \ - is_under(pciexrc<>, pciexfn/pcibus[b]/pcidev[d]/pcifn[f]) - #define PCIBDF_IS_UNDER_DEV \ is_under(pciexbus/pciexdev/pciexfn, pcibus[b]/pcidev[d]/pcifn[f]) @@ -131,12 +117,6 @@ "60400" && \ confprop(asru(pcibus[b]/pcidev[d]/pcifn[f]), TOPO_PCI_CLASS) != "60401") -#define BDF_IS_PCI_IMM_LEAF \ - (confprop(asru(pciexfn/pcibus[b]/pcidev[d]/pcifn[f]),TOPO_PCI_CLASS) \ - != "60400" && \ - confprop(asru(pciexfn/pcibus[b]/pcidev[d]/pcifn[f]), TOPO_PCI_CLASS) \ - != "60401") - #define IS_BDG \ (confprop(asru(pciexbus/pciexdev/pciexfn), TOPO_PCI_EXCAP) == \ "pcibus") @@ -362,7 +342,7 @@ * - fatlink: fatal link or physical level error */ event error.io.pciex.nr-d@pciexrc/pciexbus/pciexdev/pciexfn; -event error.io.pciex.ca-d@pciexrc/pciexbus/pciexdev/pciexfn; +event error.io.pciex.flt-ca-d@pciexrc/pciexbus/pciexdev/pciexfn; event error.io.pciex.mtlp-d@pciexrc/pciexbus/pciexdev/pciexfn; event error.io.pciex.badreq-d@pciexrc/pciexbus/pciexdev/pciexfn; event error.io.pciex.flt-nf-d@pciexrc/pciexbus/pciexdev/pciexfn; @@ -379,7 +359,7 @@ prop fault.io.pciex.device-interr@pciexrc (1)-> error.io.pciex.flt-nf-d@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>, error.io.pciex.flt-f-d@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>, - error.io.pciex.ca-d@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>, + error.io.pciex.flt-ca-d@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>, error.io.pciex.mtlp-d@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>, ereport.io.pciex.corrlink_trip@pciexrc/pciexbus<>, error.io.pciex.fatlink@pciexrc/pciexbus<>/pciexdev<>/pciexfn<>; @@ -574,6 +554,7 @@ event error.io.pciex.sw-mtlp-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.mtlp-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.flt-ca-d@pciexbus/pciexdev/pciexfn; +event error.io.pciex.ca-d@pciexrc/pciexbus/pciexdev/pciexfn; event error.io.pciex.ca-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.ca-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.poisreq-d@pciexbus/pciexdev/pciexfn; @@ -596,16 +577,12 @@ event error.io.pciex.source-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn; event error.io.pciex.source-f-ecrcreq-u@pcibus/pcidev/pcifn; event error.io.pciex.source-nf-ecrcreq-u@pcibus/pcidev/pcifn; -event error.io.pciex.source-f-ecrcreq-u@pciexfn/pcibus/pcidev/pcifn; -event error.io.pciex.source-nf-ecrcreq-u@pciexfn/pcibus/pcidev/pcifn; event error.io.pciex.ecrccomp-u@pciexbus/pciexdev/pciexfn; event error.io.pciex.ecrccomp-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.source-f-ecrccomp-u@pciexbus/pciexdev/pciexfn; event error.io.pciex.source-nf-ecrccomp-u@pciexbus/pciexdev/pciexfn; event error.io.pciex.source-f-ecrccomp-u@pcibus/pcidev/pcifn; event error.io.pciex.source-nf-ecrccomp-u@pcibus/pcidev/pcifn; -event error.io.pciex.source-f-ecrccomp-u@pciexfn/pcibus/pcidev/pcifn; -event error.io.pciex.source-nf-ecrccomp-u@pciexfn/pcibus/pcidev/pcifn; event error.io.pciex.poiscomp-u@pciexbus/pciexdev/pciexfn; event error.io.pciex.poiscomp-u@pciexrc/pciexbus/pciexdev/pciexfn; event error.io.pciex.poiscomp-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; @@ -640,11 +617,15 @@ event error.io.pciex.f-lf-poisreq-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; +event error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn; +event error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.f-poiscomp-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.f-poiscomp-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.f-lf-poiscomp-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; +event error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn; +event error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.f-ecrcreq-d@pciexbus/pciexdev/pciexfn; event error.io.pciex.f-ecrcreq-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn; event error.io.pciex.f-ecrcreq-d@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn; @@ -737,7 +718,7 @@ * Use these for errors reported by root-complex on behalf of another device. * Can use source-id payload to identify where the message came from. */ -prop error.io.pciex.fatal@pciexbus[b]/pciexdev[d]/pciexfn[f] (0)-> +prop error.io.pciex.fatal@pciexbus[b]/pciexdev[d]/pciexfn[f] (1)-> ereport.io.pciex.rc.fe-msg@pciexrc<> { SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC }; @@ -754,7 +735,7 @@ prop error.io.pciex.fatal-u@pciexrc/pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.sec-rserr@pciexrc; -prop error.io.pciex.nonfatal@pciexbus[b]/pciexdev[d]/pciexfn[f] (0)-> +prop error.io.pciex.nonfatal@pciexbus[b]/pciexdev[d]/pciexfn[f] (1)-> ereport.io.pciex.rc.nfe-msg@pciexrc<> { SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC }; @@ -835,7 +816,7 @@ * bridge internal error */ prop error.io.pciex.sec-interr@pciexbus/pciexdev/pciexfn (2) -> - error.io.pciex.fatal@pciexbus/pciexdev/pciexfn { IS_BDG }, + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_BDG }, ereport.io.pciex.bdg.sec-interr@pciexbus/pciexdev/pciexfn { IS_BDG }; /* @@ -877,8 +858,12 @@ ereport.io.service.lost@pciexbus/pciexdev/pciexfn, ereport.io.service.degraded@pciexbus/pciexdev/pciexfn; +prop error.io.pciex.f-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; + prop error.io.pciex.flt-nf-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> - error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn; + error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn, + error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn; prop error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn/pciexbus<>/pciexdev<>/pciexfn<>; @@ -903,6 +888,19 @@ prop error.io.service.restored@pciexbus/pciexdev/pciexfn (1)-> ereport.io.service.restored@pciexbus/pciexdev/pciexfn; +prop error.io.pciex.nf-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; + +prop error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn/pciexbus<>/pciexdev<>/pciexfn<>; + +prop error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.poisreq-d@pciexbus/pciexdev/pciexfn; + +prop error.io.pciex.anf-poisreq-d@pciexbus/pciexdev/pciexfn (0)-> + ereport.io.pci.dpe@pciexbus/pciexdev/pciexfn { IS_LEAF }, + ereport.io.pciex.tl.ptlp@pciexbus/pciexdev/pciexfn { IS_LEAF }; + prop error.io.pciex.poisreq-d@pciexrc/pciexbus/pciexdev/pciexfn (1)-> ereport.io.pci.sec-mdpe@pciexrc; @@ -912,9 +910,6 @@ prop error.io.pciex.poisreq-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.sec-mdpe@pciexbus/pciexdev/pciexfn { IS_SWU }; -prop error.io.pciex.poisreq-d@pciexbus/pciexdev/pciexfn (1)-> - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; - prop error.io.pciex.poisreq-d@pciexbus/pciexdev/pciexfn (2)-> ereport.io.pci.dpe@pciexbus/pciexdev/pciexfn { IS_SWU || IS_BDG }, ereport.io.pciex.tl.ptlp@pciexbus/pciexdev/pciexfn { IS_SWU || IS_BDG }; @@ -966,8 +961,12 @@ ereport.io.service.lost@pciexbus/pciexdev/pciexfn, ereport.io.service.degraded@pciexbus/pciexdev/pciexfn; +prop error.io.pciex.f-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; + prop error.io.pciex.flt-nf-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> - error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn; + error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn, + error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn; prop error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn/pciexbus<>/pciexdev<>/pciexfn<>; @@ -986,9 +985,20 @@ ereport.io.service.unaffected@pciexbus/pciexdev/pciexfn { IS_LEAF }, error.io.service.restored@pciexbus/pciexdev/pciexfn { IS_LEAF }; -prop error.io.pciex.poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.nf-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; +prop error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn/pciexbus<>/pciexdev<>/pciexfn<>; + +prop error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn (1)-> + error.io.pciex.poiscomp-d@pciexbus/pciexdev/pciexfn; + +prop error.io.pciex.anf-poiscomp-d@pciexbus/pciexdev/pciexfn (0)-> + ereport.io.pci.mdpe@pciexbus/pciexdev/pciexfn { IS_LEAF }, + ereport.io.pci.dpe@pciexbus/pciexdev/pciexfn { IS_LEAF }, + ereport.io.pciex.tl.ptlp@pciexbus/pciexdev/pciexfn { IS_LEAF }; + prop error.io.pciex.poiscomp-d@pciexbus/pciexdev/pciexfn (3)-> ereport.io.pci.mdpe@pciexbus/pciexdev/pciexfn { IS_BDG }, ereport.io.pci.dpe@pciexbus/pciexdev/pciexfn { IS_BDG }, @@ -1082,7 +1092,7 @@ ereport.io.service.unaffected@pciexbus/pciexdev/pciexfn { IS_LEAF }, error.io.service.restored@pciexbus/pciexdev/pciexfn { IS_LEAF }; -prop error.io.pciex.ecrcreq-d@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.ecrcreq-d@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.flt-nr-u@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; prop error.io.pciex.ecrcreq-d@pciexbus/pciexdev/pciexfn (1)-> @@ -1094,7 +1104,7 @@ prop error.io.pciex.ecrcreq-d@pciexbus/pciexdev/pciexfn (0)-> ereport.io.pciex.tl.ecrc@pciexbus/pciexdev/pciexfn { IS_SWU || IS_SWD }; -prop error.io.pciex.sw-ecrcreq-d@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.sw-ecrcreq-d@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.flt-nr-u@pciexbus/pciexdev/pciexfn { IS_SWU }; /* @@ -1189,10 +1199,8 @@ * - flt-poisreq-u is just on the pciex node which generated the fault (if the * fault was generated by a pciex node and not a child pci node). * - source-poisreq-u cascades down to at least one leaf device (pciex or pci), - * whose bdf must match the source-id in the payload of the ereport generated - * from the root complex. Note that pci.esc rules have to generate the - * source-poisreq-u so we limit it to the faulty node or nodes underneath the - * faulty node. + * whose bdf (if pciex) must match the source-id in the payload of the + * ereport generated from the root complex. * - poisreq-u cascades up to the root complex and any switch ports on * route will raise a ptlp ereport, while any upstream devices generating * or forwarding the poisoned packed will raise an mdpe ereport. The root @@ -1238,10 +1246,8 @@ error.io.pci.ta-drw-d@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn; prop error.io.pci.source-f-dpdata-w-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ptlp@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }, - ereport.io.pciex.tl.ur@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ptlp@pciexrc<> { PCIBDF_IS_UNDER_RC }, + ereport.io.pciex.tl.ur@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pci.source-f-dpdata-w-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.bdg.sec-ude@pciexbus/pciexdev/pciexfn { IS_BDG && @@ -1272,10 +1278,8 @@ error.io.pci.ta-drw-d@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn; prop error.io.pci.source-nf-dpdata-w-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ptlp@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }, - ereport.io.pciex.tl.ur@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ptlp@pciexrc<> { PCIBDF_IS_UNDER_RC }, + ereport.io.pciex.tl.ur@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pci.source-nf-dpdata-w-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.bdg.sec-ude@pciexbus/pciexdev/pciexfn { IS_BDG && @@ -1318,10 +1322,8 @@ * fault was generated by a pciex node and not a child pci node). There will * be a target-mdpe downstream from here. * - source-poiscomp-u cascades down to at least one leaf device (pciex or pci), - * whose bdf must match the source-id in the payload of the ereport generated - * from the root complex. Note that pci.esc rules have to generate the - * source-poiscomp-u so we limit it to the faulty node or nodes underneath - * the faulty node. + * whose bdf (if pciex) must match the source-id in the payload of the + * ereport generated from the root complex. * - poiscomp-u cascades up to the root complex and any switches on * route will raise ptlp and sec-mdpe ereports. The root complex will also * raise a sec-mdpe and ptlp. @@ -1346,8 +1348,7 @@ SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC }; prop error.io.pci.source-f-dpdata-r-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ptlp@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ptlp@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pci.source-f-dpdata-r-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.bdg.sec-ude@pciexbus/pciexdev/pciexfn { IS_BDG && @@ -1367,8 +1368,7 @@ SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC }; prop error.io.pci.source-nf-dpdata-r-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ptlp@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ptlp@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pci.source-nf-dpdata-r-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.bdg.sec-ude@pciexbus/pciexdev/pciexfn { IS_BDG && @@ -1402,12 +1402,12 @@ * * - flt-ecrcreq-u is just on the pciex node which generated the fault. * - source-ecrcreq-u cascades down to at least one leaf device (pciex or pci), - * whose bdf must match the source-id in the payload of the ereport generated - * from the root complex. + * whose bdf (if pciex) must match the source-id in the payload of the + * ereport generated from the root complex. * - ecrcreq-u cascades up to the root complex which must report it with an ecrc * ereport and any switches on route can optionally raise an ecrc ereport. * - * Additionally, as the root complex will just throw away the packet, we'll + * Additionally, as the root complex will just throw away the packet, we may * eventually get a cto - so use an nr-d at the pciex leaf or bridge to get * the appropriate behaviour. * @@ -1424,7 +1424,7 @@ ereport.io.service.lost@pciexbus/pciexdev/pciexfn { IS_LEAF }, ereport.io.service.degraded@pciexbus/pciexdev/pciexfn { IS_LEAF }; -prop error.io.pciex.source-f-ecrcreq-u@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.source-f-ecrcreq-u@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.nr-d@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; prop error.io.pciex.source-f-ecrcreq-u@pciexbus[b]/pciexdev[d]/pciexfn[f] (1)-> @@ -1435,19 +1435,14 @@ ereport.io.service.lost@pcibus/pcidev/pcifn { IS_PCI_LEAF }, ereport.io.service.degraded@pcibus/pcidev/pcifn { IS_PCI_LEAF }; -prop error.io.pciex.source-f-ecrcreq-u@pciexfn/pcibus[b]/pcidev[d]/pcifn[f] (1)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { BDF_IS_PCI_IMM_LEAF && - SOURCE_ID_MATCHES_BDF_OR_B && IMM_PCIBDF_IS_UNDER_RC }; - -prop error.io.pciex.source-f-ecrcreq-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; +prop error.io.pciex.source-f-ecrcreq-u@pcibus[b]/pcidev[d]/pcifn[f] (1)-> + ereport.io.pciex.tl.ecrc@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pciex.flt-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn (2)-> error.io.pciex.source-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn, error.io.pciex.ecrcreq-u@pciexbus/pciexdev/pciexfn; -prop error.io.pciex.source-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.source-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.nr-d@pciexbus/pciexdev/pciexfn { IS_LEAF || IS_BDG }; prop error.io.pciex.source-nf-ecrcreq-u@pciexbus/pciexdev/pciexfn (1)-> @@ -1462,13 +1457,8 @@ ereport.io.service.unaffected@pcibus/pcidev/pcifn { IS_PCI_LEAF }, error.io.service.restored@pcibus/pcidev/pcifn { IS_PCI_LEAF }; -prop error.io.pciex.source-nf-ecrcreq-u@pciexfn/pcibus[b]/pcidev[d]/pcifn[f] (1)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { BDF_IS_PCI_IMM_LEAF && - SOURCE_ID_MATCHES_BDF_OR_B && IMM_PCIBDF_IS_UNDER_RC }; - -prop error.io.pciex.source-nf-ecrcreq-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; +prop error.io.pciex.source-nf-ecrcreq-u@pcibus[b]/pcidev[d]/pcifn[f] (1)-> + ereport.io.pciex.tl.ecrc@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pciex.ecrcreq-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.ecrcreq-u@pciexbus/pciexdev/pciexfn; @@ -1481,8 +1471,8 @@ * * - flt-ecrccomp-u is just on the pciex node which generated the fault. * - source-ecrccomp-u cascades down to at least one leaf device (pciex or pci), - * whose bdf must match the source-id in the payload of the ereport generated - * from the root complex. + * whose bdf (if pciex) must match the source-id in the payload of the + * ereport generated from the root complex. * - ecrccomp-u cascades up to the root complex, which should report it with an * ecrc ereport and any switches on route can optionally raise an ecrc * ereport. @@ -1515,13 +1505,8 @@ ereport.io.service.lost@pcibus/pcidev/pcifn { IS_PCI_LEAF }, ereport.io.service.degraded@pcibus/pcidev/pcifn { IS_PCI_LEAF }; -prop error.io.pciex.source-f-ecrccomp-u@pciexfn/pcibus[b]/pcidev[d]/pcifn[f] (1)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { BDF_IS_PCI_IMM_LEAF && - SOURCE_ID_MATCHES_BDF_OR_B && IMM_PCIBDF_IS_UNDER_RC }; - -prop error.io.pciex.source-f-ecrccomp-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; +prop error.io.pciex.source-f-ecrccomp-u@pcibus[b]/pcidev[d]/pcifn[f] (1)-> + ereport.io.pciex.tl.ecrc@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pciex.flt-nf-ecrccomp-u@pciexbus/pciexdev/pciexfn (2)-> error.io.pciex.source-nf-ecrccomp-u@pciexbus/pciexdev/pciexfn, @@ -1542,13 +1527,8 @@ ereport.io.service.unaffected@pcibus/pcidev/pcifn { IS_PCI_LEAF }, error.io.service.restored@pcibus/pcidev/pcifn { IS_PCI_LEAF }; -prop error.io.pciex.source-nf-ecrccomp-u@pciexfn/pcibus[b]/pcidev[d]/pcifn[f] (1)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { BDF_IS_PCI_IMM_LEAF && - SOURCE_ID_MATCHES_BDF_OR_B && IMM_PCIBDF_IS_UNDER_RC }; - -prop error.io.pciex.source-nf-ecrccomp-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ecrc@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; +prop error.io.pciex.source-nf-ecrccomp-u@pcibus[b]/pcidev[d]/pcifn[f] (1)-> + ereport.io.pciex.tl.ecrc@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pciex.ecrccomp-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.ecrccomp-u@pciexbus/pciexdev/pciexfn; @@ -1635,19 +1615,15 @@ * upstream malformed tlp * * This will cascade upstream to the receiver which will report it as an mtlp. - * The source-id payload could be a pciexpress leaf or a pci leaf behind a - * bridge. Or it could be completely invalid - should we trust it? */ prop error.io.pciex.mtlp-u@pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.source-mtlp-u@pciexbus/pciexdev/pciexfn; prop error.io.pciex.source-mtlp-u@pciexbus[b]/pciexdev[d]/pciexfn[f] (1)-> - ereport.io.pciex.tl.mtlp@pciexrc<> { - BDF_IS_LEAF && SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC }; + ereport.io.pciex.tl.mtlp@pciexrc<> { BDF_IS_LEAF && BDF_IS_UNDER_RC }; -prop error.io.pciex.source-mtlp-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.mtlp@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; +prop error.io.pciex.source-mtlp-u@pcibus[b]/pcidev[d]/pcifn[f] (1)-> + ereport.io.pciex.tl.mtlp@pciexrc<> { PCIBDF_IS_UNDER_RC }; /* * downstream completer aborts @@ -1668,17 +1644,21 @@ * Note that there is no ur-d (we assume that a ur reported by the root complex * is always due to a badreq-u - see below). */ +prop error.io.pciex.flt-ca-d@pciexrc/pciexbus/pciexdev/pciexfn (0)-> + error.io.pciex.ca-d@pciexrc/pciexbus/pciexdev/pciexfn, + ereport.io.pciex.tl.ca@pciexrc; + prop error.io.pciex.ca-d@pciexrc/pciexbus/pciexdev/pciexfn (1)-> ereport.io.pci.sec-sta@pciexrc; -prop error.io.pciex.ca-d@pciexrc/pciexbus/pciexdev/pciexfn (0)-> - ereport.io.pciex.tl.ca@pciexrc; +prop error.io.pciex.flt-ca-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (0)-> + ereport.io.pci.sec-sta@pciexbus/pciexdev/pciexfn; prop error.io.pciex.flt-ca-d@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (2)-> - ereport.io.pci.sec-sta@pciexbus/pciexdev/pciexfn, - ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn; + ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn, + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn; -prop error.io.pciex.flt-ca-d@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.flt-ca-d@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.ca-d@pciexbus/pciexdev/pciexfn; prop error.io.pciex.ca-d@pciexbus/pciexdev/pciexfn (1)-> @@ -1697,7 +1677,7 @@ * responding, or of the root complex sending an invalid request (the latter * case is handled by badreq-d below). * - * This is reported as a ur by the completer, which sets the + * This is reported as a ur by the completer, which for non-posted reqs sets the * appropriate error bit in the completion message to the initiator which will * set the legacy pci bit sec-ma. * @@ -1710,7 +1690,7 @@ * we can identify the leaf device from the target-ma ereport if available or * from the source-id payload of the sec-rma ereport from the bridge. */ -prop error.io.pciex.flt-ur-u@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.flt-ur-u@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_SWU || IS_LEAF || IS_BDG }; @@ -1727,7 +1707,7 @@ prop error.io.pciex.ur-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.ur-u@pciexbus/pciexdev/pciexfn; -prop error.io.pciex.ur-u@pciexrc/pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.ur-u@pciexrc/pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.sec-ma@pciexrc; /* @@ -1737,9 +1717,9 @@ * reporting an internal error, or of the root complex sending an invalid * request (the latter case is handled by badreq-d below). * - * This is reported as a ca by the completer. The completer sends the - * appropriate error bits in the completion message to the initiator which will - * set the legacy pci bit sec-rta. + * This is reported as a ca by the completer. The completer (for non-posted + * requested) sends the appropriate error bits in the completion message to + * the initiator which will set the legacy pci bit sec-rta. * * The fault can always be recognized from the sec-rta bit at the root complex. * @@ -1760,7 +1740,7 @@ * from the target-rta ereport if available or from the source-id payload of * the sec-rta ereport from the bridge. */ -prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_SWU || IS_LEAF || IS_BDG }; @@ -1768,8 +1748,10 @@ ereport.io.pci.sta@pciexbus/pciexdev/pciexfn { IS_LEAF }, ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn { IS_LEAF }; -prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (2)-> - ereport.io.pci.sta@pciexbus/pciexdev/pciexfn { IS_SWU || IS_BDG }, +prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (0)-> + ereport.io.pci.sta@pciexbus/pciexdev/pciexfn { IS_SWU || IS_BDG }; + +prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (1)-> ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn { IS_SWU || IS_BDG }; prop error.io.pciex.flt-ca-u@pciexbus/pciexdev/pciexfn (2)-> @@ -1779,7 +1761,7 @@ prop error.io.pciex.ca-u@pciexbus/pciexdev/pciexfn/pciexbus/pciexdev/pciexfn (1)-> error.io.pciex.ca-u@pciexbus/pciexdev/pciexfn; -prop error.io.pciex.ca-u@pciexrc/pciexbus/pciexdev/pciexfn (1)-> +prop error.io.pciex.ca-u@pciexrc/pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.sec-rta@pciexrc; /* @@ -1789,10 +1771,9 @@ * way to the completer) may report ur or ca. If the switch detects the problem * first then the request doesn't get forwarded on to the completer. * - * These are reported as ur/ca ereports. The reporter then sends the appropriate - * error bits in the completion message to the initiator which will set the - * legacy pci bits ma or rta (oddly there is no equivalent in pcie error - * reporting). + * These are reported as ur/ca ereports. For non-posted requests, the reporter + * then sends the appropriate error bits in the completion message to the + * initiator which will set the legacy pci bits ma or rta. * * For badreq-u, the ca/ur ereports contain a source-id payload that identifies * the initiator. @@ -1824,16 +1805,12 @@ BDF_IS_LEAF && SOURCE_ID_MATCHES_BDF && BDF_IS_UNDER_RC}; prop error.io.pci.badreq-pw-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ur@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }, - ereport.io.pciex.tl.ca@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ur@pciexrc<> { PCIBDF_IS_UNDER_RC }, + ereport.io.pciex.tl.ca@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pci.badreq-drw-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> - ereport.io.pciex.tl.ur@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }, - ereport.io.pciex.tl.ca@pciexrc<> { - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_RC }; + ereport.io.pciex.tl.ur@pciexrc<> { PCIBDF_IS_UNDER_RC }, + ereport.io.pciex.tl.ca@pciexrc<> { PCIBDF_IS_UNDER_RC }; prop error.io.pciex.badreq-u@pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.sec-sta@pciexbus/pciexdev/pciexfn { IS_SWD }; @@ -1841,6 +1818,9 @@ prop error.io.pciex.badreq-u@pciexbus/pciexdev/pciexfn (0)-> error.io.pciex.badreq-u@pciexbus/pciexdev { IS_LEAF }; +prop error.io.pciex.badreq-u@pciexbus/pciexdev/pciexfn (0)-> + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn; + prop error.io.pciex.badreq-u@pciexbus[b]/pciexdev[d] (0)-> ereport.io.pciex.tl.ur@pciexfn { (confprop(asru(pciexfn), TOPO_PCI_EXCAP) == "pciexswd") && @@ -1853,15 +1833,15 @@ prop error.io.pci.badreq-pw-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.tl.ur@pciexbus/pciexdev/pciexfn { IS_SWD && - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_DEV }, + PCIBDF_IS_UNDER_DEV }, ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn { IS_SWD && - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_DEV }; + PCIBDF_IS_UNDER_DEV }; prop error.io.pci.badreq-drw-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> ereport.io.pciex.tl.ur@pciexbus/pciexdev/pciexfn { IS_SWD && - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_DEV }, + PCIBDF_IS_UNDER_DEV }, ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn { IS_SWD && - SOURCE_ID_MATCHES_BDF_OR_B && PCIBDF_IS_UNDER_DEV }; + PCIBDF_IS_UNDER_DEV }; prop error.io.pciex.flt-badreq-u@pciexbus/pciexdev/pciexfn (0)-> ereport.io.pci.ma@pciexbus/pciexdev/pciexfn { IS_LEAF }, @@ -1935,8 +1915,7 @@ prop upset.io.pciex.discard_uc@pciexbus/pciexdev/pciexfn (1)-> ereport.io.pciex.tl.uc@pciexbus/pciexdev/pciexfn { IS_BDG }; -prop upset.io.pciex.discard_uc@pciexbus/pciexdev/pciexfn (2)-> - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn { IS_LEAF }, +prop upset.io.pciex.discard_uc@pciexbus/pciexdev/pciexfn (1)-> ereport.io.pciex.tl.uc@pciexbus/pciexdev/pciexfn { IS_LEAF }; prop upset.io.pciex.discard@pciexbus/pciexdev/pciexfn (1)-> @@ -2064,7 +2043,6 @@ * is then represented as an unsupported request. */ prop error.io.pci.ma-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, ereport.io.pciex.tl.ur@pciexbus/pciexdev/pciexfn, error.io.pciex.ur-u@pciexbus/pciexdev/pciexfn; @@ -2081,7 +2059,6 @@ * then represented as a completer abort. */ prop error.io.pci.ta-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, ereport.io.pci.sta@pciexbus/pciexdev/pciexfn, ereport.io.pciex.tl.ca@pciexbus/pciexdev/pciexfn, error.io.pciex.ca-u@pciexbus/pciexdev/pciexfn; @@ -2124,47 +2101,35 @@ * If the bridge receives data with bad ecc/parity from pci/pci-x, it will * propagate onto pci express as a poisoned tlp */ -prop error.io.pci.dpdata-dr-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (4)-> +prop error.io.pci.dpdata-dr-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (3)-> ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn, - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, ereport.io.pci.sec-mdpe@pciexbus/pciexdev/pciexfn, error.io.pciex.poiscomp-u@pciexbus/pciexdev/pciexfn; prop error.io.pci.dpdata-dr-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> - error.io.pci.source-nf-dpdata-r-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn, - error.io.pci.source-f-dpdata-r-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn, - error.io.pciex.source-nf-poiscomp-u@pciexbus/pciexdev/pciexfn, - error.io.pciex.source-f-poiscomp-u@pciexbus/pciexdev/pciexfn, + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, ereport.io.pci.mdpe@pciexbus/pciexdev/pciexfn; -prop error.io.pci.dpdata-dw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (2)-> - ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn, - error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn; +prop error.io.pci.dpdata-dw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (1)-> + ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn; prop error.io.pci.dpdata-dw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> - error.io.pciex.poisreq-u@pciexbus/pciexdev/pciexfn; - -prop error.io.pci.dpdata-dw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> - error.io.pci.source-nf-dpdata-w-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn, - error.io.pci.source-f-dpdata-w-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn; - -prop error.io.pci.dpdata-pw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (3)-> - ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn, error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, error.io.pciex.poisreq-u@pciexbus/pciexdev/pciexfn; -prop error.io.pci.dpdata-pw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (1)-> - error.io.pci.source-nf-dpdata-w-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn, - error.io.pci.source-f-dpdata-w-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn; +prop error.io.pci.dpdata-pw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (2)-> + ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn, + error.io.pciex.poisreq-u@pciexbus/pciexdev/pciexfn; + +prop error.io.pci.dpdata-pw-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> + error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn; /* * If the bridge sees an address or attribute parity error it is considered * a fatal error. */ -prop error.io.pci.ape-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (4)-> +prop error.io.pci.ape-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (2)-> ereport.io.pci.sec-dpe@pciexbus/pciexdev/pciexfn, - ereport.io.pci.sec-rserr@pciexbus/pciexdev/pciexfn, - ereport.io.pciex.bdg.sec-serr@pciexbus/pciexdev/pciexfn, error.io.pciex.fatal@pciexbus/pciexdev/pciexfn; prop error.io.pci.source-ape-u@pcibus[b]/pcidev[d]/pcifn[f] (0)-> @@ -2174,6 +2139,8 @@ BDF_IS_PCI_LEAF && SOURCE_ID_MATCHES_BDF && PCIBDF_IS_UNDER_DEV }; prop error.io.pci.ape-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> + ereport.io.pci.sec-rserr@pciexbus/pciexdev/pciexfn, + ereport.io.pciex.bdg.sec-serr@pciexbus/pciexdev/pciexfn, ereport.io.pci.sec-sta@pciexbus/pciexdev/pciexfn; /* @@ -2217,10 +2184,12 @@ * Similarly a child device may have responded with a master abort or * target abort to one of our split competions. The hardware just logs these. */ -prop error.io.pcix.spl-comp-ma-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (4)-> +prop error.io.pcix.spl-comp-ma-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (3)-> error.io.pciex.nonfatal@pciexbus/pciexdev/pciexfn, ereport.io.pcix.sec-spl-dis@pciexbus/pciexdev/pciexfn, - ereport.io.pciex.bdg.sec-ma-sc@pciexbus/pciexdev/pciexfn, + ereport.io.pciex.bdg.sec-ma-sc@pciexbus/pciexdev/pciexfn; + +prop error.io.pcix.spl-comp-ma-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (0)-> ereport.io.pci.sec-ma@pciexbus/pciexdev/pciexfn; prop error.io.pcix.spl-comp-ta-u@pciexbus/pciexdev/pciexfn/pcibus/pcidev/pcifn (4)->
--- a/usr/src/cmd/fm/fmd/common/fmd_eventq.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/cmd/fm/fmd/common/fmd_eventq.c Wed Nov 22 13:57:56 2006 -0800 @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -21,7 +20,7 @@ */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -187,7 +186,10 @@ if (evt != FMD_EVT_CTL) fmd_eventqstat_dispatch(eq); - fmd_list_insert_after(&eq->eq_list, oqe, eqe); + if (oqe == NULL) + fmd_list_prepend(&eq->eq_list, eqe); + else + fmd_list_insert_after(&eq->eq_list, oqe, eqe); eq->eq_size++; }
--- a/usr/src/cmd/fm/modules/common/eversholt/eval.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/cmd/fm/modules/common/eversholt/eval.c Wed Nov 22 13:57:56 2006 -0800 @@ -1168,8 +1168,17 @@ case T_LIST: case T_AND: if (!eval_expr(np->u.expr.left, ex, epnames, globals, croot, - arrowp, try, valuep)) - return (0); + arrowp, try, valuep)) { + /* + * if lhs is unknown, still check rhs. If that + * is false we can return false irrespectice of lhs + */ + if (!eval_expr(np->u.expr.right, ex, epnames, globals, + croot, arrowp, try, valuep)) + return (0); + if (valuep->v != 0) + return (0); + } if (valuep->v == 0) { valuep->t = UINT64; return (1); @@ -1183,8 +1192,17 @@ case T_OR: if (!eval_expr(np->u.expr.left, ex, epnames, globals, croot, - arrowp, try, valuep)) - return (0); + arrowp, try, valuep)) { + /* + * if lhs is unknown, still check rhs. If that + * is true we can return true irrespectice of lhs + */ + if (!eval_expr(np->u.expr.right, ex, epnames, globals, + croot, arrowp, try, valuep)) + return (0); + if (valuep->v == 0) + return (0); + } if (valuep->v != 0) { valuep->t = UINT64; valuep->v = 1;
--- a/usr/src/uts/common/os/ddifm.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/os/ddifm.c Wed Nov 22 13:57:56 2006 -0800 @@ -824,7 +824,7 @@ if (handle == NULL) return; - if (version != DDI_FME_VER0) { + if (version != DDI_FME_VER0 && version != DDI_FME_VER1) { ddi_acc_hdl_t *hp = impl_acc_hdl_get(handle); i_ddi_drv_ereport_post(hp->ah_dip, DVR_EVER, NULL, DDI_NOSLEEP); @@ -847,7 +847,7 @@ if (handle == NULL) return; - if (version != DDI_FME_VER0) { + if (version != DDI_FME_VER0 && version != DDI_FME_VER1) { i_ddi_drv_ereport_post(((ddi_dma_impl_t *)handle)->dmai_rdip, DVR_EVER, NULL, DDI_NOSLEEP); cmn_err(CE_PANIC, "ddi_fm_dma_err_get: " @@ -870,7 +870,7 @@ if (handle == NULL) return; - if (version != DDI_FME_VER0) { + if (version != DDI_FME_VER0 && version != DDI_FME_VER1) { ddi_acc_hdl_t *hp = impl_acc_hdl_get(handle); i_ddi_drv_ereport_post(hp->ah_dip, DVR_EVER, NULL, DDI_NOSLEEP); @@ -892,7 +892,7 @@ if (handle == NULL) return; - if (version != DDI_FME_VER0) { + if (version != DDI_FME_VER0 && version != DDI_FME_VER1) { i_ddi_drv_ereport_post(((ddi_dma_impl_t *)handle)->dmai_rdip, DVR_EVER, NULL, DDI_NOSLEEP); cmn_err(CE_PANIC, "ddi_fm_dma_err_clear: "
--- a/usr/src/uts/common/os/ndifm.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/os/ndifm.c Wed Nov 22 13:57:56 2006 -0800 @@ -604,6 +604,57 @@ return (DDI_FM_UNKNOWN); } +int +ndi_fmc_entry_error_all(dev_info_t *dip, int flag, ddi_fm_error_t *derr) +{ + ndi_fmc_t *fcp = NULL; + ndi_fmcentry_t *fep; + struct i_ddi_fmhdl *fmhdl; + int nonfatal = 0; + + ASSERT(flag == DMA_HANDLE || flag == ACC_HANDLE); + + fmhdl = DEVI(dip)->devi_fmhdl; + ASSERT(fmhdl); + + if (flag == DMA_HANDLE && DDI_FM_DMA_ERR_CAP(fmhdl->fh_cap)) { + fcp = fmhdl->fh_dma_cache; + ASSERT(fcp); + } else if (flag == ACC_HANDLE && DDI_FM_ACC_ERR_CAP(fmhdl->fh_cap)) { + fcp = fmhdl->fh_acc_cache; + ASSERT(fcp); + } + + if (fcp != NULL) { + /* + * Check active resource entries + */ + mutex_enter(&fcp->fc_lock); + for (fep = fcp->fc_active->fce_next; fep != NULL; + fep = fep->fce_next) { + /* Set the error for this resource handle */ + nonfatal++; + if (flag == ACC_HANDLE) { + ddi_acc_handle_t ap = fep->fce_resource; + + i_ddi_fm_acc_err_set(ap, derr->fme_ena, + DDI_FM_NONFATAL, DDI_FM_ERR_UNEXPECTED); + ddi_fm_acc_err_get(ap, derr, DDI_FME_VERSION); + derr->fme_acc_handle = ap; + } else { + ddi_dma_handle_t dp = fep->fce_resource; + + i_ddi_fm_dma_err_set(dp, derr->fme_ena, + DDI_FM_NONFATAL, DDI_FM_ERR_UNEXPECTED); + ddi_fm_dma_err_get(dp, derr, DDI_FME_VERSION); + derr->fme_dma_handle = dp; + } + } + mutex_exit(&fcp->fc_lock); + } + return (nonfatal ? DDI_FM_NONFATAL : DDI_FM_UNKNOWN); +} + /* * Dispatch registered error handlers for dip. If tdip != NULL, only * the error handler (if available) for tdip is invoked. Otherwise,
--- a/usr/src/uts/common/os/pcifm.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/os/pcifm.c Wed Nov 22 13:57:56 2006 -0800 @@ -46,14 +46,17 @@ /* * Expected PCI Express error mask values */ -uint32_t pcie_expected_ce_mask = PCIE_AER_CE_AD_NFE; -uint32_t pcie_expected_ue_mask = 0x0; +uint32_t pcie_expected_ce_mask = 0x0; +uint32_t pcie_expected_ue_mask = PCIE_AER_UCE_UC; +#if defined(__sparc) uint32_t pcie_expected_sue_mask = 0x0; +#else +uint32_t pcie_expected_sue_mask = PCIE_AER_SUCE_RCVD_MA; +#endif +uint32_t pcie_aer_uce_log_bits = PCIE_AER_UCE_LOG_BITS; #if defined(__sparc) -uint32_t pcie_aer_uce_log_bits = PCIE_AER_UCE_LOG_BITS; uint32_t pcie_aer_suce_log_bits = PCIE_AER_SUCE_LOG_BITS; #else -uint32_t pcie_aer_uce_log_bits = PCIE_AER_UCE_LOG_BITS & ~PCIE_AER_UCE_UR; uint32_t pcie_aer_suce_log_bits = \ PCIE_AER_SUCE_LOG_BITS & ~PCIE_AER_SUCE_RCVD_MA; #endif @@ -74,9 +77,7 @@ PCI_DET_PERR, PCI_STAT_PERROR, NULL, DDI_FM_UNKNOWN, PCI_MDPE, PCI_STAT_S_PERROR, PCI_TARG_MDPE, DDI_FM_UNKNOWN, PCI_REC_SERR, PCI_STAT_S_SYSERR, NULL, DDI_FM_UNKNOWN, -#if !defined(__sparc) - PCI_MA, PCI_STAT_R_MAST_AB, PCI_TARG_MA, DDI_FM_OK, -#else +#if defined(__sparc) PCI_MA, PCI_STAT_R_MAST_AB, PCI_TARG_MA, DDI_FM_UNKNOWN, #endif PCI_REC_TA, PCI_STAT_R_TARG_AB, PCI_TARG_REC_TA, DDI_FM_UNKNOWN, @@ -105,11 +106,7 @@ PCIEX_UC, PCIE_AER_UCE_UC, NULL, DDI_FM_OK, PCIEX_ECRC, PCIE_AER_UCE_ECRC, NULL, DDI_FM_UNKNOWN, PCIEX_CA, PCIE_AER_UCE_CA, NULL, DDI_FM_UNKNOWN, -#if !defined(__sparc) - PCIEX_UR, PCIE_AER_UCE_UR, NULL, DDI_FM_OK, -#else PCIEX_UR, PCIE_AER_UCE_UR, NULL, DDI_FM_UNKNOWN, -#endif PCIEX_POIS, PCIE_AER_UCE_PTLP, NULL, DDI_FM_UNKNOWN, NULL, NULL, NULL, NULL, }; @@ -118,9 +115,7 @@ PCIEX_S_TA_SC, PCIE_AER_SUCE_TA_ON_SC, NULL, DDI_FM_UNKNOWN, PCIEX_S_MA_SC, PCIE_AER_SUCE_MA_ON_SC, NULL, DDI_FM_UNKNOWN, PCIEX_S_RTA, PCIE_AER_SUCE_RCVD_TA, NULL, DDI_FM_UNKNOWN, -#if !defined(__sparc) - PCIEX_S_RMA, PCIE_AER_SUCE_RCVD_MA, NULL, DDI_FM_OK, -#else +#if defined(__sparc) PCIEX_S_RMA, PCIE_AER_SUCE_RCVD_MA, NULL, DDI_FM_UNKNOWN, #endif PCIEX_S_USC, PCIE_AER_SUCE_USC_ERR, NULL, DDI_FM_UNKNOWN, @@ -159,7 +154,7 @@ }; static int -pci_config_check(ddi_acc_handle_t handle) +pci_config_check(ddi_acc_handle_t handle, int fme_flag) { ddi_acc_hdl_t *hp = impl_acc_hdl_get(handle); ddi_fm_error_t de; @@ -171,12 +166,14 @@ ddi_fm_acc_err_get(handle, &de, de.fme_version); if (de.fme_status != DDI_FM_OK) { - char buf[FM_MAX_CLASS]; + if (fme_flag == DDI_FM_ERR_UNEXPECTED) { + char buf[FM_MAX_CLASS]; - (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", PCI_ERROR_SUBCLASS, - PCI_NR); - ddi_fm_ereport_post(hp->ah_dip, buf, de.fme_ena, DDI_NOSLEEP, - FM_VERSION, DATA_TYPE_UINT8, 0, NULL); + (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", + PCI_ERROR_SUBCLASS, PCI_NR); + ddi_fm_ereport_post(hp->ah_dip, buf, de.fme_ena, + DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, NULL); + } ddi_fm_acc_err_clear(handle, de.fme_version); } return (de.fme_status); @@ -184,14 +181,14 @@ static void pcix_ecc_regs_gather(pci_erpt_t *erpt_p, pcix_ecc_regs_t *pcix_ecc_regs, - uint8_t pcix_cap_ptr) + uint8_t pcix_cap_ptr, int fme_flag) { int bdg = erpt_p->pe_dflags & PCI_BRIDGE_DEV; pcix_ecc_regs->pcix_ecc_ctlstat = pci_config_get32(erpt_p->pe_hdl, (pcix_cap_ptr + (bdg ? PCI_PCIX_BDG_ECC_STATUS : PCI_PCIX_ECC_STATUS))); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcix_ecc_regs->pcix_ecc_vflags |= PCIX_ERR_ECC_STS_VALID; else return; @@ -207,7 +204,7 @@ } static void -pcix_regs_gather(pci_erpt_t *erpt_p, void *pe_regs) +pcix_regs_gather(pci_erpt_t *erpt_p, void *pe_regs, int fme_flag) { if (erpt_p->pe_dflags & PCI_BRIDGE_DEV) { pcix_bdg_error_regs_t *pcix_bdg_regs = @@ -218,14 +215,14 @@ pcix_bdg_cap_ptr = pcix_bdg_regs->pcix_bdg_cap_ptr; pcix_bdg_regs->pcix_bdg_sec_stat = pci_config_get16( erpt_p->pe_hdl, (pcix_bdg_cap_ptr + PCI_PCIX_SEC_STATUS)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcix_bdg_regs->pcix_bdg_vflags |= PCIX_BDG_SEC_STATUS_VALID; else return; pcix_bdg_regs->pcix_bdg_stat = pci_config_get32(erpt_p->pe_hdl, (pcix_bdg_cap_ptr + PCI_PCIX_BDG_STATUS)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcix_bdg_regs->pcix_bdg_vflags |= PCIX_BDG_STATUS_VALID; else return; @@ -240,7 +237,7 @@ pcix_bdg_ecc_regs = pcix_bdg_regs->pcix_bdg_ecc_regs[1]; pcix_ecc_regs_gather(erpt_p, pcix_bdg_ecc_regs, - pcix_bdg_cap_ptr); + pcix_bdg_cap_ptr, fme_flag); } else { for (i = 0; i < 2; i++) { pcix_bdg_ecc_regs = @@ -250,7 +247,7 @@ PCI_PCIX_BDG_ECC_STATUS), i); pcix_ecc_regs_gather(erpt_p, pcix_bdg_ecc_regs, - pcix_bdg_cap_ptr); + pcix_bdg_cap_ptr, fme_flag); } } } @@ -264,7 +261,7 @@ (pcix_cap_ptr + PCI_PCIX_COMMAND)); pcix_regs->pcix_status = pci_config_get32(erpt_p->pe_hdl, (pcix_cap_ptr + PCI_PCIX_STATUS)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcix_regs->pcix_vflags |= PCIX_ERR_STATUS_VALID; else return; @@ -273,13 +270,13 @@ pcix_regs->pcix_ecc_regs; pcix_ecc_regs_gather(erpt_p, pcix_ecc_regs, - pcix_cap_ptr); + pcix_cap_ptr, fme_flag); } } } static void -pcie_regs_gather(pci_erpt_t *erpt_p) +pcie_regs_gather(pci_erpt_t *erpt_p, int fme_flag) { pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)erpt_p->pe_regs; uint8_t pcie_cap_ptr; @@ -290,17 +287,19 @@ pcie_regs->pcie_err_status = pci_config_get16(erpt_p->pe_hdl, pcie_cap_ptr + PCIE_DEVSTS); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_regs->pcie_vflags |= PCIE_ERR_STATUS_VALID; else return; pcie_regs->pcie_err_ctl = pci_config_get16(erpt_p->pe_hdl, (pcie_cap_ptr + PCIE_DEVCTL)); + pcie_regs->pcie_dev_cap = pci_config_get16(erpt_p->pe_hdl, + (pcie_cap_ptr + PCIE_DEVCAP)); if ((erpt_p->pe_dflags & PCI_BRIDGE_DEV) && (erpt_p->pe_dflags & PCIX_DEV)) - pcix_regs_gather(erpt_p, pcie_regs->pcix_bdg_regs); + pcix_regs_gather(erpt_p, pcie_regs->pcix_bdg_regs, fme_flag); if (erpt_p->pe_dflags & PCIEX_RC_DEV) { pcie_rc_error_regs_t *pcie_rc_regs = pcie_regs->pcie_rc_regs; @@ -320,7 +319,7 @@ pcie_adv_regs->pcie_ue_status = pci_config_get32(erpt_p->pe_hdl, pcie_ecap_ptr + PCIE_AER_UCE_STS); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_adv_regs->pcie_adv_vflags |= PCIE_UE_STATUS_VALID; pcie_adv_regs->pcie_ue_mask = pci_config_get32(erpt_p->pe_hdl, @@ -331,7 +330,7 @@ pcie_ecap_ptr + PCIE_AER_CTL); pcie_adv_regs->pcie_ue_hdr0 = pci_config_get32(erpt_p->pe_hdl, pcie_ecap_ptr + PCIE_AER_HDR_LOG); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) { + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) { int i; pcie_adv_regs->pcie_adv_vflags |= PCIE_UE_HDR_VALID; @@ -344,7 +343,7 @@ pcie_adv_regs->pcie_ce_status = pci_config_get32(erpt_p->pe_hdl, pcie_ecap_ptr + PCIE_AER_CE_STS); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_adv_regs->pcie_adv_vflags |= PCIE_CE_STATUS_VALID; pcie_adv_regs->pcie_ce_mask = pci_config_get32(erpt_p->pe_hdl, @@ -361,12 +360,15 @@ pcie_bdg_regs->pcie_sue_status = pci_config_get32(erpt_p->pe_hdl, pcie_ecap_ptr + PCIE_AER_SUCE_STS); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + pcie_bdg_regs->pcie_sue_mask = + pci_config_get32(erpt_p->pe_hdl, + pcie_ecap_ptr + PCIE_AER_SUCE_MASK); + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_adv_regs->pcie_adv_vflags |= PCIE_SUE_STATUS_VALID; pcie_bdg_regs->pcie_sue_hdr0 = pci_config_get32(erpt_p->pe_hdl, (pcie_ecap_ptr + PCIE_AER_SHDR_LOG)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) { + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) { int i; pcie_adv_regs->pcie_adv_vflags |= PCIE_SUE_HDR_VALID; @@ -392,7 +394,7 @@ pcie_rc_regs->pcie_rc_err_status = pci_config_get32(erpt_p->pe_hdl, (pcie_ecap_ptr + PCIE_AER_RE_STS)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_adv_regs->pcie_adv_vflags |= PCIE_RC_ERR_STATUS_VALID; pcie_rc_regs->pcie_rc_ce_src_id = @@ -401,14 +403,14 @@ pcie_rc_regs->pcie_rc_ue_src_id = pci_config_get16(erpt_p->pe_hdl, (pcie_ecap_ptr + PCIE_AER_ERR_SRC_ID)); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pcie_adv_regs->pcie_adv_vflags |= PCIE_SRC_ID_VALID; } } /*ARGSUSED*/ static void -pci_regs_gather(dev_info_t *dip, pci_erpt_t *erpt_p) +pci_regs_gather(dev_info_t *dip, pci_erpt_t *erpt_p, int fme_flag) { pci_error_regs_t *pci_regs = erpt_p->pe_pci_regs; @@ -418,12 +420,12 @@ */ pci_regs->pci_err_status = pci_config_get16(erpt_p->pe_hdl, PCI_CONF_STAT); - if (pci_config_check(erpt_p->pe_hdl) != DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) != DDI_FM_OK) return; pci_regs->pci_vflags |= PCI_ERR_STATUS_VALID; pci_regs->pci_cfg_comm = pci_config_get16(erpt_p->pe_hdl, PCI_CONF_COMM); - if (pci_config_check(erpt_p->pe_hdl) != DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) != DDI_FM_OK) return; /* @@ -432,12 +434,12 @@ if (erpt_p->pe_dflags & PCI_BRIDGE_DEV) { pci_regs->pci_bdg_regs->pci_bdg_sec_stat = pci_config_get16(erpt_p->pe_hdl, PCI_BCNF_SEC_STATUS); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pci_regs->pci_bdg_regs->pci_bdg_vflags |= PCI_BDG_SEC_STAT_VALID; pci_regs->pci_bdg_regs->pci_bdg_ctrl = pci_config_get16(erpt_p->pe_hdl, PCI_BCNF_BCNTRL); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, fme_flag) == DDI_FM_OK) pci_regs->pci_bdg_regs->pci_bdg_vflags |= PCI_BDG_CTRL_VALID; } @@ -448,9 +450,9 @@ * available. */ if (erpt_p->pe_dflags & PCIEX_DEV) - pcie_regs_gather(erpt_p); + pcie_regs_gather(erpt_p, fme_flag); else if (erpt_p->pe_dflags & PCIX_DEV) - pcix_regs_gather(erpt_p, erpt_p->pe_regs); + pcix_regs_gather(erpt_p, erpt_p->pe_regs, fme_flag); } @@ -703,7 +705,6 @@ { pcie_error_regs_t *pcie_regs; pcie_adv_error_regs_t *pcie_adv_regs; - char buf[FM_MAX_CLASS]; uint8_t pcix_cap_ptr; uint8_t pcie_cap_ptr; uint16_t pcie_ecap_ptr; @@ -724,7 +725,8 @@ uint16_t aer_ptr = 0; cap_ptr = pci_config_get8(erpt_p->pe_hdl, PCI_CONF_CAP_PTR); - if (pci_config_check(erpt_p->pe_hdl) == DDI_FM_OK) { + if (pci_config_check(erpt_p->pe_hdl, DDI_FM_ERR_UNEXPECTED) == + DDI_FM_OK) { while ((cap_id = pci_config_get8(erpt_p->pe_hdl, cap_ptr)) != 0xff) { if (cap_id == PCI_CAP_ID_PCIX) { @@ -749,7 +751,8 @@ } if ((cap_ptr = pci_config_get8(erpt_p->pe_hdl, cap_ptr + 1)) == 0xff || cap_ptr == 0 || - (pci_config_check(erpt_p->pe_hdl) != DDI_FM_OK)) + (pci_config_check(erpt_p->pe_hdl, + DDI_FM_ERR_UNEXPECTED) != DDI_FM_OK)) break; } } @@ -854,10 +857,6 @@ } if (!(erpt_p->pe_dflags & PCIEX_ADV_DEV)) { - (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", - PCIEX_ERROR_SUBCLASS, PCIEX_NADV); - ddi_fm_ereport_post(dip, buf, NULL, DDI_NOSLEEP, - FM_VERSION, DATA_TYPE_UINT8, 0, NULL); return; } @@ -889,7 +888,7 @@ * Check that mask values are as expected, if not * change them to what we desire. */ - pci_regs_gather(dip, erpt_p); + pci_regs_gather(dip, erpt_p, DDI_FM_ERR_UNEXPECTED); pcie_regs = (pcie_error_regs_t *)erpt_p->pe_regs; if (pcie_regs->pcie_adv_regs->pcie_ce_mask != pcie_expected_ce_mask) { pci_config_put32(erpt_p->pe_hdl, @@ -954,14 +953,16 @@ erpt_p->pe_pci_regs = kmem_zalloc(sizeof (pci_error_regs_t), KM_SLEEP); pci_status = pci_config_get16(erpt_p->pe_hdl, PCI_CONF_STAT); - if (pci_config_check(erpt_p->pe_hdl) != DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, DDI_FM_ERR_UNEXPECTED) != + DDI_FM_OK) goto error; /* * Get header type and record if device is a bridge. */ pci_hdr_type = pci_config_get8(erpt_p->pe_hdl, PCI_CONF_HEADER); - if (pci_config_check(erpt_p->pe_hdl) != DDI_FM_OK) + if (pci_config_check(erpt_p->pe_hdl, DDI_FM_ERR_UNEXPECTED) != + DDI_FM_OK) goto error; /* @@ -1000,7 +1001,7 @@ } done: - pci_regs_gather(dip, erpt_p); + pci_regs_gather(dip, erpt_p, DDI_FM_ERR_UNEXPECTED); pci_regs_clear(erpt_p); /* @@ -1128,24 +1129,6 @@ #endif } -/* - * Function used by PCI device and nexus error handlers to check if a - * captured address resides in their DMA or ACC handle caches or the caches of - * their children devices, respectively. - */ -static int -pci_dev_hdl_lookup(dev_info_t *dip, int type, ddi_fm_error_t *derr, - void *addr) -{ - struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; - pci_erpt_t *erpt_p = (pci_erpt_t *)fmhdl->fh_bus_specific; - - if (erpt_p->pe_dflags & PCI_BRIDGE_DEV) - return (ndi_fmc_error(dip, NULL, type, derr->fme_ena, addr)); - else - return (ndi_fmc_entry_error(dip, type, derr, addr)); -} - static void pcie_ereport_post(dev_info_t *dip, ddi_fm_error_t *derr, pci_erpt_t *erpt_p, char *buf, int errtype) @@ -1228,22 +1211,31 @@ } } +/*ARGSUSED*/ static void -pcie_check_addr(dev_info_t *dip, ddi_fm_error_t *derr, pci_erpt_t *eprt_p) +pcie_check_addr(dev_info_t *dip, ddi_fm_error_t *derr, pci_erpt_t *erpt_p) { - pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)eprt_p->pe_regs; + pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)erpt_p->pe_regs; pcie_adv_error_regs_t *pcie_adv_regs = pcie_regs->pcie_adv_regs; pcie_tlp_hdr_t *ue_hdr0; uint32_t *ue_hdr; uint64_t addr = NULL; + int upstream = 0; + pci_fme_bus_specific_t *pci_fme_bsp = + (pci_fme_bus_specific_t *)derr->fme_bus_specific; - if (!(pcie_adv_regs->pcie_adv_vflags & PCIE_UE_HDR_VALID)) { - derr->fme_status = DDI_FM_UNKNOWN; + if (!(pcie_adv_regs->pcie_adv_vflags & PCIE_UE_HDR_VALID)) return; - } + ue_hdr0 = (pcie_tlp_hdr_t *)&pcie_adv_regs->pcie_ue_hdr0; ue_hdr = pcie_adv_regs->pcie_ue_hdr; + if ((pcie_regs->pcie_cap & PCIE_PCIECAP_DEV_TYPE_MASK) == + PCIE_PCIECAP_DEV_TYPE_ROOT || + (pcie_regs->pcie_cap & PCIE_PCIECAP_DEV_TYPE_MASK) == + PCIE_PCIECAP_DEV_TYPE_DOWN) + upstream = 1; + switch (ue_hdr0->type) { case PCIE_TLP_TYPE_MEM: case PCIE_TLP_TYPE_MEMLK: @@ -1259,16 +1251,17 @@ addr = (uint32_t)memio32_tlp->addr0 << 2; pcie_adv_regs->pcie_adv_bdf = memio32_tlp->rid; } - - derr->fme_status = pci_dev_hdl_lookup(dip, DMA_HANDLE, derr, - (void *) &addr); - /* - * If DMA handle is not found error could have been a memory - * mapped IO address so check in the access cache - */ - if (derr->fme_status == DDI_FM_UNKNOWN) - derr->fme_status = pci_dev_hdl_lookup(dip, ACC_HANDLE, - derr, (void *) &addr); + if (upstream) { + pci_fme_bsp->pci_bs_bdf = pcie_adv_regs->pcie_adv_bdf; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + } else if ((pcie_regs->pcie_cap & PCIE_PCIECAP_DEV_TYPE_MASK) == + PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { + pci_fme_bsp->pci_bs_bdf = erpt_p->pe_bdf; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + } + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = upstream ? DMA_HANDLE : ACC_HANDLE; break; case PCIE_TLP_TYPE_IO: @@ -1277,8 +1270,15 @@ addr = (uint32_t)memio32_tlp->addr0 << 2; pcie_adv_regs->pcie_adv_bdf = memio32_tlp->rid; - derr->fme_status = pci_dev_hdl_lookup(dip, ACC_HANDLE, - derr, (void *) &addr); + if ((pcie_regs->pcie_cap & + PCIE_PCIECAP_DEV_TYPE_MASK) == + PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { + pci_fme_bsp->pci_bs_bdf = erpt_p->pe_bdf; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + } + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = ACC_HANDLE; break; } case PCIE_TLP_TYPE_CFG0: @@ -1287,7 +1287,10 @@ pcie_cfg_t *cfg_tlp = (pcie_cfg_t *)ue_hdr; pcie_adv_regs->pcie_adv_bdf = cfg_tlp->rid; - derr->fme_status = DDI_FM_UNKNOWN; + pci_fme_bsp->pci_bs_bdf = (uint16_t)cfg_tlp->bus << 8 | + (uint16_t)cfg_tlp->dev << 3 | cfg_tlp->func; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + pci_fme_bsp->pci_bs_type = ACC_HANDLE; break; } case PCIE_TLP_TYPE_MSG: @@ -1295,7 +1298,6 @@ pcie_msg_t *msg_tlp = (pcie_msg_t *)ue_hdr; pcie_adv_regs->pcie_adv_bdf = msg_tlp->rid; - derr->fme_status = DDI_FM_UNKNOWN; break; } case PCIE_TLP_TYPE_CPL: @@ -1304,30 +1306,28 @@ pcie_cpl_t *cpl_tlp = (pcie_cpl_t *)ue_hdr; pcie_adv_regs->pcie_adv_bdf = cpl_tlp->cid; - derr->fme_status = DDI_FM_UNKNOWN; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + if (upstream) { + pci_fme_bsp->pci_bs_bdf = cpl_tlp->cid; + pci_fme_bsp->pci_bs_type = ACC_HANDLE; + } else { + pci_fme_bsp->pci_bs_bdf = cpl_tlp->rid; + pci_fme_bsp->pci_bs_type = DMA_HANDLE; + } break; } case PCIE_TLP_TYPE_MSI: default: - derr->fme_status = DDI_FM_UNKNOWN; + break; } - - /* - * If no handle was found in the children caches and their is no - * address infomation already stored and we have a captured address - * then we need to store it away so that intermediate bridges can - * check if the address exists in their handle caches. - */ - if (derr->fme_status == DDI_FM_UNKNOWN && - derr->fme_bus_specific == NULL && - addr != NULL) - derr->fme_bus_specific = (void *)(uintptr_t)addr; } +/*ARGSUSED*/ static void -pcie_pci_check_addr(dev_info_t *dip, ddi_fm_error_t *derr, pci_erpt_t *eprt_p) +pcie_pci_check_addr(dev_info_t *dip, ddi_fm_error_t *derr, pci_erpt_t *erpt_p, + int type) { - pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)eprt_p->pe_regs; + pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)erpt_p->pe_regs; pcie_adv_error_regs_t *pcie_adv_regs = pcie_regs->pcie_adv_regs; pcie_adv_bdg_error_regs_t *pcie_bdg_regs = pcie_adv_regs->pcie_adv_bdg_regs; @@ -1335,27 +1335,29 @@ pcix_attr_t *pcie_pci_sue_attr; int cmd; int dual_addr = 0; + pci_fme_bus_specific_t *pci_fme_bsp = + (pci_fme_bus_specific_t *)derr->fme_bus_specific; - if (!(pcie_adv_regs->pcie_adv_vflags & PCIE_SUE_HDR_VALID)) { - derr->fme_status = DDI_FM_UNKNOWN; + if (!(pcie_adv_regs->pcie_adv_vflags & PCIE_SUE_HDR_VALID)) return; - } pcie_pci_sue_attr = (pcix_attr_t *)&pcie_bdg_regs->pcie_sue_hdr0; cmd = (pcie_bdg_regs->pcie_sue_hdr[0] >> PCIE_AER_SUCE_HDR_CMD_LWR_SHIFT) & PCIE_AER_SUCE_HDR_CMD_LWR_MASK; + cmd_switch: + addr = pcie_bdg_regs->pcie_sue_hdr[2]; + addr = (addr << PCIE_AER_SUCE_HDR_ADDR_SHIFT) | + pcie_bdg_regs->pcie_sue_hdr[1]; switch (cmd) { case PCI_PCIX_CMD_IORD: case PCI_PCIX_CMD_IOWR: pcie_adv_regs->pcie_adv_bdf = pcie_pci_sue_attr->rid; - - addr = pcie_bdg_regs->pcie_sue_hdr[2]; - addr = (addr << PCIE_AER_SUCE_HDR_ADDR_SHIFT) | - pcie_bdg_regs->pcie_sue_hdr[1]; - - derr->fme_status = pci_dev_hdl_lookup(dip, ACC_HANDLE, - derr, (void *) &addr); + if (addr) { + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = ACC_HANDLE; + } break; case PCI_PCIX_CMD_MEMRD_DW: case PCI_PCIX_CMD_MEMWR: @@ -1364,22 +1366,31 @@ case PCI_PCIX_CMD_MEMRDBL: case PCI_PCIX_CMD_MEMWRBL: pcie_adv_regs->pcie_adv_bdf = pcie_pci_sue_attr->rid; - - addr = pcie_bdg_regs->pcie_sue_hdr[2]; - addr = (addr << PCIE_AER_SUCE_HDR_ADDR_SHIFT) | - pcie_bdg_regs->pcie_sue_hdr[1]; - - derr->fme_status = pci_dev_hdl_lookup(dip, DMA_HANDLE, - derr, (void *) &addr); - if (derr->fme_status == DDI_FM_UNKNOWN) - derr->fme_status = pci_dev_hdl_lookup(dip, ACC_HANDLE, - derr, (void *) &addr); + if (addr) { + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = type; + } break; case PCI_PCIX_CMD_CFRD: case PCI_PCIX_CMD_CFWR: pcie_adv_regs->pcie_adv_bdf = pcie_pci_sue_attr->rid; - - derr->fme_status = DDI_FM_UNKNOWN; + /* + * for type 1 config transaction we can find bdf from address + */ + if ((addr & 3) == 1) { + pci_fme_bsp->pci_bs_bdf = (addr >> 8) & 0xffffffff; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + pci_fme_bsp->pci_bs_type = ACC_HANDLE; + } + break; + case PCI_PCIX_CMD_SPL: + pcie_adv_regs->pcie_adv_bdf = pcie_pci_sue_attr->rid; + if (type == ACC_HANDLE) { + pci_fme_bsp->pci_bs_bdf = pcie_adv_regs->pcie_adv_bdf; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + pci_fme_bsp->pci_bs_type = type; + } break; case PCI_PCIX_CMD_DADR: cmd = (pcie_bdg_regs->pcie_sue_hdr[0] >> @@ -1390,27 +1401,19 @@ ++dual_addr; goto cmd_switch; default: - derr->fme_status = DDI_FM_UNKNOWN; + break; } - - /* - * If no handle was found in the children caches and their is no - * address infomation already stored and we have a captured address - * then we need to store it away so that intermediate bridges can - * check if the address exists in their handle caches. - */ - if (derr->fme_status == DDI_FM_UNKNOWN && - derr->fme_bus_specific == NULL && - addr != NULL) - derr->fme_bus_specific = (void *)(uintptr_t)addr; } +/*ARGSUSED*/ static int pcix_check_addr(dev_info_t *dip, ddi_fm_error_t *derr, - pcix_ecc_regs_t *pcix_ecc_regs) + pcix_ecc_regs_t *pcix_ecc_regs, int type) { int cmd = (pcix_ecc_regs->pcix_ecc_ctlstat >> 16) & 0xf; uint64_t addr; + pci_fme_bus_specific_t *pci_fme_bsp = + (pci_fme_bus_specific_t *)derr->fme_bus_specific; addr = pcix_ecc_regs->pcix_ecc_secaddr; addr = addr << 32; @@ -1422,27 +1425,40 @@ return (DDI_FM_FATAL); case PCI_PCIX_CMD_IORD: case PCI_PCIX_CMD_IOWR: - return (pci_dev_hdl_lookup(dip, ACC_HANDLE, derr, - (void *) &addr)); + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = type; + return (DDI_FM_UNKNOWN); case PCI_PCIX_CMD_DEVID: return (DDI_FM_FATAL); case PCI_PCIX_CMD_MEMRD_DW: case PCI_PCIX_CMD_MEMWR: case PCI_PCIX_CMD_MEMRD_BL: case PCI_PCIX_CMD_MEMWR_BL: - return (pci_dev_hdl_lookup(dip, DMA_HANDLE, derr, - (void *) &addr)); + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = type; + return (DDI_FM_UNKNOWN); case PCI_PCIX_CMD_CFRD: case PCI_PCIX_CMD_CFWR: - return (pci_dev_hdl_lookup(dip, ACC_HANDLE, derr, - (void *) &addr)); + /* + * for type 1 config transaction we can find bdf from address + */ + if ((addr & 3) == 1) { + pci_fme_bsp->pci_bs_bdf = (addr >> 8) & 0xffffffff; + pci_fme_bsp->pci_bs_flags |= PCI_BS_BDF_VALID; + pci_fme_bsp->pci_bs_type = type; + } + return (DDI_FM_UNKNOWN); case PCI_PCIX_CMD_SPL: case PCI_PCIX_CMD_DADR: - return (DDI_FM_FATAL); + return (DDI_FM_UNKNOWN); case PCI_PCIX_CMD_MEMRDBL: case PCI_PCIX_CMD_MEMWRBL: - return (pci_dev_hdl_lookup(dip, DMA_HANDLE, derr, - (void *) &addr)); + pci_fme_bsp->pci_bs_addr = addr; + pci_fme_bsp->pci_bs_flags |= PCI_BS_ADDR_VALID; + pci_fme_bsp->pci_bs_type = type; + return (DDI_FM_UNKNOWN); default: return (DDI_FM_FATAL); } @@ -1460,6 +1476,8 @@ int ret = DDI_FM_OK; char buf[FM_MAX_CLASS]; int i; + pci_fme_bus_specific_t *pci_fme_bsp = + (pci_fme_bus_specific_t *)derr->fme_bus_specific; if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) goto done; @@ -1490,12 +1508,14 @@ DATA_TYPE_UINT16, pci_bdg_regs->pci_bdg_ctrl, NULL); PCI_FM_SEV_INC(pci_bdg_err_tbl[i].flags); - if (derr->fme_bus_specific && + if (pci_fme_bsp && (pci_fme_bsp->pci_bs_flags & + PCI_BS_ADDR_VALID) && + pci_fme_bsp->pci_bs_type == ACC_HANDLE && pci_bdg_err_tbl[i].terr_class) pci_target_enqueue(derr->fme_ena, pci_bdg_err_tbl[i].terr_class, PCI_ERROR_SUBCLASS, - (uintptr_t)derr->fme_bus_specific); + pci_fme_bsp->pci_bs_addr); } } #if !defined(__sparc) @@ -1519,12 +1539,18 @@ !(pcie_regs->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED)) nonfatal++; + (void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", + PCI_ERROR_SUBCLASS, PCI_SEC_ERROR_SUBCLASS, PCI_MA); + ddi_fm_ereport_post(dip, buf, derr->fme_ena, + DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, + PCI_SEC_CONFIG_STATUS, DATA_TYPE_UINT16, + pci_bdg_regs->pci_bdg_sec_stat, PCI_BCNTRL, + DATA_TYPE_UINT16, pci_bdg_regs->pci_bdg_ctrl, NULL); } #endif } done: - /* * Need to check for poke and cautious put. We already know peek * and cautious get errors occurred (as we got a trap) and we know @@ -1539,15 +1565,6 @@ if (pci_bdg_regs->pci_bdg_sec_stat & (PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | PCI_STAT_S_PERROR | PCI_STAT_S_SYSERR)) nonfatal++; - - /* - * for cautious accesses we already have the acc_handle. Just - * need to call children to clear their error bits - */ - ret = ndi_fm_handler_dispatch(dip, NULL, derr); - PCI_FM_SEV_INC(ret); - return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : - (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); } if (derr->fme_flag == DDI_FM_ERR_POKE) { /* @@ -1566,29 +1583,10 @@ } /* - * If errant address is passed in then attempt to find - * ACC/DMA handle in caches. + * now check children below the bridge */ - if (derr->fme_bus_specific) { - int i; - - for (i = 0; i < 2; i++) { - ret = ndi_fmc_error(dip, NULL, i ? ACC_HANDLE : - DMA_HANDLE, derr->fme_ena, - (void *)&derr->fme_bus_specific); - PCI_FM_SEV_INC(ret); - } - } - - /* - * now check children below the bridge, only if errant handle was not - * found - */ - if (!derr->fme_acc_handle && !derr->fme_dma_handle) { - ret = ndi_fm_handler_dispatch(dip, NULL, derr); - PCI_FM_SEV_INC(ret); - } - + ret = ndi_fm_handler_dispatch(dip, NULL, derr); + PCI_FM_SEV_INC(ret); return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); } @@ -1660,9 +1658,28 @@ case PCI_PCIX_ECC_PHASE_DATA64: if (ecc_corr) ret = DDI_FM_OK; - else + else { + int type; + pci_error_regs_t *pci_regs = + erpt_p->pe_pci_regs; + + if (i) { + if (pci_regs->pci_bdg_regs-> + pci_bdg_sec_stat & + PCI_STAT_S_PERROR) + type = ACC_HANDLE; + else + type = DMA_HANDLE; + } else { + if (pci_regs->pci_err_status & + PCI_STAT_S_PERROR) + type = DMA_HANDLE; + else + type = ACC_HANDLE; + } ret = pcix_check_addr(dip, derr, - pcix_ecc_regs); + pcix_ecc_regs, type); + } PCI_FM_SEV_INC(ret); (void) snprintf(buf, FM_MAX_CLASS, @@ -1916,6 +1933,7 @@ int nonfatal = 0; int unknown = 0; int ok = 0; + int type; char buf[FM_MAX_CLASS]; int i; pcie_error_regs_t *pcie_regs = (pcie_error_regs_t *)erpt_p->pe_regs; @@ -1932,6 +1950,18 @@ if (!(erpt_p->pe_dflags & PCIEX_ADV_DEV)) { if (!(pcie_regs->pcie_vflags & PCIE_ERR_STATUS_VALID)) goto done; +#if !defined(__sparc) + /* + * On x86 ignore UR on non-RBER leaf devices and pciex-pci + * bridges. + */ + if ((pcie_regs->pcie_err_status & PCIE_DEVSTS_UR_DETECTED) && + !(pcie_regs->pcie_err_status & PCIE_DEVSTS_FE_DETECTED) && + ((erpt_p->pe_dflags & PCIEX_2PCI_DEV) || + !(erpt_p->pe_dflags & PCI_BRIDGE_DEV)) && + !(pcie_regs->pcie_dev_cap & PCIE_DEVCAP_ROLE_BASED_ERR_REP)) + goto done; +#endif for (i = 0; pciex_nadv_err_tbl[i].err_class != NULL; i++) { if (!(pcie_regs->pcie_err_status & pciex_nadv_err_tbl[i].reg_bit)) @@ -1962,27 +1992,64 @@ "%s.%s", PCIEX_ERROR_SUBCLASS, pciex_ue_err_tbl[i].err_class); - pcie_adv_regs->pcie_adv_bdf = 0; - if ((pcie_adv_regs->pcie_ue_status & - pcie_aer_uce_log_bits) != - pciex_ue_err_tbl[i].reg_bit) { - PCI_FM_SEV_INC(pciex_ue_err_tbl[i].flags); + /* + * First check for advisary nonfatal conditions + * - hardware endpoint successfully retrying a cto + * - hardware endpoint receiving poisoned tlp and + * dealing with it itself (but not if root complex) + * If the device has declared these as correctable + * errors then treat them as such. + */ + if ((pciex_ue_err_tbl[i].reg_bit == PCIE_AER_UCE_TO || + (pciex_ue_err_tbl[i].reg_bit == PCIE_AER_UCE_PTLP && + !(erpt_p->pe_dflags & PCIEX_RC_DEV))) && + (pcie_regs->pcie_err_status & + PCIE_DEVSTS_CE_DETECTED) && + !(pcie_regs->pcie_err_status & + PCIE_DEVSTS_NFE_DETECTED)) { pcie_ereport_post(dip, derr, erpt_p, buf, PCIEX_TYPE_UE); - } else { + continue; + } + +#if !defined(__sparc) + /* + * On x86 for leaf devices and pciex-pci bridges, + * ignore UR on non-RBER devices or on RBER devices when + * advisory nonfatal. + */ + if (pciex_ue_err_tbl[i].reg_bit == PCIE_AER_UCE_UR && + ((erpt_p->pe_dflags & PCIEX_2PCI_DEV) || + !(erpt_p->pe_dflags & PCI_BRIDGE_DEV))) { + if (!(pcie_regs->pcie_dev_cap & + PCIE_DEVCAP_ROLE_BASED_ERR_REP)) + continue; + if ((pcie_regs->pcie_err_status & + PCIE_DEVSTS_CE_DETECTED) && + !(pcie_regs->pcie_err_status & + PCIE_DEVSTS_NFE_DETECTED)) + continue; + } +#endif + pcie_adv_regs->pcie_adv_bdf = 0; + /* + * Now try and look up handle if + * - error bit is among PCIE_AER_UCE_LOG_BITS, and + * - no other PCIE_AER_UCE_LOG_BITS are set, and + * - error bit is not masked, and + * - flag is DDI_FM_UNKNOWN + */ + if ((pcie_adv_regs->pcie_ue_status & + pcie_aer_uce_log_bits) == + pciex_ue_err_tbl[i].reg_bit && + !(pciex_ue_err_tbl[i].reg_bit & + pcie_adv_regs->pcie_ue_mask) && + pciex_ue_err_tbl[i].flags == DDI_FM_UNKNOWN) pcie_check_addr(dip, derr, erpt_p); - /* - * fatal/ok errors are fatal/ok - * regardless of if we find a handle - */ - if (pciex_ue_err_tbl[i].flags == DDI_FM_FATAL) - derr->fme_status = DDI_FM_FATAL; - else if (pciex_ue_err_tbl[i].flags == DDI_FM_OK) - derr->fme_status = DDI_FM_OK; - pcie_ereport_post(dip, derr, erpt_p, buf, - PCIEX_TYPE_UE); - PCI_FM_SEV_INC(derr->fme_status); - } + + PCI_FM_SEV_INC(pciex_ue_err_tbl[i].flags); + pcie_ereport_post(dip, derr, erpt_p, buf, + PCIEX_TYPE_UE); } } @@ -2027,8 +2094,8 @@ if ((pcie_bdg_regs->pcie_sue_status & pcie_aer_suce_log_bits) != - pcie_sue_err_tbl[i].reg_bit) { - PCI_FM_SEV_INC(pcie_sue_err_tbl[i].flags); + pcie_sue_err_tbl[i].reg_bit || + pcie_sue_err_tbl[i].flags != DDI_FM_UNKNOWN) { ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, PCIEX_SEC_UE_STATUS, DATA_TYPE_UINT32, @@ -2046,17 +2113,27 @@ NULL); } else { pcie_adv_regs->pcie_adv_bdf = 0; - pcie_pci_check_addr(dip, derr, erpt_p); - /* - * fatal/nonfatal errors are fatal/nonfatal - * regardless of if we find a handle - */ - if (pcie_sue_err_tbl[i].flags == DDI_FM_FATAL) - derr->fme_status = DDI_FM_FATAL; - else if (pcie_sue_err_tbl[i].flags == - DDI_FM_NONFATAL) - derr->fme_status = DDI_FM_NONFATAL; - + switch (pcie_sue_err_tbl[i].reg_bit) { + case PCIE_AER_SUCE_RCVD_TA: + case PCIE_AER_SUCE_RCVD_MA: + case PCIE_AER_SUCE_USC_ERR: + type = ACC_HANDLE; + break; + case PCIE_AER_SUCE_TA_ON_SC: + case PCIE_AER_SUCE_MA_ON_SC: + type = DMA_HANDLE; + break; + case PCIE_AER_SUCE_UC_DATA_ERR: + case PCIE_AER_SUCE_PERR_ASSERT: + if (erpt_p->pe_pci_regs->pci_bdg_regs-> + pci_bdg_sec_stat & + PCI_STAT_S_PERROR) + type = ACC_HANDLE; + else + type = DMA_HANDLE; + break; + } + pcie_pci_check_addr(dip, derr, erpt_p, type); ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, PCIEX_SEC_UE_STATUS, DATA_TYPE_UINT32, @@ -2077,8 +2154,8 @@ pcie_bdg_regs->pcie_sue_hdr[2], #endif NULL); - PCI_FM_SEV_INC(derr->fme_status); } + PCI_FM_SEV_INC(pcie_sue_err_tbl[i].flags); } } done: @@ -2150,6 +2227,34 @@ PCI_FM_SEV_INC(ret); } + if (derr->fme_flag == DDI_FM_ERR_UNEXPECTED) { + pci_fme_bus_specific_t *pci_fme_bsp; + int ret = DDI_FM_UNKNOWN; + + pci_fme_bsp = (pci_fme_bus_specific_t *)derr->fme_bus_specific; + if (pci_fme_bsp->pci_bs_flags & PCI_BS_ADDR_VALID) { + ret = ndi_fmc_entry_error(dip, + pci_fme_bsp->pci_bs_type, derr, + (void *)&pci_fme_bsp->pci_bs_addr); + PCI_FM_SEV_INC(ret); + } + /* + * If we didn't find the handle using an addr, try using bdf. + * Note we don't do this where the bdf is for a + * device behind a pciex/pci bridge as the bridge may have + * fabricated the bdf. + */ + if (ret == DDI_FM_UNKNOWN && + (pci_fme_bsp->pci_bs_flags & PCI_BS_BDF_VALID) && + pci_fme_bsp->pci_bs_bdf == erpt_p->pe_bdf && + (erpt_p->pe_dflags & PCIEX_DEV) && + !(erpt_p->pe_dflags & PCIEX_2PCI_DEV)) { + ret = ndi_fmc_entry_error_all(dip, + pci_fme_bsp->pci_bs_type, derr); + PCI_FM_SEV_INC(ret); + } + } + derr->fme_status = (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); } @@ -2159,6 +2264,8 @@ { struct i_ddi_fmhdl *fmhdl; pci_erpt_t *erpt_p; + ddi_fm_error_t de; + pci_fme_bus_specific_t pci_fme_bs; fmhdl = DEVI(dip)->devi_fmhdl; if (!DDI_FM_EREPORT_CAP(ddi_fm_capable(dip)) && @@ -2167,19 +2274,56 @@ return; } + /* + * copy in the ddi_fm_error_t structure in case it's VER0 + */ + de.fme_version = derr->fme_version; + de.fme_status = derr->fme_status; + de.fme_flag = derr->fme_flag; + de.fme_ena = derr->fme_ena; + de.fme_acc_handle = derr->fme_acc_handle; + de.fme_dma_handle = derr->fme_dma_handle; + de.fme_bus_specific = derr->fme_bus_specific; + if (derr->fme_version >= DDI_FME_VER1) + de.fme_bus_type = derr->fme_bus_type; + else + de.fme_bus_type = DDI_FME_BUS_TYPE_DFLT; + if (de.fme_bus_type == DDI_FME_BUS_TYPE_DFLT) { + /* + * if this is the first pci device we've found convert + * fme_bus_specific to DDI_FME_BUS_TYPE_PCI + */ + bzero(&pci_fme_bs, sizeof (pci_fme_bs)); + if (de.fme_bus_specific) { + /* + * the cpu passed us an addr - this can be used to look + * up an access handle + */ + pci_fme_bs.pci_bs_addr = (uintptr_t)de.fme_bus_specific; + pci_fme_bs.pci_bs_type = ACC_HANDLE; + pci_fme_bs.pci_bs_flags |= PCI_BS_ADDR_VALID; + } + de.fme_bus_specific = (void *)&pci_fme_bs; + de.fme_bus_type = DDI_FME_BUS_TYPE_PCI; + } + ASSERT(fmhdl); - if (derr->fme_ena == NULL) - derr->fme_ena = fm_ena_generate(0, FM_ENA_FMT1); + if (de.fme_ena == NULL) + de.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); erpt_p = (pci_erpt_t *)fmhdl->fh_bus_specific; if (erpt_p == NULL) return; - pci_regs_gather(dip, erpt_p); - pci_error_report(dip, derr, erpt_p); + pci_regs_gather(dip, erpt_p, de.fme_flag); + pci_error_report(dip, &de, erpt_p); pci_regs_clear(erpt_p); + derr->fme_status = de.fme_status; + derr->fme_ena = de.fme_ena; + derr->fme_acc_handle = de.fme_acc_handle; + derr->fme_dma_handle = de.fme_dma_handle; if (xx_status != NULL) *xx_status = erpt_p->pe_pci_regs->pci_err_status; }
--- a/usr/src/uts/common/sys/ddifm.h Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/sys/ddifm.h Wed Nov 22 13:57:56 2006 -0800 @@ -73,10 +73,15 @@ ddi_acc_handle_t fme_acc_handle; /* optional acc handle */ ddi_dma_handle_t fme_dma_handle; /* optional dma handle */ void *fme_bus_specific; /* optional bus specific err */ + int fme_bus_type; /* optional bus type */ } ddi_fm_error_t; #define DDI_FME_VER0 0 -#define DDI_FME_VERSION DDI_FME_VER0 +#define DDI_FME_VER1 1 +#define DDI_FME_VERSION DDI_FME_VER1 + +#define DDI_FME_BUS_TYPE_DFLT 0 /* bus type = default */ +#define DDI_FME_BUS_TYPE_PCI 1 /* bus type = pci/pcix/pcie */ typedef int (*ddi_err_func_t)(dev_info_t *, ddi_fm_error_t *, const void *);
--- a/usr/src/uts/common/sys/ndifm.h Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/sys/ndifm.h Wed Nov 22 13:57:56 2006 -0800 @@ -68,6 +68,7 @@ const void *); extern int ndi_fmc_entry_error(dev_info_t *, int, ddi_fm_error_t *, const void *); +extern int ndi_fmc_entry_error_all(dev_info_t *, int, ddi_fm_error_t *); extern int ndi_fm_handler_dispatch(dev_info_t *, dev_info_t *, const ddi_fm_error_t *);
--- a/usr/src/uts/common/sys/pcifm.h Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/common/sys/pcifm.h Wed Nov 22 13:57:56 2006 -0800 @@ -170,12 +170,27 @@ uint16_t pcie_cap; /* PCI Express capability register */ uint16_t pcie_err_status; /* pcie device status register */ uint16_t pcie_err_ctl; /* pcie error control register */ + uint16_t pcie_dev_cap; /* pcie device capabilities register */ pcix_bdg_error_regs_t *pcix_bdg_regs; /* pcix bridge regs */ pcie_rc_error_regs_t *pcie_rc_regs; /* pcie root complex regs */ pcie_adv_error_regs_t *pcie_adv_regs; /* pcie advanced err regs */ } pcie_error_regs_t; /* + * pcie bus specific structure + */ + +typedef struct pci_fme_bus_specific { + int pci_bs_type; + uint64_t pci_bs_addr; + uint16_t pci_bs_bdf; + int pci_bs_flags; +} pci_fme_bus_specific_t; + +#define PCI_BS_ADDR_VALID 1 +#define PCI_BS_BDF_VALID 2 + +/* * target error queue defines */ #define TARGET_MAX_ERRS 6
--- a/usr/src/uts/i86pc/io/pciex/pcie_error.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/i86pc/io/pciex/pcie_error.c Wed Nov 22 13:57:56 2006 -0800 @@ -91,8 +91,8 @@ * Can be defined to mask off certain types of AER errors * By default all are set to 0; as no errors are masked */ -uint32_t pcie_aer_uce_mask = 0; -uint32_t pcie_aer_ce_mask = PCIE_AER_CE_AD_NFE; +uint32_t pcie_aer_uce_mask = PCIE_AER_UCE_UC; +uint32_t pcie_aer_ce_mask = 0; uint32_t pcie_aer_suce_mask = PCIE_AER_SUCE_RCVD_MA; /* @@ -226,8 +226,7 @@ status_reg = pci_config_get16(cfg_hdl, PCI_CONF_STAT); pci_config_put16(cfg_hdl, PCI_CONF_STAT, status_reg); command_reg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); - if (pcie_serr_disable_flag && cap_ptr != PCI_CAP_NEXT_PTR_NULL && - dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) { + if (pcie_serr_disable_flag && cap_ptr != PCI_CAP_NEXT_PTR_NULL) { pcie_command_default &= ~PCI_COMM_SERR_ENABLE; /* shouldn't happen; just in case */ if (command_reg & PCI_COMM_SERR_ENABLE) @@ -293,9 +292,10 @@ device_ctl |= pcie_device_ctrl_default; /* - * Disable UR for any non-RBER enabled leaf PCIe device + * Disable UR for any non-RBER enabled leaf PCIe device or bridge */ - if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && + if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV || + dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) && ((pci_config_get16(cfg_hdl, cap_ptr + PCIE_DEVCAP) & PCIE_DEVCAP_ROLE_BASED_ERR_REP) != PCIE_DEVCAP_ROLE_BASED_ERR_REP))
--- a/usr/src/uts/i86pc/io/pciex/pcie_pci.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/i86pc/io/pciex/pcie_pci.c Wed Nov 22 13:57:56 2006 -0800 @@ -1145,6 +1145,7 @@ ddi_fm_error_t derr; bzero(&derr, sizeof (ddi_fm_error_t)); + derr.fme_version = DDI_FME_VERSION; if (!(pepb_p->soft_state & PEPB_SOFT_STATE_INIT_ENABLE)) return (DDI_INTR_UNCLAIMED);
--- a/usr/src/uts/i86pc/os/ddi_impl.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/i86pc/os/ddi_impl.c Wed Nov 22 13:57:56 2006 -0800 @@ -2315,6 +2315,7 @@ * io framework to see if there really was an error */ bzero(&de, sizeof (ddi_fm_error_t)); + de.fme_version = DDI_FME_VERSION; de.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); if (hdlp->ah_acc.devacc_attr_access == DDI_CAUTIOUS_ACC) { de.fme_flag = DDI_FM_ERR_EXPECTED; @@ -2408,6 +2409,13 @@ peekpoke_ctlops_t *in_args = (peekpoke_ctlops_t *)arg; ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; + /* + * this function only supports cautious accesses, not peeks/pokes + * which don't have a handle + */ + if (hp == NULL) + return (DDI_FAILURE); + if (hp->ahi_acc_attr & DDI_ACCATTR_CONFIG_SPACE) { if (!mutex_tryenter(err_mutexp)) { /*
--- a/usr/src/uts/sun4u/cpu/spitfire.c Wed Nov 22 13:34:11 2006 -0800 +++ b/usr/src/uts/sun4u/cpu/spitfire.c Wed Nov 22 13:57:56 2006 -0800 @@ -4085,6 +4085,7 @@ bzero(&de, sizeof (ddi_fm_error_t)); + de.fme_version = DDI_FME_VERSION; de.fme_ena = fm_ena_generate_cpu(aflt->flt_id, aflt->flt_inst, FM_ENA_FMT1); de.fme_flag = expected;