Mercurial > illumos > illumos-gate
changeset 10556:5c3063b6bc68
6852259 Add FMA support for new members of Nehalem family
author | Adrian Frost <Adrian.Frost@Sun.COM> |
---|---|
date | Wed, 16 Sep 2009 01:27:25 -0700 |
parents | 1714de5ec218 |
children | 6c4c71e8968b |
files | usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c usr/src/uts/intel/io/intel_nhm/intel_nhm.h usr/src/uts/intel/io/intel_nhm/mem_addr.c usr/src/uts/intel/io/intel_nhm/nhm_init.c usr/src/uts/intel/os/driver_aliases usr/src/uts/intel/sys/mc_intel.h |
diffstat | 6 files changed, 59 insertions(+), 9 deletions(-) [+] |
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--- a/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c Wed Sep 16 01:27:25 2009 -0700 @@ -131,6 +131,23 @@ case INTEL_QP_U2: case INTEL_QP_U3: case INTEL_QP_U4: + case INTEL_QP_JF: + case INTEL_QP_JF0: + case INTEL_QP_JF1: + case INTEL_QP_JF2: + case INTEL_QP_JF3: + case INTEL_QP_JF4: + case INTEL_QP_JF5: + case INTEL_QP_JF6: + case INTEL_QP_JF7: + case INTEL_QP_JF8: + case INTEL_QP_JF9: + case INTEL_QP_JFa: + case INTEL_QP_JFb: + case INTEL_QP_JFc: + case INTEL_QP_JFd: + case INTEL_QP_JFe: + case INTEL_QP_JFf: quickpath = 1; break; default:
--- a/usr/src/uts/intel/io/intel_nhm/intel_nhm.h Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/intel/io/intel_nhm/intel_nhm.h Wed Sep 16 01:27:25 2009 -0700 @@ -34,6 +34,10 @@ #define NHM_EP_CPU 0x2c408086 #define NHM_WS_CPU 0x2c418086 #define NHM_CPU_RAS 0x2c1a8086 +#define NHM_JF_CPU 0x2c588086 +#define NHM_JF_CPU_RAS 0x2cda8086 +#define NHM_WM_CPU 0x2c708086 +#define NHM_WM_CPU_RAS 0x2d9a8086 #define NHM_INTERCONNECT "Intel QuickPath"
--- a/usr/src/uts/intel/io/intel_nhm/mem_addr.c Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/intel/io/intel_nhm/mem_addr.c Wed Sep 16 01:27:25 2009 -0700 @@ -749,9 +749,11 @@ first = 0; last = MAX_CPU_NODES; id = CPU_ID_RD(0); - if (id == NHM_EP_CPU || id == NHM_WS_CPU) { + if (id == NHM_EP_CPU || id == NHM_WS_CPU || id == NHM_JF_CPU || + id == NHM_WM_CPU) { id = CPU_ID_RD(1); - if (id != NHM_EP_CPU && id != NHM_WS_CPU) { + if (id != NHM_EP_CPU && id != NHM_WS_CPU && id != NHM_JF_CPU && + id != NHM_WM_CPU) { last = 1; } } else { @@ -829,10 +831,12 @@ uint32_t rir_limit; uint32_t rir_way; uint32_t mc_control; + uint32_t id; int nhm_slot; int nhm_lastslot; uint8_t rank; uint64_t base; + int ras_dev = 0; nhm_slot = choose_cpu(&nhm_lastslot); @@ -846,7 +850,10 @@ } for (i = nhm_slot; i < nhm_lastslot; i++) { - if (MC_CPU_RAS_RD(i) == NHM_CPU_RAS) { + id = MC_CPU_RAS_RD(i); + if (id == NHM_CPU_RAS || id == NHM_JF_CPU_RAS || + id == NHM_WM_CPU_RAS) { + ras_dev = 1; mc_ras_enables = MC_RAS_ENABLES_RD(i); if (RAS_LOCKSTEP_ENABLE(mc_ras_enables)) lockstep[i] = 1; @@ -923,7 +930,7 @@ } mc_control = MC_CONTROL_RD(nhm_slot); closed_page = MC_CONTROL_CLOSED_PAGE(mc_control); - if (MC_CPU_RAS_RD(nhm_slot) == NHM_CPU_RAS) + if (ras_dev) ecc_enabled = MC_CONTROL_ECCEN(mc_control); else if ((MC_STATUS_RD(nhm_slot) & WS_ECC_ENABLED) != 0) ecc_enabled = 1;
--- a/usr/src/uts/intel/io/intel_nhm/nhm_init.c Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/intel/io/intel_nhm/nhm_init.c Wed Sep 16 01:27:25 2009 -0700 @@ -234,13 +234,15 @@ uint32_t mc_dimm_clk_ratio_status; uint64_t cycle_time; uint32_t interval; + uint32_t id; int i; int hw_scrub = 0; if (ecc_enabled && (nhm_patrol_scrub || nhm_demand_scrub)) { for (i = 0; i < MAX_MEMORY_CONTROLLERS; i++) { - if (MC_CPU_RAS_RD(i) != NHM_CPU_RAS || - nhm_memory_on_ctl[i] == 0) + id = MC_CPU_RAS_RD(i); + if ((id != NHM_CPU_RAS && id != NHM_JF_CPU_RAS && + id != NHM_WM_CPU_RAS) || nhm_memory_on_ctl[i] == 0) continue; mc_ssrcontrol = MC_SSR_CONTROL_RD(i); if (nhm_demand_scrub && @@ -286,7 +288,8 @@ dimmpp = nhm_dimms; for (i = 0; i < MAX_MEMORY_CONTROLLERS; i++) { did = CPU_ID_RD(i); - if (did != NHM_EP_CPU && did != NHM_WS_CPU) { + if (did != NHM_EP_CPU && did != NHM_WS_CPU && + did != NHM_JF_CPU && did != NHM_WM_CPU) { dimmpp += CHANNELS_PER_MEMORY_CONTROLLER * MAX_DIMMS_PER_CHANNEL; continue; @@ -324,10 +327,11 @@ return (ENOTSUP); for (slot = 0; slot < MAX_CPU_NODES; slot++) { nhm_chipset = CPU_ID_RD(slot); - if (nhm_chipset == NHM_EP_CPU || nhm_chipset == NHM_WS_CPU) + if (nhm_chipset == NHM_EP_CPU || nhm_chipset == NHM_WS_CPU || + nhm_chipset == NHM_JF_CPU || nhm_chipset == NHM_WM_CPU) break; } - if (nhm_chipset != NHM_EP_CPU && nhm_chipset != NHM_WS_CPU) { + if (slot == MAX_CPU_NODES) { return (ENOTSUP); } mem_reg_init();
--- a/usr/src/uts/intel/os/driver_aliases Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/intel/os/driver_aliases Wed Sep 16 01:27:25 2009 -0700 @@ -47,6 +47,7 @@ intel_nb5000 "pci8086,4003" intel_nb5000 "pci8086,65c0" intel_nhm "pci8086,3423" +intel_nhm "pci8086,372a" xpv "pci5853,1.1" amd_iommu "pci1022,11ff" amd_iommu "pci1002,5a23"
--- a/usr/src/uts/intel/sys/mc_intel.h Wed Sep 16 00:53:40 2009 -0700 +++ b/usr/src/uts/intel/sys/mc_intel.h Wed Sep 16 01:27:25 2009 -0700 @@ -223,6 +223,23 @@ #define INTEL_QP_U2 0x34028086 #define INTEL_QP_U3 0x34048086 #define INTEL_QP_U4 0x34078086 +#define INTEL_QP_JF 0x37208086 +#define INTEL_QP_JF0 0x37008086 +#define INTEL_QP_JF1 0x37018086 +#define INTEL_QP_JF2 0x37028086 +#define INTEL_QP_JF3 0x37038086 +#define INTEL_QP_JF4 0x37048086 +#define INTEL_QP_JF5 0x37058086 +#define INTEL_QP_JF6 0x37068086 +#define INTEL_QP_JF7 0x37078086 +#define INTEL_QP_JF8 0x37088086 +#define INTEL_QP_JF9 0x37098086 +#define INTEL_QP_JFa 0x370a8086 +#define INTEL_QP_JFb 0x370b8086 +#define INTEL_QP_JFc 0x370c8086 +#define INTEL_QP_JFd 0x370d8086 +#define INTEL_QP_JFe 0x370e8086 +#define INTEL_QP_JFf 0x370f8086 /* Intel QuickPath Bus Interconnect Errors */