--- a/usr/src/uts/common/io/atge/atge_mii.c	Mon Sep 14 10:15:43 2009 -0600
+++ b/usr/src/uts/common/io/atge/atge_mii.c	Mon Sep 14 10:09:29 2009 -0700
@@ -60,6 +60,18 @@
 		return (0xffff);
 	}
 
+	/*
+	 * Some fast ethernet chips may not be able to auto-nego with
+	 * switches even though they have 1000T based PHY. Hence we mask
+	 * 1000T based capabilities.
+	 */
+	if (atgep->atge_flags & ATGE_FLAG_FASTETHER) {
+		if (reg == MII_STATUS)
+			v &= ~MII_STATUS_EXTSTAT;
+		else if (reg == MII_EXTSTATUS)
+			v = 0;
+	}
+
 	return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
 }
 
@@ -109,6 +121,14 @@
 	    GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
 	drv_usecwait(1000);
 
+	/*
+	 * Some fast ethernet chips may not be able to auto-nego with
+	 * switches even though they have 1000T based PHY. Hence we need
+	 * to write 0 to MII_MSCONTROL control register.
+	 */
+	if (atgep->atge_flags & ATGE_FLAG_FASTETHER)
+		atge_mii_write(atgep, phyaddr, MII_MSCONTROL, 0x0);
+
 	/* Enable hibernation mode. */
 	atge_mii_write(atgep, phyaddr, ATPHY_DBG_ADDR, 0x0B);
 	atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, 0xBC00);