changeset 3162:b8af42ef962d

6490658 Incorrect Serialid # calculation in pxb_id_props 6495918 system panics during dr testing in px:px_detach()
author govinda
date Thu, 23 Nov 2006 10:03:18 -0800
parents 187c511fc2bf
children 163b8acfdadd
files usr/src/uts/common/sys/pcie.h usr/src/uts/sun4/io/px/px.c usr/src/uts/sun4/io/px/px_pci.c usr/src/uts/sun4/io/px/px_pec.c
diffstat 4 files changed, 21 insertions(+), 10 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/common/sys/pcie.h	Thu Nov 23 01:47:42 2006 -0800
+++ b/usr/src/uts/common/sys/pcie.h	Thu Nov 23 10:03:18 2006 -0800
@@ -538,6 +538,13 @@
 #define	PCIE_AER_SHDR_LOG_ADDR_MASK	0xFFFFFFFFFFFFFFFF
 
 /*
+ * PCI-Express Device Serial Number Capability Offsets.
+ */
+#define	PCIE_SER_CAP		0x0	/* Enhanced Capability Header */
+#define	PCIE_SER_SID_LOWER_DW	0x4	/* Lower 32-bit Serial Number */
+#define	PCIE_SER_SID_UPPER_DW	0x8	/* Upper 32-bit Serial Number */
+
+/*
  * PCI-E Common TLP Header Fields
  */
 #define	PCIE_TLP_FMT_3DW	0x00
--- a/usr/src/uts/sun4/io/px/px.c	Thu Nov 23 01:47:42 2006 -0800
+++ b/usr/src/uts/sun4/io/px/px.c	Thu Nov 23 10:03:18 2006 -0800
@@ -627,6 +627,7 @@
 	hdl.ih_ver = DDI_INTR_VERSION;
 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
 	hdl.ih_dip = dip;
+	hdl.ih_pri = px_pwr_pil;
 
 	px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
 	(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
--- a/usr/src/uts/sun4/io/px/px_pci.c	Thu Nov 23 01:47:42 2006 -0800
+++ b/usr/src/uts/sun4/io/px/px_pci.c	Thu Nov 23 10:03:18 2006 -0800
@@ -59,9 +59,6 @@
 #include "px_pci.h"
 #include "px_debug.h"
 
-/* 32-bit Shifts */
-#define	WDSHIFT 32
-
 /* Tunables. Beware: Some are for debug purpose only. */
 /*
  * PXB MSI tunable:
@@ -1869,14 +1866,14 @@
 		}
 	}
 
-	if ((PCI_CAP_LOCATE(pxb->pxb_config_handle, PCIE_EXT_CAP_ID_SER,
-		&cap_ptr)) != DDI_FAILURE) {
-		/* serialid can be 0 thru a full 40b number */
-		serialid = PCI_XCAP_GET32(pxb->pxb_config_handle, NULL, cap_ptr,
-			4);
-		serialid <<= WDSHIFT;
+	if ((PCI_CAP_LOCATE(pxb->pxb_config_handle,
+	    PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) {
+		/* Serialid can be 0 thru a full 40b number */
+		serialid = PCI_XCAP_GET32(pxb->pxb_config_handle, NULL,
+		    cap_ptr, PCIE_SER_SID_UPPER_DW);
+		serialid <<= 32;
 		serialid |= PCI_XCAP_GET32(pxb->pxb_config_handle, NULL,
-			cap_ptr, 8);
+		    cap_ptr, PCIE_SER_SID_LOWER_DW);
 	}
 
 	if (fic)
--- a/usr/src/uts/sun4/io/px/px_pec.c	Thu Nov 23 01:47:42 2006 -0800
+++ b/usr/src/uts/sun4/io/px/px_pec.c	Thu Nov 23 10:03:18 2006 -0800
@@ -268,9 +268,11 @@
 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
 	hdl.ih_dip = dip;
 
+	/* Remove correctable error message handler */
 	if (pec_p->pec_corr_msg_msiq_id >= 0) {
 		px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID);
 
+		hdl.ih_pri = PX_ERR_LOW_PIL;
 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
 		    PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id);
 
@@ -282,10 +284,12 @@
 		pec_p->pec_corr_msg_msiq_id = (msiqid_t)-1;
 	}
 
+	/* Remove non-fatal error message handler */
 	if (pec_p->pec_non_fatal_msg_msiq_id >= 0) {
 		px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG,
 		    PCIE_MSG_INVALID);
 
+		hdl.ih_pri = PX_ERR_PIL;
 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
 		    PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id);
 
@@ -297,9 +301,11 @@
 		pec_p->pec_non_fatal_msg_msiq_id = (msiqid_t)-1;
 	}
 
+	/* Remove fatal error message handler */
 	if (pec_p->pec_fatal_msg_msiq_id >= 0) {
 		px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID);
 
+		hdl.ih_pri = PX_ERR_PIL;
 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
 		    PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id);