Mercurial > illumos > illumos-gate
changeset 9971:e29752cf7b71
6743513 align 'apic_cpus' (apic_cpus_info_t) to cache line boundary
| author | Saurabh Misra <Saurabh.Mishra@Sun.COM> |
|---|---|
| date | Thu, 25 Jun 2009 15:04:52 -0700 |
| parents | 565d92d48652 |
| children | 20b62d0bb64b |
| files | usr/src/uts/i86pc/sys/apic.h |
| diffstat | 1 files changed, 11 insertions(+), 5 deletions(-) [+] |
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--- a/usr/src/uts/i86pc/sys/apic.h Thu Jun 25 12:35:31 2009 -0700 +++ b/usr/src/uts/i86pc/sys/apic.h Thu Jun 25 15:04:52 2009 -0700 @@ -491,6 +491,14 @@ #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ +/* + * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we + * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also + * don't want the compiler to optimize apic_cpus_info. + */ +#define APIC_PADSZ 19 + +#pragma pack(1) typedef struct apic_cpus_info { uint32_t aci_local_id; uchar_t aci_local_ver; @@ -505,13 +513,11 @@ uint32_t aci_temp_bound; /* # of non user IRQ binds */ uchar_t aci_idle; /* The CPU is idle */ /* - * fill to make sure each struct is in seperate cache line. - * Or atleast that ISR_in_progress/curipl is not shared with something - * that is read/written heavily by another CPU. - * Given kmem_alloc guarantees alignment to 8 bytes, having 8 - * bytes on each side will isolate us in a 16 byte cache line. + * Fill to make sure each struct is in separate 64-byte cache line. */ + uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */ } apic_cpus_info_t; +#pragma pack() #define APIC_CPU_ONLINE 1 #define APIC_CPU_INTR_ENABLE 2