view usr/src/cmd/fm/eversholt/files/sparc/sun4u/schizo.esc @ 4:1a15d5aaf794

synchronized with onnv_86 (6202) in onnv-gate
author Koji Uno <koji.uno@sun.com>
date Mon, 31 Aug 2009 14:38:03 +0900
parents c9caec207d52
children
line wrap: on
line source

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"%Z%%M%	%I%	%E% SMI"

#pragma dictionary "SUN4U"

#define	AGENT_ID_MASK	0x1f
#define	AGENT_ID_SHIFT	24

#define	HB_FIT		1000
#define HBUS_FIT	1000
#define PCI_BUS_FIT	500
#define PCI_DEV_FIT	1000
#define	CPU_FIT		500

#define	PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0]

fru hostbridge;
asru hostbridge;

event fault.io.schizo@hostbridge,
    FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge;

event error.io.sch.saf.dstat@hostbridge;
event error.io.sch.saf.to@hostbridge;
event error.io.sch.saf.bus@hostbridge;
event error.io.sch.ecc.thresh@hostbridge;
event error.io.pci.device-ta@hostbridge/pcibus/pcidev/pcifn;

event ereport.io.sch.saf.to@hostbridge{within(5s)};
event ereport.io.sch.saf.bus@hostbridge{within(5s)};
event ereport.io.sch.saf.bca@hostbridge{within(5s)};
event ereport.io.sch.saf.bcb@hostbridge{within(5s)};
event ereport.io.sch.saf.ciq-to@hostbridge{within(5s)};
event ereport.io.sch.saf.lpq-to@hostbridge{within(5s)};
event ereport.io.sch.saf.sfpq-to@hostbridge{within(5s)};
event ereport.io.sch.saf.ufpq-to@hostbridge{within(5s)};
event ereport.io.sch.saf.ape@hostbridge{within(5s)};
event ereport.io.sch.ecc.pce@hostbridge{within(5s)};
event ereport.io.sch.ecc.pue@hostbridge{within(5s)};
event ereport.io.sch.ecc.s-pce@hostbridge{within(5s)};
event ereport.io.sch.ecc.s-pue@hostbridge{within(5s)};
event ereport.io.sch.ecc.thresh@hostbridge{within(5s)};
event ereport.io.sch.saf.dstat@hostbridge{within(5s)};

/*
 * A faulty Schizo hostbridge may cause:
 *
 *  - bca:	bad safari command from PCI block A.
 *  - bcb:	bad safari command from PCI block B.
 *  - ciq-to:	coherent input queue timeout.
 *  - lpq-to:	local PIO queue timeout.
 *  - sfpq-to:	safari foreign PIO queue timeout.
 *  - ufpq-to:	UPA foreign PIO queue timeout.
 *  - ape:	address parity error.
 *  - pue:	PIO uncorrectable error, bad reader.
 *  - s-pue:	secondary PIO UE, bad reader.
 *  - ecc:	multiple PIO CEs.
 *  - to:	safari bus timeout.
 *  - bus:	safari bus error.
 *  - dstat:	errant dstat on incoming data.
 *
 * The to, bus and dstat errors can cause a target abort to be sent onto the
 * pci bus in response to a dma request. We represent this using a device-ta
 * error to propagate into the generic pci.esc rules.
 */
prop fault.io.schizo@hostbridge (0)->
    ereport.io.sch.saf.bca@hostbridge,
    ereport.io.sch.saf.bcb@hostbridge,
    ereport.io.sch.saf.ciq-to@hostbridge,
    ereport.io.sch.saf.lpq-to@hostbridge,
    ereport.io.sch.saf.sfpq-to@hostbridge,
    ereport.io.sch.saf.ufpq-to@hostbridge,
    ereport.io.sch.saf.ape@hostbridge,
    ereport.io.sch.ecc.pue@hostbridge,
    ereport.io.sch.ecc.s-pue@hostbridge,
    error.io.sch.ecc.thresh@hostbridge,
    error.io.sch.saf.to@hostbridge,
    error.io.sch.saf.bus@hostbridge,
    error.io.sch.saf.dstat@hostbridge;

prop error.io.sch.ecc.thresh@hostbridge (2)->
    ereport.io.sch.ecc.thresh@hostbridge,
    ereport.io.sch.ecc.pce@hostbridge;

prop error.io.sch.saf.to@hostbridge (2)->
    ereport.io.sch.saf.to@hostbridge,
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.sch.saf.bus@hostbridge (2)->
    ereport.io.sch.saf.bus@hostbridge,
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.sch.saf.dstat@hostbridge (1)->
    ereport.io.sch.saf.dstat@hostbridge;

prop error.io.sch.saf.dstat@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

engine serd.io.schizo.ecc@hostbridge,
    N=3, T=1day, method=persistent,
    trip=ereport.io.sch.ecc.thresh@hostbridge;

event upset.io.schizo@hostbridge,
    engine=serd.io.schizo.ecc@hostbridge;

/*
 * An upset schizo may cause:
 *
 *  - pce:	PIO correctable error.
 */
prop upset.io.schizo@hostbridge (0)->
    ereport.io.sch.ecc.pce@hostbridge;

fru cpu;

event fault.io.datapath@cpu, FITrate=CPU_FIT, FRU=cpu;

event error.io.cpu.ecc.thresh@cpu;
event ereport.io.sch.saf.ssm-dis@hostbridge{within(5s)};
event ereport.io.sch.saf.cpu0-par@hostbridge{within(5s)};
event ereport.io.sch.saf.cpu0-bidi@hostbridge{within(5s)};
event ereport.io.sch.saf.cpu1-par@hostbridge{within(5s)};
event ereport.io.sch.saf.cpu1-bidi@hostbridge{within(5s)};

/*
 * A faulty xcal CPU[0] may cause:
 *
 *  - cpu0-par:		parity error on the unidirectional signals.
 *  - cpu0-bidi:	parity error on the bi-directional signals.
 */
prop fault.io.datapath@cpu[0] (0)->
    ereport.io.sch.saf.cpu0-par@hostbridge,
    ereport.io.sch.saf.cpu0-bidi@hostbridge;

/*
 * A faulty xcal CPU[1] may cause:
 *
 *  - cpu1-par:		parity error on the unidirectional signals.
 *  - cpu1-bidi:	parity error on the bidirectional signals.
 */
prop fault.io.datapath@cpu[1] (0)->
    ereport.io.sch.saf.cpu1-par@hostbridge,
    ereport.io.sch.saf.cpu1-bidi@hostbridge;

/*
 * A faulty CPU may cause:
 *
 *  - to:	safari bus timeout.
 *  - bus:	safari bus error.
 *  - dstat:	incorrect dstat sent to hostbridge.
 *  - ssm-dis:	ssm command sent to hostbridge when not enabled.
 *  - ape:	safari address parity error.
 *  - pue:	PIO uncorrectable error.
 *  - ecc:	multiple PIO CEs.
 */
prop fault.io.datapath@cpu (0)->
    error.io.sch.saf.to@hostbridge,
    error.io.sch.saf.bus@hostbridge,
    error.io.sch.saf.dstat@hostbridge,
    ereport.io.sch.saf.ssm-dis@hostbridge,
    ereport.io.sch.saf.ape@hostbridge;

prop fault.io.datapath@cpu[cpuid] (0)->
    ereport.io.sch.ecc.pue@hostbridge
    {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid};

prop fault.io.datapath@cpu (0)->
    error.io.cpu.ecc.thresh@cpu;

prop error.io.cpu.ecc.thresh@cpu (1)->
    ereport.io.sch.ecc.thresh@hostbridge<>;

prop error.io.cpu.ecc.thresh@cpu[cpuid] (1)->
    ereport.io.sch.ecc.pce@hostbridge<>
    {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid};

event fault.io.hbus@hostbridge,
    FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge;

/*
 * A faulty host bus may cause:
 *
 *  - ape:		address parity error.
 *  - cpu0-par:		parity error on the unidirectional signals.
 *  - cpu0-bidi:	parity error on the bidirectional signals.
 *  - cpu1-par:		parity error on the unidirectional signals.
 *  - cpu1-bidi:	parity error on the bidirectional signals.
 *  - pue:		PIO uncorrectable error.
 *  - s-pue:		secondary PIO UE.
 *  - ecc:		multiple PIO CEs.
 */
prop fault.io.hbus@hostbridge (0)->
    ereport.io.sch.saf.ape@hostbridge,
    ereport.io.sch.saf.cpu0-par@hostbridge,
    ereport.io.sch.saf.cpu0-bidi@hostbridge,
    ereport.io.sch.saf.cpu1-par@hostbridge,
    ereport.io.sch.saf.cpu1-bidi@hostbridge,
    ereport.io.sch.ecc.pue@hostbridge,
    ereport.io.sch.ecc.s-pue@hostbridge,
    error.io.sch.ecc.thresh@hostbridge;

/*
 * A bad request from a downstream device/driver may cause
 *
 *  - um:	safari unmapped address error.
 *  - mmu:	a iommu translation error.
 */
event error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn;

event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.mmu@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.saf.um@hostbridge{within(5s)};

prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.saf.um@hostbridge;

prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.mmu@PCI_HB_DEV_PATH;

prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.saf.um@hostbridge;

prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.mmu@PCI_HB_DEV_PATH;

fru pcibus;
asru pcibus;

event fault.io.pci.bus@hostbridge/pcibus,
    FITrate=PCI_BUS_FIT, FRU=pcibus, ASRU=pcibus;

event ereport.io.sch.bu@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.s-bu@hostbridge/pcibus/pcidev/pcifn{within(5s)};

/*
 * A faulty PCI bus may cause:
 *
 *  - bu:	PCI bus unusable error.
 *  - s-bu:	secondary PCI bus unusable error.
 */
prop fault.io.pci.bus@hostbridge/pcibus (0)->
    ereport.io.sch.bu@PCI_HB_DEV_PATH,
    ereport.io.sch.s-bu@PCI_HB_DEV_PATH;

fru pcibus/pcidev;
asru pcibus/pcidev/pcifn;

event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn,
    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;

event fault.io.pci.device-interr@pcibus/pcidev/pcifn,
    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;

event error.io.sch.pbm.rl@hostbridge/pcibus/pcidev/pcifn;
event error.io.sch.pbm.rl@pcibus/pcidev/pcifn;
event error.io.sch.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.io.sch.pbm.target-rl@pcibus/pcidev/pcifn;
event error.io.sch.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.io.sch.pbm.tto@hostbridge/pcibus/pcidev/pcifn;
event error.io.sch.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn;
event error.io.sch.pbm.target-tto@pcibus/pcidev/pcifn;
event error.io.sch.pbm.target-tto@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.sch.cpu.berr@cpu;
event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;

event ereport.io.sch.sbh@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.tto@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.s-tto@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)};
event ereport.io.sch.pbm.target-tto@pcibus/pcidev/pcifn{within(5s)};
event ereport.io.pci.sserr@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.cpu.ultraSPARC-III.berr@cpu{within(5s)};
event ereport.cpu.ultraSPARC-IIIplus.berr@cpu{within(5s)};
event ereport.cpu.ultraSPARC-IV.berr@cpu{within(5s)};
event ereport.cpu.ultraSPARC-IVplus.berr@cpu{within(5s)};

/*
 * A faulty PCI device may cause:
 *
 *  - sbh:	a streaming byte hole error.
 *  - rl:	it to exceed the number retriesfor a transaction.
 *  - tto:	it to not assert trdy# within the alloted timeout.
 *
 * For rl and tto, there may be a target- ereport on a child device. For rl,
 * there may also be an associated dto - the retry-to-d error propagates into
 * the pci.esc rules to handle this.
 */
prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.sbh@PCI_HB_DEV_PATH;

prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)->
    error.io.sch.pbm.rl@pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32 },
    error.io.sch.pbm.target-rl@pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32 };

prop error.io.sch.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)->
    error.io.sch.pbm.rl@pcibus/pcidev/pcifn;

prop error.io.sch.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.sch.pbm.rl@PCI_HB_DEV_PATH,
    ereport.io.sch.pbm.s-rl@PCI_HB_DEV_PATH;

prop error.io.sch.pbm.target-rl@pcibus/pcidev/pcifn (1)->
    error.io.sch.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>;

prop error.io.sch.pbm.target-rl@pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.target-rl@pcibus/pcidev/pcifn;

prop error.io.sch.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
    error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;

prop error.io.sch.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
    error.sch.cpu.berr@cpu;

prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev[fromdev]/pcifn (0)->
    error.io.sch.pbm.tto@hostbridge/pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32 };

prop error.io.sch.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.sch.pbm.tto@PCI_HB_DEV_PATH,
    ereport.io.sch.pbm.s-tto@PCI_HB_DEV_PATH;

prop error.io.sch.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)->
    error.io.sch.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn;

prop error.io.sch.pbm.target-tto@pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.target-tto@pcibus/pcidev/pcifn;

prop error.io.sch.pbm.target-tto@pcibus/pcidev/pcifn (1)->
    error.io.sch.pbm.target-tto@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>;

prop error.io.sch.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.sch.bu@PCI_HB_DEV_PATH;

/*
 * Need to add the following schizo specific propagations to complete the PCI
 * fault tree. These are to allow propagations to secondary errors and cpu
 * bus errors, and to represent the way the chip can raise both rserr and sserr
 * on detection of SERR#
 */
prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.s-ma@PCI_HB_DEV_PATH;

prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.s-rta@PCI_HB_DEV_PATH;

prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.sch.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.sch.cpu.berr@cpu;

prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.sch.cpu.berr@cpu;

prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.sch.cpu.berr@cpu;

prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.pci.rserr@PCI_HB_DEV_PATH;

prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.pci.sserr@PCI_HB_DEV_PATH;

prop error.sch.cpu.berr@cpu (1)->
    ereport.cpu.ultraSPARC-III.berr@cpu,
    ereport.cpu.ultraSPARC-IIIplus.berr@cpu,
    ereport.cpu.ultraSPARC-IV.berr@cpu,
    ereport.cpu.ultraSPARC-IVplus.berr@cpu;

event error.io.sch.ecc.drue@hostbridge;
event ereport.io.sch.ecc.drue@hostbridge{within(5s)};
event ereport.io.sch.nodiag@hostbridge;

/*
 * Upset used to hide ereports that can not be currently diagnosed.
 *
 * The drue error can cause a target abort to be sent onto the
 * pci bus in response to a dma request. We represent this using a device-ta
 * error to propagate into the generic pci.esc rules.
 */
engine serd.io.sch.nodiag@hostbridge,
    N=1000, T=1hour, method=persistent,
    trip=ereport.io.sch.nodiag@hostbridge;

event upset.io.sch.nodiag@hostbridge,
    engine=serd.io.sch.nodiag@hostbridge;

prop upset.io.sch.nodiag@hostbridge (0)->
    ereport.io.sch.ecc.s-pce@hostbridge,
    error.io.sch.ecc.drue@hostbridge,
    ereport.io.sch.nodiag@hostbridge;

prop error.io.sch.ecc.drue@hostbridge (1)->
    ereport.io.sch.ecc.drue@hostbridge;

prop error.io.sch.ecc.drue@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;