diff usr/src/uts/intel/sys/x86_archext.h @ 25257:b821679919bb

12999 MSR_AMD_DE_CFG is twice defined Reviewed by: Robert Mustacchi <rm@fingolfin.org> Approved by: Dan McDonald <danmcd@joyent.com>
author Patrick Mooney <pmooney@pfmooney.com>
date Wed, 29 Jul 2020 22:37:40 +0000
parents 54e017b9ff42
children 30063115dff3 3485cc014a43
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line diff
--- a/usr/src/uts/intel/sys/x86_archext.h	Tue Jul 28 20:24:52 2020 +0000
+++ b/usr/src/uts/intel/sys/x86_archext.h	Wed Jul 29 22:37:40 2020 +0000
@@ -603,13 +603,6 @@
 #define	IA32_PKG_THERM_INTERRUPT_TR2_IE		0x00800000
 #define	IA32_PKG_THERM_INTERRUPT_PL_NE		0x01000000
 
-/*
- * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
- * decoding. Most notably, for the AMD variant of retpolines, we must improve
- * the serializability of lfence for the lfence based method to work.
- */
-#define	MSR_AMD_DECODE_CONFIG			0xc0011029
-#define	AMD_DECODE_CONFIG_LFENCE_DISPATCH	0x02
 
 #define	MCI_CTL_VALUE		0xffffffff