Mercurial > illumos > git > illumos-joyent
changeset 25257:b821679919bb
12999 MSR_AMD_DE_CFG is twice defined
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@joyent.com>
| author | Patrick Mooney <pmooney@pfmooney.com> |
|---|---|
| date | Wed, 29 Jul 2020 22:37:40 +0000 |
| parents | d352d99f7497 |
| children | 4076af232ed9 |
| files | usr/src/uts/i86pc/os/cpuid.c usr/src/uts/intel/sys/controlregs.h usr/src/uts/intel/sys/x86_archext.h |
| diffstat | 3 files changed, 14 insertions(+), 15 deletions(-) [+] |
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--- a/usr/src/uts/i86pc/os/cpuid.c Tue Jul 28 20:24:52 2020 +0000 +++ b/usr/src/uts/i86pc/os/cpuid.c Wed Jul 29 22:37:40 2020 +0000 @@ -2746,8 +2746,8 @@ /* * We need to determine whether or not lfence is serializing. It always * is on families 0xf and 0x11. On others, it's controlled by - * MSR_AMD_DECODE_CONFIG (MSRC001_1029). If some hypervisor gives us a - * crazy old family, don't try and do anything. + * MSR_AMD_DE_CFG (MSRC001_1029). If some hypervisor gives us a crazy + * old family, don't try and do anything. */ if (cpi->cpi_family < 0xf) return (B_FALSE); @@ -2762,16 +2762,16 @@ * for it. */ if (!on_trap(&otd, OT_DATA_ACCESS)) { - val = rdmsr(MSR_AMD_DECODE_CONFIG); - val |= AMD_DECODE_CONFIG_LFENCE_DISPATCH; - wrmsr(MSR_AMD_DECODE_CONFIG, val); - val = rdmsr(MSR_AMD_DECODE_CONFIG); + val = rdmsr(MSR_AMD_DE_CFG); + val |= AMD_DE_CFG_LFENCE_DISPATCH; + wrmsr(MSR_AMD_DE_CFG, val); + val = rdmsr(MSR_AMD_DE_CFG); } else { val = 0; } no_trap(); - if ((val & AMD_DECODE_CONFIG_LFENCE_DISPATCH) != 0) + if ((val & AMD_DE_CFG_LFENCE_DISPATCH) != 0) return (B_TRUE); return (B_FALSE); }
--- a/usr/src/uts/intel/sys/controlregs.h Tue Jul 28 20:24:52 2020 +0000 +++ b/usr/src/uts/intel/sys/controlregs.h Wed Jul 29 22:37:40 2020 +0000 @@ -238,9 +238,15 @@ #define AMD_BU_CFG_E298 (UINT64_C(1) << 1) +/* + * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction + * decoding. Most notably, for the AMD variant of retpolines, we must improve + * the serializability of lfence for the lfence based method to work. + */ #define MSR_AMD_DE_CFG 0xc0011029 -#define AMD_DE_CFG_E721 (UINT64_C(1)) +#define AMD_DE_CFG_E721 (1UL << 0) +#define AMD_DE_CFG_LFENCE_DISPATCH (1UL << 1) /* AMD's osvw MSRs */ #define MSR_AMD_OSVW_ID_LEN 0xc0010140
--- a/usr/src/uts/intel/sys/x86_archext.h Tue Jul 28 20:24:52 2020 +0000 +++ b/usr/src/uts/intel/sys/x86_archext.h Wed Jul 29 22:37:40 2020 +0000 @@ -603,13 +603,6 @@ #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 -/* - * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction - * decoding. Most notably, for the AMD variant of retpolines, we must improve - * the serializability of lfence for the lfence based method to work. - */ -#define MSR_AMD_DECODE_CONFIG 0xc0011029 -#define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02 #define MCI_CTL_VALUE 0xffffffff