Mercurial > illumos > git > illumos-omnios

changeset 23910:cd16aeceed83

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
13339 Add support for Hygon Dhyana Family 18h processor Reviewed by: Robert Mustacchi <rm@fingolfin.org> Approved by: Dan McDonald <danmcd@joyent.com>
author Pu Wen <puwen@hygon.cn>
date Thu, 26 Nov 2020 19:50:37 +0800
parents c673ba511cc3
children fc9802b8f6e3
files usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c usr/src/uts/i86pc/os/cmi_hw.c usr/src/uts/i86pc/os/cpuid.c usr/src/uts/i86pc/os/cpuid_subr.c usr/src/uts/i86pc/os/cpupm/cpupm_amd.c usr/src/uts/i86pc/os/hma.c usr/src/uts/i86pc/os/startup.c usr/src/uts/intel/ia32/os/cpc_subr.c usr/src/uts/intel/io/amdzen/amdzen.c usr/src/uts/intel/io/amdzen/amdzen.h usr/src/uts/intel/pcbe/opteron_pcbe.c usr/src/uts/intel/sys/x86_archext.h
diffstat 12 files changed, 152 insertions(+), 34 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c	Thu Nov 26 19:50:37 2020 +0800
@@ -1366,7 +1366,8 @@
 	 */
 	if (!gcpu_suppress_log_on_init &&
 	    ((vendor == X86_VENDOR_Intel && family >= 0xf) ||
-	    vendor == X86_VENDOR_AMD))
+	    vendor == X86_VENDOR_AMD ||
+	    vendor == X86_VENDOR_HYGON))
 		gcpu_mca_logout(hdl, NULL, -1ULL, NULL, B_FALSE,
 		    GCPU_MPT_WHAT_POKE_ERR);
 
--- a/usr/src/uts/i86pc/os/cmi_hw.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/cmi_hw.c	Thu Nov 26 19:50:37 2020 +0800
@@ -1272,6 +1272,7 @@
 	switch (vendor) {
 	case X86_VENDOR_Intel:
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		if (cmi_ext_topo_check == 0) {
 			cpuid_get_ext_topo((cpu_t *)priv, &cmi_core_nbits,
 			    &cmi_strand_nbits);
--- a/usr/src/uts/i86pc/os/cpuid.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/cpuid.c	Thu Nov 26 19:50:37 2020 +0800
@@ -1817,6 +1817,7 @@
 		}
 		break;
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		switch (eax) {
 
 		case 0x80000001:
@@ -2077,7 +2078,8 @@
 		}
 	}
 
-	if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+	if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
 	    is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
 	    cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_1e) {
 		return (cpi->cpi_extd[0x1e].cp_eax);
@@ -2742,7 +2744,8 @@
 	uint64_t val;
 	on_trap_data_t otd;
 
-	if (cpi->cpi_vendor != X86_VENDOR_AMD)
+	if (cpi->cpi_vendor != X86_VENDOR_AMD &&
+	    cpi->cpi_vendor != X86_VENDOR_HYGON)
 		return (B_FALSE);
 
 	/*
@@ -2881,7 +2884,8 @@
 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
 	x86_spectrev2_mitigation_t v2mit;
 
-	if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+	if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
 	    cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_8) {
 		if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_IBPB)
 			add_x86_feature(featureset, X86FSET_IBPB);
@@ -3092,7 +3096,8 @@
 
 	cpi = cpu->cpu_m.mcpu_cpi;
 
-	if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+	if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) {
 		cpuid_gather_amd_topology_leaves(cpu);
 	}
 
@@ -3108,6 +3113,7 @@
 		    &cpi->cpi_ncore_per_chip);
 		break;
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		cpuid_amd_ncores(cpi, &cpi->cpi_ncpu_per_chip,
 		    &cpi->cpi_ncore_per_chip);
 		break;
@@ -3157,7 +3163,8 @@
 		cpi->cpi_clogid = 0;
 		cpi->cpi_coreid = cpu->cpu_id;
 		cpi->cpi_pkgcoreid = 0;
-		if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+		if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+		    cpi->cpi_vendor == X86_VENDOR_HYGON) {
 			cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
 		} else {
 			cpi->cpi_procnodeid = cpi->cpi_chipid;
@@ -3168,6 +3175,7 @@
 			cpuid_intel_getids(cpu, featureset);
 			break;
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			cpuid_amd_getids(cpu, featureset);
 			break;
 		default:
@@ -3358,6 +3366,9 @@
 		if (CPI_FAMILY(cpi) == 0xf)
 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
 		break;
+	case X86_VENDOR_HYGON:
+		cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
+		break;
 	default:
 		if (cpi->cpi_model == 0xf)
 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
@@ -3471,6 +3482,10 @@
 #endif
 
 		break;
+	case X86_VENDOR_HYGON:
+		/* Enable all for Hygon Dhyana CPU */
+		mask_ecx = 0xffffffff;
+		break;
 	case X86_VENDOR_TM:
 		/*
 		 * workaround the NT workaround in CMS 4.1
@@ -3934,6 +3949,7 @@
 		    x86_type == X86_TYPE_CYRIX_GXm)
 			xcpuid++;
 		break;
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_Centaur:
 	case X86_VENDOR_TM:
 	default:
@@ -3955,6 +3971,7 @@
 		switch (cpi->cpi_vendor) {
 		case X86_VENDOR_Intel:
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			if (cpi->cpi_xmaxeax < 0x80000001)
 				break;
 			cp = &cpi->cpi_extd[1];
@@ -3998,7 +4015,8 @@
 				add_x86_feature(featureset, X86FSET_1GPG);
 			}
 
-			if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
+			if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+			    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
 			    (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
 			    (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
 				add_x86_feature(featureset, X86FSET_SSE4A);
@@ -4019,7 +4037,8 @@
 			 * that AMD processors don't support sysenter
 			 * in long mode at all, so don't try to program them.
 			 */
-			if (x86_vendor == X86_VENDOR_AMD) {
+			if (x86_vendor == X86_VENDOR_AMD ||
+			    x86_vendor == X86_VENDOR_HYGON) {
 				remove_x86_feature(featureset, X86FSET_SEP);
 			}
 
@@ -4073,6 +4092,7 @@
 			}
 			/*FALLTHROUGH*/
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			if (cpi->cpi_xmaxeax < CPUID_LEAF_EXT_8)
 				break;
 			cp = &cpi->cpi_extd[8];
@@ -4084,7 +4104,8 @@
 			/*
 			 * AMD uses ebx for some extended functions.
 			 */
-			if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+			if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+			    cpi->cpi_vendor == X86_VENDOR_HYGON) {
 				/*
 				 * While we're here, check for the AMD "Error
 				 * Pointer Zero/Restore" feature. This can be
@@ -4120,6 +4141,7 @@
 		switch (cpi->cpi_vendor) {
 		case X86_VENDOR_Intel:
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			if (cpi->cpi_maxeax >= 7) {
 				cp = &cpi->cpi_extd[7];
 				cp->cp_eax = 0x80000007;
@@ -4152,7 +4174,8 @@
 	cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
 	    cpi->cpi_model, cpi->cpi_step);
 
-	if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+	if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) {
 		if (cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_8 &&
 		    cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_ERR_PTR_ZERO) {
 			/* Special handling for AMD FP not necessary. */
@@ -5032,7 +5055,8 @@
 	cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
 
 	if ((cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) ||
-	    (cpi->cpi_vendor == X86_VENDOR_AMD &&
+	    ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
 	    cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_1d &&
 	    is_x86_feature(x86_featureset, X86FSET_TOPOEXT))) {
 		uint32_t leaf;
@@ -5394,6 +5418,7 @@
 		/*FALLTHROUGH*/
 
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		edx = &cpi->cpi_support[AMD_EDX_FEATURES];
 		ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
 
@@ -5410,6 +5435,7 @@
 			break;
 
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
 				*edx &= ~CPUID_AMD_EDX_TSCP;
 			if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
@@ -5452,6 +5478,7 @@
 
 		switch (cpi->cpi_vendor) {
 		case X86_VENDOR_AMD:
+		case X86_VENDOR_HYGON:
 			if (*edx & CPUID_AMD_EDX_TSCP)
 				hwcap_flags |= AV_386_TSCP;
 			if (*ecx & CPUID_AMD_ECX_AHF64)
@@ -5596,7 +5623,8 @@
 	{
 		struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
 
-		if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+		if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+		    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
 		    cpi->cpi_xmaxeax >= 0x80000001 &&
 		    (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
 			return (1);
@@ -5814,7 +5842,9 @@
 
 	ASSERT(cpu != NULL);
 	cpi = cpu->cpu_m.mcpu_cpi;
-	if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
+	if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) &&
+	    cpi->cpi_maxeax >= 1 &&
 	    (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
 		return (1);
 	return (0);
@@ -6782,6 +6812,8 @@
 		    (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
 			return (X86_VENDOR_AMD);
 		break;
+	case X86_VENDOR_HYGON:
+		return (X86_VENDOR_AMD);
 	case X86_VENDOR_TM:
 		if (cpi->cpi_family >= 5)
 			return (X86_VENDOR_AMD);
@@ -6878,6 +6910,9 @@
 	case X86_VENDOR_AMD:
 		create = cpi->cpi_family >= 0xf;
 		break;
+	case X86_VENDOR_HYGON:
+		create = 1;
+		break;
 	default:
 		create = 0;
 		break;
@@ -6894,6 +6929,9 @@
 	case X86_VENDOR_AMD:
 		create = CPI_FAMILY(cpi) == 0xf;
 		break;
+	case X86_VENDOR_HYGON:
+		create = 1;
+		break;
 	default:
 		create = 0;
 		break;
@@ -6905,6 +6943,7 @@
 	/* generation */
 	switch (cpi->cpi_vendor) {
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		/*
 		 * AMD K5 model 1 was the first part to support this
 		 */
@@ -6931,6 +6970,9 @@
 	case X86_VENDOR_AMD:
 		create = cpi->cpi_family >= 0xf;
 		break;
+	case X86_VENDOR_HYGON:
+		create = 1;
+		break;
 	default:
 		create = 0;
 		break;
@@ -6951,6 +6993,9 @@
 	case X86_VENDOR_AMD:
 		create = cpi->cpi_family >= 0xf;
 		break;
+	case X86_VENDOR_HYGON:
+		create = 1;
+		break;
 	default:
 		create = 0;
 		break;
@@ -6981,6 +7026,9 @@
 	case X86_VENDOR_AMD:
 		create = cpi->cpi_family >= 0xf;
 		break;
+	case X86_VENDOR_HYGON:
+		create = 1;
+		break;
 	default:
 		create = 0;
 		break;
@@ -6993,6 +7041,7 @@
 	switch (cpi->cpi_vendor) {
 	case X86_VENDOR_Intel:
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_Cyrix:
 	case X86_VENDOR_TM:
 	case X86_VENDOR_Centaur:
@@ -7506,7 +7555,8 @@
 		cp.cp_ecx = 0;
 		(void) __cpuid_insn(&cp);
 		cpi->cpi_std[7] = cp;
-	} else if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+	} else if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+	    cpi->cpi_vendor == X86_VENDOR_HYGON) {
 		/* No xcpuid support */
 		if (cpi->cpi_family < 5 ||
 		    (cpi->cpi_family == 5 && cpi->cpi_model < 1))
--- a/usr/src/uts/i86pc/os/cpuid_subr.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/cpuid_subr.c	Thu Nov 26 19:50:37 2020 +0800
@@ -88,12 +88,13 @@
  *		15 for family 0x17, models 30 - 3f
  *		16 for family 0x17, models 60 - 6f
  *		17 for family 0x17, models 70 - 7f
- *		18 for family 0x19, models 00 - 0f
- *		19 for family 0x19, models 20 - 2f
+ *		18 for family 0x18, models 00 - 0f
+ *		19 for family 0x19, models 00 - 0f
+ *		20 for family 0x19, models 20 - 2f
  * Second index by (model & 0x3) for family 0fh,
  * CPUID pkg bits (Fn8000_0001_EBX[31:28]) for later families.
  */
-static uint32_t amd_skts[20][8] = {
+static uint32_t amd_skts[21][8] = {
 	/*
 	 * Family 0xf revisions B through E
 	 */
@@ -365,9 +366,24 @@
 	},
 
 	/*
+	 * Family 0x18 models 00-0f	(Dhyana)
+	 */
+#define	A_SKTS_18			18
+	{
+		X86_SOCKET_UNKNOWN,	/* 0b000 */
+		X86_SOCKET_UNKNOWN,	/* 0b001 */
+		X86_SOCKET_UNKNOWN,	/* 0b010 */
+		X86_SOCKET_UNKNOWN,	/* 0b011 */
+		X86_SOCKET_SL1,		/* 0b100 */
+		X86_SOCKET_UNKNOWN,	/* 0b101 */
+		X86_SOCKET_DM1,		/* 0b110 */
+		X86_SOCKET_SL1R2	/* 0b111 */
+	},
+
+	/*
 	 * Family 0x19 models 00-0f	(Zen 3 - Milan)
 	 */
-#define	A_SKTS_18			18
+#define	A_SKTS_19			19
 	{
 		X86_SOCKET_UNKNOWN,	/* 0b000 */
 		X86_SOCKET_UNKNOWN,	/* 0b001 */
@@ -382,7 +398,7 @@
 	/*
 	 * Family 0x19 models 20-2f	(Zen 3 - Vermeer)
 	 */
-#define	A_SKTS_19			19
+#define	A_SKTS_20			20
 	{
 		X86_SOCKET_UNKNOWN,	/* 0b000 */
 		X86_SOCKET_UNKNOWN,	/* 0b001 */
@@ -399,7 +415,7 @@
 	uint32_t	skt_code;
 	char		sktstr[16];
 };
-static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS_AMD + 1] = {
+static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS + 1] = {
 	{ X86_SOCKET_754,	"754" },
 	{ X86_SOCKET_939,	"939" },
 	{ X86_SOCKET_940,	"940" },
@@ -434,6 +450,9 @@
 	{ X86_SOCKET_FP5,	"FP5" },
 	{ X86_SOCKET_FP6,	"FP6" },
 	{ X86_SOCKET_STRX4,	"sTRX4" },
+	{ X86_SOCKET_SL1,	"SL1" },
+	{ X86_SOCKET_SL1R2,	"SL1R2" },
+	{ X86_SOCKET_DM1,	"DM1" },
 	{ X86_SOCKET_UNKNOWN,	"Unknown" }
 };
 
@@ -459,8 +478,9 @@
 	{ 0x17, 0x30, 0x3f, A_SKTS_15 },
 	{ 0x17, 0x60, 0x6f, A_SKTS_16 },
 	{ 0x17, 0x70, 0x7f, A_SKTS_17 },
-	{ 0x19, 0x00, 0x0f, A_SKTS_18 },
-	{ 0x19, 0x20, 0x2f, A_SKTS_19 }
+	{ 0x18, 0x00, 0x0f, A_SKTS_18 },
+	{ 0x19, 0x00, 0x0f, A_SKTS_19 },
+	{ 0x19, 0x20, 0x2f, A_SKTS_20 }
 };
 
 /*
@@ -629,7 +649,13 @@
 	    A_SKTS_15 },
 
 	{ 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_17_MTS_B0, "MTS-B0",
-	    A_SKTS_17 }
+	    A_SKTS_17 },
+
+	/*
+	 * =============== HygonGenuine Family 0x18 ===============
+	 */
+	{ 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_18_DN_A1, "DN_A1",
+	    A_SKTS_18 },
 };
 
 /*
@@ -759,6 +785,7 @@
 
 	switch (vendor) {
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		synth_amd_info(family, model, step, &skt, NULL, NULL);
 		break;
 
@@ -779,6 +806,7 @@
 
 	switch (vendor) {
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		synth_amd_info(family, model, step, &skt, NULL, NULL);
 
 		sktmapp = amd_sktmap_strs;
@@ -805,6 +833,7 @@
 
 	switch (vendor) {
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		synth_amd_info(family, model, step, NULL, &chiprev, NULL);
 		break;
 
@@ -823,6 +852,7 @@
 
 	switch (vendor) {
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		synth_amd_info(family, model, step, NULL, NULL, &revstr);
 		break;
 
@@ -851,6 +881,8 @@
 		return (X86_VENDOR_Intel);
 	else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
 		return (X86_VENDOR_AMD);
+	else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0)
+		return (X86_VENDOR_HYGON);
 	else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
 		return (X86_VENDOR_TM);
 	else if (strcmp(vendorstr, CyrixInstead) == 0)
--- a/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c	Thu Nov 26 19:50:37 2020 +0800
@@ -37,8 +37,9 @@
 	cpupm_mach_state_t *mach_state =
 	    (cpupm_mach_state_t *)(cp->cpu_m.mcpu_pm_mach_state);
 
-	/* AMD? */
-	if (x86_vendor != X86_VENDOR_AMD)
+	/* AMD or Hygon? */
+	if (x86_vendor != X86_VENDOR_AMD &&
+	    x86_vendor != X86_VENDOR_HYGON)
 		return (B_FALSE);
 
 	/*
--- a/usr/src/uts/i86pc/os/hma.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/hma.c	Thu Nov 26 19:50:37 2020 +0800
@@ -101,6 +101,7 @@
 		(void) hma_vmx_init();
 		break;
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		(void) hma_svm_init();
 		break;
 	default:
@@ -121,6 +122,7 @@
 		is_ready = hma_vmx_ready;
 		break;
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		is_ready = hma_svm_ready;
 		break;
 	default:
--- a/usr/src/uts/i86pc/os/startup.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/i86pc/os/startup.c	Thu Nov 26 19:50:37 2020 +0800
@@ -3211,6 +3211,7 @@
 	switch (x86_vendor) {
 	case X86_VENDOR_Intel:
 	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_TM:
 		if (is_x86_feature(x86_featureset, X86FSET_CMOV)) {
 			/*
--- a/usr/src/uts/intel/ia32/os/cpc_subr.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/intel/ia32/os/cpc_subr.c	Thu Nov 26 19:50:37 2020 +0800
@@ -140,7 +140,8 @@
 					strands_perfmon_shared = 1;
 				}
 			}
-		} else if (cpuid_getvendor(cpu[0]) == X86_VENDOR_AMD) {
+		} else if (cpuid_getvendor(cpu[0]) == X86_VENDOR_AMD ||
+		    cpuid_getvendor(cpu[0]) == X86_VENDOR_HYGON) {
 			/*
 			 * On AMD systems with HT, all of the performance
 			 * monitors exist on a per-logical CPU basis.
--- a/usr/src/uts/intel/io/amdzen/amdzen.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/intel/io/amdzen/amdzen.c	Thu Nov 26 19:50:37 2020 +0800
@@ -624,7 +624,7 @@
 		return (DDI_WALK_CONTINUE);
 	}
 
-	if (vid != AMDZEN_PCI_VID_AMD) {
+	if (vid != AMDZEN_PCI_VID_AMD && vid != AMDZEN_PCI_VID_HYGON) {
 		return (DDI_WALK_CONTINUE);
 	}
 
@@ -737,9 +737,10 @@
 		return (DDI_FAILURE);
 	}
 
-	if (vid != AMDZEN_PCI_VID_AMD) {
-		dev_err(dip, CE_WARN, "expected AMD vendor ID (0x%x), found "
-		    "0x%x", AMDZEN_PCI_VID_AMD, vid);
+	if (vid != AMDZEN_PCI_VID_AMD && vid != AMDZEN_PCI_VID_HYGON) {
+		dev_err(dip, CE_WARN, "expected vendor ID (0x%x), found 0x%x",
+		    cpuid_getvendor(CPU) == X86_VENDOR_HYGON ?
+		    AMDZEN_PCI_VID_HYGON : AMDZEN_PCI_VID_AMD, vid);
 		return (DDI_FAILURE);
 	}
 
@@ -996,7 +997,8 @@
 {
 	int ret;
 
-	if (cpuid_getvendor(CPU) != X86_VENDOR_AMD) {
+	if (cpuid_getvendor(CPU) != X86_VENDOR_AMD &&
+	    cpuid_getvendor(CPU) != X86_VENDOR_HYGON) {
 		return (ENOTSUP);
 	}
 
--- a/usr/src/uts/intel/io/amdzen/amdzen.h	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/intel/io/amdzen/amdzen.h	Thu Nov 26 19:50:37 2020 +0800
@@ -200,6 +200,11 @@
  */
 #define	AMDZEN_PCI_VID_AMD	0x1022
 
+/*
+ * Hygon PCI ID for reference
+ */
+#define	AMDZEN_PCI_VID_HYGON	0x1d94
+
 typedef enum {
 	AMDZEN_STUB_TYPE_DF,
 	AMDZEN_STUB_TYPE_NB
--- a/usr/src/uts/intel/pcbe/opteron_pcbe.c	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/intel/pcbe/opteron_pcbe.c	Thu Nov 26 19:50:37 2020 +0800
@@ -547,7 +547,8 @@
 	 * loads this module based on its name in the module directory, but it
 	 * could have been renamed.
 	 */
-	if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf)
+	if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
+	    cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
 		return (-1);
 
 	if (amd_family == 0xf) {
@@ -556,7 +557,9 @@
 		    "AMD Opteron & Athlon64");
 	} else {
 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
-		    "AMD Family %02xh", amd_family);
+		    "%s Family %02xh",
+		    cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
+		    amd_family);
 	}
 
 	/*
@@ -598,7 +601,8 @@
 		amd_pcbe_cpuref = amd_fam_11h_bkdg;
 		amd_events = family_11h_events;
 		amd_generic_events = opt_generic_events;
-	} else if (amd_family == 0x17 && amd_model <= 0x2f) {
+	} else if ((amd_family == 0x17 && amd_model <= 0x2f) ||
+	    amd_family == 0x18) {
 		amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
 		amd_events = opteron_pcbe_f17h_zen1_events;
 		amd_generic_events = family_17h_zen1_papi_events;
--- a/usr/src/uts/intel/sys/x86_archext.h	Sun Dec 06 20:23:46 2020 +0200
+++ b/usr/src/uts/intel/sys/x86_archext.h	Thu Nov 26 19:50:37 2020 +0800
@@ -804,6 +804,9 @@
 #define	X86_VENDOR_NSC		10
 #define	X86_VENDORSTR_NSC	"Geode by NSC"
 
+#define	X86_VENDOR_HYGON	11
+#define	X86_VENDORSTR_HYGON	"HygonGenuine"
+
 /*
  * Vendor string max len + \0
  */
@@ -968,6 +971,12 @@
 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0009)
 
 /*
+ * Definitions for Hygon Family 0x18
+ */
+#define	X86_CHIPREV_HYGON_18_DN_A1 \
+	_X86_CHIPREV_MKREV(X86_VENDOR_HYGON, 0x18, 0x0001)
+
+/*
  * Various socket/package types, extended as the need to distinguish
  * a new type arises.  The top 8 byte identfies the vendor and the
  * remaining 24 bits describe 24 socket types.
@@ -1026,6 +1035,15 @@
 #define	X86_SOCKET_STRX4	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23)
 #define	X86_NUM_SOCKETS_AMD	0x24
 
+/*
+ * Hygon socket types
+ */
+#define	X86_SOCKET_SL1		_X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01)
+#define	X86_SOCKET_SL1R2	_X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02)
+#define	X86_SOCKET_DM1		_X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03)
+#define	X86_NUM_SOCKETS_HYGON	0x04
+
+#define	X86_NUM_SOCKETS		(X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON)
 
 /*
  * Definitions for Intel processor models. These are all for Family 6