Mercurial > illumos > illumos-gate
annotate usr/src/uts/intel/io/pci/pci_boot.c @ 13019:05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
author | Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM> |
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date | Tue, 03 Aug 2010 18:32:30 -0700 |
parents | 92e6427b7b70 |
children |
rev | line source |
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0 | 1 /* |
2 * CDDL HEADER START | |
3 * | |
4 * The contents of this file are subject to the terms of the | |
1494 | 5 * Common Development and Distribution License (the "License"). |
6 * You may not use this file except in compliance with the License. | |
0 | 7 * |
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
9 * or http://www.opensolaris.org/os/licensing. | |
10 * See the License for the specific language governing permissions | |
11 * and limitations under the License. | |
12 * | |
13 * When distributing Covered Code, include this CDDL HEADER in each | |
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
15 * If applicable, add the following below this CDDL HEADER, with the | |
16 * fields enclosed by brackets "[]" replaced with your own identifying | |
17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
18 * | |
19 * CDDL HEADER END | |
20 */ | |
21 /* | |
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22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 23 */ |
24 | |
25 #include <sys/types.h> | |
26 #include <sys/stat.h> | |
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27 #include <sys/sysmacros.h> |
0 | 28 #include <sys/sunndi.h> |
29 #include <sys/pci.h> | |
30 #include <sys/pci_impl.h> | |
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31 #include <sys/pcie_impl.h> |
0 | 32 #include <sys/memlist.h> |
33 #include <sys/bootconf.h> | |
881 | 34 #include <io/pci/mps_table.h> |
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35 #include <sys/pci_cfgacc.h> |
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36 #include <sys/pci_cfgspace.h> |
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37 #include <sys/pci_cfgspace_impl.h> |
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38 #include <sys/psw.h> |
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39 #include "../../../../common/pci/pci_strings.h" |
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40 #include <sys/apic.h> |
2435 | 41 #include <io/pciex/pcie_nvidia.h> |
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42 #include <sys/hotplug/pci/pciehpc_acpi.h> |
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43 #include <sys/acpi/acpi.h> |
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44 #include <sys/acpica.h> |
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45 #include <sys/iommulib.h> |
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46 #include <sys/devcache.h> |
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47 #include <sys/pci_cfgacc_x86.h> |
0 | 48 |
49 #define pci_getb (*pci_getb_func) | |
50 #define pci_getw (*pci_getw_func) | |
51 #define pci_getl (*pci_getl_func) | |
52 #define pci_putb (*pci_putb_func) | |
53 #define pci_putw (*pci_putw_func) | |
54 #define pci_putl (*pci_putl_func) | |
55 #define dcmn_err if (pci_boot_debug) cmn_err | |
56 | |
57 #define CONFIG_INFO 0 | |
58 #define CONFIG_UPDATE 1 | |
59 #define CONFIG_NEW 2 | |
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60 #define CONFIG_FIX 3 |
881 | 61 #define COMPAT_BUFSIZE 512 |
0 | 62 |
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63 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ |
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64 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ |
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65 /* round down to nearest power of two */ |
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66 #define P2LE(align) \ |
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67 { \ |
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68 int i = 0; \ |
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69 while (align >>= 1) \ |
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70 i ++; \ |
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71 align = 1 << i; \ |
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72 } \ |
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73 |
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74 /* for is_vga and list_is_vga_only */ |
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75 |
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76 enum io_mem { |
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77 IO, |
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78 MEM |
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79 }; |
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80 |
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81 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ |
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82 #define LPC_IO_CONTROL_REG_1 0x40 |
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83 #define AMD8111_ENABLENMI (uint8_t)0x80 |
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84 #define DEVID_AMD8111_LPC 0x7468 |
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85 |
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86 struct pci_fixundo { |
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87 uint8_t bus; |
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88 uint8_t dev; |
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89 uint8_t fn; |
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90 void (*undofn)(uint8_t, uint8_t, uint8_t); |
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91 struct pci_fixundo *next; |
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92 }; |
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93 |
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94 struct pci_devfunc { |
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95 struct pci_devfunc *next; |
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96 dev_info_t *dip; |
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97 uchar_t dev; |
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98 uchar_t func; |
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99 boolean_t reprogram; /* this device needs to be reprogrammed */ |
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100 }; |
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101 |
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102 extern int apic_nvidia_io_max; |
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103 extern int pseudo_isa; |
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104 extern int pci_bios_maxbus; |
0 | 105 static uchar_t max_dev_pci = 32; /* PCI standard */ |
106 int pci_boot_debug = 0; | |
107 extern struct memlist *find_bus_res(int, int); | |
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108 static struct pci_fixundo *undolist = NULL; |
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109 static int num_root_bus = 0; /* count of root buses */ |
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110 extern volatile int acpi_resource_discovery; |
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111 extern uint64_t mcfg_mem_base; |
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112 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t); |
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113 extern dev_info_t *pcie_get_rc_dip(dev_info_t *); |
0 | 114 |
115 /* | |
116 * Module prototypes | |
117 */ | |
118 static void enumerate_bus_devs(uchar_t bus, int config_op); | |
119 static void create_root_bus_dip(uchar_t bus); | |
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120 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, |
0 | 121 ushort_t, int); |
122 static void add_compatible(dev_info_t *, ushort_t, ushort_t, | |
881 | 123 ushort_t, ushort_t, uchar_t, uint_t, int); |
0 | 124 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); |
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125 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, |
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126 ushort_t); |
0 | 127 static void add_model_prop(dev_info_t *, uint_t); |
128 static void add_bus_range_prop(int); | |
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129 static void add_bus_slot_names_prop(int); |
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130 static void add_ranges_prop(int, int); |
0 | 131 static void add_bus_available_prop(int); |
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132 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); |
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133 static void fix_ppb_res(uchar_t, boolean_t); |
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134 static void alloc_res_array(); |
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135 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, |
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136 ushort_t deviceid); |
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137 static void pciex_slot_names_prop(dev_info_t *, ushort_t); |
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138 static void populate_bus_res(uchar_t bus); |
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139 static void memlist_remove_list(struct memlist **list, |
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140 struct memlist *remove_list); |
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141 static boolean_t is_pcie_platform(void); |
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142 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t); |
0 | 143 |
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144 static void pci_scan_bbn(void); |
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145 static int pci_unitaddr_cache_valid(void); |
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146 static int pci_bus_unitaddr(int); |
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147 static void pci_unitaddr_cache_create(void); |
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148 |
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149 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); |
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150 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); |
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151 static void pci_cache_free_list(nvf_handle_t); |
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152 |
1494 | 153 extern int pci_slot_names_prop(int, char *, int); |
154 | |
4018 | 155 /* set non-zero to force PCI peer-bus renumbering */ |
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156 int pci_bus_always_renumber = 0; |
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157 |
0 | 158 /* |
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159 * used to register ISA resource usage which must not be made |
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160 * "available" from other PCI node' resource maps |
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161 */ |
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162 static struct { |
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163 struct memlist *io_used; |
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164 struct memlist *mem_used; |
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165 } isa_res; |
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166 |
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167 /* |
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168 * PCI unit-address cache management |
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169 */ |
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170 static nvf_ops_t pci_unitaddr_cache_ops = { |
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171 "/etc/devices/pci_unitaddr_persistent", /* path to cache */ |
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172 pci_cache_unpack_nvlist, /* read in nvlist form */ |
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173 pci_cache_pack_nvlist, /* convert to nvlist form */ |
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174 pci_cache_free_list, /* free data list */ |
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175 NULL /* write complete callback */ |
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176 }; |
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177 |
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178 typedef struct { |
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179 list_node_t pua_nodes; |
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180 int pua_index; |
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181 int pua_addr; |
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182 } pua_node_t; |
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183 |
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184 nvf_handle_t puafd_handle; |
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185 int pua_cache_valid = 0; |
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186 |
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187 |
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188 /*ARGSUSED*/ |
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189 static ACPI_STATUS |
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190 pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) |
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191 { |
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192 ACPI_BUFFER rb; |
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193 ACPI_OBJECT ro; |
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194 ACPI_DEVICE_INFO *adi; |
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195 int busnum; |
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196 |
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197 /* |
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198 * Use AcpiGetObjectInfo() to find the device _HID |
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199 * If not a PCI root-bus, ignore this device and continue |
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200 * the walk |
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201 */ |
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202 if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &adi))) |
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203 return (AE_OK); |
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204 |
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205 if (!(adi->Valid & ACPI_VALID_HID)) { |
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206 AcpiOsFree(adi); |
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207 return (AE_OK); |
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208 } |
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209 |
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210 if (strncmp(adi->HardwareId.String, PCI_ROOT_HID_STRING, |
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211 sizeof (PCI_ROOT_HID_STRING)) && |
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212 strncmp(adi->HardwareId.String, PCI_EXPRESS_ROOT_HID_STRING, |
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213 sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { |
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214 AcpiOsFree(adi); |
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215 return (AE_OK); |
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216 } |
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217 |
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218 AcpiOsFree(adi); |
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219 |
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220 /* |
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221 * XXX: ancient Big Bear broken _BBN will result in two |
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222 * bus 0 _BBNs being found, so we need to handle duplicate |
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223 * bus 0 gracefully. However, broken _BBN does not |
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224 * hide a childless root-bridge so no need to work-around it |
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225 * here |
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226 */ |
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227 rb.Pointer = &ro; |
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228 rb.Length = sizeof (ro); |
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229 if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", |
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230 NULL, &rb, ACPI_TYPE_INTEGER))) { |
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231 busnum = ro.Integer.Value; |
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232 |
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233 /* |
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234 * Ignore invalid _BBN return values here (rather |
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235 * than panic) and emit a warning; something else |
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236 * may suffer failure as a result of the broken BIOS. |
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237 */ |
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238 if ((busnum < 0) || (busnum > pci_bios_maxbus)) { |
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239 dcmn_err(CE_NOTE, |
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240 "pci_process_acpi_device: invalid _BBN 0x%x\n", |
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241 busnum); |
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242 return (AE_CTRL_DEPTH); |
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243 } |
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244 |
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245 /* PCI with valid _BBN */ |
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246 if (pci_bus_res[busnum].par_bus == (uchar_t)-1 && |
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247 pci_bus_res[busnum].dip == NULL) |
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248 create_root_bus_dip((uchar_t)busnum); |
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249 return (AE_CTRL_DEPTH); |
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250 } |
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251 |
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252 /* PCI and no _BBN, continue walk */ |
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253 return (AE_OK); |
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254 } |
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255 |
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256 /* |
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257 * Scan the ACPI namespace for all top-level instances of _BBN |
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258 * in order to discover childless root-bridges (which enumeration |
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259 * may not find; root-bridges are inferred by the existence of |
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260 * children). This scan should find all root-bridges that have |
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261 * been enumerated, and any childless root-bridges not enumerated. |
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262 * Root-bridge for bus 0 may not have a _BBN object. |
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263 */ |
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264 static void |
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265 pci_scan_bbn() |
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266 { |
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267 void *rv; |
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268 |
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269 (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); |
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270 } |
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271 |
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272 static void |
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273 pci_unitaddr_cache_init(void) |
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274 { |
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275 |
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276 puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); |
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277 ASSERT(puafd_handle); |
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278 |
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279 list_create(nvf_list(puafd_handle), sizeof (pua_node_t), |
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280 offsetof(pua_node_t, pua_nodes)); |
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281 |
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282 rw_enter(nvf_lock(puafd_handle), RW_WRITER); |
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283 (void) nvf_read_file(puafd_handle); |
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284 rw_exit(nvf_lock(puafd_handle)); |
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285 } |
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286 |
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287 /* |
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288 * Format of /etc/devices/pci_unitaddr_persistent: |
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289 * |
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290 * The persistent record of unit-address assignments contains |
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291 * a list of name/value pairs, where name is a string representation |
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292 * of the "index value" of the PCI root-bus and the value is |
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293 * the assigned unit-address. |
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294 * |
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295 * The "index value" is simply the zero-based index of the PCI |
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296 * root-buses ordered by physical bus number; first PCI bus is 0, |
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297 * second is 1, and so on. |
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298 */ |
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299 |
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300 /*ARGSUSED*/ |
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301 static int |
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302 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) |
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303 { |
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304 long index; |
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305 int32_t value; |
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306 nvpair_t *np; |
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307 pua_node_t *node; |
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308 |
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309 np = NULL; |
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310 while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { |
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311 /* name of nvpair is index value */ |
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312 if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) |
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313 continue; |
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314 |
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315 if (nvpair_value_int32(np, &value) != 0) |
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316 continue; |
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317 |
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318 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); |
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319 node->pua_index = index; |
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320 node->pua_addr = value; |
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321 list_insert_tail(nvf_list(hdl), node); |
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322 } |
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323 |
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324 pua_cache_valid = 1; |
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325 return (DDI_SUCCESS); |
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326 } |
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327 |
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328 static int |
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329 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) |
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330 { |
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331 int rval; |
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332 nvlist_t *nvl, *sub_nvl; |
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333 list_t *listp; |
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334 pua_node_t *pua; |
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335 char buf[13]; |
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336 |
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337 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); |
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338 |
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339 rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); |
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340 if (rval != DDI_SUCCESS) { |
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341 nvf_error("%s: nvlist alloc error %d\n", |
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342 nvf_cache_name(hdl), rval); |
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343 return (DDI_FAILURE); |
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344 } |
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345 |
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346 sub_nvl = NULL; |
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347 rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); |
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348 if (rval != DDI_SUCCESS) |
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349 goto error; |
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350 |
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351 listp = nvf_list(hdl); |
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352 for (pua = list_head(listp); pua != NULL; |
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353 pua = list_next(listp, pua)) { |
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354 (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); |
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355 rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); |
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356 if (rval != DDI_SUCCESS) |
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6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
357 goto error; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
358 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
359 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
360 rval = nvlist_add_nvlist(nvl, "table", sub_nvl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
361 if (rval != DDI_SUCCESS) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
362 goto error; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
363 nvlist_free(sub_nvl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
364 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
365 *ret_nvl = nvl; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
366 return (DDI_SUCCESS); |
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6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
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|
367 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
368 error: |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
369 if (sub_nvl) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
370 nvlist_free(sub_nvl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
371 ASSERT(nvl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
372 nvlist_free(nvl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
373 *ret_nvl = NULL; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
374 return (DDI_FAILURE); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
375 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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diff
changeset
|
376 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
377 static void |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
378 pci_cache_free_list(nvf_handle_t hdl) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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diff
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|
379 { |
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6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
380 list_t *listp; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
381 pua_node_t *pua; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
382 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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diff
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|
383 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
384 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
385 listp = nvf_list(hdl); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
386 for (pua = list_head(listp); pua != NULL; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
387 pua = list_next(listp, pua)) { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
388 list_remove(listp, pua); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
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10384
diff
changeset
|
389 kmem_free(pua, sizeof (pua_node_t)); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
390 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
391 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
392 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
393 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
394 static int |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
395 pci_unitaddr_cache_valid(void) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
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|
396 { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
397 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
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|
398 /* read only, no need for rw lock */ |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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10384
diff
changeset
|
399 return (pua_cache_valid); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
400 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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parents:
10384
diff
changeset
|
401 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
402 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
403 static int |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
404 pci_bus_unitaddr(int index) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
405 { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
406 pua_node_t *pua; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
407 list_t *listp; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
408 int addr; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
409 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
410 rw_enter(nvf_lock(puafd_handle), RW_READER); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
411 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
412 addr = -1; /* default return if no match */ |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
413 listp = nvf_list(puafd_handle); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
414 for (pua = list_head(listp); pua != NULL; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
415 pua = list_next(listp, pua)) { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
416 if (pua->pua_index == index) { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
417 addr = pua->pua_addr; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
418 break; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
419 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
420 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
421 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
422 rw_exit(nvf_lock(puafd_handle)); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
423 return (addr); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
424 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
425 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
426 static void |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
427 pci_unitaddr_cache_create(void) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
428 { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
429 int i, index; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
430 pua_node_t *node; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
431 list_t *listp; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
432 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
433 rw_enter(nvf_lock(puafd_handle), RW_WRITER); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
434 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
435 index = 0; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
436 listp = nvf_list(puafd_handle); |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
437 for (i = 0; i <= pci_bios_maxbus; i++) { |
10552
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
438 /* skip non-root (peer) PCI busses */ |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
439 if ((pci_bus_res[i].par_bus != (uchar_t)-1) || |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
440 (pci_bus_res[i].dip == NULL)) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
441 continue; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
442 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
443 node->pua_index = index++; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
444 node->pua_addr = pci_bus_res[i].root_addr; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
445 list_insert_tail(listp, node); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
446 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
447 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
448 (void) nvf_mark_dirty(puafd_handle); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
449 rw_exit(nvf_lock(puafd_handle)); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
450 nvf_wake_daemon(); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
451 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
452 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
453 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
454 /* |
0 | 455 * Enumerate all PCI devices |
456 */ | |
457 void | |
10552
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
458 pci_setup_tree(void) |
0 | 459 { |
8668
b2550ea1cc76
6797893 PCI bus count from BIOS induces infinite loop in pci_setup_tree due to uint8_t overflow
james north - Sun Microsystems - Austin United States <James.North@Sun.COM>
parents:
8655
diff
changeset
|
460 uint_t i, root_bus_addr = 0; |
0 | 461 |
11245
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462 /* |
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463 * enable mem-mapped pci config space accessing, |
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464 * if failed to do so during early boot |
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465 */ |
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466 if ((mcfg_mem_base == NULL) && is_pcie_platform()) |
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467 mcfg_mem_base = 0xE0000000; |
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468 |
397
0f40382f2a76
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469 alloc_res_array(); |
10804
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470 for (i = 0; i <= pci_bios_maxbus; i++) { |
0 | 471 pci_bus_res[i].par_bus = (uchar_t)-1; |
472 pci_bus_res[i].root_addr = (uchar_t)-1; | |
473 pci_bus_res[i].sub_bus = i; | |
474 } | |
475 | |
476 pci_bus_res[0].root_addr = root_bus_addr++; | |
477 create_root_bus_dip(0); | |
478 enumerate_bus_devs(0, CONFIG_INFO); | |
479 | |
480 /* | |
481 * Now enumerate peer busses | |
482 * | |
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483 * We loop till pci_bios_maxbus. On most systems, there is |
0 | 484 * one more bus at the high end, which implements the ISA |
485 * compatibility bus. We don't care about that. | |
486 * | |
487 * Note: In the old (bootconf) enumeration, the peer bus | |
488 * address did not use the bus number, and there were | |
489 * too many peer busses created. The root_bus_addr is | |
490 * used to maintain the old peer bus address assignment. | |
491 * However, we stop enumerating phantom peers with no | |
492 * device below. | |
493 */ | |
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494 for (i = 1; i <= pci_bios_maxbus; i++) { |
0 | 495 if (pci_bus_res[i].dip == NULL) { |
496 pci_bus_res[i].root_addr = root_bus_addr++; | |
497 } | |
498 enumerate_bus_devs(i, CONFIG_INFO); | |
603
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499 |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
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500 /* add slot-names property for named pci hot-plug slots */ |
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501 add_bus_slot_names_prop(i); |
0 | 502 } |
503 | |
504 } | |
505 | |
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506 /* |
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507 * >0 = present, 0 = not present, <0 = error |
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508 */ |
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509 static int |
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510 pci_bbn_present(int bus) |
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511 { |
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512 ACPI_HANDLE hdl; |
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513 int rv; |
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514 |
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6324138 Internal pci bus numbering should be independent of bios enumeration order
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515 /* no dip means no _BBN */ |
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516 if (pci_bus_res[bus].dip == NULL) |
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517 return (0); |
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518 |
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519 rv = -1; /* default return value in case of error below */ |
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520 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { |
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521 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { |
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522 case AE_OK: |
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523 rv = 1; |
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524 break; |
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525 case AE_NOT_FOUND: |
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526 rv = 0; |
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527 break; |
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528 default: |
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529 break; |
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530 } |
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|
531 } |
1413
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diff
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|
532 |
7851
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parents:
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diff
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|
533 return (rv); |
1413
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6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
534 } |
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6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
535 |
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6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
536 /* |
5c66154eab3c
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|
537 * Return non-zero if any PCI bus in the system has an associated |
5c66154eab3c
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|
538 * _BBN object, 0 otherwise. |
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6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
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|
539 */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
540 static int |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
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|
541 pci_roots_have_bbn(void) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
542 { |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
543 int i; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
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|
544 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
545 /* |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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changeset
|
546 * Scan the PCI busses and look for at least 1 _BBN |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
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|
547 */ |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
548 for (i = 0; i <= pci_bios_maxbus; i++) { |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
549 /* skip non-root (peer) PCI busses */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
550 if (pci_bus_res[i].par_bus != (uchar_t)-1) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
1007
diff
changeset
|
551 continue; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
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diff
changeset
|
552 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
553 if (pci_bbn_present(i) > 0) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
1007
diff
changeset
|
554 return (1); |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
555 } |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
556 return (0); |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
557 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
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diff
changeset
|
558 } |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
559 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
560 /* |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
561 * return non-zero if the machine is one on which we renumber |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
562 * the internal pci unit-addresses |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
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diff
changeset
|
563 */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
564 static int |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
565 pci_bus_renumber() |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
566 { |
4018 | 567 ACPI_TABLE_HEADER *fadt; |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
568 |
4018 | 569 if (pci_bus_always_renumber) |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
570 return (1); |
4018 | 571 |
572 /* get the FADT */ | |
7851
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573 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != |
e828bbb1689c
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diff
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|
574 AE_OK) |
1413
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6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
575 return (0); |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
576 |
4018 | 577 /* compare OEM Table ID to "SUNm31" */ |
578 if (strncmp("SUNm31", fadt->OemId, 6)) | |
579 return (0); | |
580 else | |
581 return (1); | |
1413
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6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
582 } |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
583 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
584 /* |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
585 * Initial enumeration of the physical PCI bus hierarchy can |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
586 * leave 'gaps' in the order of peer PCI bus unit-addresses. |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
587 * Systems with more than one peer PCI bus *must* have an ACPI |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
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changeset
|
588 * _BBN object associated with each peer bus; use the presence |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
589 * of this object to remove gaps in the numbering of the peer |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
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diff
changeset
|
590 * PCI bus unit-addresses - only peer busses with an associated |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
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diff
changeset
|
591 * _BBN are counted. |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
592 */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
593 static void |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
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diff
changeset
|
594 pci_renumber_root_busses(void) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
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diff
changeset
|
595 { |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
596 int pci_regs[] = {0, 0, 0}; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
597 int i, root_addr = 0; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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diff
changeset
|
598 |
4018 | 599 /* |
600 * Currently, we only enable the re-numbering on specific | |
601 * Sun machines; this is a work-around for the more complicated | |
602 * issue of upgrade changing physical device paths | |
603 */ | |
1413
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6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
604 if (!pci_bus_renumber()) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
605 return; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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parents:
1007
diff
changeset
|
606 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
607 /* |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
608 * If we find no _BBN objects at all, we either don't need |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
609 * to do anything or can't do anything anyway |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
610 */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
611 if (!pci_roots_have_bbn()) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
612 return; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
613 |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
614 for (i = 0; i <= pci_bios_maxbus; i++) { |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
615 /* skip non-root (peer) PCI busses */ |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
616 if (pci_bus_res[i].par_bus != (uchar_t)-1) |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
617 continue; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
618 |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
619 if (pci_bbn_present(i) < 1) { |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
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diff
changeset
|
620 pci_bus_res[i].root_addr = (uchar_t)-1; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
621 continue; |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
622 } |
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
623 |
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624 ASSERT(pci_bus_res[i].dip != NULL); |
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625 if (pci_bus_res[i].root_addr != root_addr) { |
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626 /* update reg property for node */ |
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627 pci_bus_res[i].root_addr = root_addr; |
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628 pci_regs[0] = pci_bus_res[i].root_addr; |
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629 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, |
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630 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); |
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631 } |
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632 root_addr++; |
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633 } |
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634 } |
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635 |
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636 void |
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637 pci_register_isa_resources(int type, uint32_t base, uint32_t size) |
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638 { |
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639 (void) memlist_insert( |
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640 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, |
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641 base, size); |
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642 } |
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643 |
4517 | 644 /* |
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645 * Remove the resources which are already used by devices under a subtractive |
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646 * bridge from the bus's resources lists, because they're not available, and |
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647 * shouldn't be allocated to other buses. This is necessary because tracking |
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648 * resources for subtractive bridges is not complete. (Subtractive bridges only |
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649 * track some of their claimed resources, not "the rest of the address space" as |
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650 * they should, so that allocation to peer non-subtractive PPBs is easier. We |
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651 * need a fully-capable global resource allocator). |
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652 */ |
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653 static void |
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654 remove_subtractive_res() |
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655 { |
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656 int i, j; |
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657 struct memlist *list; |
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658 |
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659 for (i = 0; i <= pci_bios_maxbus; i++) { |
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660 if (pci_bus_res[i].subtractive) { |
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661 /* remove used io ports */ |
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662 list = pci_bus_res[i].io_used; |
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663 while (list) { |
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664 for (j = 0; j <= pci_bios_maxbus; j++) |
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665 (void) memlist_remove( |
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666 &pci_bus_res[j].io_avail, |
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667 list->ml_address, list->ml_size); |
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668 list = list->ml_next; |
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669 } |
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670 /* remove used mem resource */ |
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671 list = pci_bus_res[i].mem_used; |
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672 while (list) { |
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673 for (j = 0; j <= pci_bios_maxbus; j++) { |
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674 (void) memlist_remove( |
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675 &pci_bus_res[j].mem_avail, |
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676 list->ml_address, list->ml_size); |
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677 (void) memlist_remove( |
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678 &pci_bus_res[j].pmem_avail, |
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679 list->ml_address, list->ml_size); |
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680 } |
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681 list = list->ml_next; |
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682 } |
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683 /* remove used prefetchable mem resource */ |
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684 list = pci_bus_res[i].pmem_used; |
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685 while (list) { |
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686 for (j = 0; j <= pci_bios_maxbus; j++) { |
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687 (void) memlist_remove( |
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688 &pci_bus_res[j].pmem_avail, |
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689 list->ml_address, list->ml_size); |
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690 (void) memlist_remove( |
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691 &pci_bus_res[j].mem_avail, |
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692 list->ml_address, list->ml_size); |
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693 } |
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694 list = list->ml_next; |
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695 } |
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696 } |
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697 } |
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698 } |
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699 |
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700 /* |
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701 * Set up (or complete the setup of) the bus_avail resource list |
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702 */ |
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703 static void |
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704 setup_bus_res(int bus) |
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705 { |
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706 uchar_t par_bus; |
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707 |
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708 if (pci_bus_res[bus].dip == NULL) /* unused bus */ |
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709 return; |
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710 |
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711 /* |
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712 * Set up bus_avail if not already filled in by populate_bus_res() |
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713 */ |
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714 if (pci_bus_res[bus].bus_avail == NULL) { |
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|
715 ASSERT(pci_bus_res[bus].sub_bus >= bus); |
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716 memlist_insert(&pci_bus_res[bus].bus_avail, bus, |
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717 pci_bus_res[bus].sub_bus - bus + 1); |
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718 } |
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719 |
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720 ASSERT(pci_bus_res[bus].bus_avail != NULL); |
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721 |
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722 /* |
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723 * Remove resources from parent bus node if this is not a |
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724 * root bus. |
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725 */ |
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726 par_bus = pci_bus_res[bus].par_bus; |
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727 if (par_bus != (uchar_t)-1) { |
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728 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); |
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729 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, |
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|
730 pci_bus_res[bus].bus_avail); |
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731 } |
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732 |
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733 /* remove self from bus_avail */; |
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|
734 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); |
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735 } |
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736 |
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737 static uint64_t |
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738 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) |
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|
739 { |
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|
740 uint64_t addr = 0; |
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|
741 uchar_t res_bus; |
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|
742 |
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|
743 /* |
8420
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Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
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|
744 * Skip root(peer) buses in multiple-root-bus systems when |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
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parents:
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diff
changeset
|
745 * ACPI resource discovery was not successfully done. |
6095
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|
746 */ |
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|
747 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
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diff
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|
748 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) |
5149
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6573171 unnecessary I/O resource warnings on some machines
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|
749 return (0); |
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jveta
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|
750 |
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|
751 res_bus = parbus; |
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|
752 while (pci_bus_res[res_bus].subtractive) { |
10251
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|
753 if (pci_bus_res[res_bus].io_avail) |
6095
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|
754 break; |
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|
755 res_bus = pci_bus_res[res_bus].par_bus; |
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|
756 if (res_bus == (uchar_t)-1) |
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|
757 break; /* root bus already */ |
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|
758 } |
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changeset
|
759 |
10251
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|
760 if (pci_bus_res[res_bus].io_avail) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
761 addr = memlist_find(&pci_bus_res[res_bus].io_avail, |
6095
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|
762 size, align); |
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|
763 if (addr) { |
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|
764 memlist_insert(&pci_bus_res[res_bus].io_used, |
6095
ffd81788f184
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|
765 addr, size); |
8420
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parents:
8215
diff
changeset
|
766 |
6095
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|
767 /* free the old resource */ |
10251
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changeset
|
768 memlist_free_all(&pci_bus_res[bus].io_avail); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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parents:
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diff
changeset
|
769 memlist_free_all(&pci_bus_res[bus].io_used); |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
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diff
changeset
|
770 |
6095
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diff
changeset
|
771 /* add the new resource */ |
10251
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diff
changeset
|
772 memlist_insert(&pci_bus_res[bus].io_avail, addr, size); |
6095
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|
773 } |
5149
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jveta
parents:
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changeset
|
774 } |
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jveta
parents:
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diff
changeset
|
775 |
6095
ffd81788f184
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diff
changeset
|
776 return (addr); |
ffd81788f184
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changeset
|
777 } |
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diff
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|
778 |
ffd81788f184
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diff
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|
779 static uint64_t |
ffd81788f184
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|
780 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) |
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|
781 { |
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diff
changeset
|
782 uint64_t addr = 0; |
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changeset
|
783 uchar_t res_bus; |
5149
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6573171 unnecessary I/O resource warnings on some machines
jveta
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diff
changeset
|
784 |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
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parents:
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diff
changeset
|
785 /* |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
786 * Skip root(peer) buses in multiple-root-bus systems when |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
787 * ACPI resource discovery was not successfully done. |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
788 */ |
6095
ffd81788f184
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gs150176
parents:
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diff
changeset
|
789 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
790 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
791 return (0); |
f292192855b3
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jveta
parents:
4876
diff
changeset
|
792 |
6095
ffd81788f184
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diff
changeset
|
793 res_bus = parbus; |
ffd81788f184
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diff
changeset
|
794 while (pci_bus_res[res_bus].subtractive) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
795 if (pci_bus_res[res_bus].mem_avail) |
6095
ffd81788f184
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parents:
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diff
changeset
|
796 break; |
ffd81788f184
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diff
changeset
|
797 res_bus = pci_bus_res[res_bus].par_bus; |
ffd81788f184
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diff
changeset
|
798 if (res_bus == (uchar_t)-1) |
ffd81788f184
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gs150176
parents:
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diff
changeset
|
799 break; /* root bus already */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
800 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
801 |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
802 if (pci_bus_res[res_bus].mem_avail) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
803 addr = memlist_find(&pci_bus_res[res_bus].mem_avail, |
6095
ffd81788f184
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gs150176
parents:
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diff
changeset
|
804 size, align); |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
805 if (addr) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
806 memlist_insert(&pci_bus_res[res_bus].mem_used, |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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parents:
5156
diff
changeset
|
807 addr, size); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
808 (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
809 addr, size); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
810 |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
811 /* free the old resource */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
812 memlist_free_all(&pci_bus_res[bus].mem_avail); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
813 memlist_free_all(&pci_bus_res[bus].mem_used); |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
814 |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
815 /* add the new resource */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
816 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); |
6095
ffd81788f184
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diff
changeset
|
817 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
818 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
819 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
820 return (addr); |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
821 } |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
822 |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
823 /* |
7987
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
824 * given a cap_id, return its cap_id location in config space |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
825 */ |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
826 static int |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
827 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
828 { |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
829 uint8_t curcap, cap_id_loc; |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
830 uint16_t status; |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
831 int location = -1; |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
832 |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
833 /* |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
834 * Need to check the Status register for ECP support first. |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
835 * Also please note that for type 1 devices, the |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
836 * offset could change. Should support type 1 next. |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
837 */ |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
838 status = pci_getw(bus, dev, func, PCI_CONF_STAT); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
839 if (!(status & PCI_STAT_CAP)) { |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
840 return (-1); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
841 } |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
842 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
843 |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
844 /* Walk the list of capabilities */ |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
845 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
846 curcap = pci_getb(bus, dev, func, cap_id_loc); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
847 |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
848 if (curcap == cap_id) { |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
849 location = cap_id_loc; |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
850 break; |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
851 } |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
852 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
853 } |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
854 return (location); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
855 } |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
856 |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
857 /* |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
858 * Does this resource element live in the legacy VGA range? |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
859 */ |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
860 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
861 int |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
862 is_vga(struct memlist *elem, enum io_mem io) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
863 { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
864 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
865 if (io == IO) { |
11474
857f9db4ef05
4517853 debug.h should include macros to assert implication and equivalence
Jonathan Adams <Jonathan.Adams@Sun.COM>
parents:
11327
diff
changeset
|
866 if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) || |
857f9db4ef05
4517853 debug.h should include macros to assert implication and equivalence
Jonathan Adams <Jonathan.Adams@Sun.COM>
parents:
11327
diff
changeset
|
867 (elem->ml_address == 0x3c0 && elem->ml_size == 0x20)) |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
868 return (1); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
869 } else { |
11474
857f9db4ef05
4517853 debug.h should include macros to assert implication and equivalence
Jonathan Adams <Jonathan.Adams@Sun.COM>
parents:
11327
diff
changeset
|
870 if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000) |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
871 return (1); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
872 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
873 return (0); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
874 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
875 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
876 /* |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
877 * Does this entire resource list consist only of legacy VGA resources? |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
878 */ |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
879 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
880 int |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
881 list_is_vga_only(struct memlist *l, enum io_mem io) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
882 { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
883 do { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
884 if (!is_vga(l, io)) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
885 return (0); |
11474
857f9db4ef05
4517853 debug.h should include macros to assert implication and equivalence
Jonathan Adams <Jonathan.Adams@Sun.COM>
parents:
11327
diff
changeset
|
886 } while ((l = l->ml_next) != NULL); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
887 return (1); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
888 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
889 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
890 /* |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
891 * Assign valid resources to unconfigured pci(e) bridges. We are trying |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
892 * to reprogram the bridge when its |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
893 * i) SECBUS == SUBBUS || |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
894 * ii) IOBASE > IOLIM || |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
895 * iii) MEMBASE > MEMLIM |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
896 * This must be done after one full pass through the PCI tree to collect |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
897 * all BIOS-configured resources, so that we know what resources are |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
898 * free and available to assign to the unconfigured PPBs. |
4517 | 899 */ |
900 static void | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
901 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) |
4517 | 902 { |
903 uchar_t bus, dev, func; | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
904 uchar_t parbus, subbus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
905 uint_t io_base, io_limit, mem_base, mem_limit; |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
906 uint_t io_size, mem_size, io_align, mem_align; |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
907 uint64_t addr = 0; |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
908 int *regp = NULL; |
4517 | 909 uint_t reglen; |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
910 int rv, cap_ptr, physhi; |
4517 | 911 dev_info_t *dip; |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
912 uint16_t cmd_reg; |
10293
ac02598ffdd8
6869654 pci_autoconfig: memory leak in memlist_alloc() in snv_121 on x86 on systems with zfs root
Dan Mick <Dan.Mick@Sun.COM>
parents:
10251
diff
changeset
|
913 struct memlist *list, *scratch_list; |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
914 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
915 /* skip root (peer) PCI busses */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
916 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
917 return; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
918 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
919 /* skip subtractive PPB when prog_sub is not TRUE */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
920 if (pci_bus_res[secbus].subtractive && !prog_sub) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
921 return; |
4517 | 922 |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
923 /* some entries may be empty due to discontiguous bus numbering */ |
4517 | 924 dip = pci_bus_res[secbus].dip; |
925 if (dip == NULL) | |
926 return; | |
927 | |
928 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, | |
929 "reg", ®p, ®len); | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
930 if (rv != DDI_PROP_SUCCESS || reglen == 0) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
931 return; |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
932 physhi = regp[0]; |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
933 ddi_prop_free(regp); |
4517 | 934 |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
935 func = (uchar_t)PCI_REG_FUNC_G(physhi); |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
936 dev = (uchar_t)PCI_REG_DEV_G(physhi); |
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
937 bus = (uchar_t)PCI_REG_BUS_G(physhi); |
4517 | 938 |
939 /* | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
940 * If pcie bridge, check to see if link is enabled |
4517 | 941 */ |
7987
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
942 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); |
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
943 if (cap_ptr != -1) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
944 cmd_reg = pci_getw(bus, dev, func, |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
945 (uint16_t)cap_ptr + PCIE_LINKCTL); |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
946 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
947 dcmn_err(CE_NOTE, |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
948 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
949 bus, dev, func); |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
950 return; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
951 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
952 } |
4517 | 953 |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
954 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
955 parbus = pci_bus_res[secbus].par_bus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
956 ASSERT(parbus == bus); |
6331
c8abf9eb141c
6677689 fix_ppb_res() needs to consider the Command register setting
gs150176
parents:
6211
diff
changeset
|
957 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); |
4517 | 958 |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
959 /* |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
960 * If we have a Cardbus bridge, but no bus space |
5149
f292192855b3
6573171 unnecessary I/O resource warnings on some machines
jveta
parents:
4876
diff
changeset
|
961 */ |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
962 if (pci_bus_res[secbus].num_cbb != 0 && |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
963 pci_bus_res[secbus].bus_avail == NULL) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
964 uchar_t range; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
965 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
966 /* normally there are 2 buses under a cardbus bridge */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
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diff
changeset
|
967 range = pci_bus_res[secbus].num_cbb * 2; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
968 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
969 /* |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
970 * Try to find and allocate a bus-range starting at subbus+1 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
971 * from the parent of the PPB. |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
972 */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
973 for (; range != 0; range--) { |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
974 if (memlist_find_with_startaddr( |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
975 &pci_bus_res[parbus].bus_avail, |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
976 subbus + 1, range, 1) != NULL) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
977 break; /* find bus range resource at parent */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
978 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
979 if (range != 0) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
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|
980 memlist_insert(&pci_bus_res[secbus].bus_avail, |
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981 subbus + 1, range); |
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982 subbus = subbus + range; |
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983 pci_bus_res[secbus].sub_bus = subbus; |
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984 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); |
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985 add_bus_range_prop(secbus); |
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986 |
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987 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" |
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988 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, |
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989 secbus, subbus); |
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990 } |
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991 } |
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993 /* |
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994 * Calculate required IO size and alignment |
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995 * If bus io_size is zero, we are going to assign 512 bytes per bus, |
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996 * otherwise, we'll choose the maximum value of such calculation and |
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997 * bus io_size. The size needs to be 4K aligned. |
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998 * |
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999 * We calculate alignment as the largest power of two less than the |
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1000 * the sum of all children's IO size requirements, because this will |
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1001 * align to the size of the largest child request within that size |
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1002 * (which is always a power of two). |
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1003 */ |
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1004 io_size = (subbus - secbus + 1) * 0x200; |
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1005 if (io_size < pci_bus_res[secbus].io_size) |
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1006 io_size = pci_bus_res[secbus].io_size; |
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1007 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); |
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1008 io_align = io_size; |
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1009 P2LE(io_align); |
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1010 |
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1011 /* |
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1012 * Calculate required MEM size and alignment |
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1013 * If bus mem_size is zero, we are going to assign 1M bytes per bus, |
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1014 * otherwise, we'll choose the maximum value of such calculation and |
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1015 * bus mem_size. The size needs to be 1M aligned. |
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1016 * |
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1017 * For the alignment, refer to the I/O comment above. |
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1018 */ |
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1019 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; |
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1020 if (mem_size < pci_bus_res[secbus].mem_size) { |
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1021 mem_size = pci_bus_res[secbus].mem_size; |
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1022 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); |
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1023 } |
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1024 mem_align = mem_size; |
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1025 P2LE(mem_align); |
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1026 |
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1027 /* Subtractive bridge */ |
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1028 if (pci_bus_res[secbus].subtractive && prog_sub) { |
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1029 /* |
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1030 * We program an arbitrary amount of I/O and memory resource |
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1031 * for the subtractive bridge so that child dynamic-resource- |
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1032 * allocating devices (such as Cardbus bridges) have a chance |
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1033 * of success. Until we have full-tree resource rebalancing, |
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1034 * dynamic resource allocation (thru busra) only looks at the |
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1035 * parent bridge, so all PPBs must have some allocatable |
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1036 * resource. For non-subtractive bridges, the resources come |
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1037 * from the base/limit register "windows", but subtractive |
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1038 * bridges often don't program those (since they don't need to). |
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1039 * If we put all the remaining resources on the subtractive |
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1040 * bridge, then peer non-subtractive bridges can't allocate |
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1041 * more space (even though this is probably most correct). |
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1042 * If we put the resources only on the parent, then allocations |
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1043 * from children of subtractive bridges will fail without |
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1044 * special-case code for bypassing the subtractive bridge. |
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1045 * This solution is the middle-ground temporary solution until |
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1046 * we have fully-capable resource allocation. |
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1047 */ |
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1048 |
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1049 /* |
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1050 * Add an arbitrary I/O resource to the subtractive PPB |
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1051 */ |
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1052 if (pci_bus_res[secbus].io_avail == NULL) { |
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1053 addr = get_parbus_io_res(parbus, secbus, io_size, |
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1054 io_align); |
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1055 if (addr) { |
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1056 add_ranges_prop(secbus, 1); |
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1057 pci_bus_res[secbus].io_reprogram = |
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1058 pci_bus_res[parbus].io_reprogram; |
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1059 |
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1060 cmn_err(CE_NOTE, "!add io-range on subtractive" |
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1061 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", |
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1062 bus, dev, func, (uint32_t)addr, |
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1063 (uint32_t)addr + io_size - 1); |
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1064 } |
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1065 } |
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1066 /* |
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1067 * Add an arbitrary memory resource to the subtractive PPB |
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1068 */ |
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1069 if (pci_bus_res[secbus].mem_avail == NULL) { |
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1070 addr = get_parbus_mem_res(parbus, secbus, mem_size, |
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1071 mem_align); |
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1072 if (addr) { |
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1073 add_ranges_prop(secbus, 1); |
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1074 pci_bus_res[secbus].mem_reprogram = |
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1075 pci_bus_res[parbus].mem_reprogram; |
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1076 |
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1077 cmn_err(CE_NOTE, "!add mem-range on " |
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1078 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", |
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1079 bus, dev, func, (uint32_t)addr, |
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1080 (uint32_t)addr + mem_size - 1); |
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1081 } |
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1082 } |
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1083 |
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1084 goto cmd_enable; |
4517 | 1085 } |
1086 | |
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1087 /* |
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1088 * Check to see if we need to reprogram I/O space, either because the |
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1089 * parent bus needed reprogramming and so do we, or because I/O space is |
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1090 * disabled in base/limit or command register. |
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1091 */ |
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1092 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); |
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1093 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); |
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1094 io_base = (io_base & 0xf0) << 8; |
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1095 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; |
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1096 |
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1097 /* Form list of all resources passed (avail + used) */ |
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1098 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); |
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1099 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); |
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1100 |
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1101 if ((pci_bus_res[parbus].io_reprogram || |
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1102 (io_base > io_limit) || |
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1103 (!(cmd_reg & PCI_COMM_IO))) && |
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1104 !list_is_vga_only(scratch_list, IO)) { |
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1105 if (pci_bus_res[secbus].io_used) { |
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1106 memlist_subsume(&pci_bus_res[secbus].io_used, |
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1107 &pci_bus_res[secbus].io_avail); |
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1108 } |
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1109 if (pci_bus_res[secbus].io_avail && |
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1110 (!pci_bus_res[parbus].io_reprogram) && |
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1111 (!pci_bus_res[parbus].subtractive)) { |
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1112 /* rechoose old io ports info */ |
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1113 list = pci_bus_res[secbus].io_avail; |
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1114 io_base = 0; |
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1115 do { |
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1116 if (is_vga(list, IO)) |
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1117 continue; |
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1118 if (!io_base) { |
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1119 io_base = (uint_t)list->ml_address; |
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1120 io_limit = (uint_t)list->ml_address + |
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1121 list->ml_size - 1; |
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1122 io_base = |
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1123 P2ALIGN(io_base, PPB_IO_ALIGNMENT); |
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1124 } else { |
11474
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1125 if (list->ml_address + list->ml_size > |
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1126 io_limit) { |
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1127 io_limit = (uint_t) |
11474
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1128 (list->ml_address + |
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1129 list->ml_size - 1); |
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1130 } |
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1131 } |
11474
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1132 } while ((list = list->ml_next) != NULL); |
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1133 /* 4K aligned */ |
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1134 io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; |
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1135 io_size = io_limit - io_base + 1; |
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1136 ASSERT(io_base <= io_limit); |
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1137 memlist_free_all(&pci_bus_res[secbus].io_avail); |
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1138 memlist_insert(&pci_bus_res[secbus].io_avail, |
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1139 io_base, io_size); |
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1140 memlist_insert(&pci_bus_res[parbus].io_used, |
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1141 io_base, io_size); |
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1142 (void) memlist_remove(&pci_bus_res[parbus].io_avail, |
8420
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|
1143 io_base, io_size); |
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1144 pci_bus_res[secbus].io_reprogram = B_TRUE; |
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1145 } else { |
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1146 /* get new io ports from parent bus */ |
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1147 addr = get_parbus_io_res(parbus, secbus, io_size, |
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diff
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|
1148 io_align); |
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1149 if (addr) { |
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1150 io_base = addr; |
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1151 io_limit = addr + io_size - 1; |
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1152 pci_bus_res[secbus].io_reprogram = B_TRUE; |
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1153 } |
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1154 } |
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1155 if (pci_bus_res[secbus].io_reprogram) { |
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|
1156 /* reprogram PPB regs */ |
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1157 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, |
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1158 (uchar_t)((io_base>>8) & 0xf0)); |
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1159 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, |
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1160 (uchar_t)((io_limit>>8) & 0xf0)); |
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|
1161 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); |
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|
1162 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); |
8420
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|
1163 add_ranges_prop(secbus, 1); |
6095
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|
1164 |
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1165 cmn_err(CE_NOTE, "!reprogram io-range on" |
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|
1166 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", |
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|
1167 bus, dev, func, io_base, io_limit); |
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|
1168 } |
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|
1169 } |
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|
1170 memlist_free_all(&scratch_list); |
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|
1171 |
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|
1172 /* |
6331
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|
1173 * Check memory space as we did I/O space. |
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|
1174 */ |
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|
1175 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); |
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|
1176 mem_base = (mem_base & 0xfff0) << 16; |
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|
1177 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); |
6331
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|
1178 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; |
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|
1179 |
10293
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|
1180 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); |
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|
1181 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); |
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|
1182 |
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|
1183 if ((pci_bus_res[parbus].mem_reprogram || |
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|
1184 (mem_base > mem_limit) || |
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|
1185 (!(cmd_reg & PCI_COMM_MAE))) && |
10293
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|
1186 !list_is_vga_only(scratch_list, MEM)) { |
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|
1187 if (pci_bus_res[secbus].mem_used) { |
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|
1188 memlist_subsume(&pci_bus_res[secbus].mem_used, |
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|
1189 &pci_bus_res[secbus].mem_avail); |
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1190 } |
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|
1191 if (pci_bus_res[secbus].mem_avail && |
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1192 (!pci_bus_res[parbus].mem_reprogram) && |
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1193 (!pci_bus_res[parbus].subtractive)) { |
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1194 /* rechoose old mem resource */ |
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|
1195 list = pci_bus_res[secbus].mem_avail; |
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|
1196 mem_base = 0; |
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|
1197 do { |
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|
1198 if (is_vga(list, MEM)) |
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|
1199 continue; |
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1200 if (mem_base == 0) { |
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Jonathan Adams <Jonathan.Adams@Sun.COM>
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|
1201 mem_base = (uint_t)list->ml_address; |
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1202 mem_base = P2ALIGN(mem_base, |
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|
1203 PPB_MEM_ALIGNMENT); |
11474
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|
1204 mem_limit = (uint_t)(list->ml_address + |
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|
1205 list->ml_size - 1); |
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|
1206 } else { |
11474
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1207 if ((list->ml_address + list->ml_size) > |
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|
1208 mem_limit) { |
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|
1209 mem_limit = (uint_t) |
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1210 (list->ml_address + |
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|
1211 list->ml_size - 1); |
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1212 } |
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|
1213 } |
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1214 } while ((list = list->ml_next) != NULL); |
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1215 mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; |
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1216 mem_size = mem_limit + 1 - mem_base; |
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1217 ASSERT(mem_base <= mem_limit); |
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1218 memlist_free_all(&pci_bus_res[secbus].mem_avail); |
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1219 memlist_insert(&pci_bus_res[secbus].mem_avail, |
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1220 mem_base, mem_size); |
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1221 memlist_insert(&pci_bus_res[parbus].mem_used, |
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1222 mem_base, mem_size); |
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1223 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, |
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1224 mem_base, mem_size); |
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1225 pci_bus_res[secbus].mem_reprogram = B_TRUE; |
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1226 } else { |
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|
1227 /* get new mem resource from parent bus */ |
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1228 addr = get_parbus_mem_res(parbus, secbus, mem_size, |
9588
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6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
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9527
diff
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|
1229 mem_align); |
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1230 if (addr) { |
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|
1231 mem_base = addr; |
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1232 mem_limit = addr + mem_size - 1; |
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1233 pci_bus_res[secbus].mem_reprogram = B_TRUE; |
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1234 } |
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|
1235 } |
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|
1236 |
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1237 if (pci_bus_res[secbus].mem_reprogram) { |
9221
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Guoli Shu<Kerry.Shu@Sun.COM>
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|
1238 /* reprogram PPB MEM regs */ |
6095
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1239 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, |
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|
1240 (uint16_t)((mem_base>>16) & 0xfff0)); |
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1241 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, |
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|
1242 (uint16_t)((mem_limit>>16) & 0xfff0)); |
9221
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|
1243 /* |
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|
1244 * Disable PMEM window by setting base > limit. |
f57a4c49f2b1
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1245 * We currently don't reprogram the PMEM like we've |
f57a4c49f2b1
6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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|
1246 * done for I/O and MEM. (Devices that support prefetch |
f57a4c49f2b1
6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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|
1247 * can use non-prefetch MEM.) Anyway, if the MEM access |
f57a4c49f2b1
6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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|
1248 * bit is initially disabled by BIOS, we disable the |
f57a4c49f2b1
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|
1249 * PMEM window manually by setting PMEM base > PMEM |
f57a4c49f2b1
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|
1250 * limit here, in case there are incorrect values in |
f57a4c49f2b1
6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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|
1251 * them from BIOS, so that we won't get in trouble once |
f57a4c49f2b1
6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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|
1252 * the MEM access bit is enabled at the end of this |
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6816405 cannot install osol 109 or snv_110 on Fujitsu Lifebook S7110 laptop due to hang.
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1253 * function. |
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|
1254 */ |
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|
1255 if (!(cmd_reg & PCI_COMM_MAE)) { |
f57a4c49f2b1
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|
1256 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, |
f57a4c49f2b1
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|
1257 0xfff0); |
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|
1258 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, |
f57a4c49f2b1
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|
1259 0x0); |
f57a4c49f2b1
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|
1260 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, |
f57a4c49f2b1
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|
1261 0xffffffff); |
f57a4c49f2b1
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|
1262 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, |
f57a4c49f2b1
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|
1263 0x0); |
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|
1264 } |
f57a4c49f2b1
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|
1265 |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
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|
1266 add_ranges_prop(secbus, 1); |
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|
1267 |
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1268 cmn_err(CE_NOTE, "!reprogram mem-range on" |
ffd81788f184
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1269 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", |
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|
1270 bus, dev, func, mem_base, mem_limit); |
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1271 } |
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|
1272 } |
10293
ac02598ffdd8
6869654 pci_autoconfig: memory leak in memlist_alloc() in snv_121 on x86 on systems with zfs root
Dan Mick <Dan.Mick@Sun.COM>
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|
1273 memlist_free_all(&scratch_list); |
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1274 |
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1275 cmd_enable: |
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|
1276 if (pci_bus_res[secbus].io_avail) |
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|
1277 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; |
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|
1278 if (pci_bus_res[secbus].mem_avail) |
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1279 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; |
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1280 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); |
4517 | 1281 } |
1282 | |
0 | 1283 void |
1284 pci_reprogram(void) | |
1285 { | |
1286 int i, pci_reconfig = 1; | |
1287 char *onoff; | |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
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|
1288 int bus; |
0 | 1289 |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
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|
1290 /* |
10552
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|
1291 * Scan ACPI namespace for _BBN objects, make sure that |
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|
1292 * childless root-bridges appear in devinfo tree |
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|
1293 */ |
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|
1294 pci_scan_bbn(); |
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|
1295 pci_unitaddr_cache_init(); |
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6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
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|
1296 |
bf9134a043f1
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|
1297 /* |
bf9134a043f1
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diff
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|
1298 * Fix-up unit-address assignments if cache is available |
1413
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|
1299 */ |
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|
1300 if (pci_unitaddr_cache_valid()) { |
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|
1301 int pci_regs[] = {0, 0, 0}; |
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|
1302 int new_addr; |
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|
1303 int index = 0; |
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|
1304 |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
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|
1305 for (bus = 0; bus <= pci_bios_maxbus; bus++) { |
10552
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|
1306 /* skip non-root (peer) PCI busses */ |
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|
1307 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1308 (pci_bus_res[bus].dip == NULL)) |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1309 continue; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1310 |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1311 new_addr = pci_bus_unitaddr(index); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1312 if (pci_bus_res[bus].root_addr != new_addr) { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1313 /* update reg property for node */ |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1314 pci_regs[0] = pci_bus_res[bus].root_addr = |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1315 new_addr; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1316 (void) ndi_prop_update_int_array( |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1317 DDI_DEV_T_NONE, pci_bus_res[bus].dip, |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1318 "reg", (int *)pci_regs, 3); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1319 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1320 index++; |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1321 } |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1322 } else { |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1323 /* perform legacy processing */ |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1324 pci_renumber_root_busses(); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1325 pci_unitaddr_cache_create(); |
bf9134a043f1
6472670 Internal pci root-bus addresses should be independent of bios enumeration order (non-x8400 systems)
Dana Myers <Dana.Myers@Sun.COM>
parents:
10384
diff
changeset
|
1326 } |
1413
5c66154eab3c
6324138 Internal pci bus numbering should be independent of bios enumeration order
myers
parents:
1007
diff
changeset
|
1327 |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1328 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1329 * Do root-bus resource discovery |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1330 */ |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
1331 for (bus = 0; bus <= pci_bios_maxbus; bus++) { |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1332 /* skip non-root (peer) PCI busses */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1333 if (pci_bus_res[bus].par_bus != (uchar_t)-1) |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1334 continue; |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1335 |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1336 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
1337 * 1. find resources associated with this root bus |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
changeset
|
1338 */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1339 populate_bus_res(bus); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1340 |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
changeset
|
1341 |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1342 /* |
9226
efb0bee5599d
6821665 WARNING: kb8042: inconsistent getinfo(9E) implementation
Judy Chen <Judy.Chen@Sun.COM>
parents:
9221
diff
changeset
|
1343 * 2. Remove used PCI and ISA resources from bus resource map |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
changeset
|
1344 */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1345 |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1346 memlist_remove_list(&pci_bus_res[bus].io_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1347 pci_bus_res[bus].io_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1348 memlist_remove_list(&pci_bus_res[bus].mem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1349 pci_bus_res[bus].mem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1350 memlist_remove_list(&pci_bus_res[bus].pmem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1351 pci_bus_res[bus].pmem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1352 memlist_remove_list(&pci_bus_res[bus].mem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1353 pci_bus_res[bus].pmem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1354 memlist_remove_list(&pci_bus_res[bus].pmem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1355 pci_bus_res[bus].mem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1356 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1357 memlist_remove_list(&pci_bus_res[bus].io_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1358 isa_res.io_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1359 memlist_remove_list(&pci_bus_res[bus].mem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1360 isa_res.mem_used); |
10895
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1361 |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1362 /* |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1363 * 3. Exclude <1M address range here in case below reserved |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1364 * ranges for BIOS data area, ROM area etc are wrongly reported |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1365 * in ACPI resource producer entries for PCI root bus. |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1366 * 00000000 - 000003FF RAM |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1367 * 00000400 - 000004FF BIOS data area |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1368 * 00000500 - 0009FFFF RAM |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1369 * 000A0000 - 000BFFFF VGA RAM |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1370 * 000C0000 - 000FFFFF ROM area |
275ef2b47915
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10804
diff
changeset
|
1371 */ |
10917
2c1f18099a3e
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot (fix lint)
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10895
diff
changeset
|
1372 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); |
2c1f18099a3e
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot (fix lint)
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10895
diff
changeset
|
1373 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, |
2c1f18099a3e
6881268 Fujitsu-Siemens Amilo D8820 hangs during boot when wifi card present in cardbus slot (fix lint)
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
10895
diff
changeset
|
1374 0, 0x100000); |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1375 } |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1376 |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1377 memlist_free_all(&isa_res.io_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1378 memlist_free_all(&isa_res.mem_used); |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1379 |
1895
21a9e9965d62
6404301 pci_boot.c incorrectly assigns bus-range property for root/peer bus
rw148561
parents:
1865
diff
changeset
|
1380 /* add bus-range property for root/peer bus nodes */ |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
1381 for (i = 0; i <= pci_bios_maxbus; i++) { |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
changeset
|
1382 /* create bus-range property on root/peer buses */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
changeset
|
1383 if (pci_bus_res[i].par_bus == (uchar_t)-1) |
1895
21a9e9965d62
6404301 pci_boot.c incorrectly assigns bus-range property for root/peer bus
rw148561
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1865
diff
changeset
|
1384 add_bus_range_prop(i); |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
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diff
changeset
|
1385 |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1386 /* setup bus range resource on each bus */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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parents:
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diff
changeset
|
1387 setup_bus_res(i); |
1895
21a9e9965d62
6404301 pci_boot.c incorrectly assigns bus-range property for root/peer bus
rw148561
parents:
1865
diff
changeset
|
1388 } |
21a9e9965d62
6404301 pci_boot.c incorrectly assigns bus-range property for root/peer bus
rw148561
parents:
1865
diff
changeset
|
1389 |
0 | 1390 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), |
1391 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { | |
1392 if (strcmp(onoff, "off") == 0) { | |
1393 pci_reconfig = 0; | |
1394 cmn_err(CE_NOTE, "pci device reprogramming disabled"); | |
1395 } | |
1396 ddi_prop_free(onoff); | |
1397 } | |
1398 | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
1399 remove_subtractive_res(); |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
1400 |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1401 /* reprogram the non-subtractive PPB */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1402 if (pci_reconfig) |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
1403 for (i = 0; i <= pci_bios_maxbus; i++) |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1404 fix_ppb_res(i, B_FALSE); |
2950
449abdd74783
6354996 pci_boot.c incorrectly accounts for system resources in PCI configuration
myers
parents:
2466
diff
changeset
|
1405 |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
1406 for (i = 0; i <= pci_bios_maxbus; i++) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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|
1407 /* configure devices not configured by BIOS */ |
4517 | 1408 if (pci_reconfig) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
1409 /* |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1410 * Reprogram the subtractive PPB. At this time, all its |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
1411 * siblings should have got their resources already. |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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parents:
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diff
changeset
|
1412 */ |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
1413 if (pci_bus_res[i].subtractive) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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|
1414 fix_ppb_res(i, B_TRUE); |
0 | 1415 enumerate_bus_devs(i, CONFIG_NEW); |
4517 | 1416 } |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1417 } |
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1418 |
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1419 /* All dev programmed, so we can create available prop */ |
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1420 for (i = 0; i <= pci_bios_maxbus; i++) |
0 | 1421 add_bus_available_prop(i); |
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1422 } |
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1423 |
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1424 /* |
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1425 * populate bus resources |
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1426 */ |
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1427 static void |
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1428 populate_bus_res(uchar_t bus) |
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1429 { |
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1430 |
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1431 /* scan BIOS structures */ |
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1432 pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); |
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1433 pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); |
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1434 pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); |
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1435 pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); |
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1436 |
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1437 /* |
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1438 * attempt to initialize sub_bus from the largest range-end |
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1439 * in the bus_avail list |
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1440 */ |
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1441 if (pci_bus_res[bus].bus_avail != NULL) { |
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1442 struct memlist *entry; |
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1443 int current; |
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1444 |
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1445 entry = pci_bus_res[bus].bus_avail; |
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1446 while (entry != NULL) { |
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1447 current = entry->ml_address + entry->ml_size - 1; |
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1448 if (current > pci_bus_res[bus].sub_bus) |
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1449 pci_bus_res[bus].sub_bus = current; |
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1450 entry = entry->ml_next; |
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1451 } |
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1452 } |
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1453 |
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1454 if (bus == 0) { |
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1455 /* |
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1456 * Special treatment of bus 0: |
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1457 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy |
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1458 * pcimem from boot and make I/O space the entire range |
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1459 * starting at 0x100. |
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1460 */ |
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1461 if (pci_bus_res[0].mem_avail == NULL) |
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1462 pci_bus_res[0].mem_avail = |
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1463 memlist_dup(bootops->boot_mem->pcimem); |
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1464 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ |
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1465 if (pci_bus_res[0].io_avail == NULL) |
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1466 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); |
0 | 1467 } |
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1468 |
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1469 /* |
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1470 * Create 'ranges' property here before any resources are |
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1471 * removed from the resource lists |
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1472 */ |
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1473 add_ranges_prop(bus, 0); |
0 | 1474 } |
1475 | |
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1476 |
0 | 1477 /* |
1478 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... | |
1479 */ | |
1480 static void | |
1481 create_root_bus_dip(uchar_t bus) | |
1482 { | |
1483 int pci_regs[] = {0, 0, 0}; | |
1484 dev_info_t *dip; | |
1485 | |
1486 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); | |
1487 | |
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1488 num_root_bus++; |
0 | 1489 ndi_devi_alloc_sleep(ddi_root_node(), "pci", |
789 | 1490 (pnode_t)DEVI_SID_NODEID, &dip); |
0 | 1491 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, |
1492 "#address-cells", 3); | |
1493 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
1494 "#size-cells", 2); | |
1495 pci_regs[0] = pci_bus_res[bus].root_addr; | |
1496 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, | |
1497 "reg", (int *)pci_regs, 3); | |
1498 | |
881 | 1499 /* |
1500 * If system has PCIe bus, then create different properties | |
1501 */ | |
1502 if (create_pcie_root_bus(bus, dip) == B_FALSE) | |
1503 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, | |
1504 "device_type", "pci"); | |
1505 | |
0 | 1506 (void) ndi_devi_bind_driver(dip, 0); |
1507 pci_bus_res[bus].dip = dip; | |
1508 } | |
1509 | |
1510 /* | |
1511 * For any fixed configuration (often compatability) pci devices | |
1512 * and those with their own expansion rom, create device nodes | |
1513 * to hold the already configured device details. | |
1514 */ | |
1515 void | |
1516 enumerate_bus_devs(uchar_t bus, int config_op) | |
1517 { | |
1518 uchar_t dev, func, nfunc, header; | |
1519 ushort_t venid; | |
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1520 struct pci_devfunc *devlist = NULL, *entry; |
0 | 1521 |
1522 if (config_op == CONFIG_NEW) { | |
1523 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); | |
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1524 } else if (config_op == CONFIG_FIX) { |
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1525 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); |
0 | 1526 } else |
1527 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); | |
1528 | |
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1529 if (config_op == CONFIG_NEW) { |
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1530 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; |
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1531 while (devlist) { |
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1532 entry = devlist; |
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1533 devlist = entry->next; |
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1534 if (entry->reprogram || |
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1535 pci_bus_res[bus].io_reprogram || |
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1536 pci_bus_res[bus].mem_reprogram) { |
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1537 /* reprogram device(s) */ |
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1538 (void) add_reg_props(entry->dip, bus, |
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1539 entry->dev, entry->func, CONFIG_NEW, 0); |
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1540 } |
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1541 kmem_free(entry, sizeof (*entry)); |
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1542 } |
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1543 pci_bus_res[bus].privdata = NULL; |
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1544 return; |
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1545 } |
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1546 |
0 | 1547 for (dev = 0; dev < max_dev_pci; dev++) { |
1548 nfunc = 1; | |
1549 for (func = 0; func < nfunc; func++) { | |
1550 | |
1551 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", | |
1552 dev, func); | |
1553 | |
1554 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); | |
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1555 |
0 | 1556 if ((venid == 0xffff) || (venid == 0)) { |
1557 /* no function at this address */ | |
1558 continue; | |
1559 } | |
1560 | |
1561 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); | |
1562 if (header == 0xff) { | |
1563 continue; /* illegal value */ | |
1564 } | |
1565 | |
1566 /* | |
1567 * according to some mail from Microsoft posted | |
1568 * to the pci-drivers alias, their only requirement | |
1569 * for a multifunction device is for the 1st | |
1570 * function to have to PCI_HEADER_MULTI bit set. | |
1571 */ | |
1572 if ((func == 0) && (header & PCI_HEADER_MULTI)) { | |
1573 nfunc = 8; | |
1574 } | |
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1575 |
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1576 if (config_op == CONFIG_FIX || |
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1577 config_op == CONFIG_INFO) { |
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1578 /* |
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1579 * Create the node, unconditionally, on the |
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1580 * first pass only. It may still need |
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|
1581 * resource assignment, which will be |
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
1582 * done on the second, CONFIG_NEW, pass. |
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
1583 */ |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
1584 process_devfunc(bus, dev, func, header, |
793
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
1585 venid, config_op); |
825
4e9cc40be9a9
6344290 enumerate_bus_devs produces small memory leak in snv_27 on all x86/amd64 platforms
dmick
parents:
793
diff
changeset
|
1586 |
0 | 1587 } |
1588 } | |
1589 } | |
1590 | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1591 /* percolate bus used resources up through parents to root */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1592 if (config_op == CONFIG_INFO) { |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1593 int par_bus; |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1594 |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1595 par_bus = pci_bus_res[bus].par_bus; |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1596 while (par_bus != (uchar_t)-1) { |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
1597 pci_bus_res[par_bus].io_size += |
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
1598 pci_bus_res[bus].io_size; |
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
1599 pci_bus_res[par_bus].mem_size += |
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
1600 pci_bus_res[bus].mem_size; |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1601 |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1602 if (pci_bus_res[bus].io_used) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1603 memlist_merge(&pci_bus_res[bus].io_used, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1604 &pci_bus_res[par_bus].io_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1605 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1606 if (pci_bus_res[bus].mem_used) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1607 memlist_merge(&pci_bus_res[bus].mem_used, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1608 &pci_bus_res[par_bus].mem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1609 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1610 if (pci_bus_res[bus].pmem_used) |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1611 memlist_merge(&pci_bus_res[bus].pmem_used, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1612 &pci_bus_res[par_bus].pmem_used); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1613 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
1614 bus = par_bus; |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
1615 par_bus = pci_bus_res[par_bus].par_bus; |
0 | 1616 } |
1617 } | |
1618 } | |
1619 | |
1620 static int | |
1621 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, | |
1622 ushort_t subvenid, ushort_t subdevid) | |
1623 { | |
1624 static int prop_exist = -1; | |
1625 static char *pciide_str; | |
1626 char compat[32]; | |
1627 | |
1628 if (prop_exist == -1) { | |
1629 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, | |
1630 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", | |
1631 &pciide_str) == DDI_SUCCESS); | |
1632 } | |
1633 | |
1634 if (!prop_exist) | |
1635 return (0); | |
1636 | |
1637 /* compare property value against various forms of compatible */ | |
1638 if (subvenid) { | |
1639 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", | |
1640 venid, devid, subvenid, subdevid, revid); | |
1641 if (strcmp(pciide_str, compat) == 0) | |
1642 return (1); | |
1643 | |
1644 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", | |
1645 venid, devid, subvenid, subdevid); | |
1646 if (strcmp(pciide_str, compat) == 0) | |
1647 return (1); | |
1648 | |
1649 (void) snprintf(compat, sizeof (compat), "pci%x,%x", | |
1650 subvenid, subdevid); | |
1651 if (strcmp(pciide_str, compat) == 0) | |
1652 return (1); | |
1653 } | |
1654 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", | |
1655 venid, devid, revid); | |
1656 if (strcmp(pciide_str, compat) == 0) | |
1657 return (1); | |
1658 | |
1659 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); | |
1660 if (strcmp(pciide_str, compat) == 0) | |
1661 return (1); | |
1662 | |
1663 return (0); | |
1664 } | |
1665 | |
1666 static int | |
1667 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, | |
1668 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) | |
1669 { | |
1670 struct ide_table { /* table for PCI_MASS_OTHER */ | |
1671 ushort_t venid; | |
1672 ushort_t devid; | |
1673 } *entry; | |
1674 | |
6211
5ef7bda7ecea
6662348 ata: Cannot DVD install Intel DG33TL motherboard
ml40262
parents:
6095
diff
changeset
|
1675 /* XXX SATA and other devices: need a way to add dynamically */ |
0 | 1676 static struct ide_table ide_other[] = { |
1677 {0x1095, 0x3112}, | |
1678 {0x1095, 0x3114}, | |
1679 {0x1095, 0x3512}, | |
6984
620f4148fdb0
5031620 Some cards based upon the SiL 680(A) ATA controller won't bind due to a hardware lie.
tt30446
parents:
6927
diff
changeset
|
1680 {0x1095, 0x680}, /* Sil0680 */ |
6211
5ef7bda7ecea
6662348 ata: Cannot DVD install Intel DG33TL motherboard
ml40262
parents:
6095
diff
changeset
|
1681 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ |
0 | 1682 {0, 0} |
1683 }; | |
1684 | |
1685 if (basecl != PCI_CLASS_MASS) | |
1686 return (0); | |
1687 | |
1688 if (subcl == PCI_MASS_IDE) { | |
1689 return (1); | |
1690 } | |
1691 | |
6984
620f4148fdb0
5031620 Some cards based upon the SiL 680(A) ATA controller won't bind due to a hardware lie.
tt30446
parents:
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diff
changeset
|
1692 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) |
620f4148fdb0
5031620 Some cards based upon the SiL 680(A) ATA controller won't bind due to a hardware lie.
tt30446
parents:
6927
diff
changeset
|
1693 return (1); |
620f4148fdb0
5031620 Some cards based upon the SiL 680(A) ATA controller won't bind due to a hardware lie.
tt30446
parents:
6927
diff
changeset
|
1694 |
0 | 1695 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { |
1696 return (0); | |
1697 } | |
1698 | |
1699 entry = &ide_other[0]; | |
1700 while (entry->venid) { | |
1701 if (entry->venid == venid && entry->devid == devid) | |
1702 return (1); | |
1703 entry++; | |
1704 } | |
6984
620f4148fdb0
5031620 Some cards based upon the SiL 680(A) ATA controller won't bind due to a hardware lie.
tt30446
parents:
6927
diff
changeset
|
1705 return (0); |
0 | 1706 } |
1707 | |
1708 static int | |
1709 is_display(uint_t classcode) | |
1710 { | |
1711 static uint_t disp_classes[] = { | |
1712 0x000100, | |
1713 0x030000, | |
1714 0x030001 | |
1715 }; | |
1716 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); | |
1717 | |
1718 for (i = 0; i < nclasses; i++) { | |
1719 if (classcode == disp_classes[i]) | |
1720 return (1); | |
1721 } | |
1722 return (0); | |
1723 } | |
1724 | |
2121
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1725 static void |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1726 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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1895
diff
changeset
|
1727 void (*undofn)(uint8_t, uint8_t, uint8_t)) |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1728 { |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1729 struct pci_fixundo *newundo; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1730 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1731 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
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|
1732 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1733 /* |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1734 * Adding an item to this list means that we must turn its NMIENABLE |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1735 * bit back on at a later time. |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
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|
1736 */ |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1737 newundo->bus = bus; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1738 newundo->dev = dev; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1739 newundo->fn = fn; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1740 newundo->undofn = undofn; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1741 newundo->next = undolist; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1742 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1743 /* add to the undo list in LIFO order */ |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1744 undolist = newundo; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1745 } |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1746 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1747 void |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1748 add_pci_fixes(void) |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
sethg
parents:
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diff
changeset
|
1749 { |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1750 int i; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
1895
diff
changeset
|
1751 |
10804
f38860d83eb4
6890417 pci_autoconfig: acpi_pci_probe() uses pci_bios_nbus falsely
Dana Myers <Dana.Myers@Sun.COM>
parents:
10554
diff
changeset
|
1752 for (i = 0; i <= pci_bios_maxbus; i++) { |
2121
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1753 /* |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1754 * For each bus, apply needed fixes to the appropriate devices. |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1755 * This must be done before the main enumeration loop because |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1756 * some fixes must be applied to devices normally encountered |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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parents:
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diff
changeset
|
1757 * later in the pci scan (e.g. if a fix to device 7 must be |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1758 * applied before scanning device 6, applying fixes in the |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1759 * normal enumeration loop would obviously be too late). |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1760 */ |
31a173288bb3
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|
1761 enumerate_bus_devs(i, CONFIG_FIX); |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1762 } |
31a173288bb3
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diff
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|
1763 } |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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|
1764 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1765 void |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1766 undo_pci_fixes(void) |
31a173288bb3
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diff
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|
1767 { |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1768 struct pci_fixundo *nextundo; |
31a173288bb3
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diff
changeset
|
1769 uint8_t bus, dev, fn; |
31a173288bb3
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diff
changeset
|
1770 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1771 /* |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1772 * All fixes in the undo list are performed unconditionally. Future |
31a173288bb3
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parents:
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diff
changeset
|
1773 * fixes may require selective undo. |
31a173288bb3
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diff
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|
1774 */ |
31a173288bb3
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diff
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|
1775 while (undolist != NULL) { |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1776 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1777 bus = undolist->bus; |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1778 dev = undolist->dev; |
31a173288bb3
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diff
changeset
|
1779 fn = undolist->fn; |
31a173288bb3
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diff
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|
1780 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
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|
1781 (*(undolist->undofn))(bus, dev, fn); |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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diff
changeset
|
1782 |
31a173288bb3
6423164 USB keyboard & mouse don't work on w2100z running b39
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changeset
|
1783 nextundo = undolist->next; |
31a173288bb3
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|
1784 kmem_free(undolist, sizeof (struct pci_fixundo)); |
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changeset
|
1785 undolist = nextundo; |
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|
1786 } |
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|
1787 } |
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changeset
|
1788 |
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changeset
|
1789 static void |
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|
1790 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) |
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|
1791 { |
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|
1792 uint8_t val8; |
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|
1793 |
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|
1794 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); |
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|
1795 /* |
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|
1796 * The NMIONERR bit is turned back on to allow the SMM BIOS |
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|
1797 * to handle more critical PCI errors (e.g. PERR#). |
31a173288bb3
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diff
changeset
|
1798 */ |
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|
1799 val8 |= AMD8111_ENABLENMI; |
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|
1800 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); |
31a173288bb3
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|
1801 } |
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changeset
|
1802 |
31a173288bb3
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diff
changeset
|
1803 static void |
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changeset
|
1804 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) |
31a173288bb3
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changeset
|
1805 { |
31a173288bb3
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diff
changeset
|
1806 uint8_t val8; |
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diff
changeset
|
1807 |
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diff
changeset
|
1808 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); |
31a173288bb3
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diff
changeset
|
1809 |
31a173288bb3
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diff
changeset
|
1810 if ((val8 & AMD8111_ENABLENMI) == 0) |
31a173288bb3
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diff
changeset
|
1811 return; |
31a173288bb3
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diff
changeset
|
1812 |
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diff
changeset
|
1813 /* |
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|
1814 * We reset NMIONERR in the LPC because master-abort on the PCI |
31a173288bb3
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|
1815 * bridge side of the 8111 will cause NMI, which might cause SMI, |
31a173288bb3
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changeset
|
1816 * which sometimes prevents all devices from being enumerated. |
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changeset
|
1817 */ |
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|
1818 val8 &= ~AMD8111_ENABLENMI; |
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changeset
|
1819 |
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changeset
|
1820 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); |
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changeset
|
1821 |
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|
1822 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); |
31a173288bb3
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|
1823 } |
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|
1824 |
6095
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|
1825 static void |
6927
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|
1826 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) |
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1827 { |
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1828 uint16_t status; |
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1829 uint8_t header; |
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1830 uint8_t cap_ptr; |
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1831 uint8_t cap_id; |
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1832 uint16_t pmcsr; |
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1833 |
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1834 status = pci_getw(bus, dev, func, PCI_CONF_STAT); |
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1835 if (!(status & PCI_STAT_CAP)) |
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|
1836 return; /* No capabilities list */ |
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|
1837 |
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1838 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; |
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|
1839 if (header == PCI_HEADER_CARDBUS) |
9284
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6482159 kernel hangs in pcic_attach at boot time on Fujitsu FMV6800MG laptop
Casper H.S. Dik <Casper.Dik@Sun.COM>
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changeset
|
1840 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); |
6927
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1841 else |
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|
1842 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); |
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1843 /* |
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1844 * Walk the capabilities list searching for a PM entry. |
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1845 */ |
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1846 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { |
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|
1847 cap_ptr &= PCI_CAP_PTR_MASK; |
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1848 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); |
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1849 if (cap_id == PCI_CAP_ID_PM) { |
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|
1850 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); |
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|
1851 pmcsr &= ~(PCI_PMCSR_STATE_MASK); |
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1852 pmcsr |= PCI_PMCSR_D0; /* D0 state */ |
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|
1853 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); |
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|
1854 break; |
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1855 } |
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1856 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); |
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|
1857 } |
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|
1858 |
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1859 } |
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1860 |
9149
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|
1861 #define is_isa(bc, sc) \ |
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1862 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) |
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1863 |
6927
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|
1864 static void |
2121
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1865 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, |
0 | 1866 ushort_t vendorid, int config_op) |
1867 { | |
1868 char nodename[32], unitaddr[5]; | |
1869 dev_info_t *dip; | |
3745
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1870 uchar_t basecl, subcl, progcl, intr, revid; |
0 | 1871 ushort_t subvenid, subdevid, status; |
881 | 1872 ushort_t slot_num; |
0 | 1873 uint_t classcode, revclass; |
4876 | 1874 int reprogram = 0, pciide = 0; |
0 | 1875 int power[2] = {1, 1}; |
881 | 1876 int pciex = 0; |
1877 ushort_t is_pci_bridge = 0; | |
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1878 struct pci_devfunc *devlist = NULL, *entry = NULL; |
12054
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|
1879 boolean_t slot_valid; |
8215
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|
1880 gfx_entry_t *gfxp; |
11245
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1881 pcie_req_id_t bdf; |
0 | 1882 |
1883 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); | |
1884 | |
1885 switch (header & PCI_HEADER_TYPE_M) { | |
1886 case PCI_HEADER_ZERO: | |
1887 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); | |
1888 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); | |
1889 break; | |
1890 case PCI_HEADER_CARDBUS: | |
1891 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); | |
1892 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); | |
6095
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1893 /* Record the # of cardbus bridges found on the bus */ |
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1894 if (config_op == CONFIG_INFO) |
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1895 pci_bus_res[bus].num_cbb++; |
0 | 1896 break; |
1897 default: | |
1898 subvenid = 0; | |
1899 subdevid = 0; | |
1900 break; | |
1901 } | |
1902 | |
2121
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1903 if (config_op == CONFIG_FIX) { |
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1904 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { |
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1905 pci_fix_amd8111(bus, dev, func); |
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1906 } |
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1907 return; |
2121
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1908 } |
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1909 |
0 | 1910 /* XXX should be use generic names? derive from class? */ |
1911 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); | |
1912 classcode = revclass >> 8; | |
1913 revid = revclass & 0xff; | |
1914 | |
1915 /* figure out if this is pci-ide */ | |
1916 basecl = classcode >> 16; | |
1917 subcl = (classcode >> 8) & 0xff; | |
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1918 progcl = classcode & 0xff; |
4876 | 1919 |
0 | 1920 |
4876 | 1921 if (is_display(classcode)) |
0 | 1922 (void) snprintf(nodename, sizeof (nodename), "display"); |
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1923 else if (!pseudo_isa && is_isa(basecl, subcl)) |
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1924 (void) snprintf(nodename, sizeof (nodename), "isa"); |
0 | 1925 else if (subvenid != 0) |
1926 (void) snprintf(nodename, sizeof (nodename), | |
1927 "pci%x,%x", subvenid, subdevid); | |
1928 else | |
1929 (void) snprintf(nodename, sizeof (nodename), | |
1930 "pci%x,%x", vendorid, deviceid); | |
1931 | |
1932 /* make sure parent bus dip has been created */ | |
8420
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1933 if (pci_bus_res[bus].dip == NULL) |
0 | 1934 create_root_bus_dip(bus); |
1935 | |
1936 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, | |
1937 DEVI_SID_NODEID, &dip); | |
1938 | |
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1939 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid, |
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1940 &slot_num, &is_pci_bridge) == B_TRUE) |
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1941 pciex = 1; |
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1942 |
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1943 bdf = PCI_GETBDF(bus, dev, func); |
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1944 /* |
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1945 * Record BAD AMD bridges which don't support MMIO config access. |
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1946 */ |
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1947 if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) || |
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1948 IS_AMD_8132_CHIP(vendorid, deviceid)) { |
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1949 uchar_t secbus = 0; |
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1950 uchar_t subbus = 0; |
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1951 |
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1952 if ((basecl == PCI_CLASS_BRIDGE) && |
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1953 (subcl == PCI_BRIDGE_PCI)) { |
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1954 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); |
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1955 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); |
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1956 } |
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1957 pci_cfgacc_add_workaround(bdf, secbus, subbus); |
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1958 } |
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1959 |
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1960 /* |
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1961 * Only populate bus_t if this is a PCIE platform, and |
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1962 * the device is sitting under a PCIE root complex(RC) . |
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1963 * Some particular machines have both PCIE RC and PCI |
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1964 * hostbridge, in which case only devices under PCIE RC |
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1965 * get their bus_t populated. |
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1966 */ |
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1967 if ((mcfg_mem_base != NULL) && (pcie_get_rc_dip(dip) != NULL)) { |
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1968 ck804_fix_aer_ptr(dip, bdf); |
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1969 (void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL); |
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1970 } |
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1971 |
0 | 1972 /* add properties */ |
1973 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); | |
1974 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); | |
1975 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); | |
1976 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
1977 "class-code", classcode); | |
1978 if (func == 0) | |
1979 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); | |
1980 else | |
1981 (void) snprintf(unitaddr, sizeof (unitaddr), | |
1982 "%x,%x", dev, func); | |
1983 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, | |
1984 "unit-address", unitaddr); | |
1985 | |
793
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1986 /* add device_type for display nodes */ |
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1987 if (is_display(classcode)) { |
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1988 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, |
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1989 "device_type", "display"); |
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1990 } |
0 | 1991 /* add special stuff for header type */ |
1992 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { | |
1993 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); | |
1994 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); | |
1995 | |
1996 if (subvenid != 0) { | |
1997 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
1998 "subsystem-id", subdevid); | |
1999 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2000 "subsystem-vendor-id", subvenid); | |
2001 } | |
881 | 2002 if (!pciex) |
2003 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2004 "min-grant", mingrant); | |
2005 if (!pciex) | |
2006 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2007 "max-latency", maxlatency); | |
0 | 2008 } |
2009 | |
2010 /* interrupt, record if not 0 */ | |
2011 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); | |
2012 if (intr != 0) | |
2013 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2014 "interrupts", intr); | |
2015 | |
2016 /* | |
2017 * Add support for 133 mhz pci eventually | |
2018 */ | |
2019 status = pci_getw(bus, dev, func, PCI_CONF_STAT); | |
2020 | |
2021 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2022 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); | |
881 | 2023 if (!pciex && (status & PCI_STAT_FBBC)) |
0 | 2024 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, |
2025 "fast-back-to-back"); | |
881 | 2026 if (!pciex && (status & PCI_STAT_66MHZ)) |
0 | 2027 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, |
2028 "66mhz-capable"); | |
2029 if (status & PCI_STAT_UDF) | |
2030 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, | |
2031 "udf-supported"); | |
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2032 if (pciex && slot_valid) { |
881 | 2033 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, |
2034 "physical-slot#", slot_num); | |
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2035 if (!is_pci_bridge) |
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2036 pciex_slot_names_prop(dip, slot_num); |
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2037 } |
0 | 2038 |
2039 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, | |
2040 "power-consumption", power, 2); | |
2041 | |
6927
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2042 /* Set the device PM state to D0 */ |
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2043 set_devpm_d0(bus, dev, func); |
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2044 |
881 | 2045 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) |
7987
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Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
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2046 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); |
6095
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2047 else { |
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2048 /* |
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2049 * Record the non-PPB devices on the bus for possible |
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2050 * reprogramming at 2nd bus enumeration. |
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2051 * Note: PPB reprogramming is done in fix_ppb_res() |
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2052 */ |
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2053 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; |
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2054 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); |
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2055 entry->dip = dip; |
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2056 entry->dev = dev; |
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2057 entry->func = func; |
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2058 entry->next = devlist; |
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2059 pci_bus_res[bus].privdata = entry; |
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2060 } |
881 | 2061 |
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2062 if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) { |
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2063 create_ioapic_node(bus, dev, func, vendorid, deviceid); |
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2064 } |
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2065 |
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2066 /* check for NVIDIA CK8-04/MCP55 based LPC bridge */ |
881 | 2067 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && |
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2068 (func == 0)) { |
2435 | 2069 add_nvidia_isa_bridge_props(dip, bus, dev, func); |
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2070 /* each LPC bridge has an integrated IOAPIC */ |
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2071 apic_nvidia_io_max++; |
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2072 } |
0 | 2073 |
881 | 2074 if (pciex && is_pci_bridge) |
2075 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", | |
2076 (char *)"PCIe-PCI bridge"); | |
2077 else | |
2078 add_model_prop(dip, classcode); | |
2079 | |
0 | 2080 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, |
881 | 2081 revid, classcode, pciex); |
4876 | 2082 |
2083 /* | |
2084 * See if this device is a controller that advertises | |
2085 * itself to be a standard ATA task file controller, or one that | |
2086 * has been hard coded. | |
2087 * | |
2088 * If it is, check if any other higher precedence driver listed in | |
2089 * driver_aliases will claim the node by calling | |
2090 * ddi_compatibile_driver_major. If so, clear pciide and do not | |
2091 * create a pci-ide node or any other special handling. | |
2092 * | |
2093 * If another driver does not bind, set the node name to pci-ide | |
2094 * and then let the special pci-ide handling for registers and | |
2095 * child pci-ide nodes proceed below. | |
2096 */ | |
2097 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, | |
2098 subvenid, subdevid) == 1) { | |
2099 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { | |
2100 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); | |
2101 pciide = 1; | |
2102 } | |
2103 } | |
2104 | |
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2105 DEVI_SET_PCI(dip); |
0 | 2106 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); |
2107 (void) ndi_devi_bind_driver(dip, 0); | |
2108 | |
2109 /* special handling for pci-ide */ | |
2110 if (pciide) { | |
2111 dev_info_t *cdip; | |
2112 | |
2113 /* | |
2114 * Create properties specified by P1275 Working Group | |
2115 * Proposal #414 Version 1 | |
2116 */ | |
2117 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, | |
2118 "device_type", "pci-ide"); | |
2119 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2120 "#address-cells", 1); | |
2121 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2122 "#size-cells", 0); | |
2123 | |
2124 /* allocate two child nodes */ | |
2125 ndi_devi_alloc_sleep(dip, "ide", | |
789 | 2126 (pnode_t)DEVI_SID_NODEID, &cdip); |
0 | 2127 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, |
2128 "reg", 0); | |
2129 (void) ndi_devi_bind_driver(cdip, 0); | |
2130 ndi_devi_alloc_sleep(dip, "ide", | |
789 | 2131 (pnode_t)DEVI_SID_NODEID, &cdip); |
0 | 2132 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, |
2133 "reg", 1); | |
2134 (void) ndi_devi_bind_driver(cdip, 0); | |
2135 | |
2136 reprogram = 0; /* don't reprogram pci-ide bridge */ | |
2137 } | |
2138 | |
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2139 if (is_display(classcode)) { |
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2140 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); |
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2141 gfxp->g_dip = dip; |
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2142 gfxp->g_prev = NULL; |
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2143 gfxp->g_next = gfx_devinfo_list; |
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2144 gfx_devinfo_list = gfxp; |
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2145 if (gfxp->g_next) |
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2146 gfxp->g_next->g_prev = gfxp; |
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2147 } |
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2148 |
9149
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2149 /* special handling for isa */ |
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2150 if (!pseudo_isa && is_isa(basecl, subcl)) { |
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2151 /* add device_type */ |
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2152 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, |
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2153 "device_type", "isa"); |
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2154 } |
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2155 |
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2156 if (reprogram && (entry != NULL)) |
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2157 entry->reprogram = B_TRUE; |
10384
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6870146 Intel IOMMU has device tree bug that can cause panics
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2158 |
0 | 2159 } |
2160 | |
2161 /* | |
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2162 * Some vendors do not use unique subsystem IDs in their products, which |
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2163 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. |
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2164 * Allow for these compatible forms to be excluded on a per-device basis. |
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2165 */ |
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2166 /*ARGSUSED*/ |
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2167 static boolean_t |
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2168 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, |
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2169 ushort_t subdevid, uchar_t revid, uint_t classcode) |
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2170 { |
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2171 /* Nvidia display adapters */ |
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2172 if ((venid == 0x10de) && (is_display(classcode))) |
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2173 return (B_TRUE); |
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2174 |
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2175 return (B_FALSE); |
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2176 } |
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2177 |
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2178 /* |
0 | 2179 * Set the compatible property to a value compliant with |
2180 * rev 2.1 of the IEEE1275 PCI binding. | |
881 | 2181 * (Also used for PCI-Express devices). |
0 | 2182 * |
2183 * pciVVVV,DDDD.SSSS.ssss.RR (0) | |
2184 * pciVVVV,DDDD.SSSS.ssss (1) | |
2185 * pciSSSS,ssss (2) | |
2186 * pciVVVV,DDDD.RR (3) | |
2187 * pciVVVV,DDDD (4) | |
2188 * pciclass,CCSSPP (5) | |
2189 * pciclass,CCSS (6) | |
2190 * | |
2191 * The Subsystem (SSSS) forms are not inserted if | |
2192 * subsystem-vendor-id is 0. | |
2193 * | |
881 | 2194 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above |
2195 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" | |
2196 * | |
0 | 2197 * Set with setprop and \x00 between each |
2198 * to generate the encoded string array form. | |
2199 */ | |
2200 void | |
2201 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, | |
881 | 2202 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, |
2203 int pciex) | |
0 | 2204 { |
881 | 2205 int i = 0; |
2206 int size = COMPAT_BUFSIZE; | |
2207 char *compat[13]; | |
0 | 2208 char *buf, *curr; |
2209 | |
2210 curr = buf = kmem_alloc(size, KM_SLEEP); | |
2211 | |
881 | 2212 if (pciex) { |
2213 if (subvenid) { | |
2214 compat[i++] = curr; /* form 0 */ | |
2215 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", | |
2216 vendorid, deviceid, subvenid, subdevid, revid); | |
2217 size -= strlen(curr) + 1; | |
2218 curr += strlen(curr) + 1; | |
2219 | |
2220 compat[i++] = curr; /* form 1 */ | |
2221 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", | |
2222 vendorid, deviceid, subvenid, subdevid); | |
2223 size -= strlen(curr) + 1; | |
2224 curr += strlen(curr) + 1; | |
2225 | |
2226 } | |
2227 compat[i++] = curr; /* form 3 */ | |
2228 (void) snprintf(curr, size, "pciex%x,%x.%x", | |
2229 vendorid, deviceid, revid); | |
2230 size -= strlen(curr) + 1; | |
2231 curr += strlen(curr) + 1; | |
2232 | |
2233 compat[i++] = curr; /* form 4 */ | |
2234 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); | |
2235 size -= strlen(curr) + 1; | |
2236 curr += strlen(curr) + 1; | |
2237 | |
2238 compat[i++] = curr; /* form 5 */ | |
2239 (void) snprintf(curr, size, "pciexclass,%06x", classcode); | |
2240 size -= strlen(curr) + 1; | |
2241 curr += strlen(curr) + 1; | |
2242 | |
2243 compat[i++] = curr; /* form 6 */ | |
2244 (void) snprintf(curr, size, "pciexclass,%04x", | |
2245 (classcode >> 8)); | |
2246 size -= strlen(curr) + 1; | |
2247 curr += strlen(curr) + 1; | |
2248 } | |
2249 | |
0 | 2250 if (subvenid) { |
2251 compat[i++] = curr; /* form 0 */ | |
2252 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", | |
2253 vendorid, deviceid, subvenid, subdevid, revid); | |
2254 size -= strlen(curr) + 1; | |
2255 curr += strlen(curr) + 1; | |
2256 | |
2257 compat[i++] = curr; /* form 1 */ | |
2258 (void) snprintf(curr, size, "pci%x,%x.%x.%x", | |
2259 vendorid, deviceid, subvenid, subdevid); | |
2260 size -= strlen(curr) + 1; | |
2261 curr += strlen(curr) + 1; | |
2262 | |
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2263 if (subsys_compat_exclude(vendorid, deviceid, subvenid, |
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2264 subdevid, revid, classcode) == B_FALSE) { |
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2265 compat[i++] = curr; /* form 2 */ |
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2266 (void) snprintf(curr, size, "pci%x,%x", subvenid, |
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2267 subdevid); |
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2268 size -= strlen(curr) + 1; |
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2269 curr += strlen(curr) + 1; |
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2270 } |
0 | 2271 } |
2272 compat[i++] = curr; /* form 3 */ | |
2273 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); | |
2274 size -= strlen(curr) + 1; | |
2275 curr += strlen(curr) + 1; | |
2276 | |
2277 compat[i++] = curr; /* form 4 */ | |
2278 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); | |
2279 size -= strlen(curr) + 1; | |
2280 curr += strlen(curr) + 1; | |
2281 | |
2282 compat[i++] = curr; /* form 5 */ | |
2283 (void) snprintf(curr, size, "pciclass,%06x", classcode); | |
2284 size -= strlen(curr) + 1; | |
2285 curr += strlen(curr) + 1; | |
2286 | |
2287 compat[i++] = curr; /* form 6 */ | |
2288 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); | |
881 | 2289 size -= strlen(curr) + 1; |
2290 curr += strlen(curr) + 1; | |
0 | 2291 |
2292 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, | |
2293 "compatible", compat, i); | |
2294 kmem_free(buf, COMPAT_BUFSIZE); | |
2295 } | |
2296 | |
2297 /* | |
2298 * Adjust the reg properties for a dual channel PCI-IDE device. | |
2299 * | |
2300 * NOTE: don't do anything that changes the order of the hard-decodes | |
2301 * and programmed BARs. The kernel driver depends on these values | |
2302 * being in this order regardless of whether they're for a 'native' | |
2303 * mode BAR or not. | |
2304 */ | |
2305 /* | |
2306 * config info for pci-ide devices | |
2307 */ | |
2308 static struct { | |
2309 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ | |
2310 uchar_t bar_offset; /* offset for alt status register */ | |
2311 ushort_t addr; /* compatibility mode base address */ | |
2312 ushort_t length; /* number of ports for this BAR */ | |
2313 } pciide_bar[] = { | |
2314 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ | |
2315 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ | |
2316 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ | |
2317 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ | |
2318 }; | |
2319 | |
2320 static int | |
2321 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) | |
2322 { | |
2323 int hard_decode = 0; | |
2324 | |
2325 /* | |
2326 * Adjust the base and len for the BARs of the PCI-IDE | |
2327 * device's primary and secondary controllers. The first | |
2328 * two BARs are for the primary controller and the next | |
2329 * two BARs are for the secondary controller. The fifth | |
2330 * and sixth bars are never adjusted. | |
2331 */ | |
2332 if (index >= 0 && index <= 3) { | |
2333 *lenp = pciide_bar[index].length; | |
2334 | |
2335 if (progcl & pciide_bar[index].native_mask) { | |
2336 *basep += pciide_bar[index].bar_offset; | |
2337 } else { | |
2338 *basep = pciide_bar[index].addr; | |
2339 hard_decode = 1; | |
2340 } | |
2341 } | |
2342 | |
2343 /* | |
2344 * if either base or len is zero make certain both are zero | |
2345 */ | |
2346 if (*basep == 0 || *lenp == 0) { | |
2347 *basep = 0; | |
2348 *lenp = 0; | |
2349 hard_decode = 0; | |
2350 } | |
2351 | |
2352 return (hard_decode); | |
2353 } | |
2354 | |
2355 | |
2356 /* | |
2357 * Add the "reg" and "assigned-addresses" property | |
2358 */ | |
2359 static int | |
2360 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, | |
2361 int config_op, int pciide) | |
2362 { | |
2363 uchar_t baseclass, subclass, progclass, header; | |
2364 ushort_t bar_sz; | |
2365 uint_t value = 0, len, devloc; | |
2366 uint_t base, base_hi, type; | |
2367 ushort_t offset, end; | |
2368 int max_basereg, j, reprogram = 0; | |
2369 uint_t phys_hi; | |
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2370 struct memlist **io_avail, **io_used; |
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2371 struct memlist **mem_avail, **mem_used; |
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2372 struct memlist **pmem_avail, **pmem_used; |
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2373 uchar_t res_bus; |
0 | 2374 |
2375 pci_regspec_t regs[16] = {{0}}; | |
2376 pci_regspec_t assigned[15] = {{0}}; | |
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2377 int nreg, nasgn; |
0 | 2378 |
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2379 io_avail = &pci_bus_res[bus].io_avail; |
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2380 io_used = &pci_bus_res[bus].io_used; |
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2381 mem_avail = &pci_bus_res[bus].mem_avail; |
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2382 mem_used = &pci_bus_res[bus].mem_used; |
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2383 pmem_avail = &pci_bus_res[bus].pmem_avail; |
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2384 pmem_used = &pci_bus_res[bus].pmem_used; |
0 | 2385 |
2386 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; | |
2387 regs[0].pci_phys_hi = devloc; | |
2388 nreg = 1; /* rest of regs[0] is all zero */ | |
2389 nasgn = 0; | |
2390 | |
2391 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); | |
2392 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); | |
2393 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); | |
2394 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; | |
2395 | |
2396 switch (header) { | |
2397 case PCI_HEADER_ZERO: | |
2398 max_basereg = PCI_BASE_NUM; | |
2399 break; | |
2400 case PCI_HEADER_PPB: | |
2401 max_basereg = PCI_BCNF_BASE_NUM; | |
2402 break; | |
2403 case PCI_HEADER_CARDBUS: | |
2404 max_basereg = PCI_CBUS_BASE_NUM; | |
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2405 reprogram = 1; |
0 | 2406 break; |
2407 default: | |
2408 max_basereg = 0; | |
2409 break; | |
2410 } | |
2411 | |
2412 /* | |
2413 * Create the register property by saving the current | |
2448
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2414 * value of the base register. Write 0xffffffff to the |
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2415 * base register. Read the value back to determine the |
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2416 * required size of the address space. Restore the base |
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2417 * register contents. |
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2418 * |
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2419 * Do not disable I/O and memory access for bridges; this |
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2420 * has the side-effect of making the bridge transparent to |
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2421 * secondary-bus activity (see sections 4.1-4.3 of the |
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2422 * PCI-PCI Bridge Spec V1.2). For non-bridges, disable |
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2423 * I/O and memory access to avoid difficulty with USB |
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2424 * emulation (see OHCI spec1.0a appendix B |
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|
2425 * "Host Controller Mapping") |
0 | 2426 */ |
2427 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); | |
2428 for (j = 0, offset = PCI_CONF_BASE0; offset < end; | |
2429 j++, offset += bar_sz) { | |
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6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
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11075
diff
changeset
|
2430 uint_t command; |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2431 |
0 | 2432 /* determine the size of the address space */ |
2433 base = pci_getl(bus, dev, func, offset); | |
11169
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2434 if (baseclass != PCI_CLASS_BRIDGE) { |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2435 command = (uint_t)pci_getw(bus, dev, func, |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2436 PCI_CONF_COMM); |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2437 pci_putw(bus, dev, func, PCI_CONF_COMM, |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2438 command & ~(PCI_COMM_MAE | PCI_COMM_IO)); |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2439 } |
0 | 2440 pci_putl(bus, dev, func, offset, 0xffffffff); |
2441 value = pci_getl(bus, dev, func, offset); | |
2442 pci_putl(bus, dev, func, offset, base); | |
11169
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6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
parents:
11075
diff
changeset
|
2443 if (baseclass != PCI_CLASS_BRIDGE) |
d46461938be8
6853338 pci_autoconfig: should disable IO/MEM decode while changing the BAR of OHCI host controller
Dana Myers <Dana.Myers@Sun.COM>
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diff
changeset
|
2444 pci_putw(bus, dev, func, PCI_CONF_COMM, command); |
0 | 2445 |
2446 /* construct phys hi,med.lo, size hi, lo */ | |
2447 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { | |
9427
5ae364e5dba1
6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
parents:
9284
diff
changeset
|
2448 int hard_decode = 0; |
5ae364e5dba1
6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
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changeset
|
2449 |
0 | 2450 /* i/o space */ |
2451 bar_sz = PCI_BAR_SZ_32; | |
2452 value &= PCI_BASE_IO_ADDR_M; | |
2453 len = ((value ^ (value-1)) + 1) >> 1; | |
2454 | |
2455 /* XXX Adjust first 4 IDE registers */ | |
2456 if (pciide) { | |
301
78b2c1965ca8
6288075 SATA hard disks can't be seen on W2100z machines
yt160523
parents:
277
diff
changeset
|
2457 if (subclass != PCI_MASS_IDE) |
0 | 2458 progclass = (PCI_IDE_IF_NATIVE_PRI | |
2459 PCI_IDE_IF_NATIVE_SEC); | |
2460 hard_decode = pciIdeAdjustBAR(progclass, j, | |
2461 &base, &len); | |
2462 } else if (value == 0) { | |
2463 /* skip base regs with size of 0 */ | |
2464 continue; | |
2465 } | |
2466 | |
9427
5ae364e5dba1
6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
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9284
diff
changeset
|
2467 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | |
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6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
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9284
diff
changeset
|
2468 (hard_decode ? PCI_RELOCAT_B : offset); |
5ae364e5dba1
6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
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9284
diff
changeset
|
2469 regs[nreg].pci_phys_low = hard_decode ? |
5ae364e5dba1
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9284
diff
changeset
|
2470 base & PCI_BASE_IO_ADDR_M : 0; |
5ae364e5dba1
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diff
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|
2471 assigned[nasgn].pci_phys_hi = |
5ae364e5dba1
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Max zhen <Max.Zhen@Sun.COM>
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9284
diff
changeset
|
2472 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; |
0 | 2473 regs[nreg].pci_size_low = |
2474 assigned[nasgn].pci_size_low = len; | |
2475 type = base & (~PCI_BASE_IO_ADDR_M); | |
2476 base &= PCI_BASE_IO_ADDR_M; | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2477 /* |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2478 * A device under a subtractive PPB can allocate |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2479 * resources from its parent bus if there is no resource |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2480 * available on its own bus. |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2481 */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2482 if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
2483 res_bus = bus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2484 while (pci_bus_res[res_bus].subtractive) { |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2485 res_bus = pci_bus_res[res_bus].par_bus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
changeset
|
2486 if (res_bus == (uchar_t)-1) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
2487 break; /* root bus already */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2488 if (pci_bus_res[res_bus].io_avail) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2489 io_avail = &pci_bus_res |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2490 [res_bus].io_avail; |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
2491 break; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
2492 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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5156
diff
changeset
|
2493 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2494 } |
0 | 2495 |
2496 /* | |
2497 * first pass - gather what's there | |
2498 * update/second pass - adjust/allocate regions | |
2499 * config - allocate regions | |
2500 */ | |
2501 if (config_op == CONFIG_INFO) { /* first pass */ | |
2502 /* take out of the resource map of the bus */ | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
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|
2503 if (base != 0) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2504 (void) memlist_remove(io_avail, base, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2505 len); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2506 memlist_insert(io_used, base, len); |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2507 } else { |
0 | 2508 reprogram = 1; |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2509 } |
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2510 pci_bus_res[bus].io_size += len; |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2511 } else if ((*io_avail && base == 0) || |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
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|
2512 pci_bus_res[bus].io_reprogram) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2513 base = (uint_t)memlist_find(io_avail, len, len); |
0 | 2514 if (base != 0) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2515 memlist_insert(io_used, base, len); |
0 | 2516 /* XXX need to worry about 64-bit? */ |
2517 pci_putl(bus, dev, func, offset, | |
2518 base | type); | |
2519 base = pci_getl(bus, dev, func, offset); | |
2520 base &= PCI_BASE_IO_ADDR_M; | |
2521 } | |
2522 if (base == 0) { | |
2523 cmn_err(CE_WARN, "failed to program" | |
825
4e9cc40be9a9
6344290 enumerate_bus_devs produces small memory leak in snv_27 on all x86/amd64 platforms
dmick
parents:
793
diff
changeset
|
2524 " IO space [%d/%d/%d] BAR@0x%x" |
4e9cc40be9a9
6344290 enumerate_bus_devs produces small memory leak in snv_27 on all x86/amd64 platforms
dmick
parents:
793
diff
changeset
|
2525 " length 0x%x", |
793
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
2526 bus, dev, func, offset, len); |
6927
bcfd34eb2a9c
6606300 Installation Hangs on Toshiba Satellite 5200(Dynabook G9) laptop
gs150176
parents:
6331
diff
changeset
|
2527 } |
0 | 2528 } |
2529 assigned[nasgn].pci_phys_low = base; | |
2530 nreg++, nasgn++; | |
2531 | |
2532 } else { | |
2533 /* memory space */ | |
2534 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { | |
2535 bar_sz = PCI_BAR_SZ_64; | |
2536 base_hi = pci_getl(bus, dev, func, offset + 4); | |
2537 phys_hi = PCI_ADDR_MEM64; | |
2538 } else { | |
2539 bar_sz = PCI_BAR_SZ_32; | |
2540 base_hi = 0; | |
2541 phys_hi = PCI_ADDR_MEM32; | |
2542 } | |
2543 | |
2544 /* skip base regs with size of 0 */ | |
2545 value &= PCI_BASE_M_ADDR_M; | |
2546 | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2547 if (value == 0) |
0 | 2548 continue; |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2549 |
0 | 2550 len = ((value ^ (value-1)) + 1) >> 1; |
2551 regs[nreg].pci_size_low = | |
2552 assigned[nasgn].pci_size_low = len; | |
2553 | |
2554 phys_hi |= (devloc | offset); | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
2555 if (base & PCI_BASE_PREF_M) |
0 | 2556 phys_hi |= PCI_PREFETCH_B; |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
2557 |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2558 /* |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2559 * A device under a subtractive PPB can allocate |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
2560 * resources from its parent bus if there is no resource |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
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|
2561 * available on its own bus. |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
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|
2562 */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
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|
2563 if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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5156
diff
changeset
|
2564 res_bus = bus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2565 while (pci_bus_res[res_bus].subtractive) { |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2566 res_bus = pci_bus_res[res_bus].par_bus; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2567 if (res_bus == (uchar_t)-1) |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2568 break; /* root bus already */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2569 mem_avail = |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2570 &pci_bus_res[res_bus].mem_avail; |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
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diff
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|
2571 pmem_avail = |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
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diff
changeset
|
2572 &pci_bus_res [res_bus].pmem_avail; |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
2573 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
2574 * Break out as long as at least |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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parents:
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diff
changeset
|
2575 * mem_avail is available |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
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|
2576 */ |
10251
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6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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parents:
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diff
changeset
|
2577 if ((*pmem_avail && |
8420
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diff
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|
2578 (phys_hi & PCI_PREFETCH_B)) || |
10251
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6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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parents:
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diff
changeset
|
2579 *mem_avail) |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
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diff
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|
2580 break; |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
changeset
|
2581 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2582 } |
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
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diff
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|
2583 |
0 | 2584 regs[nreg].pci_phys_hi = |
2585 assigned[nasgn].pci_phys_hi = phys_hi; | |
2586 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; | |
2587 assigned[nasgn].pci_phys_mid = base_hi; | |
2588 type = base & ~PCI_BASE_M_ADDR_M; | |
2589 base &= PCI_BASE_M_ADDR_M; | |
2590 | |
2591 if (config_op == CONFIG_INFO) { | |
2592 /* take out of the resource map of the bus */ | |
8420
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Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
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|
2593 if (base != NULL) { |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
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|
2594 /* remove from PMEM and MEM space */ |
10251
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6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
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diff
changeset
|
2595 (void) memlist_remove(mem_avail, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
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diff
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|
2596 base, len); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
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diff
changeset
|
2597 (void) memlist_remove(pmem_avail, |
8420
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6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
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diff
changeset
|
2598 base, len); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2599 /* only note as used in correct map */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2600 if (phys_hi & PCI_PREFETCH_B) |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2601 memlist_insert(pmem_used, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2602 base, len); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2603 else |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2604 memlist_insert(mem_used, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2605 base, len); |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2606 } else { |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2607 reprogram = 1; |
9588
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2608 } |
a4912846ca7d
6833233 pci_autoconfig: needs to consider child requirement for ppb reprogram MEM/IO size decision
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
9527
diff
changeset
|
2609 pci_bus_res[bus].mem_size += len; |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2610 } else if ((*mem_avail && base == NULL) || |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2611 pci_bus_res[bus].mem_reprogram) { |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2612 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2613 * When desired, attempt a prefetchable |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2614 * allocation first |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2615 */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2616 if (phys_hi & PCI_PREFETCH_B) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2617 base = (uint_t)memlist_find(pmem_avail, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2618 len, len); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2619 if (base != NULL) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2620 memlist_insert(pmem_used, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2621 base, len); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2622 (void) memlist_remove(mem_avail, |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
2623 base, len); |
8068
922479cd111c
6764872 resource conflict in pci MEM and Prefetch MEM
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
7987
diff
changeset
|
2624 } |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2625 } |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2626 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2627 * If prefetchable allocation was not |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2628 * desired, or failed, attempt ordinary |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2629 * memory allocation |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2630 */ |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2631 if (base == NULL) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2632 base = (uint_t)memlist_find(mem_avail, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2633 len, len); |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2634 if (base != NULL) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2635 memlist_insert(mem_used, |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2636 base, len); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2637 (void) memlist_remove( |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2638 pmem_avail, base, len); |
8068
922479cd111c
6764872 resource conflict in pci MEM and Prefetch MEM
Guoli Shu<Kerry.Shu@Sun.COM>
parents:
7987
diff
changeset
|
2639 } |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2640 } |
0 | 2641 if (base != NULL) { |
2642 pci_putl(bus, dev, func, offset, | |
2643 base | type); | |
2644 base = pci_getl(bus, dev, func, offset); | |
2645 base &= PCI_BASE_M_ADDR_M; | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2646 } else |
0 | 2647 cmn_err(CE_WARN, "failed to program " |
793
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
2648 "mem space [%d/%d/%d] BAR@0x%x" |
825
4e9cc40be9a9
6344290 enumerate_bus_devs produces small memory leak in snv_27 on all x86/amd64 platforms
dmick
parents:
793
diff
changeset
|
2649 " length 0x%x", |
793
d4faf770bcc4
6333242 pci I/O address allocation requires 1K alignment; fails
dmick
parents:
789
diff
changeset
|
2650 bus, dev, func, offset, len); |
0 | 2651 } |
2652 assigned[nasgn].pci_phys_low = base; | |
2653 nreg++, nasgn++; | |
2654 } | |
2655 } | |
2656 switch (header) { | |
2657 case PCI_HEADER_ZERO: | |
2658 offset = PCI_CONF_ROM; | |
2659 break; | |
2660 case PCI_HEADER_PPB: | |
2661 offset = PCI_BCNF_ROM; | |
2662 break; | |
2663 default: /* including PCI_HEADER_CARDBUS */ | |
2664 goto done; | |
2665 } | |
2666 | |
2667 /* | |
2668 * Add the expansion rom memory space | |
2669 * Determine the size of the ROM base reg; don't write reserved bits | |
2670 * ROM isn't in the PCI memory space. | |
2671 */ | |
2672 base = pci_getl(bus, dev, func, offset); | |
2673 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); | |
2674 value = pci_getl(bus, dev, func, offset); | |
2675 pci_putl(bus, dev, func, offset, base); | |
881 | 2676 if (value & PCI_BASE_ROM_ENABLE) |
2677 value &= PCI_BASE_ROM_ADDR_M; | |
2678 else | |
2679 value = 0; | |
0 | 2680 |
2681 if (value != 0) { | |
2682 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; | |
2683 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | | |
2684 PCI_ADDR_MEM32 | devloc) + offset; | |
2685 base &= PCI_BASE_ROM_ADDR_M; | |
2686 assigned[nasgn].pci_phys_low = base; | |
2687 len = ((value ^ (value-1)) + 1) >> 1; | |
2688 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; | |
2689 nreg++, nasgn++; | |
277 | 2690 /* take it out of the memory resource */ |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2691 if (base != NULL) { |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2692 (void) memlist_remove(mem_avail, base, len); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2693 memlist_insert(mem_used, base, len); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2694 pci_bus_res[bus].mem_size += len; |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2695 } |
0 | 2696 } |
2697 | |
2698 /* | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2699 * Account for "legacy" (alias) video adapter resources |
0 | 2700 */ |
2701 | |
2702 /* add the three hard-decode, aliased address spaces for VGA */ | |
2703 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || | |
2704 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { | |
2705 | |
2706 /* VGA hard decode 0x3b0-0x3bb */ | |
2707 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = | |
2708 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); | |
2709 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; | |
2710 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; | |
2711 nreg++, nasgn++; | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2712 (void) memlist_remove(io_avail, 0x3b0, 0xc); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2713 memlist_insert(io_used, 0x3b0, 0xc); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2714 pci_bus_res[bus].io_size += 0xc; |
0 | 2715 |
2716 /* VGA hard decode 0x3c0-0x3df */ | |
2717 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = | |
2718 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); | |
2719 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; | |
2720 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; | |
2721 nreg++, nasgn++; | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2722 (void) memlist_remove(io_avail, 0x3c0, 0x20); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2723 memlist_insert(io_used, 0x3c0, 0x20); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2724 pci_bus_res[bus].io_size += 0x20; |
0 | 2725 |
2726 /* Video memory */ | |
2727 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = | |
9427
5ae364e5dba1
6303630 "reg" property of pci-ide and display devices are not IEEE-1275 compliant
Max zhen <Max.Zhen@Sun.COM>
parents:
9284
diff
changeset
|
2728 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); |
0 | 2729 regs[nreg].pci_phys_low = |
2730 assigned[nasgn].pci_phys_low = 0xa0000; | |
2731 regs[nreg].pci_size_low = | |
2732 assigned[nasgn].pci_size_low = 0x20000; | |
2733 nreg++, nasgn++; | |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2734 /* remove from MEM and PMEM space */ |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2735 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2736 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2737 memlist_insert(mem_used, 0xa0000, 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2738 pci_bus_res[bus].mem_size += 0x20000; |
0 | 2739 } |
2740 | |
2741 /* add the hard-decode, aliased address spaces for 8514 */ | |
2742 if ((baseclass == PCI_CLASS_DISPLAY) && | |
4517 | 2743 (subclass == PCI_DISPLAY_VGA) && |
2744 (progclass & PCI_DISPLAY_IF_8514)) { | |
0 | 2745 |
2746 /* hard decode 0x2e8 */ | |
2747 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = | |
2748 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); | |
2749 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; | |
2750 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; | |
2751 nreg++, nasgn++; | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2752 (void) memlist_remove(io_avail, 0x2e8, 0x1); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2753 memlist_insert(io_used, 0x2e8, 0x1); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2754 pci_bus_res[bus].io_size += 0x1; |
0 | 2755 |
2756 /* hard decode 0x2ea-0x2ef */ | |
2757 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = | |
2758 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); | |
2759 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; | |
2760 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; | |
2761 nreg++, nasgn++; | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2762 (void) memlist_remove(io_avail, 0x2ea, 0x6); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2763 memlist_insert(io_used, 0x2ea, 0x6); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2764 pci_bus_res[bus].io_size += 0x6; |
0 | 2765 } |
2766 | |
2767 done: | |
2768 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", | |
2769 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); | |
2770 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, | |
2771 "assigned-addresses", | |
2772 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); | |
6927
bcfd34eb2a9c
6606300 Installation Hangs on Toshiba Satellite 5200(Dynabook G9) laptop
gs150176
parents:
6331
diff
changeset
|
2773 |
0 | 2774 return (reprogram); |
2775 } | |
2776 | |
2777 static void | |
881 | 2778 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, |
7987
df16f85b3404
6745976 pcie error handling for adjust for no aer on URs is incorrect.
Erwin T Tsaur <Erwin.Tsaur@Sun.COM>
parents:
7851
diff
changeset
|
2779 int pciex, ushort_t is_pci_bridge) |
0 | 2780 { |
881 | 2781 char *dev_type; |
0 | 2782 int i; |
2783 uint_t val, io_range[2], mem_range[2], pmem_range[2]; | |
2784 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); | |
2785 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); | |
6095
ffd81788f184
6324898 pci resource allocator needs to be aware of subtractive bridges
gs150176
parents:
5156
diff
changeset
|
2786 uchar_t progclass; |
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2787 |
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2788 ASSERT(secbus <= subbus); |
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2789 |
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2790 /* |
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2791 * Check if it's a subtractive PPB. |
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2792 */ |
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2793 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); |
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2794 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) |
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2795 pci_bus_res[secbus].subtractive = B_TRUE; |
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2796 |
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2797 /* |
397
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2798 * Some BIOSes lie about max pci busses, we allow for |
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2799 * such mistakes here |
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2800 */ |
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|
2801 if (subbus > pci_bios_maxbus) { |
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2802 pci_bios_maxbus = subbus; |
397
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2803 alloc_res_array(); |
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2804 } |
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2805 |
0 | 2806 ASSERT(pci_bus_res[secbus].dip == NULL); |
2807 pci_bus_res[secbus].dip = dip; | |
2808 pci_bus_res[secbus].par_bus = bus; | |
2809 | |
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2810 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; |
881 | 2811 |
0 | 2812 /* setup bus number hierarchy */ |
2813 pci_bus_res[secbus].sub_bus = subbus; | |
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2814 /* |
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2815 * Keep track of the largest subordinate bus number (this is essential |
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2816 * for peer busses because there is no other way of determining its |
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2817 * subordinate bus number). |
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2818 */ |
0 | 2819 if (subbus > pci_bus_res[bus].sub_bus) |
2820 pci_bus_res[bus].sub_bus = subbus; | |
2466
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2821 /* |
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2822 * Loop through subordinate busses, initializing their parent bus |
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2823 * field to this bridge's parent. The subordinate busses' parent |
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2824 * fields may very well be further refined later, as child bridges |
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2825 * are enumerated. (The value is to note that the subordinate busses |
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2826 * are not peer busses by changing their par_bus fields to anything |
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2827 * other than -1.) |
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2828 */ |
0 | 2829 for (i = secbus + 1; i <= subbus; i++) |
2830 pci_bus_res[i].par_bus = bus; | |
2831 | |
2832 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, | |
881 | 2833 "device_type", dev_type); |
0 | 2834 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, |
2835 "#address-cells", 3); | |
2836 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, | |
2837 "#size-cells", 2); | |
2838 | |
2839 /* | |
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2840 * Collect bridge window specifications, and use them to populate |
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2841 * the "avail" resources for the bus. Not all of those resources will |
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2842 * end up being available; this is done top-down, and so the initial |
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2843 * collection of windows populates the 'ranges' property for the |
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|
2844 * bus node. Later, as children are found, resources are removed from |
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2845 * the 'avail' list, so that it becomes the freelist for |
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2846 * this point in the tree. ranges may be set again after bridge |
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2847 * reprogramming in fix_ppb_res(), in which case it's set from |
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2848 * used + avail. |
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|
2849 * |
0 | 2850 * According to PPB spec, the base register should be programmed |
2851 * with a value bigger than the limit register when there are | |
2852 * no resources available. This applies to io, memory, and | |
2853 * prefetchable memory. | |
2854 */ | |
4517 | 2855 |
2856 /* | |
2857 * io range | |
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2858 * We determine i/o windows that are left unconfigured by BIOS |
4517 | 2859 * through its i/o enable bit as Microsoft recommends OEMs to do. |
2860 * If it is unset, we disable i/o and mark it for reconfiguration in | |
2861 * later passes by setting the base > limit | |
2862 */ | |
2863 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); | |
2864 if (val & PCI_COMM_IO) { | |
2865 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); | |
2866 io_range[0] = ((val & 0xf0) << 8); | |
2867 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); | |
2868 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; | |
2869 } else { | |
2870 io_range[0] = 0x9fff; | |
2871 io_range[1] = 0x1000; | |
2872 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, | |
2873 (uint8_t)((io_range[0] >> 8) & 0xf0)); | |
2874 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, | |
2875 (uint8_t)((io_range[1] >> 8) & 0xf0)); | |
2876 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); | |
2877 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); | |
2878 } | |
2879 | |
0 | 2880 if (io_range[0] != 0 && io_range[0] < io_range[1]) { |
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|
2881 memlist_insert(&pci_bus_res[secbus].io_avail, |
0 | 2882 (uint64_t)io_range[0], |
2883 (uint64_t)(io_range[1] - io_range[0] + 1)); | |
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2884 memlist_insert(&pci_bus_res[bus].io_used, |
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2885 (uint64_t)io_range[0], |
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2886 (uint64_t)(io_range[1] - io_range[0] + 1)); |
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|
2887 if (pci_bus_res[bus].io_avail != NULL) { |
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|
2888 (void) memlist_remove(&pci_bus_res[bus].io_avail, |
0 | 2889 (uint64_t)io_range[0], |
2890 (uint64_t)(io_range[1] - io_range[0] + 1)); | |
2891 } | |
2892 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", | |
2893 secbus, io_range[0], io_range[1]); | |
25 | 2894 /* if 32-bit supported, make sure upper bits are not set */ |
2895 if ((val & 0xf) == 1 && | |
2896 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { | |
2897 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" | |
2898 " pci-pci bridge [%d/%d/%d]", bus, dev, func); | |
2899 } | |
0 | 2900 } |
2901 | |
2902 /* mem range */ | |
2903 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); | |
2904 mem_range[0] = ((val & 0xFFF0) << 16); | |
2905 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); | |
2906 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; | |
2907 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { | |
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|
2908 memlist_insert(&pci_bus_res[secbus].mem_avail, |
0 | 2909 (uint64_t)mem_range[0], |
2910 (uint64_t)(mem_range[1] - mem_range[0] + 1)); | |
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2911 memlist_insert(&pci_bus_res[bus].mem_used, |
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2912 (uint64_t)mem_range[0], |
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2913 (uint64_t)(mem_range[1] - mem_range[0] + 1)); |
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|
2914 /* remove from parent resource list */ |
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2915 (void) memlist_remove(&pci_bus_res[bus].mem_avail, |
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|
2916 (uint64_t)mem_range[0], |
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|
2917 (uint64_t)(mem_range[1] - mem_range[0] + 1)); |
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2918 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, |
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2919 (uint64_t)mem_range[0], |
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|
2920 (uint64_t)(mem_range[1] - mem_range[0] + 1)); |
0 | 2921 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", |
2922 secbus, mem_range[0], mem_range[1]); | |
2923 } | |
2924 | |
2925 /* prefetchable memory range */ | |
2926 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); | |
2927 pmem_range[0] = ((val & 0xFFF0) << 16); | |
2928 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); | |
2929 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; | |
2930 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { | |
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2931 memlist_insert(&pci_bus_res[secbus].pmem_avail, |
0 | 2932 (uint64_t)pmem_range[0], |
2933 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); | |
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2934 memlist_insert(&pci_bus_res[bus].pmem_used, |
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2935 (uint64_t)pmem_range[0], |
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2936 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); |
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2937 /* remove from parent resource list */ |
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2938 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, |
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2939 (uint64_t)pmem_range[0], |
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|
2940 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); |
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2941 (void) memlist_remove(&pci_bus_res[bus].mem_avail, |
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2942 (uint64_t)pmem_range[0], |
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|
2943 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); |
0 | 2944 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", |
2945 secbus, pmem_range[0], pmem_range[1]); | |
25 | 2946 /* if 64-bit supported, make sure upper bits are not set */ |
2947 if ((val & 0xf) == 1 && | |
2948 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { | |
2949 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" | |
2950 " pci-pci bridge [%d/%d/%d]", bus, dev, func); | |
2951 } | |
0 | 2952 } |
2953 | |
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2954 /* |
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2955 * Add VGA legacy resources to the bridge's pci_bus_res if it |
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|
2956 * has VGA_ENABLE set. Note that we put them in 'avail', |
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2957 * because that's used to populate the ranges prop; they'll be |
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2958 * removed from there by the VGA device once it's found. Also, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2959 * remove them from the parent's available list and note them as |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2960 * used in the parent. |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2961 */ |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2962 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2963 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2964 PCI_BCNF_BCNTRL_VGA_ENABLE) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2965 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2966 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2967 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2968 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2969 if (pci_bus_res[bus].io_avail != NULL) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2970 (void) memlist_remove(&pci_bus_res[bus].io_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2971 0x3b0, 0xc); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2972 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2973 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2974 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2975 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2976 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2977 if (pci_bus_res[bus].io_avail != NULL) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2978 (void) memlist_remove(&pci_bus_res[bus].io_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2979 0x3c0, 0x20); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2980 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2981 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2982 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2983 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2984 |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2985 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2986 if (pci_bus_res[bus].mem_avail != NULL) { |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2987 (void) memlist_remove(&pci_bus_res[bus].mem_avail, |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2988 0xa0000, 0x20000); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2989 } |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
2990 } |
0 | 2991 add_bus_range_prop(secbus); |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
2992 add_ranges_prop(secbus, 1); |
0 | 2993 } |
2994 | |
58
f37950de9bc8
6259731 cfgadm_pci plugin 'hpc_card_info_t' tables are out of date
anish
parents:
25
diff
changeset
|
2995 extern const struct pci_class_strings_s class_pci[]; |
f37950de9bc8
6259731 cfgadm_pci plugin 'hpc_card_info_t' tables are out of date
anish
parents:
25
diff
changeset
|
2996 extern int class_pci_items; |
0 | 2997 |
2998 static void | |
2999 add_model_prop(dev_info_t *dip, uint_t classcode) | |
3000 { | |
3001 const char *desc; | |
3002 int i; | |
3003 uchar_t baseclass = classcode >> 16; | |
3004 uchar_t subclass = (classcode >> 8) & 0xff; | |
3005 uchar_t progclass = classcode & 0xff; | |
3006 | |
3007 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { | |
3008 desc = "IDE controller"; | |
3009 } else { | |
3010 for (desc = 0, i = 0; i < class_pci_items; i++) { | |
3011 if ((baseclass == class_pci[i].base_class) && | |
3012 (subclass == class_pci[i].sub_class) && | |
3013 (progclass == class_pci[i].prog_class)) { | |
58
f37950de9bc8
6259731 cfgadm_pci plugin 'hpc_card_info_t' tables are out of date
anish
parents:
25
diff
changeset
|
3014 desc = class_pci[i].actual_desc; |
0 | 3015 break; |
3016 } | |
3017 } | |
58
f37950de9bc8
6259731 cfgadm_pci plugin 'hpc_card_info_t' tables are out of date
anish
parents:
25
diff
changeset
|
3018 if (i == class_pci_items) |
0 | 3019 desc = "Unknown class of pci/pnpbios device"; |
3020 } | |
3021 | |
3022 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", | |
3023 (char *)desc); | |
3024 } | |
3025 | |
3026 static void | |
3027 add_bus_range_prop(int bus) | |
3028 { | |
3029 int bus_range[2]; | |
3030 | |
3031 if (pci_bus_res[bus].dip == NULL) | |
3032 return; | |
3033 bus_range[0] = bus; | |
3034 bus_range[1] = pci_bus_res[bus].sub_bus; | |
3035 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, | |
3036 "bus-range", (int *)bus_range, 2); | |
3037 } | |
3038 | |
603
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3039 /* |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3040 * Add slot-names property for any named pci hot-plug slots |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3041 */ |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3042 static void |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3043 add_bus_slot_names_prop(int bus) |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3044 { |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3045 char slotprop[256]; |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3046 int len; |
12054
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3047 extern int pci_irq_nroutes; |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3048 char *slotcap_name; |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3049 |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3050 /* |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3051 * If no irq routing table, then go with the slot-names as set up |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3052 * in pciex_slot_names_prop() from slot capability register (if any). |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3053 */ |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3054 if (pci_irq_nroutes == 0) |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3055 return; |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3056 |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3057 /* |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3058 * Otherise delete the slot-names we already have and use the irq |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3059 * routing table values as returned by pci_slot_names_prop() instead, |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3060 * but keep any property of value "pcie0" as that can't be represented |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3061 * in the irq routing table. |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3062 */ |
5156
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3063 if (pci_bus_res[bus].dip != NULL) { |
12054
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3064 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pci_bus_res[bus].dip, |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3065 DDI_PROP_DONTPASS, "slot-names", &slotcap_name) != |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3066 DDI_SUCCESS || strcmp(slotcap_name, "pcie0") != 0) |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3067 (void) ndi_prop_remove(DDI_DEV_T_NONE, |
bcacc803343d
6688291 PCI-E slot number of 0 should be respected
Stephen Hanson <Stephen.Hanson@Sun.COM>
parents:
11600
diff
changeset
|
3068 pci_bus_res[bus].dip, "slot-names"); |
5156
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3069 } |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3070 |
603
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3071 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3072 if (len > 0) { |
2466
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3073 /* |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3074 * Only create a peer bus node if this bus may be a peer bus. |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3075 * It may be a peer bus if the dip is NULL and if par_bus is |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3076 * -1 (par_bus is -1 if this bus was not found to be |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3077 * subordinate to any PCI-PCI bridge). |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3078 * If it's not a peer bus, then the ACPI BBN-handling code |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3079 * will remove it later. |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3080 */ |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3081 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3082 pci_bus_res[bus].dip == NULL) { |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3083 |
603
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3084 create_root_bus_dip(bus); |
2466
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3085 } |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3086 if (pci_bus_res[bus].dip != NULL) { |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3087 ASSERT((len % sizeof (int)) == 0); |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3088 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3089 pci_bus_res[bus].dip, "slot-names", |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3090 (int *)slotprop, len / sizeof (int)); |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3091 } else { |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3092 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3093 "IRQ routing table; Not adding slot-names " |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3094 "property for incorrect bus %d", bus); |
bfa6f0caa03d
6424853 pci_autoconfig should work around broken pci irq routing table entries for the slot-names property
sethg
parents:
2448
diff
changeset
|
3095 } |
603
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3096 } |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3097 } |
3c7918e59df0
6323578 slot-names property got lost in the new boot shuffle
jg
parents:
397
diff
changeset
|
3098 |
8420
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
3099 /* |
448e8a10ab62
6782932 pci_autoconfig: PCI enumerator needs to use PCI root-bus _CRS when present
Dana Myers <Dana.Myers@Sun.COM>
parents:
8215
diff
changeset
|
3100 * Handle both PCI root and PCI-PCI bridge range properties; |
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3101 * non-zero 'ppb' argument select PCI-PCI bridges versus root. |
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|
3102 */ |
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|
3103 static void |
448e8a10ab62
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|
3104 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) |
0 | 3105 { |
8420
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|
3106 ppb_ranges_t *ppb_rp = *rp; |
448e8a10ab62
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Dana Myers <Dana.Myers@Sun.COM>
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|
3107 pci_ranges_t *pci_rp = *rp; |
0 | 3108 |
8420
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|
3109 while (entry != NULL) { |
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|
3110 if (ppb) { |
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|
3111 ppb_rp->child_high = ppb_rp->parent_high = type; |
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|
3112 ppb_rp->child_mid = ppb_rp->parent_mid = |
11474
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|
3113 (uint32_t)(entry->ml_address >> 32); /* XXX */ |
8420
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|
3114 ppb_rp->child_low = ppb_rp->parent_low = |
11474
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|
3115 (uint32_t)entry->ml_address; |
8420
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|
3116 ppb_rp->size_high = |
11474
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|
3117 (uint32_t)(entry->ml_size >> 32); /* XXX */ |
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|
3118 ppb_rp->size_low = (uint32_t)entry->ml_size; |
8420
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|
3119 *rp = ++ppb_rp; |
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|
3120 } else { |
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|
3121 pci_rp->child_high = type; |
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|
3122 pci_rp->child_mid = pci_rp->parent_high = |
11474
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|
3123 (uint32_t)(entry->ml_address >> 32); /* XXX */ |
8420
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|
3124 pci_rp->child_low = pci_rp->parent_low = |
11474
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|
3125 (uint32_t)entry->ml_address; |
8420
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|
3126 pci_rp->size_high = |
11474
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|
3127 (uint32_t)(entry->ml_size >> 32); /* XXX */ |
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Jonathan Adams <Jonathan.Adams@Sun.COM>
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|
3128 pci_rp->size_low = (uint32_t)entry->ml_size; |
8420
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|
3129 *rp = ++pci_rp; |
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|
3130 } |
11474
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|
3131 entry = entry->ml_next; |
8420
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|
3132 } |
0 | 3133 } |
3134 | |
3135 static void | |
8420
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|
3136 add_ranges_prop(int bus, int ppb) |
0 | 3137 { |
8420
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|
3138 int total, alloc_size; |
448e8a10ab62
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|
3139 void *rp, *next_rp; |
10251
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Dan Mick <Dan.Mick@Sun.COM>
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|
3140 struct memlist *iolist, *memlist, *pmemlist; |
8420
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|
3141 |
8738
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diff
changeset
|
3142 /* no devinfo node - unused bus, return */ |
5797a74500fc
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|
3143 if (pci_bus_res[bus].dip == NULL) |
5797a74500fc
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|
3144 return; |
5797a74500fc
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changeset
|
3145 |
10251
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|
3146 iolist = memlist = pmemlist = (struct memlist *)NULL; |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3147 |
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6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3148 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3149 memlist_merge(&pci_bus_res[bus].io_used, &iolist); |
e188a43bda3c
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|
3150 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); |
e188a43bda3c
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|
3151 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3152 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3153 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3154 |
e188a43bda3c
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|
3155 total = memlist_count(iolist); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3156 total += memlist_count(memlist); |
e188a43bda3c
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|
3157 total += memlist_count(pmemlist); |
0 | 3158 |
8420
448e8a10ab62
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|
3159 /* no property is created if no ranges are present */ |
448e8a10ab62
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|
3160 if (total == 0) |
448e8a10ab62
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|
3161 return; |
448e8a10ab62
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|
3162 |
448e8a10ab62
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|
3163 alloc_size = total * |
448e8a10ab62
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|
3164 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); |
448e8a10ab62
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|
3165 |
448e8a10ab62
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|
3166 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); |
0 | 3167 |
10251
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|
3168 memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
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|
3169 memlist_to_ranges(&next_rp, memlist, |
8420
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|
3170 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); |
10251
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|
3171 memlist_to_ranges(&next_rp, pmemlist, |
8420
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|
3172 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); |
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|
3173 |
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|
3174 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, |
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|
3175 "ranges", (int *)rp, alloc_size / sizeof (int)); |
0 | 3176 |
8420
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|
3177 kmem_free(rp, alloc_size); |
10251
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|
3178 memlist_free_all(&iolist); |
e188a43bda3c
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|
3179 memlist_free_all(&memlist); |
e188a43bda3c
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|
3180 memlist_free_all(&pmemlist); |
8420
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|
3181 } |
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|
3182 |
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|
3183 static void |
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3184 memlist_remove_list(struct memlist **list, struct memlist *remove_list) |
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|
3185 { |
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|
3186 while (list && *list && remove_list) { |
11474
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|
3187 (void) memlist_remove(list, remove_list->ml_address, |
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|
3188 remove_list->ml_size); |
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|
3189 remove_list = remove_list->ml_next; |
8420
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|
3190 } |
0 | 3191 } |
3192 | |
3193 static int | |
3194 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) | |
3195 { | |
3196 int i = 0; | |
3197 | |
3198 while (list) { | |
3199 /* assume 32-bit addresses */ | |
3200 sp->pci_phys_hi = type; | |
3201 sp->pci_phys_mid = 0; | |
11474
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|
3202 sp->pci_phys_low = (uint32_t)list->ml_address; |
0 | 3203 sp->pci_size_hi = 0; |
11474
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|
3204 sp->pci_size_low = (uint32_t)list->ml_size; |
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|
3205 |
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|
3206 list = list->ml_next; |
0 | 3207 sp++, i++; |
3208 } | |
3209 return (i); | |
3210 } | |
3211 | |
3212 static void | |
3213 add_bus_available_prop(int bus) | |
3214 { | |
3215 int i, count; | |
3216 struct pci_phys_spec *sp; | |
3217 | |
8738
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|
3218 /* no devinfo node - unused bus, return */ |
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|
3219 if (pci_bus_res[bus].dip == NULL) |
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|
3220 return; |
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|
3221 |
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|
3222 count = memlist_count(pci_bus_res[bus].io_avail) + |
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|
3223 memlist_count(pci_bus_res[bus].mem_avail) + |
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
3224 memlist_count(pci_bus_res[bus].pmem_avail); |
0 | 3225 |
3226 if (count == 0) /* nothing available */ | |
3227 return; | |
3228 | |
3229 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); | |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
3230 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, |
0 | 3231 PCI_ADDR_IO | PCI_REG_REL_M); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
3232 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, |
0 | 3233 PCI_ADDR_MEM32 | PCI_REG_REL_M); |
10251
e188a43bda3c
6831312 cpu_freq / cpu_freq_hz is zero on IBM HS22 Nehalem blade
Dan Mick <Dan.Mick@Sun.COM>
parents:
9588
diff
changeset
|
3234 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, |
0 | 3235 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); |
3236 ASSERT(i == count); | |
3237 | |
3238 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, | |
3239 "available", (int *)sp, | |
3240 i * sizeof (struct pci_phys_spec) / sizeof (int)); | |
3241 kmem_free(sp, count * sizeof (*sp)); | |
3242 } | |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3243 |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3244 static void |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3245 alloc_res_array(void) |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3246 { |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3247 static int array_size = 0; |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3248 int old_size; |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3249 void *old_res; |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3250 |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3251 if (array_size > pci_bios_maxbus + 1) |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3252 return; /* array is big enough */ |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3253 |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3254 old_size = array_size; |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3255 old_res = pci_bus_res; |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3256 |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3257 if (array_size == 0) |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3258 array_size = 16; /* start with a reasonable number */ |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3259 |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3260 while (array_size <= pci_bios_maxbus + 1) |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3261 array_size <<= 1; |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3262 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3263 array_size * sizeof (struct pci_bus_resource), KM_SLEEP); |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3264 |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3265 if (old_res) { /* copy content and free old array */ |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3266 bcopy(old_res, pci_bus_res, |
13019
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3267 old_size * sizeof (struct pci_bus_resource)); |
05a4e7665357
6973912 pci_autoconfig: alloc_res_array() feels a little off (by one)
Praveen Kumar Dasaraju Rama <Praveen.Dasaraju@Oracle.COM>
parents:
12683
diff
changeset
|
3268 kmem_free(old_res, old_size * sizeof (struct pci_bus_resource)); |
397
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3269 } |
0f40382f2a76
6309532 don't trust that BIOS - it's lying about its number of PCI buses
szhou
parents:
301
diff
changeset
|
3270 } |
3745
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3271 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3272 static void |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3273 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3274 ushort_t deviceid) |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3275 { |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3276 static dev_info_t *ioapicsnode = NULL; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3277 static int numioapics = 0; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3278 dev_info_t *ioapic_node; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3279 uint64_t physaddr; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3280 uint32_t lobase, hibase = 0; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3281 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3282 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3283 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3284 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3285 /* We (and the rest of the world) only support memory-mapped IOAPICs */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3286 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3287 return; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3288 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3289 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3290 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3291 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3292 lobase &= PCI_BASE_M_ADDR_M; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3293 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3294 physaddr = (((uint64_t)hibase) << 32) | lobase; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3295 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3296 /* |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3297 * Create a nexus node for all IOAPICs under the root node. |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3298 */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3299 if (ioapicsnode == NULL) { |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3300 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3301 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3302 return; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3303 } |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3304 (void) ndi_devi_online(ioapicsnode, 0); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3305 } |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3306 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3307 /* |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3308 * Create a child node for this IOAPIC |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3309 */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3310 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3311 DEVI_SID_NODEID, numioapics++); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3312 if (ioapic_node == NULL) { |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3313 return; |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3314 } |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3315 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3316 /* Vendor and Device ID */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3317 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3318 IOAPICS_PROP_VENID, vendorid); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3319 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3320 IOAPICS_PROP_DEVID, deviceid); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3321 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3322 /* device_type */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3323 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3324 "device_type", IOAPICS_DEV_TYPE); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3325 |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3326 /* reg */ |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3327 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3328 "reg", physaddr); |
9405aaf598cd
6490454 pcplusmp: Need workaround for IOAPIC masking erratum
sethg
parents:
3446
diff
changeset
|
3329 } |
5156
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3330 |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3331 /* |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3332 * NOTE: For PCIe slots, the name is generated from the slot number |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3333 * information obtained from Slot Capabilities register. |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3334 * For non-PCIe slots, it is generated based on the slot number |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3335 * information in the PCI IRQ table. |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3336 */ |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3337 static void |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3338 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3339 { |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3340 char slotprop[256]; |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3341 int len; |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3342 |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3343 bzero(slotprop, sizeof (slotprop)); |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3344 |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3345 /* set mask to 1 as there is only one slot (i.e dev 0) */ |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3346 *(uint32_t *)slotprop = 1; |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3347 len = 4; |
6b4e412afcf5
6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
prasad
parents:
5149
diff
changeset
|
3348 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", |
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6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
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3349 slot_num); |
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6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
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3350 len += strlen(slotprop + len) + 1; |
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6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
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3351 len += len % 4; |
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6524011 pcie slots show up in cfgadm as "Slot<n>" vs. "pcie<n>" in Nevada/s10u4
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3352 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", |
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3353 (int *)slotprop, len / sizeof (int)); |
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3354 } |
11245
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3355 |
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3356 /* |
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3357 * This is currently a hack, a better way is needed to determine if it |
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3358 * is a PCIE platform. |
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6831378 identify device type during early boot
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3359 */ |
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6831378 identify device type during early boot
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3360 static boolean_t |
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6831378 identify device type during early boot
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3361 is_pcie_platform() |
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3362 { |
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6831378 identify device type during early boot
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3363 uint8_t bus; |
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|
3364 |
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3365 for (bus = 0; bus < pci_bios_maxbus; bus++) { |
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3366 if (look_for_any_pciex_device(bus)) |
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3367 return (B_TRUE); |
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3368 } |
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3369 return (B_FALSE); |
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3370 } |
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|
3371 |
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|
3372 /* |
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3373 * Enable reporting of AER capability next pointer. |
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3374 * This needs to be done only for CK8-04 devices |
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3375 * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13 |
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3376 * NOTE: BIOS is disabling this, it needs to be enabled temporarily |
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3377 * |
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3378 * This function is adapted from npe_ck804_fix_aer_ptr(), and is |
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3379 * called from pci_boot.c. |
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3380 */ |
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3381 static void |
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3382 ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf) |
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3383 { |
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3384 dev_info_t *rcdip; |
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3385 ushort_t cya1; |
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3386 |
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3387 rcdip = pcie_get_rc_dip(dip); |
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3388 ASSERT(rcdip != NULL); |
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|
3389 |
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3390 if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) == |
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3391 NVIDIA_VENDOR_ID) && |
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3392 (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) == |
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3393 NVIDIA_CK804_DEVICE_ID) && |
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3394 (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >= |
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3395 NVIDIA_CK804_AER_VALID_REVID)) { |
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3396 cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF); |
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3397 if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK)) |
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3398 (void) pci_cfgacc_put16(rcdip, bdf, |
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3399 NVIDIA_CK804_VEND_CYA1_OFF, |
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|
3400 cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL); |
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3401 } |
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3402 } |