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annotate usr/src/uts/common/io/ntxn/nic_phan_reg.h @ 7956:59ff93e4da95

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PSARC 2008/045 NetXen 10 Gigabit Ethernet Driver 6472698 NetXen 1Gb/10Gb nic driver
author lucy wang - Sun Microsystems - Beijing China <xiuyan.wang@Sun.COM>
date Tue, 28 Oct 2008 10:06:13 +0800
parents
children 5dca9cd6354a
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7956
59ff93e4da95 PSARC 2008/045 NetXen 10 Gigabit Ethernet Driver
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1 /*
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2 * CDDL HEADER START
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3 *
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4 * The contents of this file are subject to the terms of the
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5 * Common Development and Distribution License (the "License").
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6 * You may not use this file except in compliance with the License.
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7 *
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8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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9 * or http://www.opensolaris.org/os/licensing.
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10 * See the License for the specific language governing permissions
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11 * and limitations under the License.
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12 *
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13 * When distributing Covered Code, include this CDDL HEADER in each
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14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 * If applicable, add the following below this CDDL HEADER, with the
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16 * fields enclosed by brackets "[]" replaced with your own identifying
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17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 *
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19 * CDDL HEADER END
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20 */
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21 /*
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22 * Copyright 2008 NetXen, Inc. All rights reserved.
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23 * Use is subject to license terms.
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24 */
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25 #ifndef NIC_PHAN_REG_H
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26 #define NIC_PHAN_REG_H
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27
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28 #define NIC_CRB_BASE UNM_CAM_RAM(0x200)
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29 #define NIC_CRB_BASE_2 UNM_CAM_RAM(0x700)
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30 #define UNM_NIC_REG(X) (NIC_CRB_BASE+(X))
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31 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2+(X))
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32
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33 #define CRB_CUT_THRU_PAGE_SIZE UNM_CAM_RAM(0x170)
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34
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35 #define CRB_CMD_PRODUCER_OFFSET UNM_NIC_REG(0x08)
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36 #define CRB_CMD_CONSUMER_OFFSET UNM_NIC_REG(0x0c)
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37 /* C0 EPG BUG */
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38 #define CRB_PAUSE_ADDR_LO UNM_NIC_REG(0x10)
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39 #define CRB_PAUSE_ADDR_HI UNM_NIC_REG(0x14)
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40 #define NX_CDRP_CRB_OFFSET UNM_NIC_REG(0x18)
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41 #define NX_ARG1_CRB_OFFSET UNM_NIC_REG(0x1c)
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42 #define NX_ARG2_CRB_OFFSET UNM_NIC_REG(0x20)
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43 #define NX_ARG3_CRB_OFFSET UNM_NIC_REG(0x24)
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44 #define NX_SIGN_CRB_OFFSET UNM_NIC_REG(0x28)
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45 #define CRB_CMDPEG_CMDRING UNM_NIC_REG(0x38)
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46 #define CRB_HOST_DUMMY_BUF_ADDR_HI UNM_NIC_REG(0x3c)
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47 #define CRB_HOST_DUMMY_BUF_ADDR_LO UNM_NIC_REG(0x40)
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48 #define CRB_CMDPEG_STATE UNM_NIC_REG(0x50)
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49 /* interrupt coalescing */
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50 #define CRB_GLOBAL_INT_COAL UNM_NIC_REG(0x64)
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51 #define CRB_INT_COAL_MODE UNM_NIC_REG(0x68)
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52 #define CRB_MAX_RCV_BUFS UNM_NIC_REG(0x6c)
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53 #define CRB_TX_INT_THRESHOLD UNM_NIC_REG(0x70)
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54 #define CRB_RX_PKT_TIMER UNM_NIC_REG(0x74)
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55 #define CRB_TX_PKT_TIMER UNM_NIC_REG(0x78)
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56 #define CRB_RX_PKT_CNT UNM_NIC_REG(0x7c)
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57 #define CRB_RX_TMR_CNT UNM_NIC_REG(0x80)
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58 #define CRB_RCV_INTR_COUNT UNM_NIC_REG(0x84)
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59 /* XG Link status */
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60 #define CRB_XG_STATE UNM_NIC_REG(0x94)
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61 /* XG PF Link status */
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62 #define CRB_XG_STATE_P3 UNM_NIC_REG(0x98)
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63 /* Debug -performance */
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64 #define CRB_TX_STATE UNM_NIC_REG(0xac)
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65 #define CRB_TX_COUNT UNM_NIC_REG(0xb0)
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66 #define CRB_RX_STATE UNM_NIC_REG(0xb4)
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67 #define CRB_RX_PERF_DEBUG_1 UNM_NIC_REG(0xb8)
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68 /* LRO On/OFF */
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69 #define CRB_RX_LRO_CONTROL UNM_NIC_REG(0xbc)
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70 /* Multiport Mode */
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71 #define CRB_MPORT_MODE UNM_NIC_REG(0xc4)
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72 #define CRB_INT_VECTOR UNM_NIC_REG(0xd4)
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73 #define CRB_PF_LINK_SPEED_1 UNM_NIC_REG(0xe8)
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74 #define CRB_PF_LINK_SPEED_2 UNM_NIC_REG(0xec)
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75 #define CRB_HOST_DUMMY_BUF UNM_NIC_REG(0xfc)
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76
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77 #define CRB_SCRATCHPAD_TEST UNM_NIC_REG(0x280)
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78
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79 #define CRB_RCVPEG_STATE UNM_NIC_REG(0x13c)
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80
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81 /* 12 registers to store MAC addresses for 8 PCI functions */
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82 #define CRB_MAC_BLOCK_START UNM_CAM_RAM(0x1c0)
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83
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84 #define CRB_CMD_PRODUCER_OFFSET_1 UNM_NIC_REG(0x1ac)
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85 #define CRB_CMD_CONSUMER_OFFSET_1 UNM_NIC_REG(0x1b0)
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86 #define CRB_TEMP_STATE UNM_NIC_REG(0x1b4)
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87 #define CRB_CMD_PRODUCER_OFFSET_2 UNM_NIC_REG(0x1b8)
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88 #define CRB_CMD_CONSUMER_OFFSET_2 UNM_NIC_REG(0x1bc)
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89
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90 #define CRB_CMD_PRODUCER_OFFSET_3 UNM_NIC_REG(0x1d0)
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91 #define CRB_CMD_CONSUMER_OFFSET_3 UNM_NIC_REG(0x1d4)
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92 /* sw int status/mask registers */
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93 #define CRB_SW_INT_MASK_OFFSET_0 0x1d8
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94 #define CRB_SW_INT_MASK_OFFSET_1 0x1e0
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95 #define CRB_SW_INT_MASK_OFFSET_2 0x1e4
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96 #define CRB_SW_INT_MASK_OFFSET_3 0x1e8
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97 #define CRB_SW_INT_MASK_OFFSET_4 0x450
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98 #define CRB_SW_INT_MASK_OFFSET_5 0x454
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99 #define CRB_SW_INT_MASK_OFFSET_6 0x458
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100 #define CRB_SW_INT_MASK_OFFSET_7 0x45c
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101 #define CRB_SW_INT_MASK_0 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0)
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102 #define CRB_SW_INT_MASK_1 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1)
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103 #define CRB_SW_INT_MASK_2 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2)
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104 #define CRB_SW_INT_MASK_3 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3)
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105 #define CRB_SW_INT_MASK_4 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4)
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106 #define CRB_SW_INT_MASK_5 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5)
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107 #define CRB_SW_INT_MASK_6 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6)
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108 #define CRB_SW_INT_MASK_7 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7)
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109
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110 #define CRB_NIC_DEBUG_STRUCT_BASE UNM_NIC_REG(0x288)
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111
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112 /*
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113 * capabilities register, can be used to selectively enable/disable features
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114 * for backward compability
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115 */
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116 #define CRB_NIC_CAPABILITIES_HOST UNM_NIC_REG(0x1a8)
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117 #define CRB_NIC_MSI_MODE_HOST UNM_NIC_REG(0x270)
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118 #define INTR_SCHEME_PERPORT 0x1
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119 #define MSI_MODE_MULTIFUNC 0x1
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120
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121 #define CRB_EPG_QUEUE_BUSY_COUNT UNM_NIC_REG(0x200)
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122
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123 #define CRB_V2P_0 UNM_NIC_REG(0x290)
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124 #define CRB_V2P_1 UNM_NIC_REG(0x294)
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125 #define CRB_V2P_2 UNM_NIC_REG(0x298)
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126 #define CRB_V2P_3 UNM_NIC_REG(0x29c)
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127 #define CRB_V2P(port) (CRB_V2P_0+((port)*4))
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128 #define CRB_DRIVER_VERSION UNM_NIC_REG(0x2a0)
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129
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130 #define CRB_CNT_DBG1 UNM_NIC_REG(0x2a4)
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131 #define CRB_CNT_DBG2 UNM_NIC_REG(0x2a8)
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132 #define CRB_CNT_DBG3 UNM_NIC_REG(0x2ac)
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133
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134 /*
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135 * Driver must set the version number register as follows:
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136 * (major << 16) | (minor << 8) | (subminor)
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137 */
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138
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139 /* last -> 0x2a0 */
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140
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141 /* Upper 16 bits of CRB_TEMP_STATE:temperature value. Lower 16 bits: state */
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142 #define nx_get_temp_val(x) ((x) >> 16)
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143 #define nx_get_temp_state(x) ((x) & 0xffff)
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144 #define nx_encode_temp(val, state) (((val) << 16) | (state))
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145
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146 #define lower32(x) ((__uint32_t)((x) & 0xffffffff))
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147 #define upper32(x) ((__uint32_t)(((unsigned long long)(x) >> 32) & \
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148 0xffffffff))
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149
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150 /*
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151 * Temperature control.
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152 */
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153 enum {
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154 NX_TEMP_NORMAL = 0x1, /* Normal operating range */
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155 NX_TEMP_WARN, /* Sound alert, temperature getting high */
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156 NX_TEMP_PANIC /* Fatal error, hardware has shut down. */
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157 };
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158
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159 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))
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160 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))
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161 #endif /* NIC_PHAN_REG_H */