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annotate usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h @ 7956:59ff93e4da95

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PSARC 2008/045 NetXen 10 Gigabit Ethernet Driver 6472698 NetXen 1Gb/10Gb nic driver
author lucy wang - Sun Microsystems - Beijing China <xiuyan.wang@Sun.COM>
date Tue, 28 Oct 2008 10:06:13 +0800
parents
children 5dca9cd6354a
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7956
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1 /*
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2 * CDDL HEADER START
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3 *
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4 * The contents of this file are subject to the terms of the
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5 * Common Development and Distribution License (the "License").
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6 * You may not use this file except in compliance with the License.
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7 *
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8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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9 * or http://www.opensolaris.org/os/licensing.
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10 * See the License for the specific language governing permissions
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11 * and limitations under the License.
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12 *
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13 * When distributing Covered Code, include this CDDL HEADER in each
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14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 * If applicable, add the following below this CDDL HEADER, with the
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16 * fields enclosed by brackets "[]" replaced with your own identifying
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17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 *
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19 * CDDL HEADER END
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20 */
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21 /*
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22 * Copyright 2008 NetXen, Inc. All rights reserved.
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23 * Use is subject to license terms.
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24 */
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25 #ifndef __NX_HW_REGS_H
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26 #define __NX_HW_REGS_H
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27
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28 /*
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29 * PCI related defines.
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30 */
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31
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32 /*
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33 * Interrupt related defines.
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34 */
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35 #define PCIX_TARGET_STATUS (0x10118)
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36 #define PCIX_TARGET_STATUS_F1 (0x10160)
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37 #define PCIX_TARGET_STATUS_F2 (0x10164)
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38 #define PCIX_TARGET_STATUS_F3 (0x10168)
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39 #define PCIX_TARGET_STATUS_F4 (0x10360)
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40 #define PCIX_TARGET_STATUS_F5 (0x10364)
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41 #define PCIX_TARGET_STATUS_F6 (0x10368)
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42 #define PCIX_TARGET_STATUS_F7 (0x1036c)
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43
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44 #define PCIX_TARGET_MASK (0x10128)
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45 #define PCIX_TARGET_MASK_F1 (0x10170)
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46 #define PCIX_TARGET_MASK_F2 (0x10174)
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47 #define PCIX_TARGET_MASK_F3 (0x10178)
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48 #define PCIX_TARGET_MASK_F4 (0x10370)
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49 #define PCIX_TARGET_MASK_F5 (0x10374)
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50 #define PCIX_TARGET_MASK_F6 (0x10378)
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51 #define PCIX_TARGET_MASK_F7 (0x1037c)
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52
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53 /*
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54 * Message Signaled Interrupts
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55 */
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56 #define PCIX_MSI_F0 (0x13000)
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57 #define PCIX_MSI_F1 (0x13004)
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58 #define PCIX_MSI_F2 (0x13008)
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59 #define PCIX_MSI_F3 (0x1300c)
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60 #define PCIX_MSI_F4 (0x13010)
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61 #define PCIX_MSI_F5 (0x13014)
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62 #define PCIX_MSI_F6 (0x13018)
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63 #define PCIX_MSI_F7 (0x1301c)
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64 #define PCIX_MSI_F(FUNC) (0x13000 +((FUNC) * 4))
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65
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66 /*
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67 *
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68 */
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69 #define PCIX_INT_VECTOR (0x10100)
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70 #define PCIX_INT_MASK (0x10104)
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71
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72 /*
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73 * Interrupt state machine and other bits.
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74 */
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75 #define PCIE_MISCCFG_RC (0x1206c)
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76
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77
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78 #define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))
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79 #define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
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80 #define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
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81 #define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
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82 #define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
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83 #define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
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84 #define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
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85 #define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
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86
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87 #define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))
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88 #define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
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89 #define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
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90 #define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
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91 #define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
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92 #define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
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93 #define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
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94 #define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
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95
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96 #define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))
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97 #define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK))
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98 #define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))
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99
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100 #define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
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101
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102
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103 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
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104 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
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105
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106 /*
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107 * PCI Interrupt Vector Values.
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108 */
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109 #define PCIX_INT_VECTOR_BIT_F0 0x0080
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110 #define PCIX_INT_VECTOR_BIT_F1 0x0100
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111 #define PCIX_INT_VECTOR_BIT_F2 0x0200
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112 #define PCIX_INT_VECTOR_BIT_F3 0x0400
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113 #define PCIX_INT_VECTOR_BIT_F4 0x0800
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114 #define PCIX_INT_VECTOR_BIT_F5 0x1000
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115 #define PCIX_INT_VECTOR_BIT_F6 0x2000
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116 #define PCIX_INT_VECTOR_BIT_F7 0x4000
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117
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118 struct nx_legacy_intr_set {
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119 __uint32_t int_vec_bit;
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120 __uint32_t tgt_status_reg;
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121 __uint32_t tgt_mask_reg;
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122 __uint32_t pci_int_reg;
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123 };
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124
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125 #define NX_LEGACY_INTR_CONFIG \
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126 { \
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127 { PCIX_INT_VECTOR_BIT_F0, \
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128 ISR_INT_TARGET_STATUS, \
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129 ISR_INT_TARGET_MASK, \
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130 ISR_MSI_INT_TRIGGER(0) }, \
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131 \
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132 { PCIX_INT_VECTOR_BIT_F1, \
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133 ISR_INT_TARGET_STATUS_F1, \
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134 ISR_INT_TARGET_MASK_F1, \
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135 ISR_MSI_INT_TRIGGER(1) }, \
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136 \
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137 { PCIX_INT_VECTOR_BIT_F2, \
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138 ISR_INT_TARGET_STATUS_F2, \
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139 ISR_INT_TARGET_MASK_F2, \
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140 ISR_MSI_INT_TRIGGER(2) }, \
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141 \
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142 { PCIX_INT_VECTOR_BIT_F3, \
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143 ISR_INT_TARGET_STATUS_F3, \
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144 ISR_INT_TARGET_MASK_F3, \
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145 ISR_MSI_INT_TRIGGER(3) }, \
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146 \
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147 { PCIX_INT_VECTOR_BIT_F4, \
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148 ISR_INT_TARGET_STATUS_F4, \
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149 ISR_INT_TARGET_MASK_F4, \
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150 ISR_MSI_INT_TRIGGER(4) }, \
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151 \
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152 { PCIX_INT_VECTOR_BIT_F5, \
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153 ISR_INT_TARGET_STATUS_F5, \
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154 ISR_INT_TARGET_MASK_F5, \
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155 ISR_MSI_INT_TRIGGER(5) }, \
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156 \
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157 { PCIX_INT_VECTOR_BIT_F6, \
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158 ISR_INT_TARGET_STATUS_F6, \
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159 ISR_INT_TARGET_MASK_F6, \
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160 ISR_MSI_INT_TRIGGER(6) }, \
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161 \
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162 { PCIX_INT_VECTOR_BIT_F7, \
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163 ISR_INT_TARGET_STATUS_F7, \
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164 ISR_INT_TARGET_MASK_F7, \
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165 ISR_MSI_INT_TRIGGER(7) }, \
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166 }
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167
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168 #endif /* __NX_HW_REGS_H */