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annotate usr/src/uts/common/io/atge/atge_cmn_reg.h @ 13768:ed21ea5d20cf

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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter Reviewed by: Garrett D'Amore <garrett@damore.org> Reviewed by: Milan Jurik <milan.jurik@xylab.cz> Approved by: Dan McDonald <danmcd@nexenta.com>
author Gary Mills <gary_mills@fastmail.fm>
date Fri, 10 Aug 2012 10:52:49 -0400
parents db56a54bf91c
children
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1 /*
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2 * CDDL HEADER START
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3 *
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4 * The contents of this file are subject to the terms of the
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5 * Common Development and Distribution License (the "License").
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6 * You may not use this file except in compliance with the License.
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7 *
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8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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9 * or http://www.opensolaris.org/os/licensing.
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10 * See the License for the specific language governing permissions
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11 * and limitations under the License.
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12 *
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13 * When distributing Covered Code, include this CDDL HEADER in each
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14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 * If applicable, add the following below this CDDL HEADER, with the
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16 * fields enclosed by brackets "[]" replaced with your own identifying
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17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 *
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19 * CDDL HEADER END
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20 */
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21 /*
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22 * Copyright (c) 2012 Gary Mills
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23 *
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24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
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25 * Use is subject to license terms.
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26 */
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27 /*
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28 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
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29 * All rights reserved.
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30 *
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31 * Redistribution and use in source and binary forms, with or without
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32 * modification, are permitted provided that the following conditions
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33 * are met:
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34 * 1. Redistributions of source code must retain the above copyright
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35 * notice unmodified, this list of conditions, and the following
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36 * disclaimer.
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37 * 2. Redistributions in binary form must reproduce the above copyright
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38 * notice, this list of conditions and the following disclaimer in the
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39 * documentation and/or other materials provided with the distribution.
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40 *
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41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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51 * SUCH DAMAGE.
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52 */
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53
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54 #ifndef _ATGE_CMN_REG_H
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55 #define _ATGE_CMN_REG_H
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56
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57 #ifdef __cplusplus
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58 extern "C" {
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59 #endif
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60
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61 #define ATGE_SPI_CTRL 0x200
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62 #define SPI_VPD_ENB 0x00002000
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63
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64 #define PCIE_DEVCTRL 0x0060 /* L1 */
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65
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66 /*
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67 * Station Address
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68 */
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69 #define ATGE_PAR0 0x1488
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70 #define ATGE_PAR1 0x148C
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71
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72 #define ATGE_MASTER_CFG 0x1400
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73 #define MASTER_RESET 0x00000001
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74 #define MASTER_ITIMER_ENB 0x00000004 /* L1 */
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75 #define MASTER_MANUAL_INT_ENB 0x00000008
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76 #define MASTER_INT_RDCLR 0x00000040
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77 #define MASTER_SA_TIMER_ENB 0x00000080
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78 #define MASTER_MTIMER_ENB 0x00000100
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79 #define MASTER_LED_MODE 0x00000200
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80 #define MASTER_MANUAL_INTR_ENB 0x00000200
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81 #define MASTER_IM_TX_TIMER_ENB 0x00000400
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82 #define MASTER_IM_RX_TIMER_ENB 0x00000800
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83 #define MASTER_CLK_SEL_DIS 0x00001000
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84 #define MASTER_CLK_SWH_MODE 0x00002000
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85 #define MASTER_INTR_RD_CLR 0x00004000
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86 #define MASTER_CHIP_REV_MASK 0x00FF0000
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87 #define MASTER_CHIP_ID_MASK 0xFF000000
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88 #define MASTER_CHIP_ID_MASKXXX 0x7F000000 /* XXX */
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89 #define MASTER_OTP_SEL 0x80000000
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90 #define MASTER_TEST_MODE_SHIFT 2
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91 #define MASTER_CHIP_REV_SHIFT 16
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92 #define MASTER_CHIP_ID_SHIFT 24
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93
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94 #define ATGE_RESET_TIMEOUT 100
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95
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96 #define ATGE_IDLE_STATUS 0x1410
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97 #define IDLE_STATUS_RXMAC 0x00000001
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98 #define IDLE_STATUS_TXMAC 0x00000002
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99 #define IDLE_STATUS_RXQ 0x00000004
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100 #define IDLE_STATUS_TXQ 0x00000008
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101 #define IDLE_STATUS_DMARD 0x00000010
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102 #define IDLE_STATUS_DMAWR 0x00000020
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103 #define IDLE_STATUS_SMB 0x00000040
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104 #define IDLE_STATUS_CMB 0x00000080
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105
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106 #define ATGE_SERDES_LOCK 0x1424
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107 #define SERDES_LOCK_DET 0x00000001
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108 #define SERDES_LOCK_DET_ENB 0x00000002
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109 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000
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110 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000
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111
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112 #define ATGE_MAC_CFG 0x1480
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113 #define ATGE_CFG_TX_ENB 0x00000001
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114 #define ATGE_CFG_RX_ENB 0x00000002
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115 #define ATGE_CFG_TX_FC 0x00000004
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116 #define ATGE_CFG_RX_FC 0x00000008
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117 #define ATGE_CFG_LOOP 0x00000010
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118 #define ATGE_CFG_FULL_DUPLEX 0x00000020
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119 #define ATGE_CFG_TX_CRC_ENB 0x00000040
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120 #define ATGE_CFG_TX_AUTO_PAD 0x00000080
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121 #define ATGE_CFG_TX_LENCHK 0x00000100
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122 #define ATGE_CFG_RX_JUMBO_ENB 0x00000200
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123 #define ATGE_CFG_PREAMBLE_MASK 0x00003C00
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124 #define ATGE_CFG_VLAN_TAG_STRIP 0x00004000
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125 #define ATGE_CFG_PROMISC 0x00008000
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126 #define ATGE_CFG_TX_PAUSE 0x00010000
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127 #define ATGE_CFG_SCNT 0x00020000
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128 #define ATGE_CFG_SYNC_RST_TX 0x00040000
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129 #define ATGE_CFG_SPEED_MASK 0x00300000
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130 #define ATGE_CFG_SPEED_10_100 0x00100000
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131 #define ATGE_CFG_SPEED_1000 0x00200000
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132 #define ATGE_CFG_DBG_TX_BACKOFF 0x00400000
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133 #define ATGE_CFG_TX_JUMBO_ENB 0x00800000
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134 #define ATGE_CFG_RXCSUM_ENB 0x01000000
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135 #define ATGE_CFG_ALLMULTI 0x02000000
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136 #define ATGE_CFG_BCAST 0x04000000
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137 #define ATGE_CFG_DBG 0x08000000
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138 #define ATGE_CFG_SINGLE_PAUSE_ENB 0x10000000
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139 #define ATGE_CFG_HASH_ALG_CRC32 0x20000000
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140 #define ATGE_CFG_SPEED_MODE_SW 0x40000000
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141 #define ATGE_CFG_PREAMBLE_SHIFT 10
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142 #define ATGE_CFG_PREAMBLE_DEFAULT 7
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143
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144 /*
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145 * Interrupt related registers.
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146 */
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147 #define ATGE_INTR_MASK 0x1604
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148 #define ATGE_INTR_STATUS 0x1600
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149 #define INTR_SMB 0x00000001
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150 #define INTR_MOD_TIMER 0x00000002
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151 #define INTR_MANUAL_TIMER 0x00000004
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152 #define INTR_RX_FIFO_OFLOW 0x00000008
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153 #define INTR_RD_UNDERRUN 0x00000010
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154 #define INTR_RRD_OFLOW 0x00000020
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155 #define INTR_TX_FIFO_UNDERRUN 0x00000040
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156 #define INTR_LINK_CHG 0x00000080
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157 #define INTR_HOST_RD_UNDERRUN 0x00000100
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158 #define INTR_HOST_RRD_OFLOW 0x00000200
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159 #define INTR_DMA_RD_TO_RST 0x00000400
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160 #define INTR_DMA_WR_TO_RST 0x00000800
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161 #define INTR_GPHY 0x00001000
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162 #define INTR_RX_PKT 0x00010000
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163 #define INTR_TX_PKT 0x00020000
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164 #define INTR_TX_DMA 0x00040000 /* L1 intr status */
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165 #define INTR_MAC_RX 0x00400000
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166 #define INTR_MAC_TX 0x00800000
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167 #define INTR_UNDERRUN 0x01000000
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168 #define INTR_FRAME_ERROR 0x02000000
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169 #define INTR_FRAME_OK 0x04000000
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170 #define INTR_CSUM_ERROR 0x08000000
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171 #define INTR_PHY_LINK_DOWN 0x10000000
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172 #define INTR_DIS_SM 0x20000000
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173 #define INTR_DIS_DMA 0x40000000
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174 #define INTR_DIS_INT 0x80000000
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175
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176 /* L1E intr status */
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177 #define INTR_RX_PKT1 0x00080000
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178 #define INTR_RX_PKT2 0x00100000
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179 #define INTR_RX_PKT3 0x00200000
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180
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181 /*
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182 * L1E specific errors. We keep it here since some errors are common for
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183 * both L1 and L1E chip.
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184 *
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185 */
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186 #define L1E_INTR_ERRORS \
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187 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)
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188
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189 /*
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190 * TXQ CFG registers.
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191 */
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192 #define ATGE_TXQ_CFG 0x1580
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193 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F
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194 #define TXQ_CFG_ENB 0x00000020
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195 #define TXQ_CFG_ENHANCED_MODE 0x00000040
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196 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
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197 #define TXQ_CFG_TPD_BURST_SHIFT 0
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198 #define TXQ_CFG_TPD_BURST_DEFAULT 4
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199 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
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200 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
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201
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202 /*
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203 * Common registers for DMA CFG.
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204 */
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205 #define ATGE_DMA_CFG 0x15C0
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206 #define DMA_CFG_IN_ORDER 0x00000001
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207 #define DMA_CFG_ENH_ORDER 0x00000002
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208 #define DMA_CFG_OUT_ORDER 0x00000004
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209 #define DMA_CFG_RCB_64 0x00000000
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210 #define DMA_CFG_RCB_128 0x00000008
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211 #define DMA_CFG_RD_BURST_128 0x00000000
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212 #define DMA_CFG_RD_BURST_256 0x00000010
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213 #define DMA_CFG_RD_BURST_512 0x00000020
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214 #define DMA_CFG_RD_BURST_1024 0x00000030
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215 #define DMA_CFG_RD_BURST_2048 0x00000040
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216 #define DMA_CFG_RD_BURST_4096 0x00000050
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217 #define DMA_CFG_WR_BURST_128 0x00000000
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218 #define DMA_CFG_WR_BURST_256 0x00000080
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219 #define DMA_CFG_WR_BURST_512 0x00000100
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220 #define DMA_CFG_WR_BURST_1024 0x00000180
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221 #define DMA_CFG_WR_BURST_2048 0x00000200
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222 #define DMA_CFG_WR_BURST_4096 0x00000280
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223
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224 /* L1E specific but can go into common regs */
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225 #define DMA_CFG_RXCMB_ENB 0x00200000
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226 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
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227 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
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228 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
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229 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
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230 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
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231 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
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232
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233 /*
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234 * Common PHY registers.
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235 */
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236 #define ATGE_MDIO 0x1414
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237 #define MDIO_DATA_MASK 0x0000FFFF
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238 #define MDIO_REG_ADDR_MASK 0x001F0000
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239 #define MDIO_OP_READ 0x00200000
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240 #define MDIO_OP_WRITE 0x00000000
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241 #define MDIO_SUP_PREAMBLE 0x00400000
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242 #define MDIO_OP_EXECUTE 0x00800000
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243 #define MDIO_CLK_25_4 0x00000000
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244 #define MDIO_CLK_25_6 0x02000000
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245 #define MDIO_CLK_25_8 0x03000000
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246 #define MDIO_CLK_25_10 0x04000000
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247 #define MDIO_CLK_25_14 0x05000000
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248 #define MDIO_CLK_25_20 0x06000000
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249 #define MDIO_CLK_25_28 0x07000000
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250 #define MDIO_OP_BUSY 0x08000000
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251 #define MDIO_DATA_SHIFT 0
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252 #define MDIO_REG_ADDR_SHIFT 16
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253
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254 #define MDIO_REG_ADDR(x) \
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255 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
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256
11353
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257 #define ATGE_GPHY_CTRL 0x140C /* 16-bits */
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258 #define GPHY_CTRL_RST 0x0000
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259 #define GPHY_CTRL_CLR 0x0001
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260 #define ATPHY_CDTC 0x16
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261 #define PHY_CDTC_ENB 0x0001
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262 #define PHY_CDTC_POFF 0x8
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263 #define ATPHY_CDTS 0x1C
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264
10393
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265
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266 #define ATGE_PHY_ADDR 0
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267 #define ATGE_PHY_STATUS 0x1418
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268 #define PHY_TIMEOUT 1000
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269
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270 #define ATGE_DESC_TPD_CNT 0x155C
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271 #define DESC_TPD_CNT_MASK 0x00003FF
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272 #define DESC_TPD_CNT_SHIFT 0
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273
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274 #define ATGE_DMA_BLOCK 0x1534
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275 #define DMA_BLOCK_LOAD 0x00000001
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276
13768
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277 /* From Freebsd if_alcreg.h */
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278 /* 0x0000 - 0x02FF : PCIe configuration space */
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279
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280 #define ATGE_PEX_UNC_ERR_SEV 0x10C
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281 #define PEX_UNC_ERR_SEV_TRN 0x00000001
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282 #define PEX_UNC_ERR_SEV_DLP 0x00000010
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283 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
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284 #define PEX_UNC_ERR_SEV_FCP 0x00002000
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285 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
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286 #define PEX_UNC_ERR_SEV_CA 0x00008000
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287 #define PEX_UNC_ERR_SEV_UC 0x00010000
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288 #define PEX_UNC_ERR_SEV_ROV 0x00020000
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289 #define PEX_UNC_ERR_SEV_MLFP 0x00040000
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290 #define PEX_UNC_ERR_SEV_ECRC 0x00080000
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291 #define PEX_UNC_ERR_SEV_UR 0x00100000
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292
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293 #define ATGE_PCIE_PHYMISC 0x1000
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294 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
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295
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296 #define ATGE_PCIE_PHYMISC2 0x1004
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297 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
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298 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
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299 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
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300 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
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301
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302 #define ATGE_LTSSM_ID_CFG 0x12FC
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303 #define LTSSM_ID_WRO_ENB 0x00001000
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304
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305 #define ATGE_SMB_STAT_TIMER 0x15C4
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306 #define SMB_STAT_TIMER_MASK 0x00FFFFFF
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307 #define SMB_STAT_TIMER_SHIFT 0
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308
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309 #define ATGE_CMB_TD_THRESH 0x15C8
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310 #define CMB_TD_THRESH_MASK 0x0000FFFF
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311 #define CMB_TD_THRESH_SHIFT 0
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312
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313 #define ATGE_CMB_TX_TIMER 0x15CC
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314 #define CMB_TX_TIMER_MASK 0x0000FFFF
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315 #define CMB_TX_TIMER_SHIFT 0
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316
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317 #define ATGE_MBOX_RD0_PROD_IDX 0x15E0
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318
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319 #define ATGE_MBOX_RD1_PROD_IDX 0x15E4
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320
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321 #define ATGE_MBOX_RD2_PROD_IDX 0x15E8
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322
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323 #define ATGE_MBOX_RD3_PROD_IDX 0x15EC
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324
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325 #define ATGE_MBOX_RD_PROD_MASK 0x0000FFFF
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326 #define MBOX_RD_PROD_SHIFT 0
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327
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328 #define ATGE_MBOX_TD_PROD_IDX 0x15F0
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329 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
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330 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
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331 #define MBOX_TD_PROD_HI_IDX_SHIFT 0
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332 #define MBOX_TD_PROD_LO_IDX_SHIFT 16
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333
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334 #define ATGE_MBOX_TD_CONS_IDX 0x15F4
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335 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
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336 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
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337 #define MBOX_TD_CONS_HI_IDX_SHIFT 0
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338 #define MBOX_TD_CONS_LO_IDX_SHIFT 16
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339
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340 #define ATGE_MBOX_RD01_CONS_IDX 0x15F8
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341 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
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342 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
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343 #define MBOX_RD0_CONS_IDX_SHIFT 0
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344 #define MBOX_RD1_CONS_IDX_SHIFT 16
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345
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diff changeset
346 #define ATGE_MBOX_RD23_CONS_IDX 0x15FC
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347 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
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diff changeset
348 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
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349 #define MBOX_RD2_CONS_IDX_SHIFT 0
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diff changeset
350 #define MBOX_RD3_CONS_IDX_SHIFT 16
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diff changeset
351
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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diff changeset
352 #define ATGE_INTR_RETRIG_TIMER 0x1608
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
353 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
354 #define INTR_RETRIG_TIMER_SHIFT 0
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
355
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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diff changeset
356 #define ATGE_HDS_CFG 0x160C
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
357 #define HDS_CFG_ENB 0x00000001
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
358 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
359 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
360 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
361 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
362
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
363 /* AR813x/AR815x registers for MAC statistics */
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
364 #define ATGE_RX_MIB_BASE 0x1700
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
365
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
366 #define ATGE_TX_MIB_BASE 0x1760
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
367
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
368 #define ATGE_CLK_GATING_CFG 0x1814
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
369 #define CLK_GATING_DMAW_ENB 0x0001
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
370 #define CLK_GATING_DMAR_ENB 0x0002
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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parents: 11353
diff changeset
371 #define CLK_GATING_TXQ_ENB 0x0004
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Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
372 #define CLK_GATING_RXQ_ENB 0x0008
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
373 #define CLK_GATING_TXMAC_ENB 0x0010
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
374 #define CLK_GATING_RXMAC_ENB 0x0020
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
375
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
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diff changeset
376 #define ATGE_DEBUG_DATA0 0x1900
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
377
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
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diff changeset
378 #define ATGE_DEBUG_DATA1 0x1904
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
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diff changeset
379
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
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diff changeset
380 #define ATGE_MII_DBG_ADDR 0x1D
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parents: 11353
diff changeset
381 #define ATGE_MII_DBG_DATA 0x1E
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Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
382 /* End Freebsd if_alcreg.h */
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
383
10393
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
384 #define ATGE_MBOX 0x15F0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
385 #define MBOX_RD_PROD_IDX_MASK 0x000007FF
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
386 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
387 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
388 #define MBOX_RD_PROD_IDX_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
389 #define MBOX_RRD_CONS_IDX_SHIFT 11
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
390 #define MBOX_TD_PROD_IDX_SHIFT 22
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
391
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
392
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
393 #define ATGE_IPG_IFG_CFG 0x1484
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
394 #define IPG_IFG_IPGT_MASK 0x0000007F
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
395 #define IPG_IFG_MIFG_MASK 0x0000FF00
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
396 #define IPG_IFG_IPG1_MASK 0x007F0000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
397 #define IPG_IFG_IPG2_MASK 0x7F000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
398 #define IPG_IFG_IPGT_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
399 #define IPG_IFG_IPGT_DEFAULT 0x60
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
400 #define IPG_IFG_MIFG_SHIFT 8
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
401 #define IPG_IFG_MIFG_DEFAULT 0x50
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
402 #define IPG_IFG_IPG1_SHIFT 16
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
403 #define IPG_IFG_IPG1_DEFAULT 0x40
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
404 #define IPG_IFG_IPG2_SHIFT 24
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
405 #define IPG_IFG_IPG2_DEFAULT 0x60
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
406
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
407 /* half-duplex parameter configuration. */
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
408 #define ATGE_HDPX_CFG 0x1498
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
409 #define HDPX_CFG_LCOL_MASK 0x000003FF
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
410 #define HDPX_CFG_RETRY_MASK 0x0000F000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
411 #define HDPX_CFG_EXC_DEF_EN 0x00010000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
412 #define HDPX_CFG_NO_BACK_C 0x00020000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
413 #define HDPX_CFG_NO_BACK_P 0x00040000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
414 #define HDPX_CFG_ABEBE 0x00080000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
415 #define HDPX_CFG_ABEBT_MASK 0x00F00000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
416 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
417 #define HDPX_CFG_LCOL_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
418 #define HDPX_CFG_LCOL_DEFAULT 0x37
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
419 #define HDPX_CFG_RETRY_SHIFT 12
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
420 #define HDPX_CFG_RETRY_DEFAULT 0x0F
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
421 #define HDPX_CFG_ABEBT_SHIFT 20
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
422 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
423 #define HDPX_CFG_JAMIPG_SHIFT 24
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
424 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
425
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
426 #define ATGE_FRAME_SIZE 0x149C
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
427
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
428 #define ATGE_WOL_CFG 0x14A0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
429 #define WOL_CFG_PATTERN 0x00000001
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
430 #define WOL_CFG_PATTERN_ENB 0x00000002
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
431 #define WOL_CFG_MAGIC 0x00000004
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
432 #define WOL_CFG_MAGIC_ENB 0x00000008
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
433 #define WOL_CFG_LINK_CHG 0x00000010
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
434 #define WOL_CFG_LINK_CHG_ENB 0x00000020
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
435 #define WOL_CFG_PATTERN_DET 0x00000100
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
436 #define WOL_CFG_MAGIC_DET 0x00000200
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
437 #define WOL_CFG_LINK_CHG_DET 0x00000400
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
438 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
439 #define WOL_CFG_PATTERN0 0x00010000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
440 #define WOL_CFG_PATTERN1 0x00020000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
441 #define WOL_CFG_PATTERN2 0x00040000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
442 #define WOL_CFG_PATTERN3 0x00080000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
443 #define WOL_CFG_PATTERN4 0x00100000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
444 #define WOL_CFG_PATTERN5 0x00200000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
445 #define WOL_CFG_PATTERN6 0x00400000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
446
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
447 /* WOL pattern length. */
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
448 #define ATGE_PATTERN_CFG0 0x14A4
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
449 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
450 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
451 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
452 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
453
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
454 #define ATGE_PATTERN_CFG1 0x14A8
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
455 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
456 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
457 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
458
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
459 #define ATGE_TICK_USECS 2
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
460 #define ATGE_USECS(x) ((x) / ATGE_TICK_USECS)
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
461
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
462 #define ATGE_INTR_CLR_TIMER 0x140E /* 16-bits */
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
463 #define ATGE_IM_TIMER 0x1408
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
464 #define ATGE_IM_TIMER2 0x140A
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
465 #define ATGE_IM_TIMER_MIN 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
466 #define ATGE_IM_TIMER_MAX 130000 /* 130 ms */
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
467 #define ATGE_IM_TIMER_DEFAULT 100
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
468 #define ATGE_IM_RX_TIMER_DEFAULT 1
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
469 #define ATGE_IM_TX_TIMER_DEFAULT 1
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
470 #define IM_TIMER_TX_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
471 #define IM_TIMER_RX_SHIFT 16
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
472
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
473 #define ATGE_DESC_ADDR_HI 0x1540
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
474 #define ATGE_DESC_RD_ADDR_LO 0x1544
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
475 #define ATGE_DESC_RRD_ADDR_LO 0x1548
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
476 #define ATGE_DESC_TPD_ADDR_LO 0x154C
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
477 #define ATGE_DESC_CMB_ADDR_LO 0x1550
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
478 #define ATGE_DESC_SMB_ADDR_LO 0x1554
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
479 #define ATGE_DESC_RRD_RD_CNT 0x1558
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
480
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
481 #define ATGE_RXQ_JUMBO_CFG 0x15A4
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
482 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
483 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
484 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
485 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
486 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
487 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
488 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
489
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
490 #define ATGE_RXQ_FIFO_PAUSE_THRESH 0x15A8
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
491 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
492 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
493 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
494 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
495
13768
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
496 /*
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
497 * RXQ CFG register.
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
498 */
10393
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
499 #define ATGE_RXQ_CFG 0x15A0
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
500 #define RXQ_CFG_ALIGN_32 0x00000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
501 #define RXQ_CFG_ALIGN_64 0x00000001
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
502 #define RXQ_CFG_ALIGN_128 0x00000002
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
503 #define RXQ_CFG_ALIGN_256 0x00000003
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
504 #define RXQ_CFG_QUEUE1_ENB 0x00000010
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
505 #define RXQ_CFG_QUEUE2_ENB 0x00000020
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
506 #define RXQ_CFG_QUEUE3_ENB 0x00000040
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
507 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
508 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
509 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
510 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
511 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
512 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
513 #define RXQ_CFG_RSS_MODE_DIS 0x00000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
514 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
515 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
516 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
517 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
518 #define RXQ_CFG_RSS_HASH_ENB 0x20000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
519 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
520 #define RXQ_CFG_ENB 0x80000000
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
521 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
522
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
523 /* 64bit multicast hash register. */
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
524 #define ATGE_MAR0 0x1490
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
525 #define ATGE_MAR1 0x1494
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
526
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
527 #define ATPHY_DBG_ADDR 0x1D
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
528 #define ATPHY_DBG_DATA 0x1E
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
diff changeset
529
13768
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
530 /* From Freebsd if_alcreg.h */
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
531 #define MII_ANA_CFG0 0x00
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
532 #define ANA_RESTART_CAL 0x0001
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
533 #define ANA_MANUL_SWICH_ON_MASK 0x001E
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
534 #define ANA_MAN_ENABLE 0x0020
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
535 #define ANA_SEL_HSP 0x0040
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
536 #define ANA_EN_HB 0x0080
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
537 #define ANA_EN_HBIAS 0x0100
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
538 #define ANA_OEN_125M 0x0200
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
539 #define ANA_EN_LCKDT 0x0400
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
540 #define ANA_LCKDT_PHY 0x0800
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
541 #define ANA_AFE_MODE 0x1000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
542 #define ANA_VCO_SLOW 0x2000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
543 #define ANA_VCO_FAST 0x4000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
544 #define ANA_SEL_CLK125M_DSP 0x8000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
545 #define ANA_MANUL_SWICH_ON_SHIFT 1
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
546
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
547 #define MII_ANA_CFG4 0x04
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
548 #define ANA_IECHO_ADJ_MASK 0x0F
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
549 #define ANA_IECHO_ADJ_3_MASK 0x000F
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
550 #define ANA_IECHO_ADJ_2_MASK 0x00F0
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
551 #define ANA_IECHO_ADJ_1_MASK 0x0F00
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
552 #define ANA_IECHO_ADJ_0_MASK 0xF000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
553 #define ANA_IECHO_ADJ_3_SHIFT 0
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
554 #define ANA_IECHO_ADJ_2_SHIFT 4
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
555 #define ANA_IECHO_ADJ_1_SHIFT 8
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
556 #define ANA_IECHO_ADJ_0_SHIFT 12
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
557
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
558 #define MII_ANA_CFG5 0x05
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
559 #define ANA_SERDES_CDR_BW_MASK 0x0003
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
560 #define ANA_MS_PAD_DBG 0x0004
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
561 #define ANA_SPEEDUP_DBG 0x0008
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
562 #define ANA_SERDES_TH_LOS_MASK 0x0030
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
563 #define ANA_SERDES_EN_DEEM 0x0040
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
564 #define ANA_SERDES_TXELECIDLE 0x0080
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
565 #define ANA_SERDES_BEACON 0x0100
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
566 #define ANA_SERDES_HALFTXDR 0x0200
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
567 #define ANA_SERDES_SEL_HSP 0x0400
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
568 #define ANA_SERDES_EN_PLL 0x0800
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
569 #define ANA_SERDES_EN 0x1000
ed21ea5d20cf 212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
Gary Mills <gary_mills@fastmail.fm>
parents: 11353
diff changeset
570 #define ANA_SERDES_EN_LCKDT 0x2000
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571 #define ANA_SERDES_CDR_BW_SHIFT 0
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572 #define ANA_SERDES_TH_LOS_SHIFT 4
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573
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574 #define MII_ANA_CFG11 0x0B
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575 #define ANA_PS_HIB_EN 0x8000
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576
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577 #define MII_ANA_CFG18 0x12
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578 #define ANA_TEST_MODE_10BT_01MASK 0x0003
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579 #define ANA_LOOP_SEL_10BT 0x0004
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580 #define ANA_RGMII_MODE_SW 0x0008
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581 #define ANA_EN_LONGECABLE 0x0010
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582 #define ANA_TEST_MODE_10BT_2 0x0020
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583 #define ANA_EN_10BT_IDLE 0x0400
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584 #define ANA_EN_MASK_TB 0x0800
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585 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
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586 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
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587 #define ANA_TEST_MODE_10BT_01SHIFT 0
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588 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12
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589 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14
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590
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591 #define MII_ANA_CFG41 0x29
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592 #define ANA_TOP_PS_EN 0x8000
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593
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594 #define MII_ANA_CFG54 0x36
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595 #define ANA_LONG_CABLE_TH_100_MASK 0x003F
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596 #define ANA_DESERVED 0x0040
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597 #define ANA_EN_LIT_CH 0x0080
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598 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
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599 #define ANA_BP_BAD_LINK_ACCUM 0x4000
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600 #define ANA_BP_SMALL_BW 0x8000
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601 #define ANA_LONG_CABLE_TH_100_SHIFT 0
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602 #define ANA_SHORT_CABLE_TH_100_SHIFT 8
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603 /* End Freebsd if_alcreg.h */
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604
11353
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605 #define ATGE_TD_EOP 0x00000001
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606 #define ATGE_TD_BUFLEN_MASK 0x00003FFF
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607 #define ATGE_TD_BUFLEN_SHIFT 0
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608 #define ATGE_TX_BYTES(x) \
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609 (((x) << ATGE_TD_BUFLEN_SHIFT) & ATGE_TD_BUFLEN_MASK)
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diff changeset
610
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611 #define ATGE_ISR_ACK_GPHY 19
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612
10393
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diff changeset
613 #ifdef __cplusplus
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614 }
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615 #endif
f08ea7a5507b PSARC/2009/405 Atheros/Attansic Ethernet Gigbit Ethernet Driver
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616
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617 #endif /* _ATGE_CMN_REG_H */