Mercurial > illumos > illumos-gate
annotate usr/src/uts/i86pc/os/cpuid.c @ 4606:ffcd05844ec5
6495401 cpuid based cache hierarchy awareness
| author | esaxe |
|---|---|
| date | Fri, 06 Jul 2007 14:54:20 -0700 |
| parents | b6104e41b06c |
| children | f90cf8fd4710 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * CDDL HEADER START | |
| 3 * | |
| 4 * The contents of this file are subject to the terms of the | |
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5 * Common Development and Distribution License (the "License"). |
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6 * You may not use this file except in compliance with the License. |
| 0 | 7 * |
| 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
| 9 * or http://www.opensolaris.org/os/licensing. | |
| 10 * See the License for the specific language governing permissions | |
| 11 * and limitations under the License. | |
| 12 * | |
| 13 * When distributing Covered Code, include this CDDL HEADER in each | |
| 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
| 15 * If applicable, add the following below this CDDL HEADER, with the | |
| 16 * fields enclosed by brackets "[]" replaced with your own identifying | |
| 17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
| 18 * | |
| 19 * CDDL HEADER END | |
| 20 */ | |
| 21 /* | |
| 3434 | 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 0 | 23 * Use is subject to license terms. |
| 24 */ | |
| 25 | |
| 26 #pragma ident "%Z%%M% %I% %E% SMI" | |
| 27 | |
| 28 /* | |
| 29 * Various routines to handle identification | |
| 30 * and classification of x86 processors. | |
| 31 */ | |
| 32 | |
| 33 #include <sys/types.h> | |
| 34 #include <sys/archsystm.h> | |
| 35 #include <sys/x86_archext.h> | |
| 36 #include <sys/kmem.h> | |
| 37 #include <sys/systm.h> | |
| 38 #include <sys/cmn_err.h> | |
| 39 #include <sys/sunddi.h> | |
| 40 #include <sys/sunndi.h> | |
| 41 #include <sys/cpuvar.h> | |
| 42 #include <sys/processor.h> | |
| 3434 | 43 #include <sys/pg.h> |
| 0 | 44 #include <sys/fp.h> |
| 45 #include <sys/controlregs.h> | |
| 46 #include <sys/auxv_386.h> | |
| 47 #include <sys/bitmap.h> | |
| 48 #include <sys/memnode.h> | |
| 49 | |
| 50 /* | |
| 51 * Pass 0 of cpuid feature analysis happens in locore. It contains special code | |
| 52 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with | |
| 53 * them accordingly. For most modern processors, feature detection occurs here | |
| 54 * in pass 1. | |
| 55 * | |
| 56 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() | |
| 57 * for the boot CPU and does the basic analysis that the early kernel needs. | |
| 58 * x86_feature is set based on the return value of cpuid_pass1() of the boot | |
| 59 * CPU. | |
| 60 * | |
| 61 * Pass 1 includes: | |
| 62 * | |
| 63 * o Determining vendor/model/family/stepping and setting x86_type and | |
| 64 * x86_vendor accordingly. | |
| 65 * o Processing the feature flags returned by the cpuid instruction while | |
| 66 * applying any workarounds or tricks for the specific processor. | |
| 67 * o Mapping the feature flags into Solaris feature bits (X86_*). | |
| 68 * o Processing extended feature flags if supported by the processor, | |
| 69 * again while applying specific processor knowledge. | |
| 70 * o Determining the CMT characteristics of the system. | |
| 71 * | |
| 72 * Pass 1 is done on non-boot CPUs during their initialization and the results | |
| 73 * are used only as a meager attempt at ensuring that all processors within the | |
| 74 * system support the same features. | |
| 75 * | |
| 76 * Pass 2 of cpuid feature analysis happens just at the beginning | |
| 77 * of startup(). It just copies in and corrects the remainder | |
| 78 * of the cpuid data we depend on: standard cpuid functions that we didn't | |
| 79 * need for pass1 feature analysis, and extended cpuid functions beyond the | |
| 80 * simple feature processing done in pass1. | |
| 81 * | |
| 82 * Pass 3 of cpuid analysis is invoked after basic kernel services; in | |
| 83 * particular kernel memory allocation has been made available. It creates a | |
| 84 * readable brand string based on the data collected in the first two passes. | |
| 85 * | |
| 86 * Pass 4 of cpuid analysis is invoked after post_startup() when all | |
| 87 * the support infrastructure for various hardware features has been | |
| 88 * initialized. It determines which processor features will be reported | |
| 89 * to userland via the aux vector. | |
| 90 * | |
| 91 * All passes are executed on all CPUs, but only the boot CPU determines what | |
| 92 * features the kernel will use. | |
| 93 * | |
| 94 * Much of the worst junk in this file is for the support of processors | |
| 95 * that didn't really implement the cpuid instruction properly. | |
| 96 * | |
| 97 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, | |
| 98 * the pass numbers. Accordingly, changes to the pass code may require changes | |
| 99 * to the accessor code. | |
| 100 */ | |
| 101 | |
| 102 uint_t x86_feature = 0; | |
| 103 uint_t x86_vendor = X86_VENDOR_IntelClone; | |
| 104 uint_t x86_type = X86_TYPE_OTHER; | |
| 105 | |
| 106 uint_t pentiumpro_bug4046376; | |
| 107 uint_t pentiumpro_bug4064495; | |
| 108 | |
| 109 uint_t enable486; | |
| 110 | |
| 111 /* | |
| 112 * This set of strings are for processors rumored to support the cpuid | |
| 113 * instruction, and is used by locore.s to figure out how to set x86_vendor | |
| 114 */ | |
| 115 const char CyrixInstead[] = "CyrixInstead"; | |
| 116 | |
| 117 /* | |
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118 * monitor/mwait info. |
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119 */ |
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120 struct mwait_info { |
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121 size_t mon_min; /* min size to avoid missed wakeups */ |
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122 size_t mon_max; /* size to avoid false wakeups */ |
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123 uint32_t support; /* processor support of monitor/mwait */ |
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124 }; |
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125 |
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126 /* |
| 0 | 127 * These constants determine how many of the elements of the |
| 128 * cpuid we cache in the cpuid_info data structure; the | |
| 129 * remaining elements are accessible via the cpuid instruction. | |
| 130 */ | |
| 131 | |
| 132 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ | |
| 133 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ | |
| 134 | |
| 135 struct cpuid_info { | |
| 136 uint_t cpi_pass; /* last pass completed */ | |
| 137 /* | |
| 138 * standard function information | |
| 139 */ | |
| 140 uint_t cpi_maxeax; /* fn 0: %eax */ | |
| 141 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ | |
| 142 uint_t cpi_vendor; /* enum of cpi_vendorstr */ | |
| 143 | |
| 144 uint_t cpi_family; /* fn 1: extended family */ | |
| 145 uint_t cpi_model; /* fn 1: extended model */ | |
| 146 uint_t cpi_step; /* fn 1: stepping */ | |
| 147 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ | |
| 148 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ | |
| 149 int cpi_clogid; /* fn 1: %ebx: thread # */ | |
| 1228 | 150 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ |
| 0 | 151 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ |
| 152 uint_t cpi_ncache; /* fn 2: number of elements */ | |
| 4606 | 153 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ |
| 154 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ | |
| 155 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ | |
| 156 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ | |
| 1228 | 157 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ |
| 0 | 158 /* |
| 159 * extended function information | |
| 160 */ | |
| 161 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ | |
| 162 char cpi_brandstr[49]; /* fn 0x8000000[234] */ | |
| 163 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ | |
| 164 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ | |
| 1228 | 165 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ |
| 166 id_t cpi_coreid; | |
| 167 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ | |
| 168 /* Intel: fn 4: %eax[31-26] */ | |
| 0 | 169 /* |
| 170 * supported feature information | |
| 171 */ | |
| 3446 | 172 uint32_t cpi_support[5]; |
| 0 | 173 #define STD_EDX_FEATURES 0 |
| 174 #define AMD_EDX_FEATURES 1 | |
| 175 #define TM_EDX_FEATURES 2 | |
| 176 #define STD_ECX_FEATURES 3 | |
| 3446 | 177 #define AMD_ECX_FEATURES 4 |
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178 /* |
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179 * Synthesized information, where known. |
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180 */ |
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181 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ |
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182 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ |
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183 uint32_t cpi_socket; /* Chip package/socket type */ |
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184 |
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185 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ |
| 0 | 186 }; |
| 187 | |
| 188 | |
| 189 static struct cpuid_info cpuid_info0; | |
| 190 | |
| 191 /* | |
| 192 * These bit fields are defined by the Intel Application Note AP-485 | |
| 193 * "Intel Processor Identification and the CPUID Instruction" | |
| 194 */ | |
| 195 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) | |
| 196 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) | |
| 197 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) | |
| 198 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) | |
| 199 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) | |
| 200 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) | |
| 201 | |
| 202 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) | |
| 203 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) | |
| 204 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) | |
| 205 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) | |
| 206 | |
| 207 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) | |
| 208 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) | |
| 209 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) | |
| 210 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) | |
| 211 | |
| 212 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ | |
| 213 #define CPI_XMAXEAX_MAX 0x80000100 | |
| 4606 | 214 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ |
| 215 | |
| 216 /* | |
| 217 * Function 4 (Deterministic Cache Parameters) macros | |
| 218 * Defined by Intel Application Note AP-485 | |
| 219 */ | |
| 220 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) | |
| 221 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) | |
| 222 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) | |
| 223 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) | |
| 224 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) | |
| 225 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) | |
| 226 | |
| 227 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) | |
| 228 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) | |
| 229 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) | |
| 230 | |
| 231 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) | |
| 232 | |
| 233 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) | |
| 234 | |
| 0 | 235 |
| 236 /* | |
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237 * A couple of shorthand macros to identify "later" P6-family chips |
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238 * like the Pentium M and Core. First, the "older" P6-based stuff |
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239 * (loosely defined as "pre-Pentium-4"): |
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240 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon |
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241 */ |
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242 |
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243 #define IS_LEGACY_P6(cpi) ( \ |
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244 cpi->cpi_family == 6 && \ |
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245 (cpi->cpi_model == 1 || \ |
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246 cpi->cpi_model == 3 || \ |
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247 cpi->cpi_model == 5 || \ |
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248 cpi->cpi_model == 6 || \ |
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249 cpi->cpi_model == 7 || \ |
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250 cpi->cpi_model == 8 || \ |
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251 cpi->cpi_model == 0xA || \ |
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252 cpi->cpi_model == 0xB) \ |
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253 ) |
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254 |
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255 /* A "new F6" is everything with family 6 that's not the above */ |
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256 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) |
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257 |
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258 /* |
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259 * AMD family 0xf socket types. |
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260 * First index is 0 for revs B thru E, 1 for F and G. |
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261 * Second index by (model & 0x3) |
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262 */ |
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263 static uint32_t amd_skts[2][4] = { |
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264 { |
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265 X86_SOCKET_754, /* 0b00 */ |
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266 X86_SOCKET_940, /* 0b01 */ |
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267 X86_SOCKET_754, /* 0b10 */ |
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268 X86_SOCKET_939 /* 0b11 */ |
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269 }, |
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270 { |
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271 X86_SOCKET_S1g1, /* 0b00 */ |
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272 X86_SOCKET_F1207, /* 0b01 */ |
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273 X86_SOCKET_UNKNOWN, /* 0b10 */ |
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274 X86_SOCKET_AM2 /* 0b11 */ |
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275 } |
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276 }; |
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277 |
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278 /* |
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279 * Table for mapping AMD Family 0xf model/stepping combination to |
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280 * chip "revision" and socket type. Only rm_family 0xf is used at the |
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281 * moment, but AMD family 0x10 will extend the exsiting revision names |
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282 * so will likely also use this table. |
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283 * |
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284 * The first member of this array that matches a given family, extended model |
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285 * plus model range, and stepping range will be considered a match. |
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286 */ |
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287 static const struct amd_rev_mapent { |
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288 uint_t rm_family; |
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289 uint_t rm_modello; |
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290 uint_t rm_modelhi; |
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291 uint_t rm_steplo; |
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292 uint_t rm_stephi; |
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293 uint32_t rm_chiprev; |
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294 const char *rm_chiprevstr; |
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295 int rm_sktidx; |
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296 } amd_revmap[] = { |
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297 /* |
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298 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. |
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299 */ |
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300 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, |
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301 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, |
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302 /* |
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303 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 |
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304 */ |
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305 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 }, |
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306 /* |
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307 * Rev CG is the rest of extended model 0x0 - i.e., everything |
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308 * but the rev B and C0 combinations covered above. |
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309 */ |
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310 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 }, |
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311 /* |
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312 * Rev D has extended model 0x1. |
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313 */ |
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314 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 }, |
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315 /* |
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316 * Rev E has extended model 0x2. |
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317 * Extended model 0x3 is unused but available to grow into. |
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318 */ |
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319 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 }, |
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320 /* |
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321 * Rev F has extended models 0x4 and 0x5. |
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322 */ |
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323 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 }, |
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324 /* |
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325 * Rev G has extended model 0x6. |
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326 */ |
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327 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 }, |
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328 }; |
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329 |
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330 /* |
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331 * Info for monitor/mwait idle loop. |
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332 * |
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333 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's |
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334 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November |
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335 * 2006. |
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336 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual |
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337 * Documentation Updates" #33633, Rev 2.05, December 2006. |
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338 */ |
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339 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ |
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340 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ |
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341 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ |
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342 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) |
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343 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) |
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344 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) |
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345 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) |
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346 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) |
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347 /* |
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348 * Number of sub-cstates for a given c-state. |
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349 */ |
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350 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ |
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351 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) |
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352 |
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353 static void |
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354 synth_amd_info(struct cpuid_info *cpi) |
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355 { |
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356 const struct amd_rev_mapent *rmp; |
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357 uint_t family, model, step; |
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358 int i; |
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359 |
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360 /* |
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361 * Currently only AMD family 0xf uses these fields. |
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362 */ |
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363 if (cpi->cpi_family != 0xf) |
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364 return; |
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365 |
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366 family = cpi->cpi_family; |
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367 model = cpi->cpi_model; |
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368 step = cpi->cpi_step; |
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369 |
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370 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); |
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371 i++, rmp++) { |
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372 if (family == rmp->rm_family && |
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373 model >= rmp->rm_modello && model <= rmp->rm_modelhi && |
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374 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { |
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375 cpi->cpi_chiprev = rmp->rm_chiprev; |
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376 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; |
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377 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; |
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378 return; |
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379 } |
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380 } |
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381 } |
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382 |
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383 static void |
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384 synth_info(struct cpuid_info *cpi) |
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385 { |
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386 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; |
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387 cpi->cpi_chiprevstr = "Unknown"; |
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388 cpi->cpi_socket = X86_SOCKET_UNKNOWN; |
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389 |
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390 switch (cpi->cpi_vendor) { |
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391 case X86_VENDOR_AMD: |
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392 synth_amd_info(cpi); |
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393 break; |
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394 |
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395 default: |
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396 break; |
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397 |
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398 } |
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399 } |
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400 |
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401 /* |
| 3446 | 402 * Apply up various platform-dependent restrictions where the |
| 403 * underlying platform restrictions mean the CPU can be marked | |
| 404 * as less capable than its cpuid instruction would imply. | |
| 405 */ | |
| 406 | |
| 407 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ | |
| 408 | |
| 409 /* | |
| 0 | 410 * Some undocumented ways of patching the results of the cpuid |
| 411 * instruction to permit running Solaris 10 on future cpus that | |
| 412 * we don't currently support. Could be set to non-zero values | |
| 413 * via settings in eeprom. | |
| 414 */ | |
| 415 | |
| 416 uint32_t cpuid_feature_ecx_include; | |
| 417 uint32_t cpuid_feature_ecx_exclude; | |
| 418 uint32_t cpuid_feature_edx_include; | |
| 419 uint32_t cpuid_feature_edx_exclude; | |
| 420 | |
| 3446 | 421 void |
| 422 cpuid_alloc_space(cpu_t *cpu) | |
| 423 { | |
| 424 /* | |
| 425 * By convention, cpu0 is the boot cpu, which is set up | |
| 426 * before memory allocation is available. All other cpus get | |
| 427 * their cpuid_info struct allocated here. | |
| 428 */ | |
| 429 ASSERT(cpu->cpu_id != 0); | |
| 430 cpu->cpu_m.mcpu_cpi = | |
| 431 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); | |
| 432 } | |
| 433 | |
| 434 void | |
| 435 cpuid_free_space(cpu_t *cpu) | |
| 436 { | |
| 4606 | 437 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 438 int i; | |
| 439 | |
| 3446 | 440 ASSERT(cpu->cpu_id != 0); |
| 4606 | 441 |
| 442 /* | |
| 443 * Free up any function 4 related dynamic storage | |
| 444 */ | |
| 445 for (i = 1; i < cpi->cpi_std_4_size; i++) | |
| 446 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); | |
| 447 if (cpi->cpi_std_4_size > 0) | |
| 448 kmem_free(cpi->cpi_std_4, | |
| 449 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); | |
| 450 | |
| 3446 | 451 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); |
| 452 } | |
| 453 | |
| 0 | 454 uint_t |
| 455 cpuid_pass1(cpu_t *cpu) | |
| 456 { | |
| 457 uint32_t mask_ecx, mask_edx; | |
| 458 uint_t feature = X86_CPUID; | |
| 459 struct cpuid_info *cpi; | |
| 1228 | 460 struct cpuid_regs *cp; |
| 0 | 461 int xcpuid; |
| 462 | |
| 3446 | 463 |
| 0 | 464 /* |
| 3446 | 465 * Space statically allocated for cpu0, ensure pointer is set |
| 0 | 466 */ |
| 467 if (cpu->cpu_id == 0) | |
| 3446 | 468 cpu->cpu_m.mcpu_cpi = &cpuid_info0; |
| 469 cpi = cpu->cpu_m.mcpu_cpi; | |
| 470 ASSERT(cpi != NULL); | |
| 0 | 471 cp = &cpi->cpi_std[0]; |
| 1228 | 472 cp->cp_eax = 0; |
| 473 cpi->cpi_maxeax = __cpuid_insn(cp); | |
| 0 | 474 { |
| 475 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; | |
| 476 *iptr++ = cp->cp_ebx; | |
| 477 *iptr++ = cp->cp_edx; | |
| 478 *iptr++ = cp->cp_ecx; | |
| 479 *(char *)&cpi->cpi_vendorstr[12] = '\0'; | |
| 480 } | |
| 481 | |
| 482 /* | |
| 483 * Map the vendor string to a type code | |
| 484 */ | |
| 485 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) | |
| 486 cpi->cpi_vendor = X86_VENDOR_Intel; | |
| 487 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) | |
| 488 cpi->cpi_vendor = X86_VENDOR_AMD; | |
| 489 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) | |
| 490 cpi->cpi_vendor = X86_VENDOR_TM; | |
| 491 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) | |
| 492 /* | |
| 493 * CyrixInstead is a variable used by the Cyrix detection code | |
| 494 * in locore. | |
| 495 */ | |
| 496 cpi->cpi_vendor = X86_VENDOR_Cyrix; | |
| 497 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) | |
| 498 cpi->cpi_vendor = X86_VENDOR_UMC; | |
| 499 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) | |
| 500 cpi->cpi_vendor = X86_VENDOR_NexGen; | |
| 501 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) | |
| 502 cpi->cpi_vendor = X86_VENDOR_Centaur; | |
| 503 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) | |
| 504 cpi->cpi_vendor = X86_VENDOR_Rise; | |
| 505 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) | |
| 506 cpi->cpi_vendor = X86_VENDOR_SiS; | |
| 507 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) | |
| 508 cpi->cpi_vendor = X86_VENDOR_NSC; | |
| 509 else | |
| 510 cpi->cpi_vendor = X86_VENDOR_IntelClone; | |
| 511 | |
| 512 x86_vendor = cpi->cpi_vendor; /* for compatibility */ | |
| 513 | |
| 514 /* | |
| 515 * Limit the range in case of weird hardware | |
| 516 */ | |
| 517 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) | |
| 518 cpi->cpi_maxeax = CPI_MAXEAX_MAX; | |
| 519 if (cpi->cpi_maxeax < 1) | |
| 520 goto pass1_done; | |
| 521 | |
| 522 cp = &cpi->cpi_std[1]; | |
| 1228 | 523 cp->cp_eax = 1; |
| 524 (void) __cpuid_insn(cp); | |
| 0 | 525 |
| 526 /* | |
| 527 * Extract identifying constants for easy access. | |
| 528 */ | |
| 529 cpi->cpi_model = CPI_MODEL(cpi); | |
| 530 cpi->cpi_family = CPI_FAMILY(cpi); | |
| 531 | |
|
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532 if (cpi->cpi_family == 0xf) |
| 0 | 533 cpi->cpi_family += CPI_FAMILY_XTD(cpi); |
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534 |
|
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535 /* |
|
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536 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. |
|
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537 * Intel, and presumably everyone else, uses model == 0xf, as |
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538 * one would expect (max value means possible overflow). Sigh. |
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539 */ |
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540 |
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541 switch (cpi->cpi_vendor) { |
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542 case X86_VENDOR_AMD: |
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543 if (CPI_FAMILY(cpi) == 0xf) |
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544 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
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545 break; |
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546 default: |
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547 if (cpi->cpi_model == 0xf) |
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548 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
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549 break; |
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550 } |
| 0 | 551 |
| 552 cpi->cpi_step = CPI_STEP(cpi); | |
| 553 cpi->cpi_brandid = CPI_BRANDID(cpi); | |
| 554 | |
| 555 /* | |
| 556 * *default* assumptions: | |
| 557 * - believe %edx feature word | |
| 558 * - ignore %ecx feature word | |
| 559 * - 32-bit virtual and physical addressing | |
| 560 */ | |
| 561 mask_edx = 0xffffffff; | |
| 562 mask_ecx = 0; | |
| 563 | |
| 564 cpi->cpi_pabits = cpi->cpi_vabits = 32; | |
| 565 | |
| 566 switch (cpi->cpi_vendor) { | |
| 567 case X86_VENDOR_Intel: | |
| 568 if (cpi->cpi_family == 5) | |
| 569 x86_type = X86_TYPE_P5; | |
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570 else if (IS_LEGACY_P6(cpi)) { |
| 0 | 571 x86_type = X86_TYPE_P6; |
| 572 pentiumpro_bug4046376 = 1; | |
| 573 pentiumpro_bug4064495 = 1; | |
| 574 /* | |
| 575 * Clear the SEP bit when it was set erroneously | |
| 576 */ | |
| 577 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) | |
| 578 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; | |
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579 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { |
| 0 | 580 x86_type = X86_TYPE_P4; |
| 581 /* | |
| 582 * We don't currently depend on any of the %ecx | |
| 583 * features until Prescott, so we'll only check | |
| 584 * this from P4 onwards. We might want to revisit | |
| 585 * that idea later. | |
| 586 */ | |
| 587 mask_ecx = 0xffffffff; | |
| 588 } else if (cpi->cpi_family > 0xf) | |
| 589 mask_ecx = 0xffffffff; | |
| 590 break; | |
| 591 case X86_VENDOR_IntelClone: | |
| 592 default: | |
| 593 break; | |
| 594 case X86_VENDOR_AMD: | |
| 595 #if defined(OPTERON_ERRATUM_108) | |
| 596 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { | |
| 597 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; | |
| 598 cpi->cpi_model = 0xc; | |
| 599 } else | |
| 600 #endif | |
| 601 if (cpi->cpi_family == 5) { | |
| 602 /* | |
| 603 * AMD K5 and K6 | |
| 604 * | |
| 605 * These CPUs have an incomplete implementation | |
| 606 * of MCA/MCE which we mask away. | |
| 607 */ | |
| 1228 | 608 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); |
| 609 | |
| 610 /* | |
| 611 * Model 0 uses the wrong (APIC) bit | |
| 612 * to indicate PGE. Fix it here. | |
| 613 */ | |
| 0 | 614 if (cpi->cpi_model == 0) { |
| 615 if (cp->cp_edx & 0x200) { | |
| 616 cp->cp_edx &= ~0x200; | |
| 617 cp->cp_edx |= CPUID_INTC_EDX_PGE; | |
| 618 } | |
| 1228 | 619 } |
| 620 | |
| 621 /* | |
| 622 * Early models had problems w/ MMX; disable. | |
| 623 */ | |
| 624 if (cpi->cpi_model < 6) | |
| 625 mask_edx &= ~CPUID_INTC_EDX_MMX; | |
| 626 } | |
| 627 | |
| 628 /* | |
| 629 * For newer families, SSE3 and CX16, at least, are valid; | |
| 630 * enable all | |
| 631 */ | |
| 632 if (cpi->cpi_family >= 0xf) | |
|
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633 mask_ecx = 0xffffffff; |
| 0 | 634 break; |
| 635 case X86_VENDOR_TM: | |
| 636 /* | |
| 637 * workaround the NT workaround in CMS 4.1 | |
| 638 */ | |
| 639 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && | |
| 640 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) | |
| 641 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 642 break; | |
| 643 case X86_VENDOR_Centaur: | |
| 644 /* | |
| 645 * workaround the NT workarounds again | |
| 646 */ | |
| 647 if (cpi->cpi_family == 6) | |
| 648 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 649 break; | |
| 650 case X86_VENDOR_Cyrix: | |
| 651 /* | |
| 652 * We rely heavily on the probing in locore | |
| 653 * to actually figure out what parts, if any, | |
| 654 * of the Cyrix cpuid instruction to believe. | |
| 655 */ | |
| 656 switch (x86_type) { | |
| 657 case X86_TYPE_CYRIX_486: | |
| 658 mask_edx = 0; | |
| 659 break; | |
| 660 case X86_TYPE_CYRIX_6x86: | |
| 661 mask_edx = 0; | |
| 662 break; | |
| 663 case X86_TYPE_CYRIX_6x86L: | |
| 664 mask_edx = | |
| 665 CPUID_INTC_EDX_DE | | |
| 666 CPUID_INTC_EDX_CX8; | |
| 667 break; | |
| 668 case X86_TYPE_CYRIX_6x86MX: | |
| 669 mask_edx = | |
| 670 CPUID_INTC_EDX_DE | | |
| 671 CPUID_INTC_EDX_MSR | | |
| 672 CPUID_INTC_EDX_CX8 | | |
| 673 CPUID_INTC_EDX_PGE | | |
| 674 CPUID_INTC_EDX_CMOV | | |
| 675 CPUID_INTC_EDX_MMX; | |
| 676 break; | |
| 677 case X86_TYPE_CYRIX_GXm: | |
| 678 mask_edx = | |
| 679 CPUID_INTC_EDX_MSR | | |
| 680 CPUID_INTC_EDX_CX8 | | |
| 681 CPUID_INTC_EDX_CMOV | | |
| 682 CPUID_INTC_EDX_MMX; | |
| 683 break; | |
| 684 case X86_TYPE_CYRIX_MediaGX: | |
| 685 break; | |
| 686 case X86_TYPE_CYRIX_MII: | |
| 687 case X86_TYPE_VIA_CYRIX_III: | |
| 688 mask_edx = | |
| 689 CPUID_INTC_EDX_DE | | |
| 690 CPUID_INTC_EDX_TSC | | |
| 691 CPUID_INTC_EDX_MSR | | |
| 692 CPUID_INTC_EDX_CX8 | | |
| 693 CPUID_INTC_EDX_PGE | | |
| 694 CPUID_INTC_EDX_CMOV | | |
| 695 CPUID_INTC_EDX_MMX; | |
| 696 break; | |
| 697 default: | |
| 698 break; | |
| 699 } | |
| 700 break; | |
| 701 } | |
| 702 | |
| 703 /* | |
| 704 * Now we've figured out the masks that determine | |
| 705 * which bits we choose to believe, apply the masks | |
| 706 * to the feature words, then map the kernel's view | |
| 707 * of these feature words into its feature word. | |
| 708 */ | |
| 709 cp->cp_edx &= mask_edx; | |
| 710 cp->cp_ecx &= mask_ecx; | |
| 711 | |
| 712 /* | |
| 3446 | 713 * apply any platform restrictions (we don't call this |
| 714 * immediately after __cpuid_insn here, because we need the | |
| 715 * workarounds applied above first) | |
| 0 | 716 */ |
| 3446 | 717 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); |
| 0 | 718 |
| 3446 | 719 /* |
| 720 * fold in overrides from the "eeprom" mechanism | |
| 721 */ | |
| 0 | 722 cp->cp_edx |= cpuid_feature_edx_include; |
| 723 cp->cp_edx &= ~cpuid_feature_edx_exclude; | |
| 724 | |
| 725 cp->cp_ecx |= cpuid_feature_ecx_include; | |
| 726 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; | |
| 727 | |
| 728 if (cp->cp_edx & CPUID_INTC_EDX_PSE) | |
| 729 feature |= X86_LARGEPAGE; | |
| 730 if (cp->cp_edx & CPUID_INTC_EDX_TSC) | |
| 731 feature |= X86_TSC; | |
| 732 if (cp->cp_edx & CPUID_INTC_EDX_MSR) | |
| 733 feature |= X86_MSR; | |
| 734 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) | |
| 735 feature |= X86_MTRR; | |
| 736 if (cp->cp_edx & CPUID_INTC_EDX_PGE) | |
| 737 feature |= X86_PGE; | |
| 738 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) | |
| 739 feature |= X86_CMOV; | |
| 740 if (cp->cp_edx & CPUID_INTC_EDX_MMX) | |
| 741 feature |= X86_MMX; | |
| 742 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && | |
| 743 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) | |
| 744 feature |= X86_MCA; | |
| 745 if (cp->cp_edx & CPUID_INTC_EDX_PAE) | |
| 746 feature |= X86_PAE; | |
| 747 if (cp->cp_edx & CPUID_INTC_EDX_CX8) | |
| 748 feature |= X86_CX8; | |
| 749 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) | |
| 750 feature |= X86_CX16; | |
| 751 if (cp->cp_edx & CPUID_INTC_EDX_PAT) | |
| 752 feature |= X86_PAT; | |
| 753 if (cp->cp_edx & CPUID_INTC_EDX_SEP) | |
| 754 feature |= X86_SEP; | |
| 755 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { | |
| 756 /* | |
| 757 * In our implementation, fxsave/fxrstor | |
| 758 * are prerequisites before we'll even | |
| 759 * try and do SSE things. | |
| 760 */ | |
| 761 if (cp->cp_edx & CPUID_INTC_EDX_SSE) | |
| 762 feature |= X86_SSE; | |
| 763 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) | |
| 764 feature |= X86_SSE2; | |
| 765 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) | |
| 766 feature |= X86_SSE3; | |
| 767 } | |
| 768 if (cp->cp_edx & CPUID_INTC_EDX_DE) | |
| 3446 | 769 feature |= X86_DE; |
|
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770 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { |
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771 cpi->cpi_mwait.support |= MWAIT_SUPPORT; |
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772 feature |= X86_MWAIT; |
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773 } |
| 0 | 774 |
| 775 if (feature & X86_PAE) | |
| 776 cpi->cpi_pabits = 36; | |
| 777 | |
| 778 /* | |
| 779 * Hyperthreading configuration is slightly tricky on Intel | |
| 780 * and pure clones, and even trickier on AMD. | |
| 781 * | |
| 782 * (AMD chose to set the HTT bit on their CMP processors, | |
| 783 * even though they're not actually hyperthreaded. Thus it | |
| 784 * takes a bit more work to figure out what's really going | |
| 3446 | 785 * on ... see the handling of the CMP_LGCY bit below) |
| 0 | 786 */ |
| 787 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { | |
| 788 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); | |
| 789 if (cpi->cpi_ncpu_per_chip > 1) | |
| 790 feature |= X86_HTT; | |
| 1228 | 791 } else { |
| 792 cpi->cpi_ncpu_per_chip = 1; | |
| 0 | 793 } |
| 794 | |
| 795 /* | |
| 796 * Work on the "extended" feature information, doing | |
| 797 * some basic initialization for cpuid_pass2() | |
| 798 */ | |
| 799 xcpuid = 0; | |
| 800 switch (cpi->cpi_vendor) { | |
| 801 case X86_VENDOR_Intel: | |
|
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802 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) |
| 0 | 803 xcpuid++; |
| 804 break; | |
| 805 case X86_VENDOR_AMD: | |
| 806 if (cpi->cpi_family > 5 || | |
| 807 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 808 xcpuid++; | |
| 809 break; | |
| 810 case X86_VENDOR_Cyrix: | |
| 811 /* | |
| 812 * Only these Cyrix CPUs are -known- to support | |
| 813 * extended cpuid operations. | |
| 814 */ | |
| 815 if (x86_type == X86_TYPE_VIA_CYRIX_III || | |
| 816 x86_type == X86_TYPE_CYRIX_GXm) | |
| 817 xcpuid++; | |
| 818 break; | |
| 819 case X86_VENDOR_Centaur: | |
| 820 case X86_VENDOR_TM: | |
| 821 default: | |
| 822 xcpuid++; | |
| 823 break; | |
| 824 } | |
| 825 | |
| 826 if (xcpuid) { | |
| 827 cp = &cpi->cpi_extd[0]; | |
| 1228 | 828 cp->cp_eax = 0x80000000; |
| 829 cpi->cpi_xmaxeax = __cpuid_insn(cp); | |
| 0 | 830 } |
| 831 | |
| 832 if (cpi->cpi_xmaxeax & 0x80000000) { | |
| 833 | |
| 834 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) | |
| 835 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; | |
| 836 | |
| 837 switch (cpi->cpi_vendor) { | |
| 838 case X86_VENDOR_Intel: | |
| 839 case X86_VENDOR_AMD: | |
| 840 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 841 break; | |
| 842 cp = &cpi->cpi_extd[1]; | |
| 1228 | 843 cp->cp_eax = 0x80000001; |
| 844 (void) __cpuid_insn(cp); | |
| 3446 | 845 |
| 0 | 846 if (cpi->cpi_vendor == X86_VENDOR_AMD && |
| 847 cpi->cpi_family == 5 && | |
| 848 cpi->cpi_model == 6 && | |
| 849 cpi->cpi_step == 6) { | |
| 850 /* | |
| 851 * K6 model 6 uses bit 10 to indicate SYSC | |
| 852 * Later models use bit 11. Fix it here. | |
| 853 */ | |
| 854 if (cp->cp_edx & 0x400) { | |
| 855 cp->cp_edx &= ~0x400; | |
| 856 cp->cp_edx |= CPUID_AMD_EDX_SYSC; | |
| 857 } | |
| 858 } | |
| 859 | |
| 3446 | 860 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); |
| 861 | |
| 0 | 862 /* |
| 863 * Compute the additions to the kernel's feature word. | |
| 864 */ | |
| 865 if (cp->cp_edx & CPUID_AMD_EDX_NX) | |
| 866 feature |= X86_NX; | |
| 867 | |
| 868 /* | |
| 3446 | 869 * If both the HTT and CMP_LGCY bits are set, |
| 1228 | 870 * then we're not actually HyperThreaded. Read |
| 871 * "AMD CPUID Specification" for more details. | |
| 0 | 872 */ |
| 873 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
| 1228 | 874 (feature & X86_HTT) && |
| 3446 | 875 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { |
| 0 | 876 feature &= ~X86_HTT; |
| 1228 | 877 feature |= X86_CMP; |
| 878 } | |
| 3446 | 879 #if defined(__amd64) |
| 0 | 880 /* |
| 881 * It's really tricky to support syscall/sysret in | |
| 882 * the i386 kernel; we rely on sysenter/sysexit | |
| 883 * instead. In the amd64 kernel, things are -way- | |
| 884 * better. | |
| 885 */ | |
| 886 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) | |
| 887 feature |= X86_ASYSC; | |
| 888 | |
| 889 /* | |
| 890 * While we're thinking about system calls, note | |
| 891 * that AMD processors don't support sysenter | |
| 892 * in long mode at all, so don't try to program them. | |
| 893 */ | |
| 894 if (x86_vendor == X86_VENDOR_AMD) | |
| 895 feature &= ~X86_SEP; | |
| 896 #endif | |
| 3446 | 897 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) |
| 898 feature |= X86_TSCP; | |
| 0 | 899 break; |
| 900 default: | |
| 901 break; | |
| 902 } | |
| 903 | |
| 1228 | 904 /* |
| 905 * Get CPUID data about processor cores and hyperthreads. | |
| 906 */ | |
| 0 | 907 switch (cpi->cpi_vendor) { |
| 908 case X86_VENDOR_Intel: | |
| 1228 | 909 if (cpi->cpi_maxeax >= 4) { |
| 910 cp = &cpi->cpi_std[4]; | |
| 911 cp->cp_eax = 4; | |
| 912 cp->cp_ecx = 0; | |
| 913 (void) __cpuid_insn(cp); | |
| 3446 | 914 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); |
| 1228 | 915 } |
| 916 /*FALLTHROUGH*/ | |
| 0 | 917 case X86_VENDOR_AMD: |
| 918 if (cpi->cpi_xmaxeax < 0x80000008) | |
| 919 break; | |
| 920 cp = &cpi->cpi_extd[8]; | |
| 1228 | 921 cp->cp_eax = 0x80000008; |
| 922 (void) __cpuid_insn(cp); | |
| 3446 | 923 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); |
| 924 | |
| 0 | 925 /* |
| 926 * Virtual and physical address limits from | |
| 927 * cpuid override previously guessed values. | |
| 928 */ | |
| 929 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); | |
| 930 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); | |
| 931 break; | |
| 932 default: | |
| 933 break; | |
| 934 } | |
| 1228 | 935 |
| 4606 | 936 /* |
| 937 * Derive the number of cores per chip | |
| 938 */ | |
| 1228 | 939 switch (cpi->cpi_vendor) { |
| 940 case X86_VENDOR_Intel: | |
| 941 if (cpi->cpi_maxeax < 4) { | |
| 942 cpi->cpi_ncore_per_chip = 1; | |
| 943 break; | |
| 944 } else { | |
| 945 cpi->cpi_ncore_per_chip = | |
| 946 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; | |
| 947 } | |
| 948 break; | |
| 949 case X86_VENDOR_AMD: | |
| 950 if (cpi->cpi_xmaxeax < 0x80000008) { | |
| 951 cpi->cpi_ncore_per_chip = 1; | |
| 952 break; | |
| 953 } else { | |
| 954 cpi->cpi_ncore_per_chip = | |
| 955 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; | |
| 956 } | |
| 957 break; | |
| 958 default: | |
| 959 cpi->cpi_ncore_per_chip = 1; | |
| 960 break; | |
| 961 } | |
| 0 | 962 } |
| 963 | |
| 1228 | 964 /* |
| 965 * If more than one core, then this processor is CMP. | |
| 966 */ | |
| 967 if (cpi->cpi_ncore_per_chip > 1) | |
| 968 feature |= X86_CMP; | |
| 3446 | 969 |
| 1228 | 970 /* |
| 971 * If the number of cores is the same as the number | |
| 972 * of CPUs, then we cannot have HyperThreading. | |
| 973 */ | |
| 974 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) | |
| 975 feature &= ~X86_HTT; | |
| 976 | |
| 0 | 977 if ((feature & (X86_HTT | X86_CMP)) == 0) { |
| 1228 | 978 /* |
| 979 * Single-core single-threaded processors. | |
| 980 */ | |
| 0 | 981 cpi->cpi_chipid = -1; |
| 982 cpi->cpi_clogid = 0; | |
| 1228 | 983 cpi->cpi_coreid = cpu->cpu_id; |
| 0 | 984 } else if (cpi->cpi_ncpu_per_chip > 1) { |
| 1228 | 985 uint_t i; |
| 986 uint_t chipid_shift = 0; | |
| 987 uint_t coreid_shift = 0; | |
| 988 uint_t apic_id = CPI_APIC_ID(cpi); | |
| 989 | |
| 990 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) | |
| 991 chipid_shift++; | |
| 992 cpi->cpi_chipid = apic_id >> chipid_shift; | |
| 993 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); | |
| 0 | 994 |
| 1228 | 995 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
| 996 if (feature & X86_CMP) { | |
| 997 /* | |
| 998 * Multi-core (and possibly multi-threaded) | |
| 999 * processors. | |
| 1000 */ | |
| 1001 uint_t ncpu_per_core; | |
| 1002 if (cpi->cpi_ncore_per_chip == 1) | |
| 1003 ncpu_per_core = cpi->cpi_ncpu_per_chip; | |
| 1004 else if (cpi->cpi_ncore_per_chip > 1) | |
| 1005 ncpu_per_core = cpi->cpi_ncpu_per_chip / | |
| 1006 cpi->cpi_ncore_per_chip; | |
| 1007 /* | |
| 1008 * 8bit APIC IDs on dual core Pentiums | |
| 1009 * look like this: | |
| 1010 * | |
| 1011 * +-----------------------+------+------+ | |
| 1012 * | Physical Package ID | MC | HT | | |
| 1013 * +-----------------------+------+------+ | |
| 1014 * <------- chipid --------> | |
| 1015 * <------- coreid ---------------> | |
| 1016 * <--- clogid --> | |
| 1017 * | |
| 1018 * Where the number of bits necessary to | |
| 1019 * represent MC and HT fields together equals | |
| 1020 * to the minimum number of bits necessary to | |
| 1021 * store the value of cpi->cpi_ncpu_per_chip. | |
| 1022 * Of those bits, the MC part uses the number | |
| 1023 * of bits necessary to store the value of | |
| 1024 * cpi->cpi_ncore_per_chip. | |
| 1025 */ | |
| 1026 for (i = 1; i < ncpu_per_core; i <<= 1) | |
| 1027 coreid_shift++; | |
|
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1028 cpi->cpi_coreid = apic_id >> coreid_shift; |
| 1228 | 1029 } else if (feature & X86_HTT) { |
| 1030 /* | |
| 1031 * Single-core multi-threaded processors. | |
| 1032 */ | |
| 1033 cpi->cpi_coreid = cpi->cpi_chipid; | |
| 1034 } | |
| 1035 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { | |
| 1036 /* | |
| 1037 * AMD currently only has dual-core processors with | |
| 1038 * single-threaded cores. If they ever release | |
| 1039 * multi-threaded processors, then this code | |
| 1040 * will have to be updated. | |
| 1041 */ | |
| 1042 cpi->cpi_coreid = cpu->cpu_id; | |
| 1043 } else { | |
| 1044 /* | |
| 1045 * All other processors are currently | |
| 1046 * assumed to have single cores. | |
| 1047 */ | |
| 1048 cpi->cpi_coreid = cpi->cpi_chipid; | |
| 1049 } | |
| 0 | 1050 } |
| 1051 | |
|
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1052 /* |
|
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1053 * Synthesize chip "revision" and socket type |
|
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|
1054 */ |
|
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|
1055 synth_info(cpi); |
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1056 |
| 0 | 1057 pass1_done: |
| 1058 cpi->cpi_pass = 1; | |
| 1059 return (feature); | |
| 1060 } | |
| 1061 | |
| 1062 /* | |
| 1063 * Make copies of the cpuid table entries we depend on, in | |
| 1064 * part for ease of parsing now, in part so that we have only | |
| 1065 * one place to correct any of it, in part for ease of | |
| 1066 * later export to userland, and in part so we can look at | |
| 1067 * this stuff in a crash dump. | |
| 1068 */ | |
| 1069 | |
| 1070 /*ARGSUSED*/ | |
| 1071 void | |
| 1072 cpuid_pass2(cpu_t *cpu) | |
| 1073 { | |
| 1074 uint_t n, nmax; | |
| 1075 int i; | |
| 1228 | 1076 struct cpuid_regs *cp; |
| 0 | 1077 uint8_t *dp; |
| 1078 uint32_t *iptr; | |
| 1079 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1080 | |
| 1081 ASSERT(cpi->cpi_pass == 1); | |
| 1082 | |
| 1083 if (cpi->cpi_maxeax < 1) | |
| 1084 goto pass2_done; | |
| 1085 | |
| 1086 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) | |
| 1087 nmax = NMAX_CPI_STD; | |
| 1088 /* | |
| 1089 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1090 */ | |
| 1091 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { | |
| 1228 | 1092 cp->cp_eax = n; |
| 4606 | 1093 |
| 1094 /* | |
| 1095 * CPUID function 4 expects %ecx to be initialized | |
| 1096 * with an index which indicates which cache to return | |
| 1097 * information about. The OS is expected to call function 4 | |
| 1098 * with %ecx set to 0, 1, 2, ... until it returns with | |
| 1099 * EAX[4:0] set to 0, which indicates there are no more | |
| 1100 * caches. | |
| 1101 * | |
| 1102 * Here, populate cpi_std[4] with the information returned by | |
| 1103 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() | |
| 1104 * when dynamic memory allocation becomes available. | |
| 1105 * | |
| 1106 * Note: we need to explicitly initialize %ecx here, since | |
| 1107 * function 4 may have been previously invoked. | |
| 1108 */ | |
| 1109 if (n == 4) | |
| 1110 cp->cp_ecx = 0; | |
| 1111 | |
| 1228 | 1112 (void) __cpuid_insn(cp); |
| 3446 | 1113 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); |
| 0 | 1114 switch (n) { |
| 1115 case 2: | |
| 1116 /* | |
| 1117 * "the lower 8 bits of the %eax register | |
| 1118 * contain a value that identifies the number | |
| 1119 * of times the cpuid [instruction] has to be | |
| 1120 * executed to obtain a complete image of the | |
| 1121 * processor's caching systems." | |
| 1122 * | |
| 1123 * How *do* they make this stuff up? | |
| 1124 */ | |
| 1125 cpi->cpi_ncache = sizeof (*cp) * | |
| 1126 BITX(cp->cp_eax, 7, 0); | |
| 1127 if (cpi->cpi_ncache == 0) | |
| 1128 break; | |
| 1129 cpi->cpi_ncache--; /* skip count byte */ | |
| 1130 | |
| 1131 /* | |
| 1132 * Well, for now, rather than attempt to implement | |
| 1133 * this slightly dubious algorithm, we just look | |
| 1134 * at the first 15 .. | |
| 1135 */ | |
| 1136 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) | |
| 1137 cpi->cpi_ncache = sizeof (*cp) - 1; | |
| 1138 | |
| 1139 dp = cpi->cpi_cacheinfo; | |
| 1140 if (BITX(cp->cp_eax, 31, 31) == 0) { | |
| 1141 uint8_t *p = (void *)&cp->cp_eax; | |
| 1142 for (i = 1; i < 3; i++) | |
| 1143 if (p[i] != 0) | |
| 1144 *dp++ = p[i]; | |
| 1145 } | |
| 1146 if (BITX(cp->cp_ebx, 31, 31) == 0) { | |
| 1147 uint8_t *p = (void *)&cp->cp_ebx; | |
| 1148 for (i = 0; i < 4; i++) | |
| 1149 if (p[i] != 0) | |
| 1150 *dp++ = p[i]; | |
| 1151 } | |
| 1152 if (BITX(cp->cp_ecx, 31, 31) == 0) { | |
| 1153 uint8_t *p = (void *)&cp->cp_ecx; | |
| 1154 for (i = 0; i < 4; i++) | |
| 1155 if (p[i] != 0) | |
| 1156 *dp++ = p[i]; | |
| 1157 } | |
| 1158 if (BITX(cp->cp_edx, 31, 31) == 0) { | |
| 1159 uint8_t *p = (void *)&cp->cp_edx; | |
| 1160 for (i = 0; i < 4; i++) | |
| 1161 if (p[i] != 0) | |
| 1162 *dp++ = p[i]; | |
| 1163 } | |
| 1164 break; | |
|
4481
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1165 |
| 0 | 1166 case 3: /* Processor serial number, if PSN supported */ |
|
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1167 break; |
|
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|
1168 |
| 0 | 1169 case 4: /* Deterministic cache parameters */ |
|
4481
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1170 break; |
|
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1171 |
| 0 | 1172 case 5: /* Monitor/Mwait parameters */ |
|
4481
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1173 |
|
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|
1174 /* |
|
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1175 * check cpi_mwait.support which was set in cpuid_pass1 |
|
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1176 */ |
|
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1177 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) |
|
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1178 break; |
|
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|
1179 |
|
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1180 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); |
|
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1181 cpi->cpi_mwait.mon_max = (size_t)MWAIT_SIZE_MAX(cpi); |
|
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1182 if (MWAIT_EXTENSION(cpi)) { |
|
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1183 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; |
|
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1184 if (MWAIT_INT_ENABLE(cpi)) |
|
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1185 cpi->cpi_mwait.support |= |
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1186 MWAIT_ECX_INT_ENABLE; |
|
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1187 } |
|
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|
1188 break; |
| 0 | 1189 default: |
| 1190 break; | |
| 1191 } | |
| 1192 } | |
| 1193 | |
| 1194 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) | |
| 1195 goto pass2_done; | |
| 1196 | |
| 1197 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) | |
| 1198 nmax = NMAX_CPI_EXTD; | |
| 1199 /* | |
| 1200 * Copy the extended properties, fixing them as we go. | |
| 1201 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1202 */ | |
| 1203 iptr = (void *)cpi->cpi_brandstr; | |
| 1204 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { | |
| 1228 | 1205 cp->cp_eax = 0x80000000 + n; |
| 1206 (void) __cpuid_insn(cp); | |
| 3446 | 1207 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); |
| 0 | 1208 switch (n) { |
| 1209 case 2: | |
| 1210 case 3: | |
| 1211 case 4: | |
| 1212 /* | |
| 1213 * Extract the brand string | |
| 1214 */ | |
| 1215 *iptr++ = cp->cp_eax; | |
| 1216 *iptr++ = cp->cp_ebx; | |
| 1217 *iptr++ = cp->cp_ecx; | |
| 1218 *iptr++ = cp->cp_edx; | |
| 1219 break; | |
| 1220 case 5: | |
| 1221 switch (cpi->cpi_vendor) { | |
| 1222 case X86_VENDOR_AMD: | |
| 1223 /* | |
| 1224 * The Athlon and Duron were the first | |
| 1225 * parts to report the sizes of the | |
| 1226 * TLB for large pages. Before then, | |
| 1227 * we don't trust the data. | |
| 1228 */ | |
| 1229 if (cpi->cpi_family < 6 || | |
| 1230 (cpi->cpi_family == 6 && | |
| 1231 cpi->cpi_model < 1)) | |
| 1232 cp->cp_eax = 0; | |
| 1233 break; | |
| 1234 default: | |
| 1235 break; | |
| 1236 } | |
| 1237 break; | |
| 1238 case 6: | |
| 1239 switch (cpi->cpi_vendor) { | |
| 1240 case X86_VENDOR_AMD: | |
| 1241 /* | |
| 1242 * The Athlon and Duron were the first | |
| 1243 * AMD parts with L2 TLB's. | |
| 1244 * Before then, don't trust the data. | |
| 1245 */ | |
| 1246 if (cpi->cpi_family < 6 || | |
| 1247 cpi->cpi_family == 6 && | |
| 1248 cpi->cpi_model < 1) | |
| 1249 cp->cp_eax = cp->cp_ebx = 0; | |
| 1250 /* | |
| 1251 * AMD Duron rev A0 reports L2 | |
| 1252 * cache size incorrectly as 1K | |
| 1253 * when it is really 64K | |
| 1254 */ | |
| 1255 if (cpi->cpi_family == 6 && | |
| 1256 cpi->cpi_model == 3 && | |
| 1257 cpi->cpi_step == 0) { | |
| 1258 cp->cp_ecx &= 0xffff; | |
| 1259 cp->cp_ecx |= 0x400000; | |
| 1260 } | |
| 1261 break; | |
| 1262 case X86_VENDOR_Cyrix: /* VIA C3 */ | |
| 1263 /* | |
| 1264 * VIA C3 processors are a bit messed | |
| 1265 * up w.r.t. encoding cache sizes in %ecx | |
| 1266 */ | |
| 1267 if (cpi->cpi_family != 6) | |
| 1268 break; | |
| 1269 /* | |
| 1270 * model 7 and 8 were incorrectly encoded | |
| 1271 * | |
| 1272 * xxx is model 8 really broken? | |
| 1273 */ | |
| 1274 if (cpi->cpi_model == 7 || | |
| 1275 cpi->cpi_model == 8) | |
| 1276 cp->cp_ecx = | |
| 1277 BITX(cp->cp_ecx, 31, 24) << 16 | | |
| 1278 BITX(cp->cp_ecx, 23, 16) << 12 | | |
| 1279 BITX(cp->cp_ecx, 15, 8) << 8 | | |
| 1280 BITX(cp->cp_ecx, 7, 0); | |
| 1281 /* | |
| 1282 * model 9 stepping 1 has wrong associativity | |
| 1283 */ | |
| 1284 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) | |
| 1285 cp->cp_ecx |= 8 << 12; | |
| 1286 break; | |
| 1287 case X86_VENDOR_Intel: | |
| 1288 /* | |
| 1289 * Extended L2 Cache features function. | |
| 1290 * First appeared on Prescott. | |
| 1291 */ | |
| 1292 default: | |
| 1293 break; | |
| 1294 } | |
| 1295 break; | |
| 1296 default: | |
| 1297 break; | |
| 1298 } | |
| 1299 } | |
| 1300 | |
| 1301 pass2_done: | |
| 1302 cpi->cpi_pass = 2; | |
| 1303 } | |
| 1304 | |
| 1305 static const char * | |
| 1306 intel_cpubrand(const struct cpuid_info *cpi) | |
| 1307 { | |
| 1308 int i; | |
| 1309 | |
| 1310 if ((x86_feature & X86_CPUID) == 0 || | |
| 1311 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
| 1312 return ("i486"); | |
| 1313 | |
| 1314 switch (cpi->cpi_family) { | |
| 1315 case 5: | |
| 1316 return ("Intel Pentium(r)"); | |
| 1317 case 6: | |
| 1318 switch (cpi->cpi_model) { | |
| 1319 uint_t celeron, xeon; | |
| 1228 | 1320 const struct cpuid_regs *cp; |
| 0 | 1321 case 0: |
| 1322 case 1: | |
| 1323 case 2: | |
| 1324 return ("Intel Pentium(r) Pro"); | |
| 1325 case 3: | |
| 1326 case 4: | |
| 1327 return ("Intel Pentium(r) II"); | |
| 1328 case 6: | |
| 1329 return ("Intel Celeron(r)"); | |
| 1330 case 5: | |
| 1331 case 7: | |
| 1332 celeron = xeon = 0; | |
| 1333 cp = &cpi->cpi_std[2]; /* cache info */ | |
| 1334 | |
| 1335 for (i = 1; i < 3; i++) { | |
| 1336 uint_t tmp; | |
| 1337 | |
| 1338 tmp = (cp->cp_eax >> (8 * i)) & 0xff; | |
| 1339 if (tmp == 0x40) | |
| 1340 celeron++; | |
| 1341 if (tmp >= 0x44 && tmp <= 0x45) | |
| 1342 xeon++; | |
| 1343 } | |
| 1344 | |
| 1345 for (i = 0; i < 2; i++) { | |
| 1346 uint_t tmp; | |
| 1347 | |
| 1348 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; | |
| 1349 if (tmp == 0x40) | |
| 1350 celeron++; | |
| 1351 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1352 xeon++; | |
| 1353 } | |
| 1354 | |
| 1355 for (i = 0; i < 4; i++) { | |
| 1356 uint_t tmp; | |
| 1357 | |
| 1358 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; | |
| 1359 if (tmp == 0x40) | |
| 1360 celeron++; | |
| 1361 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1362 xeon++; | |
| 1363 } | |
| 1364 | |
| 1365 for (i = 0; i < 4; i++) { | |
| 1366 uint_t tmp; | |
| 1367 | |
| 1368 tmp = (cp->cp_edx >> (8 * i)) & 0xff; | |
| 1369 if (tmp == 0x40) | |
| 1370 celeron++; | |
| 1371 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1372 xeon++; | |
| 1373 } | |
| 1374 | |
| 1375 if (celeron) | |
| 1376 return ("Intel Celeron(r)"); | |
| 1377 if (xeon) | |
| 1378 return (cpi->cpi_model == 5 ? | |
| 1379 "Intel Pentium(r) II Xeon(tm)" : | |
| 1380 "Intel Pentium(r) III Xeon(tm)"); | |
| 1381 return (cpi->cpi_model == 5 ? | |
| 1382 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : | |
| 1383 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); | |
| 1384 default: | |
| 1385 break; | |
| 1386 } | |
| 1387 default: | |
| 1388 break; | |
| 1389 } | |
| 1390 | |
|
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1391 /* BrandID is present if the field is nonzero */ |
|
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|
1392 if (cpi->cpi_brandid != 0) { |
| 0 | 1393 static const struct { |
| 1394 uint_t bt_bid; | |
| 1395 const char *bt_str; | |
| 1396 } brand_tbl[] = { | |
| 1397 { 0x1, "Intel(r) Celeron(r)" }, | |
| 1398 { 0x2, "Intel(r) Pentium(r) III" }, | |
| 1399 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, | |
| 1400 { 0x4, "Intel(r) Pentium(r) III" }, | |
| 1401 { 0x6, "Mobile Intel(r) Pentium(r) III" }, | |
| 1402 { 0x7, "Mobile Intel(r) Celeron(r)" }, | |
| 1403 { 0x8, "Intel(r) Pentium(r) 4" }, | |
| 1404 { 0x9, "Intel(r) Pentium(r) 4" }, | |
| 1405 { 0xa, "Intel(r) Celeron(r)" }, | |
| 1406 { 0xb, "Intel(r) Xeon(tm)" }, | |
| 1407 { 0xc, "Intel(r) Xeon(tm) MP" }, | |
| 1408 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, | |
|
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1409 { 0xf, "Mobile Intel(r) Celeron(r)" }, |
|
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1410 { 0x11, "Mobile Genuine Intel(r)" }, |
|
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1411 { 0x12, "Intel(r) Celeron(r) M" }, |
|
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1412 { 0x13, "Mobile Intel(r) Celeron(r)" }, |
|
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1413 { 0x14, "Intel(r) Celeron(r)" }, |
|
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1414 { 0x15, "Mobile Genuine Intel(r)" }, |
|
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1415 { 0x16, "Intel(r) Pentium(r) M" }, |
|
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|
1416 { 0x17, "Mobile Intel(r) Celeron(r)" } |
| 0 | 1417 }; |
| 1418 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); | |
| 1419 uint_t sgn; | |
| 1420 | |
| 1421 sgn = (cpi->cpi_family << 8) | | |
| 1422 (cpi->cpi_model << 4) | cpi->cpi_step; | |
| 1423 | |
| 1424 for (i = 0; i < btblmax; i++) | |
| 1425 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) | |
| 1426 break; | |
| 1427 if (i < btblmax) { | |
| 1428 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) | |
| 1429 return ("Intel(r) Celeron(r)"); | |
| 1430 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) | |
| 1431 return ("Intel(r) Xeon(tm) MP"); | |
| 1432 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) | |
| 1433 return ("Intel(r) Xeon(tm)"); | |
| 1434 return (brand_tbl[i].bt_str); | |
| 1435 } | |
| 1436 } | |
| 1437 | |
| 1438 return (NULL); | |
| 1439 } | |
| 1440 | |
| 1441 static const char * | |
| 1442 amd_cpubrand(const struct cpuid_info *cpi) | |
| 1443 { | |
| 1444 if ((x86_feature & X86_CPUID) == 0 || | |
| 1445 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
| 1446 return ("i486 compatible"); | |
| 1447 | |
| 1448 switch (cpi->cpi_family) { | |
| 1449 case 5: | |
| 1450 switch (cpi->cpi_model) { | |
| 1451 case 0: | |
| 1452 case 1: | |
| 1453 case 2: | |
| 1454 case 3: | |
| 1455 case 4: | |
| 1456 case 5: | |
| 1457 return ("AMD-K5(r)"); | |
| 1458 case 6: | |
| 1459 case 7: | |
| 1460 return ("AMD-K6(r)"); | |
| 1461 case 8: | |
| 1462 return ("AMD-K6(r)-2"); | |
| 1463 case 9: | |
| 1464 return ("AMD-K6(r)-III"); | |
| 1465 default: | |
| 1466 return ("AMD (family 5)"); | |
| 1467 } | |
| 1468 case 6: | |
| 1469 switch (cpi->cpi_model) { | |
| 1470 case 1: | |
| 1471 return ("AMD-K7(tm)"); | |
| 1472 case 0: | |
| 1473 case 2: | |
| 1474 case 4: | |
| 1475 return ("AMD Athlon(tm)"); | |
| 1476 case 3: | |
| 1477 case 7: | |
| 1478 return ("AMD Duron(tm)"); | |
| 1479 case 6: | |
| 1480 case 8: | |
| 1481 case 10: | |
| 1482 /* | |
| 1483 * Use the L2 cache size to distinguish | |
| 1484 */ | |
| 1485 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? | |
| 1486 "AMD Athlon(tm)" : "AMD Duron(tm)"); | |
| 1487 default: | |
| 1488 return ("AMD (family 6)"); | |
| 1489 } | |
| 1490 default: | |
| 1491 break; | |
| 1492 } | |
| 1493 | |
| 1494 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && | |
| 1495 cpi->cpi_brandid != 0) { | |
| 1496 switch (BITX(cpi->cpi_brandid, 7, 5)) { | |
| 1497 case 3: | |
| 1498 return ("AMD Opteron(tm) UP 1xx"); | |
| 1499 case 4: | |
| 1500 return ("AMD Opteron(tm) DP 2xx"); | |
| 1501 case 5: | |
| 1502 return ("AMD Opteron(tm) MP 8xx"); | |
| 1503 default: | |
| 1504 return ("AMD Opteron(tm)"); | |
| 1505 } | |
| 1506 } | |
| 1507 | |
| 1508 return (NULL); | |
| 1509 } | |
| 1510 | |
| 1511 static const char * | |
| 1512 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) | |
| 1513 { | |
| 1514 if ((x86_feature & X86_CPUID) == 0 || | |
| 1515 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || | |
| 1516 type == X86_TYPE_CYRIX_486) | |
| 1517 return ("i486 compatible"); | |
| 1518 | |
| 1519 switch (type) { | |
| 1520 case X86_TYPE_CYRIX_6x86: | |
| 1521 return ("Cyrix 6x86"); | |
| 1522 case X86_TYPE_CYRIX_6x86L: | |
| 1523 return ("Cyrix 6x86L"); | |
| 1524 case X86_TYPE_CYRIX_6x86MX: | |
| 1525 return ("Cyrix 6x86MX"); | |
| 1526 case X86_TYPE_CYRIX_GXm: | |
| 1527 return ("Cyrix GXm"); | |
| 1528 case X86_TYPE_CYRIX_MediaGX: | |
| 1529 return ("Cyrix MediaGX"); | |
| 1530 case X86_TYPE_CYRIX_MII: | |
| 1531 return ("Cyrix M2"); | |
| 1532 case X86_TYPE_VIA_CYRIX_III: | |
| 1533 return ("VIA Cyrix M3"); | |
| 1534 default: | |
| 1535 /* | |
| 1536 * Have another wild guess .. | |
| 1537 */ | |
| 1538 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) | |
| 1539 return ("Cyrix 5x86"); | |
| 1540 else if (cpi->cpi_family == 5) { | |
| 1541 switch (cpi->cpi_model) { | |
| 1542 case 2: | |
| 1543 return ("Cyrix 6x86"); /* Cyrix M1 */ | |
| 1544 case 4: | |
| 1545 return ("Cyrix MediaGX"); | |
| 1546 default: | |
| 1547 break; | |
| 1548 } | |
| 1549 } else if (cpi->cpi_family == 6) { | |
| 1550 switch (cpi->cpi_model) { | |
| 1551 case 0: | |
| 1552 return ("Cyrix 6x86MX"); /* Cyrix M2? */ | |
| 1553 case 5: | |
| 1554 case 6: | |
| 1555 case 7: | |
| 1556 case 8: | |
| 1557 case 9: | |
| 1558 return ("VIA C3"); | |
| 1559 default: | |
| 1560 break; | |
| 1561 } | |
| 1562 } | |
| 1563 break; | |
| 1564 } | |
| 1565 return (NULL); | |
| 1566 } | |
| 1567 | |
| 1568 /* | |
| 1569 * This only gets called in the case that the CPU extended | |
| 1570 * feature brand string (0x80000002, 0x80000003, 0x80000004) | |
| 1571 * aren't available, or contain null bytes for some reason. | |
| 1572 */ | |
| 1573 static void | |
| 1574 fabricate_brandstr(struct cpuid_info *cpi) | |
| 1575 { | |
| 1576 const char *brand = NULL; | |
| 1577 | |
| 1578 switch (cpi->cpi_vendor) { | |
| 1579 case X86_VENDOR_Intel: | |
| 1580 brand = intel_cpubrand(cpi); | |
| 1581 break; | |
| 1582 case X86_VENDOR_AMD: | |
| 1583 brand = amd_cpubrand(cpi); | |
| 1584 break; | |
| 1585 case X86_VENDOR_Cyrix: | |
| 1586 brand = cyrix_cpubrand(cpi, x86_type); | |
| 1587 break; | |
| 1588 case X86_VENDOR_NexGen: | |
| 1589 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 1590 brand = "NexGen Nx586"; | |
| 1591 break; | |
| 1592 case X86_VENDOR_Centaur: | |
| 1593 if (cpi->cpi_family == 5) | |
| 1594 switch (cpi->cpi_model) { | |
| 1595 case 4: | |
| 1596 brand = "Centaur C6"; | |
| 1597 break; | |
| 1598 case 8: | |
| 1599 brand = "Centaur C2"; | |
| 1600 break; | |
| 1601 case 9: | |
| 1602 brand = "Centaur C3"; | |
| 1603 break; | |
| 1604 default: | |
| 1605 break; | |
| 1606 } | |
| 1607 break; | |
| 1608 case X86_VENDOR_Rise: | |
| 1609 if (cpi->cpi_family == 5 && | |
| 1610 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) | |
| 1611 brand = "Rise mP6"; | |
| 1612 break; | |
| 1613 case X86_VENDOR_SiS: | |
| 1614 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 1615 brand = "SiS 55x"; | |
| 1616 break; | |
| 1617 case X86_VENDOR_TM: | |
| 1618 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) | |
| 1619 brand = "Transmeta Crusoe TM3x00 or TM5x00"; | |
| 1620 break; | |
| 1621 case X86_VENDOR_NSC: | |
| 1622 case X86_VENDOR_UMC: | |
| 1623 default: | |
| 1624 break; | |
| 1625 } | |
| 1626 if (brand) { | |
| 1627 (void) strcpy((char *)cpi->cpi_brandstr, brand); | |
| 1628 return; | |
| 1629 } | |
| 1630 | |
| 1631 /* | |
| 1632 * If all else fails ... | |
| 1633 */ | |
| 1634 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), | |
| 1635 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, | |
| 1636 cpi->cpi_model, cpi->cpi_step); | |
| 1637 } | |
| 1638 | |
| 1639 /* | |
| 1640 * This routine is called just after kernel memory allocation | |
| 1641 * becomes available on cpu0, and as part of mp_startup() on | |
| 1642 * the other cpus. | |
| 1643 * | |
| 4606 | 1644 * Fixup the brand string, and collect any information from cpuid |
| 1645 * that requires dynamicically allocated storage to represent. | |
| 0 | 1646 */ |
| 1647 /*ARGSUSED*/ | |
| 1648 void | |
| 1649 cpuid_pass3(cpu_t *cpu) | |
| 1650 { | |
| 4606 | 1651 int i, max, shft, level, size; |
| 1652 struct cpuid_regs regs; | |
| 1653 struct cpuid_regs *cp; | |
| 0 | 1654 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 1655 | |
| 1656 ASSERT(cpi->cpi_pass == 2); | |
| 1657 | |
| 4606 | 1658 /* |
| 1659 * Function 4: Deterministic cache parameters | |
| 1660 * | |
| 1661 * Take this opportunity to detect the number of threads | |
| 1662 * sharing the last level cache, and construct a corresponding | |
| 1663 * cache id. The respective cpuid_info members are initialized | |
| 1664 * to the default case of "no last level cache sharing". | |
| 1665 */ | |
| 1666 cpi->cpi_ncpu_shr_last_cache = 1; | |
| 1667 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; | |
| 1668 | |
| 1669 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { | |
| 1670 | |
| 1671 /* | |
| 1672 * Find the # of elements (size) returned by fn 4, and along | |
| 1673 * the way detect last level cache sharing details. | |
| 1674 */ | |
| 1675 bzero(®s, sizeof (regs)); | |
| 1676 cp = ®s; | |
| 1677 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { | |
| 1678 cp->cp_eax = 4; | |
| 1679 cp->cp_ecx = i; | |
| 1680 | |
| 1681 (void) __cpuid_insn(cp); | |
| 1682 | |
| 1683 if (CPI_CACHE_TYPE(cp) == 0) | |
| 1684 break; | |
| 1685 level = CPI_CACHE_LVL(cp); | |
| 1686 if (level > max) { | |
| 1687 max = level; | |
| 1688 cpi->cpi_ncpu_shr_last_cache = | |
| 1689 CPI_NTHR_SHR_CACHE(cp) + 1; | |
| 1690 } | |
| 1691 } | |
| 1692 cpi->cpi_std_4_size = size = i; | |
| 1693 | |
| 1694 /* | |
| 1695 * Allocate the cpi_std_4 array. The first element | |
| 1696 * references the regs for fn 4, %ecx == 0, which | |
| 1697 * cpuid_pass2() stashed in cpi->cpi_std[4]. | |
| 1698 */ | |
| 1699 if (size > 0) { | |
| 1700 cpi->cpi_std_4 = | |
| 1701 kmem_alloc(size * sizeof (cp), KM_SLEEP); | |
| 1702 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; | |
| 1703 | |
| 1704 /* | |
| 1705 * Allocate storage to hold the additional regs | |
| 1706 * for function 4, %ecx == 1 .. cpi_std_4_size. | |
| 1707 * | |
| 1708 * The regs for fn 4, %ecx == 0 has already | |
| 1709 * been allocated as indicated above. | |
| 1710 */ | |
| 1711 for (i = 1; i < size; i++) { | |
| 1712 cp = cpi->cpi_std_4[i] = | |
| 1713 kmem_zalloc(sizeof (regs), KM_SLEEP); | |
| 1714 cp->cp_eax = 4; | |
| 1715 cp->cp_ecx = i; | |
| 1716 | |
| 1717 (void) __cpuid_insn(cp); | |
| 1718 } | |
| 1719 } | |
| 1720 /* | |
| 1721 * Determine the number of bits needed to represent | |
| 1722 * the number of CPUs sharing the last level cache. | |
| 1723 * | |
| 1724 * Shift off that number of bits from the APIC id to | |
| 1725 * derive the cache id. | |
| 1726 */ | |
| 1727 shft = 0; | |
| 1728 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) | |
| 1729 shft++; | |
| 1730 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; | |
| 0 | 1731 } |
| 1732 | |
| 1733 /* | |
| 4606 | 1734 * Now fixup the brand string |
| 0 | 1735 */ |
| 4606 | 1736 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { |
| 1737 fabricate_brandstr(cpi); | |
| 1738 } else { | |
| 0 | 1739 |
| 1740 /* | |
| 4606 | 1741 * If we successfully extracted a brand string from the cpuid |
| 1742 * instruction, clean it up by removing leading spaces and | |
| 1743 * similar junk. | |
| 0 | 1744 */ |
| 4606 | 1745 if (cpi->cpi_brandstr[0]) { |
| 1746 size_t maxlen = sizeof (cpi->cpi_brandstr); | |
| 1747 char *src, *dst; | |
| 1748 | |
| 1749 dst = src = (char *)cpi->cpi_brandstr; | |
| 1750 src[maxlen - 1] = '\0'; | |
| 1751 /* | |
| 1752 * strip leading spaces | |
| 1753 */ | |
| 1754 while (*src == ' ') | |
| 1755 src++; | |
| 1756 /* | |
| 1757 * Remove any 'Genuine' or "Authentic" prefixes | |
| 1758 */ | |
| 1759 if (strncmp(src, "Genuine ", 8) == 0) | |
| 1760 src += 8; | |
| 1761 if (strncmp(src, "Authentic ", 10) == 0) | |
| 1762 src += 10; | |
| 1763 | |
| 1764 /* | |
| 1765 * Now do an in-place copy. | |
| 1766 * Map (R) to (r) and (TM) to (tm). | |
| 1767 * The era of teletypes is long gone, and there's | |
| 1768 * -really- no need to shout. | |
| 1769 */ | |
| 1770 while (*src != '\0') { | |
| 1771 if (src[0] == '(') { | |
| 1772 if (strncmp(src + 1, "R)", 2) == 0) { | |
| 1773 (void) strncpy(dst, "(r)", 3); | |
| 1774 src += 3; | |
| 1775 dst += 3; | |
| 1776 continue; | |
| 1777 } | |
| 1778 if (strncmp(src + 1, "TM)", 3) == 0) { | |
| 1779 (void) strncpy(dst, "(tm)", 4); | |
| 1780 src += 4; | |
| 1781 dst += 4; | |
| 1782 continue; | |
| 1783 } | |
| 0 | 1784 } |
| 4606 | 1785 *dst++ = *src++; |
| 0 | 1786 } |
| 4606 | 1787 *dst = '\0'; |
| 1788 | |
| 1789 /* | |
| 1790 * Finally, remove any trailing spaces | |
| 1791 */ | |
| 1792 while (--dst > cpi->cpi_brandstr) | |
| 1793 if (*dst == ' ') | |
| 1794 *dst = '\0'; | |
| 1795 else | |
| 1796 break; | |
| 1797 } else | |
| 1798 fabricate_brandstr(cpi); | |
| 1799 } | |
| 0 | 1800 cpi->cpi_pass = 3; |
| 1801 } | |
| 1802 | |
| 1803 /* | |
| 1804 * This routine is called out of bind_hwcap() much later in the life | |
| 1805 * of the kernel (post_startup()). The job of this routine is to resolve | |
| 1806 * the hardware feature support and kernel support for those features into | |
| 1807 * what we're actually going to tell applications via the aux vector. | |
| 1808 */ | |
| 1809 uint_t | |
| 1810 cpuid_pass4(cpu_t *cpu) | |
| 1811 { | |
| 1812 struct cpuid_info *cpi; | |
| 1813 uint_t hwcap_flags = 0; | |
| 1814 | |
| 1815 if (cpu == NULL) | |
| 1816 cpu = CPU; | |
| 1817 cpi = cpu->cpu_m.mcpu_cpi; | |
| 1818 | |
| 1819 ASSERT(cpi->cpi_pass == 3); | |
| 1820 | |
| 1821 if (cpi->cpi_maxeax >= 1) { | |
| 1822 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; | |
| 1823 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; | |
| 1824 | |
| 1825 *edx = CPI_FEATURES_EDX(cpi); | |
| 1826 *ecx = CPI_FEATURES_ECX(cpi); | |
| 1827 | |
| 1828 /* | |
| 1829 * [these require explicit kernel support] | |
| 1830 */ | |
| 1831 if ((x86_feature & X86_SEP) == 0) | |
| 1832 *edx &= ~CPUID_INTC_EDX_SEP; | |
| 1833 | |
| 1834 if ((x86_feature & X86_SSE) == 0) | |
| 1835 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); | |
| 1836 if ((x86_feature & X86_SSE2) == 0) | |
| 1837 *edx &= ~CPUID_INTC_EDX_SSE2; | |
| 1838 | |
| 1839 if ((x86_feature & X86_HTT) == 0) | |
| 1840 *edx &= ~CPUID_INTC_EDX_HTT; | |
| 1841 | |
| 1842 if ((x86_feature & X86_SSE3) == 0) | |
| 1843 *ecx &= ~CPUID_INTC_ECX_SSE3; | |
| 1844 | |
| 1845 /* | |
| 1846 * [no explicit support required beyond x87 fp context] | |
| 1847 */ | |
| 1848 if (!fpu_exists) | |
| 1849 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); | |
| 1850 | |
| 1851 /* | |
| 1852 * Now map the supported feature vector to things that we | |
| 1853 * think userland will care about. | |
| 1854 */ | |
| 1855 if (*edx & CPUID_INTC_EDX_SEP) | |
| 1856 hwcap_flags |= AV_386_SEP; | |
| 1857 if (*edx & CPUID_INTC_EDX_SSE) | |
| 1858 hwcap_flags |= AV_386_FXSR | AV_386_SSE; | |
| 1859 if (*edx & CPUID_INTC_EDX_SSE2) | |
| 1860 hwcap_flags |= AV_386_SSE2; | |
| 1861 if (*ecx & CPUID_INTC_ECX_SSE3) | |
| 1862 hwcap_flags |= AV_386_SSE3; | |
| 1863 | |
| 1864 if (*edx & CPUID_INTC_EDX_FPU) | |
| 1865 hwcap_flags |= AV_386_FPU; | |
| 1866 if (*edx & CPUID_INTC_EDX_MMX) | |
| 1867 hwcap_flags |= AV_386_MMX; | |
| 1868 | |
| 1869 if (*edx & CPUID_INTC_EDX_TSC) | |
| 1870 hwcap_flags |= AV_386_TSC; | |
| 1871 if (*edx & CPUID_INTC_EDX_CX8) | |
| 1872 hwcap_flags |= AV_386_CX8; | |
| 1873 if (*edx & CPUID_INTC_EDX_CMOV) | |
| 1874 hwcap_flags |= AV_386_CMOV; | |
| 1875 if (*ecx & CPUID_INTC_ECX_MON) | |
| 1876 hwcap_flags |= AV_386_MON; | |
| 1877 if (*ecx & CPUID_INTC_ECX_CX16) | |
| 1878 hwcap_flags |= AV_386_CX16; | |
| 1879 } | |
| 1880 | |
| 1228 | 1881 if (x86_feature & X86_HTT) |
| 0 | 1882 hwcap_flags |= AV_386_PAUSE; |
| 1883 | |
| 1884 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 1885 goto pass4_done; | |
| 1886 | |
| 1887 switch (cpi->cpi_vendor) { | |
| 1228 | 1888 struct cpuid_regs cp; |
| 3446 | 1889 uint32_t *edx, *ecx; |
| 0 | 1890 |
| 3446 | 1891 case X86_VENDOR_Intel: |
| 1892 /* | |
| 1893 * Seems like Intel duplicated what we necessary | |
| 1894 * here to make the initial crop of 64-bit OS's work. | |
| 1895 * Hopefully, those are the only "extended" bits | |
| 1896 * they'll add. | |
| 1897 */ | |
| 1898 /*FALLTHROUGH*/ | |
| 1899 | |
| 0 | 1900 case X86_VENDOR_AMD: |
| 1901 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; | |
| 3446 | 1902 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; |
| 0 | 1903 |
| 1904 *edx = CPI_FEATURES_XTD_EDX(cpi); | |
| 3446 | 1905 *ecx = CPI_FEATURES_XTD_ECX(cpi); |
| 1906 | |
| 1907 /* | |
| 1908 * [these features require explicit kernel support] | |
| 1909 */ | |
| 1910 switch (cpi->cpi_vendor) { | |
| 1911 case X86_VENDOR_Intel: | |
| 1912 break; | |
| 1913 | |
| 1914 case X86_VENDOR_AMD: | |
| 1915 if ((x86_feature & X86_TSCP) == 0) | |
| 1916 *edx &= ~CPUID_AMD_EDX_TSCP; | |
| 1917 break; | |
| 1918 | |
| 1919 default: | |
| 1920 break; | |
| 1921 } | |
| 0 | 1922 |
| 1923 /* | |
| 1924 * [no explicit support required beyond | |
| 1925 * x87 fp context and exception handlers] | |
| 1926 */ | |
| 1927 if (!fpu_exists) | |
| 1928 *edx &= ~(CPUID_AMD_EDX_MMXamd | | |
| 1929 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); | |
| 1930 | |
| 1931 if ((x86_feature & X86_NX) == 0) | |
| 1932 *edx &= ~CPUID_AMD_EDX_NX; | |
| 3446 | 1933 #if !defined(__amd64) |
| 0 | 1934 *edx &= ~CPUID_AMD_EDX_LM; |
| 1935 #endif | |
| 1936 /* | |
| 1937 * Now map the supported feature vector to | |
| 1938 * things that we think userland will care about. | |
| 1939 */ | |
| 3446 | 1940 #if defined(__amd64) |
| 0 | 1941 if (*edx & CPUID_AMD_EDX_SYSC) |
| 1942 hwcap_flags |= AV_386_AMD_SYSC; | |
| 3446 | 1943 #endif |
| 0 | 1944 if (*edx & CPUID_AMD_EDX_MMXamd) |
| 1945 hwcap_flags |= AV_386_AMD_MMX; | |
| 1946 if (*edx & CPUID_AMD_EDX_3DNow) | |
| 1947 hwcap_flags |= AV_386_AMD_3DNow; | |
| 1948 if (*edx & CPUID_AMD_EDX_3DNowx) | |
| 1949 hwcap_flags |= AV_386_AMD_3DNowx; | |
| 3446 | 1950 |
| 1951 switch (cpi->cpi_vendor) { | |
| 1952 case X86_VENDOR_AMD: | |
| 1953 if (*edx & CPUID_AMD_EDX_TSCP) | |
| 1954 hwcap_flags |= AV_386_TSCP; | |
| 1955 if (*ecx & CPUID_AMD_ECX_AHF64) | |
| 1956 hwcap_flags |= AV_386_AHF; | |
| 1957 break; | |
| 1958 | |
| 1959 case X86_VENDOR_Intel: | |
| 1960 /* | |
| 1961 * Aarrgh. | |
| 1962 * Intel uses a different bit in the same word. | |
| 1963 */ | |
| 1964 if (*ecx & CPUID_INTC_ECX_AHF64) | |
| 1965 hwcap_flags |= AV_386_AHF; | |
| 1966 break; | |
| 1967 | |
| 1968 default: | |
| 1969 break; | |
| 1970 } | |
| 0 | 1971 break; |
| 1972 | |
| 1973 case X86_VENDOR_TM: | |
| 1228 | 1974 cp.cp_eax = 0x80860001; |
| 1975 (void) __cpuid_insn(&cp); | |
| 1976 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; | |
| 0 | 1977 break; |
| 1978 | |
| 1979 default: | |
| 1980 break; | |
| 1981 } | |
| 1982 | |
| 1983 pass4_done: | |
| 1984 cpi->cpi_pass = 4; | |
| 1985 return (hwcap_flags); | |
| 1986 } | |
| 1987 | |
| 1988 | |
| 1989 /* | |
| 1990 * Simulate the cpuid instruction using the data we previously | |
| 1991 * captured about this CPU. We try our best to return the truth | |
| 1992 * about the hardware, independently of kernel support. | |
| 1993 */ | |
| 1994 uint32_t | |
| 1228 | 1995 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) |
| 0 | 1996 { |
| 1997 struct cpuid_info *cpi; | |
| 1228 | 1998 struct cpuid_regs *xcp; |
| 0 | 1999 |
| 2000 if (cpu == NULL) | |
| 2001 cpu = CPU; | |
| 2002 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2003 | |
| 2004 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2005 | |
| 2006 /* | |
| 2007 * CPUID data is cached in two separate places: cpi_std for standard | |
| 2008 * CPUID functions, and cpi_extd for extended CPUID functions. | |
| 2009 */ | |
| 1228 | 2010 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) |
| 2011 xcp = &cpi->cpi_std[cp->cp_eax]; | |
| 2012 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && | |
| 2013 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) | |
| 2014 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; | |
| 0 | 2015 else |
| 2016 /* | |
| 2017 * The caller is asking for data from an input parameter which | |
| 2018 * the kernel has not cached. In this case we go fetch from | |
| 2019 * the hardware and return the data directly to the user. | |
| 2020 */ | |
| 1228 | 2021 return (__cpuid_insn(cp)); |
| 2022 | |
| 2023 cp->cp_eax = xcp->cp_eax; | |
| 2024 cp->cp_ebx = xcp->cp_ebx; | |
| 2025 cp->cp_ecx = xcp->cp_ecx; | |
| 2026 cp->cp_edx = xcp->cp_edx; | |
| 0 | 2027 return (cp->cp_eax); |
| 2028 } | |
| 2029 | |
| 2030 int | |
| 2031 cpuid_checkpass(cpu_t *cpu, int pass) | |
| 2032 { | |
| 2033 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && | |
| 2034 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); | |
| 2035 } | |
| 2036 | |
| 2037 int | |
| 2038 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) | |
| 2039 { | |
| 2040 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2041 | |
| 2042 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); | |
| 2043 } | |
| 2044 | |
| 2045 int | |
| 1228 | 2046 cpuid_is_cmt(cpu_t *cpu) |
| 0 | 2047 { |
| 2048 if (cpu == NULL) | |
| 2049 cpu = CPU; | |
| 2050 | |
| 2051 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2052 | |
| 2053 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); | |
| 2054 } | |
| 2055 | |
| 2056 /* | |
| 2057 * AMD and Intel both implement the 64-bit variant of the syscall | |
| 2058 * instruction (syscallq), so if there's -any- support for syscall, | |
| 2059 * cpuid currently says "yes, we support this". | |
| 2060 * | |
| 2061 * However, Intel decided to -not- implement the 32-bit variant of the | |
| 2062 * syscall instruction, so we provide a predicate to allow our caller | |
| 2063 * to test that subtlety here. | |
| 2064 */ | |
| 2065 /*ARGSUSED*/ | |
| 2066 int | |
| 2067 cpuid_syscall32_insn(cpu_t *cpu) | |
| 2068 { | |
| 2069 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); | |
| 2070 | |
| 3446 | 2071 if (cpu == NULL) |
| 2072 cpu = CPU; | |
| 2073 | |
| 2074 /*CSTYLED*/ | |
| 2075 { | |
| 2076 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2077 | |
| 2078 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
| 2079 cpi->cpi_xmaxeax >= 0x80000001 && | |
| 2080 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) | |
| 2081 return (1); | |
| 2082 } | |
| 0 | 2083 return (0); |
| 2084 } | |
| 2085 | |
| 2086 int | |
| 2087 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) | |
| 2088 { | |
| 2089 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2090 | |
| 2091 static const char fmt[] = | |
|
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2092 "x86 (%s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2093 static const char fmt_ht[] = |
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2094 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2095 |
| 2096 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2097 | |
| 1228 | 2098 if (cpuid_is_cmt(cpu)) |
| 0 | 2099 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, |
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2100 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
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2101 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2102 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2103 return (snprintf(s, n, fmt, | |
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2104 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
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2105 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2106 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2107 } | |
| 2108 | |
| 2109 const char * | |
| 2110 cpuid_getvendorstr(cpu_t *cpu) | |
| 2111 { | |
| 2112 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2113 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); | |
| 2114 } | |
| 2115 | |
| 2116 uint_t | |
| 2117 cpuid_getvendor(cpu_t *cpu) | |
| 2118 { | |
| 2119 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2120 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); | |
| 2121 } | |
| 2122 | |
| 2123 uint_t | |
| 2124 cpuid_getfamily(cpu_t *cpu) | |
| 2125 { | |
| 2126 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2127 return (cpu->cpu_m.mcpu_cpi->cpi_family); | |
| 2128 } | |
| 2129 | |
| 2130 uint_t | |
| 2131 cpuid_getmodel(cpu_t *cpu) | |
| 2132 { | |
| 2133 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2134 return (cpu->cpu_m.mcpu_cpi->cpi_model); | |
| 2135 } | |
| 2136 | |
| 2137 uint_t | |
| 2138 cpuid_get_ncpu_per_chip(cpu_t *cpu) | |
| 2139 { | |
| 2140 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2141 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); | |
| 2142 } | |
| 2143 | |
| 2144 uint_t | |
| 1228 | 2145 cpuid_get_ncore_per_chip(cpu_t *cpu) |
| 2146 { | |
| 2147 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2148 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); | |
| 2149 } | |
| 2150 | |
| 2151 uint_t | |
| 4606 | 2152 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) |
| 2153 { | |
| 2154 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2155 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); | |
| 2156 } | |
| 2157 | |
| 2158 id_t | |
| 2159 cpuid_get_last_lvl_cacheid(cpu_t *cpu) | |
| 2160 { | |
| 2161 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2162 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); | |
| 2163 } | |
| 2164 | |
| 2165 uint_t | |
| 0 | 2166 cpuid_getstep(cpu_t *cpu) |
| 2167 { | |
| 2168 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2169 return (cpu->cpu_m.mcpu_cpi->cpi_step); | |
| 2170 } | |
| 2171 | |
| 4581 | 2172 uint_t |
| 2173 cpuid_getsig(struct cpu *cpu) | |
| 2174 { | |
| 2175 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2176 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); | |
| 2177 } | |
| 2178 | |
|
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2179 uint32_t |
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2180 cpuid_getchiprev(struct cpu *cpu) |
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2181 { |
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2182 ASSERT(cpuid_checkpass(cpu, 1)); |
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2183 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); |
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2184 } |
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2185 |
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2186 const char * |
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2187 cpuid_getchiprevstr(struct cpu *cpu) |
|
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|
2188 { |
|
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|
2189 ASSERT(cpuid_checkpass(cpu, 1)); |
|
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|
2190 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); |
|
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PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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|
2191 } |
|
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|
2192 |
|
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|
2193 uint32_t |
|
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|
2194 cpuid_getsockettype(struct cpu *cpu) |
|
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PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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|
2195 { |
|
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|
2196 ASSERT(cpuid_checkpass(cpu, 1)); |
|
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|
2197 return (cpu->cpu_m.mcpu_cpi->cpi_socket); |
|
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|
2198 } |
|
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|
2199 |
| 3434 | 2200 int |
| 2201 cpuid_get_chipid(cpu_t *cpu) | |
| 0 | 2202 { |
| 2203 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2204 | |
| 1228 | 2205 if (cpuid_is_cmt(cpu)) |
| 0 | 2206 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); |
| 2207 return (cpu->cpu_id); | |
| 2208 } | |
| 2209 | |
| 1228 | 2210 id_t |
| 3434 | 2211 cpuid_get_coreid(cpu_t *cpu) |
| 1228 | 2212 { |
| 2213 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2214 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); | |
| 2215 } | |
| 2216 | |
| 0 | 2217 int |
| 3434 | 2218 cpuid_get_clogid(cpu_t *cpu) |
| 0 | 2219 { |
| 2220 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2221 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); | |
| 2222 } | |
| 2223 | |
| 2224 void | |
| 2225 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) | |
| 2226 { | |
| 2227 struct cpuid_info *cpi; | |
| 2228 | |
| 2229 if (cpu == NULL) | |
| 2230 cpu = CPU; | |
| 2231 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2232 | |
| 2233 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2234 | |
| 2235 if (pabits) | |
| 2236 *pabits = cpi->cpi_pabits; | |
| 2237 if (vabits) | |
| 2238 *vabits = cpi->cpi_vabits; | |
| 2239 } | |
| 2240 | |
| 2241 /* | |
| 2242 * Returns the number of data TLB entries for a corresponding | |
| 2243 * pagesize. If it can't be computed, or isn't known, the | |
| 2244 * routine returns zero. If you ask about an architecturally | |
| 2245 * impossible pagesize, the routine will panic (so that the | |
| 2246 * hat implementor knows that things are inconsistent.) | |
| 2247 */ | |
| 2248 uint_t | |
| 2249 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) | |
| 2250 { | |
| 2251 struct cpuid_info *cpi; | |
| 2252 uint_t dtlb_nent = 0; | |
| 2253 | |
| 2254 if (cpu == NULL) | |
| 2255 cpu = CPU; | |
| 2256 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2257 | |
| 2258 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2259 | |
| 2260 /* | |
| 2261 * Check the L2 TLB info | |
| 2262 */ | |
| 2263 if (cpi->cpi_xmaxeax >= 0x80000006) { | |
| 1228 | 2264 struct cpuid_regs *cp = &cpi->cpi_extd[6]; |
| 0 | 2265 |
| 2266 switch (pagesize) { | |
| 2267 | |
| 2268 case 4 * 1024: | |
| 2269 /* | |
| 2270 * All zero in the top 16 bits of the register | |
| 2271 * indicates a unified TLB. Size is in low 16 bits. | |
| 2272 */ | |
| 2273 if ((cp->cp_ebx & 0xffff0000) == 0) | |
| 2274 dtlb_nent = cp->cp_ebx & 0x0000ffff; | |
| 2275 else | |
| 2276 dtlb_nent = BITX(cp->cp_ebx, 27, 16); | |
| 2277 break; | |
| 2278 | |
| 2279 case 2 * 1024 * 1024: | |
| 2280 if ((cp->cp_eax & 0xffff0000) == 0) | |
| 2281 dtlb_nent = cp->cp_eax & 0x0000ffff; | |
| 2282 else | |
| 2283 dtlb_nent = BITX(cp->cp_eax, 27, 16); | |
| 2284 break; | |
| 2285 | |
| 2286 default: | |
| 2287 panic("unknown L2 pagesize"); | |
| 2288 /*NOTREACHED*/ | |
| 2289 } | |
| 2290 } | |
| 2291 | |
| 2292 if (dtlb_nent != 0) | |
| 2293 return (dtlb_nent); | |
| 2294 | |
| 2295 /* | |
| 2296 * No L2 TLB support for this size, try L1. | |
| 2297 */ | |
| 2298 if (cpi->cpi_xmaxeax >= 0x80000005) { | |
| 1228 | 2299 struct cpuid_regs *cp = &cpi->cpi_extd[5]; |
| 0 | 2300 |
| 2301 switch (pagesize) { | |
| 2302 case 4 * 1024: | |
| 2303 dtlb_nent = BITX(cp->cp_ebx, 23, 16); | |
| 2304 break; | |
| 2305 case 2 * 1024 * 1024: | |
| 2306 dtlb_nent = BITX(cp->cp_eax, 23, 16); | |
| 2307 break; | |
| 2308 default: | |
| 2309 panic("unknown L1 d-TLB pagesize"); | |
| 2310 /*NOTREACHED*/ | |
| 2311 } | |
| 2312 } | |
| 2313 | |
| 2314 return (dtlb_nent); | |
| 2315 } | |
| 2316 | |
| 2317 /* | |
| 2318 * Return 0 if the erratum is not present or not applicable, positive | |
| 2319 * if it is, and negative if the status of the erratum is unknown. | |
| 2320 * | |
| 2321 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) | |
|
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|
2322 * Processors" #25759, Rev 3.57, August 2005 |
| 0 | 2323 */ |
| 2324 int | |
| 2325 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) | |
| 2326 { | |
| 2327 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1228 | 2328 uint_t eax; |
| 0 | 2329 |
|
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6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
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|
2330 /* |
|
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6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
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|
2331 * Bail out if this CPU isn't an AMD CPU, or if it's |
|
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6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
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|
2332 * a legacy (32-bit) AMD CPU. |
|
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|
2333 */ |
|
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|
2334 if (cpi->cpi_vendor != X86_VENDOR_AMD || |
|
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|
2335 cpi->cpi_family == 4 || cpi->cpi_family == 5 || |
|
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|
2336 cpi->cpi_family == 6) |
|
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|
2337 |
| 0 | 2338 return (0); |
| 2339 | |
| 2340 eax = cpi->cpi_std[1].cp_eax; | |
| 2341 | |
| 2342 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) | |
| 2343 #define SH_B3(eax) (eax == 0xf51) | |
|
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|
2344 #define B(eax) (SH_B0(eax) || SH_B3(eax)) |
| 0 | 2345 |
| 2346 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) | |
| 2347 | |
| 2348 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) | |
| 2349 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) | |
| 2350 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) | |
|
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|
2351 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) |
| 0 | 2352 |
| 2353 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) | |
| 2354 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) | |
| 2355 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) | |
|
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|
2356 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) |
| 0 | 2357 |
| 2358 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) | |
| 2359 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ | |
| 2360 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) | |
| 2361 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) | |
| 2362 #define BH_E4(eax) (eax == 0x20fb1) | |
| 2363 #define SH_E5(eax) (eax == 0x20f42) | |
| 2364 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) | |
| 2365 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) | |
|
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|
2366 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ |
|
eb879d43ab47
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|
2367 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ |
|
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|
2368 DH_E6(eax) || JH_E6(eax)) |
| 0 | 2369 |
| 2370 switch (erratum) { | |
| 2371 case 1: | |
|
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|
2372 return (cpi->cpi_family < 0x10); |
| 0 | 2373 case 51: /* what does the asterisk mean? */ |
| 2374 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2375 case 52: | |
| 2376 return (B(eax)); | |
| 2377 case 57: | |
|
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|
2378 return (cpi->cpi_family <= 0x10); |
| 0 | 2379 case 58: |
| 2380 return (B(eax)); | |
| 2381 case 60: | |
|
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|
2382 return (cpi->cpi_family <= 0x10); |
| 0 | 2383 case 61: |
| 2384 case 62: | |
| 2385 case 63: | |
| 2386 case 64: | |
| 2387 case 65: | |
| 2388 case 66: | |
| 2389 case 68: | |
| 2390 case 69: | |
| 2391 case 70: | |
| 2392 case 71: | |
| 2393 return (B(eax)); | |
| 2394 case 72: | |
| 2395 return (SH_B0(eax)); | |
| 2396 case 74: | |
| 2397 return (B(eax)); | |
| 2398 case 75: | |
|
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|
2399 return (cpi->cpi_family < 0x10); |
| 0 | 2400 case 76: |
| 2401 return (B(eax)); | |
| 2402 case 77: | |
|
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|
2403 return (cpi->cpi_family <= 0x10); |
| 0 | 2404 case 78: |
| 2405 return (B(eax) || SH_C0(eax)); | |
| 2406 case 79: | |
| 2407 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2408 case 80: | |
| 2409 case 81: | |
| 2410 case 82: | |
| 2411 return (B(eax)); | |
| 2412 case 83: | |
| 2413 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2414 case 85: | |
|
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|
2415 return (cpi->cpi_family < 0x10); |
| 0 | 2416 case 86: |
| 2417 return (SH_C0(eax) || CG(eax)); | |
| 2418 case 88: | |
| 2419 #if !defined(__amd64) | |
| 2420 return (0); | |
| 2421 #else | |
| 2422 return (B(eax) || SH_C0(eax)); | |
| 2423 #endif | |
| 2424 case 89: | |
|
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|
2425 return (cpi->cpi_family < 0x10); |
| 0 | 2426 case 90: |
| 2427 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2428 case 91: | |
| 2429 case 92: | |
| 2430 return (B(eax) || SH_C0(eax)); | |
| 2431 case 93: | |
| 2432 return (SH_C0(eax)); | |
| 2433 case 94: | |
| 2434 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2435 case 95: | |
| 2436 #if !defined(__amd64) | |
| 2437 return (0); | |
| 2438 #else | |
| 2439 return (B(eax) || SH_C0(eax)); | |
| 2440 #endif | |
| 2441 case 96: | |
| 2442 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2443 case 97: | |
| 2444 case 98: | |
| 2445 return (SH_C0(eax) || CG(eax)); | |
| 2446 case 99: | |
| 2447 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2448 case 100: | |
| 2449 return (B(eax) || SH_C0(eax)); | |
| 2450 case 101: | |
| 2451 case 103: | |
| 2452 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2453 case 104: | |
| 2454 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2455 case 105: | |
| 2456 case 106: | |
| 2457 case 107: | |
| 2458 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2459 case 108: | |
| 2460 return (DH_CG(eax)); | |
| 2461 case 109: | |
| 2462 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2463 case 110: | |
| 2464 return (D0(eax) || EX(eax)); | |
| 2465 case 111: | |
| 2466 return (CG(eax)); | |
| 2467 case 112: | |
| 2468 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2469 case 113: | |
| 2470 return (eax == 0x20fc0); | |
| 2471 case 114: | |
| 2472 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 2473 case 115: | |
| 2474 return (SH_E0(eax) || JH_E1(eax)); | |
| 2475 case 116: | |
| 2476 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 2477 case 117: | |
| 2478 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2479 case 118: | |
| 2480 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || | |
| 2481 JH_E6(eax)); | |
| 2482 case 121: | |
| 2483 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2484 case 122: | |
|
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|
2485 return (cpi->cpi_family < 0x10); |
| 0 | 2486 case 123: |
| 2487 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); | |
|
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2488 case 131: |
|
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|
2489 return (cpi->cpi_family < 0x10); |
|
938
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diff
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|
2490 case 6336786: |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
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diff
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|
2491 /* |
|
2d438f28c673
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diff
changeset
|
2492 * Test for AdvPowerMgmtInfo.TscPStateInvariant |
|
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|
2493 * if this is a K8 family or newer processor |
|
938
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diff
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|
2494 */ |
|
2d438f28c673
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diff
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|
2495 if (CPI_FAMILY(cpi) == 0xf) { |
| 1228 | 2496 struct cpuid_regs regs; |
| 2497 regs.cp_eax = 0x80000007; | |
| 2498 (void) __cpuid_insn(®s); | |
| 2499 return (!(regs.cp_edx & 0x100)); | |
|
938
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|
2500 } |
|
2d438f28c673
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diff
changeset
|
2501 return (0); |
|
1582
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|
2502 case 6323525: |
|
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|
2503 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | |
|
eb879d43ab47
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|
2504 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); |
|
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|
2505 |
| 0 | 2506 default: |
| 2507 return (-1); | |
| 2508 } | |
| 2509 } | |
| 2510 | |
| 2511 static const char assoc_str[] = "associativity"; | |
| 2512 static const char line_str[] = "line-size"; | |
| 2513 static const char size_str[] = "size"; | |
| 2514 | |
| 2515 static void | |
| 2516 add_cache_prop(dev_info_t *devi, const char *label, const char *type, | |
| 2517 uint32_t val) | |
| 2518 { | |
| 2519 char buf[128]; | |
| 2520 | |
| 2521 /* | |
| 2522 * ndi_prop_update_int() is used because it is desirable for | |
| 2523 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. | |
| 2524 */ | |
| 2525 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) | |
| 2526 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); | |
| 2527 } | |
| 2528 | |
| 2529 /* | |
| 2530 * Intel-style cache/tlb description | |
| 2531 * | |
| 2532 * Standard cpuid level 2 gives a randomly ordered | |
| 2533 * selection of tags that index into a table that describes | |
| 2534 * cache and tlb properties. | |
| 2535 */ | |
| 2536 | |
| 2537 static const char l1_icache_str[] = "l1-icache"; | |
| 2538 static const char l1_dcache_str[] = "l1-dcache"; | |
| 2539 static const char l2_cache_str[] = "l2-cache"; | |
| 3446 | 2540 static const char l3_cache_str[] = "l3-cache"; |
| 0 | 2541 static const char itlb4k_str[] = "itlb-4K"; |
| 2542 static const char dtlb4k_str[] = "dtlb-4K"; | |
| 2543 static const char itlb4M_str[] = "itlb-4M"; | |
| 2544 static const char dtlb4M_str[] = "dtlb-4M"; | |
| 2545 static const char itlb424_str[] = "itlb-4K-2M-4M"; | |
| 2546 static const char dtlb44_str[] = "dtlb-4K-4M"; | |
| 2547 static const char sl1_dcache_str[] = "sectored-l1-dcache"; | |
| 2548 static const char sl2_cache_str[] = "sectored-l2-cache"; | |
| 2549 static const char itrace_str[] = "itrace-cache"; | |
| 2550 static const char sl3_cache_str[] = "sectored-l3-cache"; | |
| 2551 | |
| 2552 static const struct cachetab { | |
| 2553 uint8_t ct_code; | |
| 2554 uint8_t ct_assoc; | |
| 2555 uint16_t ct_line_size; | |
| 2556 size_t ct_size; | |
| 2557 const char *ct_label; | |
| 2558 } intel_ctab[] = { | |
| 2559 /* maintain descending order! */ | |
| 3446 | 2560 { 0xb4, 4, 0, 256, dtlb4k_str }, |
| 0 | 2561 { 0xb3, 4, 0, 128, dtlb4k_str }, |
| 2562 { 0xb0, 4, 0, 128, itlb4k_str }, | |
| 2563 { 0x87, 8, 64, 1024*1024, l2_cache_str}, | |
| 2564 { 0x86, 4, 64, 512*1024, l2_cache_str}, | |
| 2565 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, | |
| 2566 { 0x84, 8, 32, 1024*1024, l2_cache_str}, | |
| 2567 { 0x83, 8, 32, 512*1024, l2_cache_str}, | |
| 2568 { 0x82, 8, 32, 256*1024, l2_cache_str}, | |
| 2569 { 0x7f, 2, 64, 512*1024, l2_cache_str}, | |
| 2570 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, | |
| 2571 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, | |
| 2572 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, | |
| 2573 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, | |
| 2574 { 0x79, 8, 64, 128*1024, sl2_cache_str}, | |
| 2575 { 0x78, 8, 64, 1024*1024, l2_cache_str}, | |
| 3446 | 2576 { 0x73, 8, 0, 64*1024, itrace_str}, |
| 0 | 2577 { 0x72, 8, 0, 32*1024, itrace_str}, |
| 2578 { 0x71, 8, 0, 16*1024, itrace_str}, | |
| 2579 { 0x70, 8, 0, 12*1024, itrace_str}, | |
| 2580 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, | |
| 2581 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, | |
| 2582 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, | |
| 2583 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, | |
| 2584 { 0x5d, 0, 0, 256, dtlb44_str}, | |
| 2585 { 0x5c, 0, 0, 128, dtlb44_str}, | |
| 2586 { 0x5b, 0, 0, 64, dtlb44_str}, | |
| 2587 { 0x52, 0, 0, 256, itlb424_str}, | |
| 2588 { 0x51, 0, 0, 128, itlb424_str}, | |
| 2589 { 0x50, 0, 0, 64, itlb424_str}, | |
| 3446 | 2590 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, |
| 2591 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, | |
| 2592 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, | |
| 2593 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, | |
| 2594 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, | |
| 2595 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, | |
| 2596 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, | |
| 0 | 2597 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, |
| 2598 { 0x44, 4, 32, 1024*1024, l2_cache_str}, | |
| 2599 { 0x43, 4, 32, 512*1024, l2_cache_str}, | |
| 2600 { 0x42, 4, 32, 256*1024, l2_cache_str}, | |
| 2601 { 0x41, 4, 32, 128*1024, l2_cache_str}, | |
| 3446 | 2602 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, |
| 2603 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, | |
| 0 | 2604 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, |
| 2605 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, | |
| 3446 | 2606 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, |
| 0 | 2607 { 0x39, 4, 64, 128*1024, sl2_cache_str}, |
| 2608 { 0x30, 8, 64, 32*1024, l1_icache_str}, | |
| 2609 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, | |
| 2610 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, | |
| 2611 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, | |
| 2612 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, | |
| 2613 { 0x22, 4, 64, 512*1024, sl3_cache_str}, | |
| 2614 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, | |
| 3446 | 2615 { 0x0b, 4, 0, 4, itlb4M_str}, |
| 0 | 2616 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, |
| 2617 { 0x08, 4, 32, 16*1024, l1_icache_str}, | |
| 2618 { 0x06, 4, 32, 8*1024, l1_icache_str}, | |
| 2619 { 0x04, 4, 0, 8, dtlb4M_str}, | |
| 2620 { 0x03, 4, 0, 64, dtlb4k_str}, | |
| 2621 { 0x02, 4, 0, 2, itlb4M_str}, | |
| 2622 { 0x01, 4, 0, 32, itlb4k_str}, | |
| 2623 { 0 } | |
| 2624 }; | |
| 2625 | |
| 2626 static const struct cachetab cyrix_ctab[] = { | |
| 2627 { 0x70, 4, 0, 32, "tlb-4K" }, | |
| 2628 { 0x80, 4, 16, 16*1024, "l1-cache" }, | |
| 2629 { 0 } | |
| 2630 }; | |
| 2631 | |
| 2632 /* | |
| 2633 * Search a cache table for a matching entry | |
| 2634 */ | |
| 2635 static const struct cachetab * | |
| 2636 find_cacheent(const struct cachetab *ct, uint_t code) | |
| 2637 { | |
| 2638 if (code != 0) { | |
| 2639 for (; ct->ct_code != 0; ct++) | |
| 2640 if (ct->ct_code <= code) | |
| 2641 break; | |
| 2642 if (ct->ct_code == code) | |
| 2643 return (ct); | |
| 2644 } | |
| 2645 return (NULL); | |
| 2646 } | |
| 2647 | |
| 2648 /* | |
| 2649 * Walk the cacheinfo descriptor, applying 'func' to every valid element | |
| 2650 * The walk is terminated if the walker returns non-zero. | |
| 2651 */ | |
| 2652 static void | |
| 2653 intel_walk_cacheinfo(struct cpuid_info *cpi, | |
| 2654 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 2655 { | |
| 2656 const struct cachetab *ct; | |
| 2657 uint8_t *dp; | |
| 2658 int i; | |
| 2659 | |
| 2660 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 2661 return; | |
| 2662 for (i = 0; i < cpi->cpi_ncache; i++, dp++) | |
| 2663 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { | |
| 2664 if (func(arg, ct) != 0) | |
| 2665 break; | |
| 2666 } | |
| 2667 } | |
| 2668 | |
| 2669 /* | |
| 2670 * (Like the Intel one, except for Cyrix CPUs) | |
| 2671 */ | |
| 2672 static void | |
| 2673 cyrix_walk_cacheinfo(struct cpuid_info *cpi, | |
| 2674 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 2675 { | |
| 2676 const struct cachetab *ct; | |
| 2677 uint8_t *dp; | |
| 2678 int i; | |
| 2679 | |
| 2680 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 2681 return; | |
| 2682 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { | |
| 2683 /* | |
| 2684 * Search Cyrix-specific descriptor table first .. | |
| 2685 */ | |
| 2686 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { | |
| 2687 if (func(arg, ct) != 0) | |
| 2688 break; | |
| 2689 continue; | |
| 2690 } | |
| 2691 /* | |
| 2692 * .. else fall back to the Intel one | |
| 2693 */ | |
| 2694 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { | |
| 2695 if (func(arg, ct) != 0) | |
| 2696 break; | |
| 2697 continue; | |
| 2698 } | |
| 2699 } | |
| 2700 } | |
| 2701 | |
| 2702 /* | |
| 2703 * A cacheinfo walker that adds associativity, line-size, and size properties | |
| 2704 * to the devinfo node it is passed as an argument. | |
| 2705 */ | |
| 2706 static int | |
| 2707 add_cacheent_props(void *arg, const struct cachetab *ct) | |
| 2708 { | |
| 2709 dev_info_t *devi = arg; | |
| 2710 | |
| 2711 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); | |
| 2712 if (ct->ct_line_size != 0) | |
| 2713 add_cache_prop(devi, ct->ct_label, line_str, | |
| 2714 ct->ct_line_size); | |
| 2715 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); | |
| 2716 return (0); | |
| 2717 } | |
| 2718 | |
| 2719 static const char fully_assoc[] = "fully-associative?"; | |
| 2720 | |
| 2721 /* | |
| 2722 * AMD style cache/tlb description | |
| 2723 * | |
| 2724 * Extended functions 5 and 6 directly describe properties of | |
| 2725 * tlbs and various cache levels. | |
| 2726 */ | |
| 2727 static void | |
| 2728 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 2729 { | |
| 2730 switch (assoc) { | |
| 2731 case 0: /* reserved; ignore */ | |
| 2732 break; | |
| 2733 default: | |
| 2734 add_cache_prop(devi, label, assoc_str, assoc); | |
| 2735 break; | |
| 2736 case 0xff: | |
| 2737 add_cache_prop(devi, label, fully_assoc, 1); | |
| 2738 break; | |
| 2739 } | |
| 2740 } | |
| 2741 | |
| 2742 static void | |
| 2743 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 2744 { | |
| 2745 if (size == 0) | |
| 2746 return; | |
| 2747 add_cache_prop(devi, label, size_str, size); | |
| 2748 add_amd_assoc(devi, label, assoc); | |
| 2749 } | |
| 2750 | |
| 2751 static void | |
| 2752 add_amd_cache(dev_info_t *devi, const char *label, | |
| 2753 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 2754 { | |
| 2755 if (size == 0 || line_size == 0) | |
| 2756 return; | |
| 2757 add_amd_assoc(devi, label, assoc); | |
| 2758 /* | |
| 2759 * Most AMD parts have a sectored cache. Multiple cache lines are | |
| 2760 * associated with each tag. A sector consists of all cache lines | |
| 2761 * associated with a tag. For example, the AMD K6-III has a sector | |
| 2762 * size of 2 cache lines per tag. | |
| 2763 */ | |
| 2764 if (lines_per_tag != 0) | |
| 2765 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 2766 add_cache_prop(devi, label, line_str, line_size); | |
| 2767 add_cache_prop(devi, label, size_str, size * 1024); | |
| 2768 } | |
| 2769 | |
| 2770 static void | |
| 2771 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 2772 { | |
| 2773 switch (assoc) { | |
| 2774 case 0: /* off */ | |
| 2775 break; | |
| 2776 case 1: | |
| 2777 case 2: | |
| 2778 case 4: | |
| 2779 add_cache_prop(devi, label, assoc_str, assoc); | |
| 2780 break; | |
| 2781 case 6: | |
| 2782 add_cache_prop(devi, label, assoc_str, 8); | |
| 2783 break; | |
| 2784 case 8: | |
| 2785 add_cache_prop(devi, label, assoc_str, 16); | |
| 2786 break; | |
| 2787 case 0xf: | |
| 2788 add_cache_prop(devi, label, fully_assoc, 1); | |
| 2789 break; | |
| 2790 default: /* reserved; ignore */ | |
| 2791 break; | |
| 2792 } | |
| 2793 } | |
| 2794 | |
| 2795 static void | |
| 2796 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 2797 { | |
| 2798 if (size == 0 || assoc == 0) | |
| 2799 return; | |
| 2800 add_amd_l2_assoc(devi, label, assoc); | |
| 2801 add_cache_prop(devi, label, size_str, size); | |
| 2802 } | |
| 2803 | |
| 2804 static void | |
| 2805 add_amd_l2_cache(dev_info_t *devi, const char *label, | |
| 2806 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 2807 { | |
| 2808 if (size == 0 || assoc == 0 || line_size == 0) | |
| 2809 return; | |
| 2810 add_amd_l2_assoc(devi, label, assoc); | |
| 2811 if (lines_per_tag != 0) | |
| 2812 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 2813 add_cache_prop(devi, label, line_str, line_size); | |
| 2814 add_cache_prop(devi, label, size_str, size * 1024); | |
| 2815 } | |
| 2816 | |
| 2817 static void | |
| 2818 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) | |
| 2819 { | |
| 1228 | 2820 struct cpuid_regs *cp; |
| 0 | 2821 |
| 2822 if (cpi->cpi_xmaxeax < 0x80000005) | |
| 2823 return; | |
| 2824 cp = &cpi->cpi_extd[5]; | |
| 2825 | |
| 2826 /* | |
| 2827 * 4M/2M L1 TLB configuration | |
| 2828 * | |
| 2829 * We report the size for 2M pages because AMD uses two | |
| 2830 * TLB entries for one 4M page. | |
| 2831 */ | |
| 2832 add_amd_tlb(devi, "dtlb-2M", | |
| 2833 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); | |
| 2834 add_amd_tlb(devi, "itlb-2M", | |
| 2835 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); | |
| 2836 | |
| 2837 /* | |
| 2838 * 4K L1 TLB configuration | |
| 2839 */ | |
| 2840 | |
| 2841 switch (cpi->cpi_vendor) { | |
| 2842 uint_t nentries; | |
| 2843 case X86_VENDOR_TM: | |
| 2844 if (cpi->cpi_family >= 5) { | |
| 2845 /* | |
| 2846 * Crusoe processors have 256 TLB entries, but | |
| 2847 * cpuid data format constrains them to only | |
| 2848 * reporting 255 of them. | |
| 2849 */ | |
| 2850 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) | |
| 2851 nentries = 256; | |
| 2852 /* | |
| 2853 * Crusoe processors also have a unified TLB | |
| 2854 */ | |
| 2855 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), | |
| 2856 nentries); | |
| 2857 break; | |
| 2858 } | |
| 2859 /*FALLTHROUGH*/ | |
| 2860 default: | |
| 2861 add_amd_tlb(devi, itlb4k_str, | |
| 2862 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); | |
| 2863 add_amd_tlb(devi, dtlb4k_str, | |
| 2864 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); | |
| 2865 break; | |
| 2866 } | |
| 2867 | |
| 2868 /* | |
| 2869 * data L1 cache configuration | |
| 2870 */ | |
| 2871 | |
| 2872 add_amd_cache(devi, l1_dcache_str, | |
| 2873 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), | |
| 2874 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 2875 | |
| 2876 /* | |
| 2877 * code L1 cache configuration | |
| 2878 */ | |
| 2879 | |
| 2880 add_amd_cache(devi, l1_icache_str, | |
| 2881 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), | |
| 2882 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); | |
| 2883 | |
| 2884 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 2885 return; | |
| 2886 cp = &cpi->cpi_extd[6]; | |
| 2887 | |
| 2888 /* Check for a unified L2 TLB for large pages */ | |
| 2889 | |
| 2890 if (BITX(cp->cp_eax, 31, 16) == 0) | |
| 2891 add_amd_l2_tlb(devi, "l2-tlb-2M", | |
| 2892 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 2893 else { | |
| 2894 add_amd_l2_tlb(devi, "l2-dtlb-2M", | |
| 2895 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 2896 add_amd_l2_tlb(devi, "l2-itlb-2M", | |
| 2897 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 2898 } | |
| 2899 | |
| 2900 /* Check for a unified L2 TLB for 4K pages */ | |
| 2901 | |
| 2902 if (BITX(cp->cp_ebx, 31, 16) == 0) { | |
| 2903 add_amd_l2_tlb(devi, "l2-tlb-4K", | |
| 2904 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 2905 } else { | |
| 2906 add_amd_l2_tlb(devi, "l2-dtlb-4K", | |
| 2907 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 2908 add_amd_l2_tlb(devi, "l2-itlb-4K", | |
| 2909 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 2910 } | |
| 2911 | |
| 2912 add_amd_l2_cache(devi, l2_cache_str, | |
| 2913 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), | |
| 2914 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 2915 } | |
| 2916 | |
| 2917 /* | |
| 2918 * There are two basic ways that the x86 world describes it cache | |
| 2919 * and tlb architecture - Intel's way and AMD's way. | |
| 2920 * | |
| 2921 * Return which flavor of cache architecture we should use | |
| 2922 */ | |
| 2923 static int | |
| 2924 x86_which_cacheinfo(struct cpuid_info *cpi) | |
| 2925 { | |
| 2926 switch (cpi->cpi_vendor) { | |
| 2927 case X86_VENDOR_Intel: | |
| 2928 if (cpi->cpi_maxeax >= 2) | |
| 2929 return (X86_VENDOR_Intel); | |
| 2930 break; | |
| 2931 case X86_VENDOR_AMD: | |
| 2932 /* | |
| 2933 * The K5 model 1 was the first part from AMD that reported | |
| 2934 * cache sizes via extended cpuid functions. | |
| 2935 */ | |
| 2936 if (cpi->cpi_family > 5 || | |
| 2937 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 2938 return (X86_VENDOR_AMD); | |
| 2939 break; | |
| 2940 case X86_VENDOR_TM: | |
| 2941 if (cpi->cpi_family >= 5) | |
| 2942 return (X86_VENDOR_AMD); | |
| 2943 /*FALLTHROUGH*/ | |
| 2944 default: | |
| 2945 /* | |
| 2946 * If they have extended CPU data for 0x80000005 | |
| 2947 * then we assume they have AMD-format cache | |
| 2948 * information. | |
| 2949 * | |
| 2950 * If not, and the vendor happens to be Cyrix, | |
| 2951 * then try our-Cyrix specific handler. | |
| 2952 * | |
| 2953 * If we're not Cyrix, then assume we're using Intel's | |
| 2954 * table-driven format instead. | |
| 2955 */ | |
| 2956 if (cpi->cpi_xmaxeax >= 0x80000005) | |
| 2957 return (X86_VENDOR_AMD); | |
| 2958 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) | |
| 2959 return (X86_VENDOR_Cyrix); | |
| 2960 else if (cpi->cpi_maxeax >= 2) | |
| 2961 return (X86_VENDOR_Intel); | |
| 2962 break; | |
| 2963 } | |
| 2964 return (-1); | |
| 2965 } | |
| 2966 | |
| 2967 /* | |
| 2968 * create a node for the given cpu under the prom root node. | |
| 2969 * Also, create a cpu node in the device tree. | |
| 2970 */ | |
| 2971 static dev_info_t *cpu_nex_devi = NULL; | |
| 2972 static kmutex_t cpu_node_lock; | |
| 2973 | |
| 2974 /* | |
| 2975 * Called from post_startup() and mp_startup() | |
| 2976 */ | |
| 2977 void | |
| 2978 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) | |
| 2979 { | |
| 2980 dev_info_t *cpu_devi; | |
| 2981 int create; | |
| 2982 | |
| 2983 mutex_enter(&cpu_node_lock); | |
| 2984 | |
| 2985 /* | |
| 2986 * create a nexus node for all cpus identified as 'cpu_id' under | |
| 2987 * the root node. | |
| 2988 */ | |
| 2989 if (cpu_nex_devi == NULL) { | |
| 2990 if (ndi_devi_alloc(ddi_root_node(), "cpus", | |
| 789 | 2991 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { |
| 0 | 2992 mutex_exit(&cpu_node_lock); |
| 2993 return; | |
| 2994 } | |
| 2995 (void) ndi_devi_online(cpu_nex_devi, 0); | |
| 2996 } | |
| 2997 | |
| 2998 /* | |
| 2999 * create a child node for cpu identified as 'cpu_id' | |
| 3000 */ | |
| 3001 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, | |
|
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|
3002 cpu_id); |
| 0 | 3003 if (cpu_devi == NULL) { |
| 3004 mutex_exit(&cpu_node_lock); | |
| 3005 return; | |
| 3006 } | |
| 3007 | |
| 3008 /* device_type */ | |
| 3009 | |
| 3010 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 3011 "device_type", "cpu"); | |
| 3012 | |
| 3013 /* reg */ | |
| 3014 | |
| 3015 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3016 "reg", cpu_id); | |
| 3017 | |
| 3018 /* cpu-mhz, and clock-frequency */ | |
| 3019 | |
| 3020 if (cpu_freq > 0) { | |
| 3021 long long mul; | |
| 3022 | |
| 3023 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3024 "cpu-mhz", cpu_freq); | |
| 3025 | |
| 3026 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) | |
| 3027 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3028 "clock-frequency", (int)mul); | |
| 3029 } | |
| 3030 | |
| 3031 (void) ndi_devi_online(cpu_devi, 0); | |
| 3032 | |
| 3033 if ((x86_feature & X86_CPUID) == 0) { | |
| 3034 mutex_exit(&cpu_node_lock); | |
| 3035 return; | |
| 3036 } | |
| 3037 | |
| 3038 /* vendor-id */ | |
| 3039 | |
| 3040 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
|
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|
3041 "vendor-id", cpi->cpi_vendorstr); |
| 0 | 3042 |
| 3043 if (cpi->cpi_maxeax == 0) { | |
| 3044 mutex_exit(&cpu_node_lock); | |
| 3045 return; | |
| 3046 } | |
| 3047 | |
| 3048 /* | |
| 3049 * family, model, and step | |
| 3050 */ | |
| 3051 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
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3052 "family", CPI_FAMILY(cpi)); |
| 0 | 3053 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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3054 "cpu-model", CPI_MODEL(cpi)); |
| 0 | 3055 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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|
3056 "stepping-id", CPI_STEP(cpi)); |
| 0 | 3057 |
| 3058 /* type */ | |
| 3059 | |
| 3060 switch (cpi->cpi_vendor) { | |
| 3061 case X86_VENDOR_Intel: | |
| 3062 create = 1; | |
| 3063 break; | |
| 3064 default: | |
| 3065 create = 0; | |
| 3066 break; | |
| 3067 } | |
| 3068 if (create) | |
| 3069 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
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|
3070 "type", CPI_TYPE(cpi)); |
| 0 | 3071 |
| 3072 /* ext-family */ | |
| 3073 | |
| 3074 switch (cpi->cpi_vendor) { | |
| 3075 case X86_VENDOR_Intel: | |
| 3076 case X86_VENDOR_AMD: | |
| 3077 create = cpi->cpi_family >= 0xf; | |
| 3078 break; | |
| 3079 default: | |
| 3080 create = 0; | |
| 3081 break; | |
| 3082 } | |
| 3083 if (create) | |
| 3084 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3085 "ext-family", CPI_FAMILY_XTD(cpi)); | |
| 3086 | |
| 3087 /* ext-model */ | |
| 3088 | |
| 3089 switch (cpi->cpi_vendor) { | |
| 3090 case X86_VENDOR_Intel: | |
|
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|
3091 create = CPI_MODEL(cpi) == 0xf; |
|
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|
3092 break; |
| 0 | 3093 case X86_VENDOR_AMD: |
|
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|
3094 create = CPI_FAMILY(cpi) == 0xf; |
| 0 | 3095 break; |
| 3096 default: | |
| 3097 create = 0; | |
| 3098 break; | |
| 3099 } | |
| 3100 if (create) | |
| 3101 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
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3102 "ext-model", CPI_MODEL_XTD(cpi)); |
| 0 | 3103 |
| 3104 /* generation */ | |
| 3105 | |
| 3106 switch (cpi->cpi_vendor) { | |
| 3107 case X86_VENDOR_AMD: | |
| 3108 /* | |
| 3109 * AMD K5 model 1 was the first part to support this | |
| 3110 */ | |
| 3111 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 3112 break; | |
| 3113 default: | |
| 3114 create = 0; | |
| 3115 break; | |
| 3116 } | |
| 3117 if (create) | |
| 3118 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3119 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); | |
| 3120 | |
| 3121 /* brand-id */ | |
| 3122 | |
| 3123 switch (cpi->cpi_vendor) { | |
| 3124 case X86_VENDOR_Intel: | |
| 3125 /* | |
| 3126 * brand id first appeared on Pentium III Xeon model 8, | |
| 3127 * and Celeron model 8 processors and Opteron | |
| 3128 */ | |
| 3129 create = cpi->cpi_family > 6 || | |
| 3130 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); | |
| 3131 break; | |
| 3132 case X86_VENDOR_AMD: | |
| 3133 create = cpi->cpi_family >= 0xf; | |
| 3134 break; | |
| 3135 default: | |
| 3136 create = 0; | |
| 3137 break; | |
| 3138 } | |
| 3139 if (create && cpi->cpi_brandid != 0) { | |
| 3140 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3141 "brand-id", cpi->cpi_brandid); | |
| 3142 } | |
| 3143 | |
| 3144 /* chunks, and apic-id */ | |
| 3145 | |
| 3146 switch (cpi->cpi_vendor) { | |
| 3147 /* | |
| 3148 * first available on Pentium IV and Opteron (K8) | |
| 3149 */ | |
|
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3150 case X86_VENDOR_Intel: |
|
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3151 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
|
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3152 break; |
|
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|
3153 case X86_VENDOR_AMD: |
| 0 | 3154 create = cpi->cpi_family >= 0xf; |
| 3155 break; | |
| 3156 default: | |
| 3157 create = 0; | |
| 3158 break; | |
| 3159 } | |
| 3160 if (create) { | |
| 3161 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
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3162 "chunks", CPI_CHUNKS(cpi)); |
| 0 | 3163 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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|
3164 "apic-id", CPI_APIC_ID(cpi)); |
|
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|
3165 if (cpi->cpi_chipid >= 0) { |
| 0 | 3166 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
| 3167 "chip#", cpi->cpi_chipid); | |
|
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|
3168 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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|
3169 "clog#", cpi->cpi_clogid); |
|
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|
3170 } |
| 0 | 3171 } |
| 3172 | |
| 3173 /* cpuid-features */ | |
| 3174 | |
| 3175 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3176 "cpuid-features", CPI_FEATURES_EDX(cpi)); | |
| 3177 | |
| 3178 | |
| 3179 /* cpuid-features-ecx */ | |
| 3180 | |
| 3181 switch (cpi->cpi_vendor) { | |
| 3182 case X86_VENDOR_Intel: | |
|
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|
3183 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
| 0 | 3184 break; |
| 3185 default: | |
| 3186 create = 0; | |
| 3187 break; | |
| 3188 } | |
| 3189 if (create) | |
| 3190 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3191 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); | |
| 3192 | |
| 3193 /* ext-cpuid-features */ | |
| 3194 | |
| 3195 switch (cpi->cpi_vendor) { | |
|
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|
3196 case X86_VENDOR_Intel: |
| 0 | 3197 case X86_VENDOR_AMD: |
| 3198 case X86_VENDOR_Cyrix: | |
| 3199 case X86_VENDOR_TM: | |
| 3200 case X86_VENDOR_Centaur: | |
| 3201 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 3202 break; | |
| 3203 default: | |
| 3204 create = 0; | |
| 3205 break; | |
| 3206 } | |
|
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|
3207 if (create) { |
| 0 | 3208 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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|
3209 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); |
|
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|
3210 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
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|
3211 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); |
|
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|
3212 } |
| 0 | 3213 |
| 3214 /* | |
| 3215 * Brand String first appeared in Intel Pentium IV, AMD K5 | |
| 3216 * model 1, and Cyrix GXm. On earlier models we try and | |
| 3217 * simulate something similar .. so this string should always | |
| 3218 * same -something- about the processor, however lame. | |
| 3219 */ | |
| 3220 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 3221 "brand-string", cpi->cpi_brandstr); | |
| 3222 | |
| 3223 /* | |
| 3224 * Finally, cache and tlb information | |
| 3225 */ | |
| 3226 switch (x86_which_cacheinfo(cpi)) { | |
| 3227 case X86_VENDOR_Intel: | |
| 3228 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 3229 break; | |
| 3230 case X86_VENDOR_Cyrix: | |
| 3231 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 3232 break; | |
| 3233 case X86_VENDOR_AMD: | |
| 3234 amd_cache_info(cpi, cpu_devi); | |
| 3235 break; | |
| 3236 default: | |
| 3237 break; | |
| 3238 } | |
| 3239 | |
| 3240 mutex_exit(&cpu_node_lock); | |
| 3241 } | |
| 3242 | |
| 3243 struct l2info { | |
| 3244 int *l2i_csz; | |
| 3245 int *l2i_lsz; | |
| 3246 int *l2i_assoc; | |
| 3247 int l2i_ret; | |
| 3248 }; | |
| 3249 | |
| 3250 /* | |
| 3251 * A cacheinfo walker that fetches the size, line-size and associativity | |
| 3252 * of the L2 cache | |
| 3253 */ | |
| 3254 static int | |
| 3255 intel_l2cinfo(void *arg, const struct cachetab *ct) | |
| 3256 { | |
| 3257 struct l2info *l2i = arg; | |
| 3258 int *ip; | |
| 3259 | |
| 3260 if (ct->ct_label != l2_cache_str && | |
| 3261 ct->ct_label != sl2_cache_str) | |
| 3262 return (0); /* not an L2 -- keep walking */ | |
| 3263 | |
| 3264 if ((ip = l2i->l2i_csz) != NULL) | |
| 3265 *ip = ct->ct_size; | |
| 3266 if ((ip = l2i->l2i_lsz) != NULL) | |
| 3267 *ip = ct->ct_line_size; | |
| 3268 if ((ip = l2i->l2i_assoc) != NULL) | |
| 3269 *ip = ct->ct_assoc; | |
| 3270 l2i->l2i_ret = ct->ct_size; | |
| 3271 return (1); /* was an L2 -- terminate walk */ | |
| 3272 } | |
| 3273 | |
| 3274 static void | |
| 3275 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) | |
| 3276 { | |
| 1228 | 3277 struct cpuid_regs *cp; |
| 0 | 3278 uint_t size, assoc; |
| 3279 int *ip; | |
| 3280 | |
| 3281 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 3282 return; | |
| 3283 cp = &cpi->cpi_extd[6]; | |
| 3284 | |
| 3285 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && | |
| 3286 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { | |
| 3287 uint_t cachesz = size * 1024; | |
| 3288 | |
| 3289 | |
| 3290 if ((ip = l2i->l2i_csz) != NULL) | |
| 3291 *ip = cachesz; | |
| 3292 if ((ip = l2i->l2i_lsz) != NULL) | |
| 3293 *ip = BITX(cp->cp_ecx, 7, 0); | |
| 3294 if ((ip = l2i->l2i_assoc) != NULL) | |
| 3295 *ip = assoc; | |
| 3296 l2i->l2i_ret = cachesz; | |
| 3297 } | |
| 3298 } | |
| 3299 | |
| 3300 int | |
| 3301 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) | |
| 3302 { | |
| 3303 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 3304 struct l2info __l2info, *l2i = &__l2info; | |
| 3305 | |
| 3306 l2i->l2i_csz = csz; | |
| 3307 l2i->l2i_lsz = lsz; | |
| 3308 l2i->l2i_assoc = assoc; | |
| 3309 l2i->l2i_ret = -1; | |
| 3310 | |
| 3311 switch (x86_which_cacheinfo(cpi)) { | |
| 3312 case X86_VENDOR_Intel: | |
| 3313 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 3314 break; | |
| 3315 case X86_VENDOR_Cyrix: | |
| 3316 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 3317 break; | |
| 3318 case X86_VENDOR_AMD: | |
| 3319 amd_l2cacheinfo(cpi, l2i); | |
| 3320 break; | |
| 3321 default: | |
| 3322 break; | |
| 3323 } | |
| 3324 return (l2i->l2i_ret); | |
| 3325 } | |
|
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3326 |
|
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|
3327 size_t |
|
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|
3328 cpuid_get_mwait_size(cpu_t *cpu) |
|
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|
3329 { |
|
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|
3330 ASSERT(cpuid_checkpass(cpu, 2)); |
|
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3331 return (cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max); |
|
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3332 } |