Mercurial > illumos > illumos-gate
annotate usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h @ 14183:68927c785889 default tip
4099 SMF methods without absolute paths no longer work
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by: Dan McDonald <danmcd@nexenta.com>
author | Jerry Jelinek <jerry.jelinek@joyent.com> |
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date | Fri, 06 Sep 2013 09:20:56 -0700 |
parents | 47f42be153c1 |
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rev | line source |
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3333 | 1 /* |
2 * CDDL HEADER START | |
3 * | |
4 * The contents of this file are subject to the terms of the | |
5 * Common Development and Distribution License (the "License"). | |
6 * You may not use this file except in compliance with the License. | |
7 * | |
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
9 * or http://www.opensolaris.org/os/licensing. | |
10 * See the License for the specific language governing permissions | |
11 * and limitations under the License. | |
12 * | |
13 * When distributing Covered Code, include this CDDL HEADER in each | |
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
15 * If applicable, add the following below this CDDL HEADER, with the | |
16 * fields enclosed by brackets "[]" replaced with your own identifying | |
17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
18 * | |
19 * CDDL HEADER END | |
20 */ | |
21 | |
22 /* | |
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23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. |
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24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. |
3333 | 25 */ |
26 | |
27 | |
28 #ifndef _AHCIVAR_H | |
29 #define _AHCIVAR_H | |
30 | |
31 #ifdef __cplusplus | |
32 extern "C" { | |
33 #endif | |
34 | |
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35 /* |
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36 * AHCI address qualifier flags (in qual field of ahci_addr struct). |
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37 */ |
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38 #define AHCI_ADDR_NULL 0x00 |
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39 #define AHCI_ADDR_PORT 0x01 |
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40 #define AHCI_ADDR_PMPORT 0x02 |
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41 #define AHCI_ADDR_PMULT 0x04 |
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42 #define AHCI_ADDR_VALID (AHCI_ADDR_PORT | \ |
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43 AHCI_ADDR_PMULT | \ |
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44 AHCI_ADDR_PMPORT) |
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45 |
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46 /* |
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47 * AHCI address structure. |
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48 */ |
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49 struct ahci_addr { |
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50 |
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51 /* HBA port number */ |
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52 uint8_t aa_port; |
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53 |
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54 /* Port multiplier port number */ |
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55 uint8_t aa_pmport; |
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56 |
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57 /* |
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58 * AHCI_ADDR_NULL |
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59 * AHCI_ADDR_PORT |
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60 * AHCI_ADDR_PMPORT |
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61 * AHCI_ADDR_PMULT |
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62 */ |
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63 uint8_t aa_qual; |
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64 }; |
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65 typedef struct ahci_addr ahci_addr_t; |
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66 |
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67 _NOTE(SCHEME_PROTECTS_DATA("unshared data", ahci_addr)) |
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68 |
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69 #define AHCI_ADDR_IS_PORT(addrp) \ |
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70 ((addrp)->aa_qual & AHCI_ADDR_PORT) |
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71 #define AHCI_ADDR_IS_PMPORT(addrp) \ |
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72 ((addrp)->aa_qual & AHCI_ADDR_PMPORT) |
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73 #define AHCI_ADDR_IS_PMULT(addrp) \ |
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74 ((addrp)->aa_qual & AHCI_ADDR_PMULT) |
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75 #define AHCI_ADDR_IS_VALID(addrp) \ |
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76 ((addrp)->aa_port < SATA_MAX_CPORTS) && \ |
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77 ((addrp)->aa_pmport < SATA_MAX_PMPORTS) && \ |
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78 ((addrp)->aa_qual & AHCI_ADDR_VALID) |
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79 |
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80 #define AHCI_ADDR_SET(addrp, port, pmport, qual) \ |
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81 { \ |
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82 (addrp)->aa_port = port; \ |
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83 (addrp)->aa_pmport = pmport; \ |
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84 (addrp)->aa_qual = qual; \ |
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85 } |
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86 #define AHCI_ADDR_SET_PORT(addrp, port) \ |
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87 AHCI_ADDR_SET(addrp, port, 0, AHCI_ADDR_PORT) |
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88 #define AHCI_ADDR_SET_PMPORT(addrp, port, pmport) \ |
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89 AHCI_ADDR_SET(addrp, port, pmport, AHCI_ADDR_PMPORT) |
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90 #define AHCI_ADDR_SET_PMULT(addrp, port) \ |
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91 AHCI_ADDR_SET(addrp, port, SATA_PMULT_HOSTPORT, AHCI_ADDR_PMULT) |
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92 |
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93 /* Type for argument of event handler */ |
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94 typedef struct ahci_event_arg { |
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95 void *ahciea_ctlp; |
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96 void *ahciea_portp; |
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97 void *ahciea_addrp; |
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98 uint32_t ahciea_event; |
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99 } ahci_event_arg_t; |
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100 |
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101 /* Warlock annotation */ |
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102 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp)) |
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103 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp)) |
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104 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_addrp)) |
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105 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event)) |
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106 |
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107 |
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108 /* |
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109 * ahci_pmult_info stores the information of a port multiplier and its |
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110 * sub-devices in case a port multiplier is attached to an HBA port. |
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111 */ |
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112 struct ahci_pmult_info { |
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113 |
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114 /* Number of the device ports */ |
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115 int ahcipmi_num_dev_ports; |
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116 |
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117 /* Device type of the sub-devices of the port multipler */ |
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118 uint8_t ahcipmi_device_type[SATA_MAX_PMPORTS]; |
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119 |
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120 /* State of port multiplier port */ |
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121 uint32_t ahcipmi_port_state[SATA_MAX_PMPORTS]; |
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122 |
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123 /* |
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124 * Port multiplier port on which there is outstanding NCQ |
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125 * commands. Only make sense in command based switching mode. |
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126 */ |
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127 uint8_t ahcipmi_ncq_pmport; |
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128 |
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129 /* Pending asynchronous notification events tags */ |
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130 uint32_t ahcipmi_snotif_tags; |
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131 }; |
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132 typedef struct ahci_pmult_info ahci_pmult_info_t; |
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133 |
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134 /* |
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135 * flags for ahciport_flags |
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136 * |
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137 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped, |
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138 * and all the outstanding commands need to be aborted and sent to upper |
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139 * layers. |
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140 * |
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141 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is |
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142 * disabled, and the command is executed in POLLING mode. |
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143 * |
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144 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which |
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145 * is used to retrieve sense data is being executed. |
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146 * |
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147 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started, |
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148 * that is PxCMD.ST is set with '1', and be cleared when the port is put into |
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149 * idle, that is PxCMD.ST is changed from '1' to '0'. |
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150 * |
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151 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which |
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152 * is used to retrieve NCQ failure context is being executed. |
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153 * |
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154 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone |
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155 * during ahci_restart_port_wait_till_ready process. |
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156 * |
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157 * AHCI_PORT_FLAG_RDWR_PMULT: this flag will be set when a READ/WRITE |
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158 * PORTMULT command is being executed. |
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159 * |
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160 * AHCI_PORT_FLAG_IGNORE_IPMS: this flag will be set when enumerating a port |
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161 * multiplier. According AHCI spec, IPMS error should be ignore during |
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162 * enumeration of port multiplier. |
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163 * |
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164 * AHCI_PORT_FLAG_PMULT_SNTF: this flag will be set when the a asynchronous |
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165 * notification event on the port multiplier is being handled. |
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166 * |
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167 * AHCI_PORT_FLAG_HOTPLUG: this flag will be set when a hot plug event is |
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168 * being handled. |
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169 * |
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170 * AHCI_PORT_FLAG_ERRPRINT: this flag will be set when error recovery message |
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171 * will be printed. Note that, for INDENTIFY DEVICE command sent to ATAPI |
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172 * device or ATAPI PACKET command, this flag won't be set. |
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173 */ |
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174 #define AHCI_PORT_FLAG_MOPPING 0x02 |
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175 #define AHCI_PORT_FLAG_POLLING 0x04 |
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176 #define AHCI_PORT_FLAG_RQSENSE 0x08 |
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177 #define AHCI_PORT_FLAG_STARTED 0x10 |
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178 #define AHCI_PORT_FLAG_RDLOGEXT 0x20 |
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179 #define AHCI_PORT_FLAG_NODEV 0x40 |
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180 #define AHCI_PORT_FLAG_RDWR_PMULT 0x80 |
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181 #define AHCI_PORT_FLAG_IGNORE_IPMS 0x100 |
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182 #define AHCI_PORT_FLAG_PMULT_SNTF 0x200 |
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183 #define AHCI_PORT_FLAG_HOTPLUG 0x400 |
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184 #define AHCI_PORT_FLAG_ERRPRINT 0x800 |
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185 |
3333 | 186 typedef struct ahci_port { |
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187 /* The physical port number */ |
3333 | 188 uint8_t ahciport_port_num; |
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189 |
3333 | 190 /* Type of the device attached to the port */ |
191 uint8_t ahciport_device_type; | |
192 /* State of the port */ | |
193 uint32_t ahciport_port_state; | |
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194 |
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195 /* Port multiplier struct */ |
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196 ahci_pmult_info_t *ahciport_pmult_info; |
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197 |
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198 /* |
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199 * AHCI_PORT_FLAG_MOPPING |
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200 * AHCI_PORT_FLAG_POLLING |
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201 * AHCI_PORT_FLAG_RQSENSE |
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202 * AHCI_PORT_FLAG_STARTED |
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203 * AHCI_PORT_FLAG_RDLOGEXT |
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204 * AHCI_PORT_FLAG_NODEV |
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205 * AHCI_PORT_FLAG_RDWR_PMULT |
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206 * AHCI_PORT_FLAG_IGNORE_IPMS |
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207 * AHCI_PORT_FLAG_PMULT_SNTF |
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208 * AHCI_PORT_FLAG_HOTPLUG |
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209 * AHCI_PORT_FLAG_ERRPRINT |
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210 */ |
3333 | 211 int ahciport_flags; |
212 | |
213 /* Pointer to received FIS structure */ | |
214 ahci_rcvd_fis_t *ahciport_rcvd_fis; | |
215 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; | |
216 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; | |
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217 ddi_dma_cookie_t ahciport_rcvd_fis_dma_cookie; |
3333 | 218 |
219 /* Pointer to command list structure */ | |
220 ahci_cmd_header_t *ahciport_cmd_list; | |
221 ddi_dma_handle_t ahciport_cmd_list_dma_handle; | |
222 ddi_acc_handle_t ahciport_cmd_list_acc_handle; | |
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223 ddi_dma_cookie_t ahciport_cmd_list_dma_cookie; |
3333 | 224 |
225 /* Pointer to cmmand table structure */ | |
226 ahci_cmd_table_t \ | |
227 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; | |
228 ddi_dma_handle_t \ | |
229 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; | |
230 ddi_acc_handle_t \ | |
231 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; | |
232 | |
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233 /* Condition variable used for sync mode commands */ |
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234 kcondvar_t ahciport_cv; |
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235 |
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236 /* The whole mutex for the port structure */ |
3333 | 237 kmutex_t ahciport_mutex; |
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238 |
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239 /* The maximum number of tags for native queuing command transfers */ |
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240 int ahciport_max_ncq_tags; |
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241 |
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242 /* Keep the tags of all pending non-ncq commands */ |
3333 | 243 uint32_t ahciport_pending_tags; |
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244 |
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245 /* |
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246 * Keep the tags of all pending ncq commands |
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247 * (READ/WRITE FPDMA QUEUED) |
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248 */ |
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249 uint32_t ahciport_pending_ncq_tags; |
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250 |
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251 /* Keep all the pending sata packets */ |
3333 | 252 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; |
253 | |
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254 /* Used to check whether corresponding packet is timeout */ |
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255 int ahciport_slot_timeout[AHCI_PORT_MAX_CMD_SLOTS]; |
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256 |
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257 /* Queue of completed (done) sata packet */ |
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258 sata_pkt_t *ahciport_doneq; |
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259 |
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260 /* Pointer of the tail of completed sata packet queue */ |
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261 sata_pkt_t **ahciport_doneqtail; |
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262 |
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263 /* the length of the completed sata packet queue */ |
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264 uint32_t ahciport_doneq_len; |
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265 |
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266 /* Keep the byte count of all PRD entries for every sata packet */ |
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267 uint32_t \ |
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268 ahciport_prd_bytecounts[AHCI_PORT_MAX_CMD_SLOTS]; |
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269 |
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270 /* Keep the error retrieval sata packet */ |
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271 sata_pkt_t *ahciport_err_retri_pkt; |
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272 |
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273 /* Keep the read/write port multiplier packet */ |
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274 sata_pkt_t *ahciport_rdwr_pmult_pkt; |
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275 |
3333 | 276 /* |
277 * SATA HBA driver is supposed to remember and maintain device | |
278 * reset state. While the reset is in progress, it doesn't accept | |
279 * any more commands until receiving the command with | |
280 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. | |
281 */ | |
282 int ahciport_reset_in_progress; | |
283 | |
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284 /* Taskq for handling event */ |
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285 ddi_taskq_t *ahciport_event_taskq; |
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286 |
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287 /* This is for error recovery handler */ |
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288 ahci_event_arg_t *ahciport_event_args; |
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289 |
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290 /* This is to calculate how many mops are in progress */ |
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291 int ahciport_mop_in_progress; |
3333 | 292 } ahci_port_t; |
293 | |
294 /* Warlock annotation */ | |
295 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) | |
296 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) | |
297 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) | |
298 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
299 ahci_port_t::ahciport_device_type)) | |
300 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
301 ahci_port_t::ahciport_port_state)) | |
302 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
303 ahci_port_t::ahciport_flags)) | |
304 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
305 ahci_port_t::ahciport_pending_tags)) | |
306 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
307 ahci_port_t::ahciport_slot_pkts)) | |
308 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, | |
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309 ahci_port_t::ahciport_slot_timeout)) |
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310 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
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311 ahci_port_t::ahciport_doneq)) |
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312 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
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313 ahci_port_t::ahciport_doneqtail)) |
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314 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
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315 ahci_port_t::ahciport_doneq_len)) |
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316 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
3333 | 317 ahci_port_t::ahciport_reset_in_progress)) |
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318 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
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319 ahci_port_t::ahciport_mop_in_progress)) |
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320 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, |
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321 ahci_port_t::ahciport_event_taskq)) |
3333 | 322 |
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323 #define AHCI_NUM_PORTS(ctlp) \ |
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324 (ctlp)->ahcictl_num_ports |
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325 |
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326 #define AHCIPORT_NUM_PMPORTS(portp) \ |
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327 (portp)->ahciport_pmult_info->ahcipmi_num_dev_ports |
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328 |
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329 #define AHCIPORT_NCQ_PMPORT(ahci_portp) \ |
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330 (ahci_portp->ahciport_pmult_info->ahcipmi_ncq_pmport) |
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331 |
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332 #define AHCIPORT_DEV_TYPE(portp, addrp) \ |
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333 (portp)->ahciport_device_type |
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334 |
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335 #define AHCIPORT_PMDEV_TYPE(portp, addrp) \ |
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336 (portp)->ahciport_pmult_info->ahcipmi_device_type \ |
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337 [(addrp)->aa_pmport] |
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338 |
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339 #define AHCIPORT_GET_DEV_TYPE(portp, addrp) \ |
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340 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ |
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341 AHCIPORT_DEV_TYPE(portp, addrp) : \ |
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342 AHCIPORT_PMDEV_TYPE(portp, addrp)) |
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343 |
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344 #define AHCIPORT_SET_DEV_TYPE(portp, addrp, type) \ |
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345 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ |
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346 AHCIPORT_DEV_TYPE(portp, addrp) = type; \ |
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347 else \ |
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348 AHCIPORT_PMDEV_TYPE(portp, addrp) = type; |
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349 |
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350 #define AHCIPORT_STATE(portp, addrp) \ |
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351 (portp)->ahciport_port_state |
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352 |
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353 #define AHCIPORT_PMSTATE(portp, addrp) \ |
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354 (portp)->ahciport_pmult_info->ahcipmi_port_state \ |
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355 [(addrp)->aa_pmport] |
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356 |
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357 #define AHCIPORT_GET_STATE(portp, addrp) \ |
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358 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ |
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359 AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp)) |
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360 |
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361 #define AHCIPORT_SET_STATE(portp, addrp, state) \ |
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362 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ |
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363 AHCIPORT_STATE(portp, addrp) = state; \ |
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364 else \ |
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365 AHCIPORT_PMSTATE(portp, addrp) = state; |
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366 |
3333 | 367 typedef struct ahci_ctl { |
368 dev_info_t *ahcictl_dip; | |
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369 |
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370 ushort_t ahcictl_venid; |
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371 ushort_t ahcictl_devid; |
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372 |
3333 | 373 /* To map port number to cport number */ |
374 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; | |
375 /* To map cport number to port number */ | |
376 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; | |
377 | |
378 /* Number of controller ports */ | |
379 int ahcictl_num_ports; | |
380 /* Number of command slots */ | |
381 int ahcictl_num_cmd_slots; | |
382 /* Number of implemented ports */ | |
383 int ahcictl_num_implemented_ports; | |
384 /* Bit map to indicate which port is implemented */ | |
385 uint32_t ahcictl_ports_implemented; | |
386 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; | |
387 | |
388 int ahcictl_flags; | |
389 int ahcictl_power_level; | |
390 off_t ahcictl_pmcsr_offset; | |
391 | |
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392 /* |
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393 * AHCI_CAP_PIO_MDRQ |
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394 * AHCI_CAP_NO_MCMDLIST_NONQUEUE |
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395 * AHCI_CAP_NCQ |
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396 * AHCI_CAP_PM |
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397 * AHCI_CAP_BUF_32BIT_DMA |
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398 * AHCI_CAP_SCLO |
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399 * AHCI_CAP_COMMU_32BIT_DMA |
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400 * AHCI_CAP_INIT_PORT_RESET |
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401 * AHCI_CAP_SNTF |
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402 * AHCI_CAP_PMULT_CBSS |
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403 * AHCI_CAP_PMULT_FBSS |
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404 * AHCI_CAP_SRST_NO_HOSTPORT |
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405 */ |
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406 int ahcictl_cap; |
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407 |
3333 | 408 /* Pci configuration space handle */ |
409 ddi_acc_handle_t ahcictl_pci_conf_handle; | |
410 | |
411 /* Mapping into bar 5 - AHCI base address */ | |
412 ddi_acc_handle_t ahcictl_ahci_acc_handle; | |
413 uintptr_t ahcictl_ahci_addr; | |
414 | |
415 /* Pointer used for sata hba framework registration */ | |
416 struct sata_hba_tran *ahcictl_sata_hba_tran; | |
417 | |
418 /* DMA attributes for the data buffer */ | |
419 ddi_dma_attr_t ahcictl_buffer_dma_attr; | |
420 /* DMA attributes for the rcvd FIS */ | |
421 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; | |
422 /* DMA attributes for the command list */ | |
423 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; | |
424 /* DMA attributes for command tables */ | |
425 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; | |
426 | |
427 /* Used for watchdog handler */ | |
428 timeout_id_t ahcictl_timeout_id; | |
429 | |
430 /* Per controller mutex */ | |
431 kmutex_t ahcictl_mutex; | |
432 | |
433 /* Components for interrupt */ | |
434 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ | |
435 int ahcictl_intr_type; /* What type of interrupt */ | |
436 int ahcictl_intr_cnt; /* # of intrs returned */ | |
437 size_t ahcictl_intr_size; /* Size of intr array */ | |
438 uint_t ahcictl_intr_pri; /* Intr priority */ | |
439 int ahcictl_intr_cap; /* Intr capabilities */ | |
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440 |
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441 /* FMA capabilities */ |
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442 int ahcictl_fm_cap; |
3333 | 443 } ahci_ctl_t; |
444 | |
445 /* Warlock annotation */ | |
446 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) | |
447 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) | |
448 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) | |
449 | |
450 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, | |
451 ahci_ctl_t::ahcictl_power_level)) | |
452 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, | |
453 ahci_ctl_t::ahcictl_flags)) | |
454 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, | |
455 ahci_ctl_t::ahcictl_timeout_id)) | |
456 | |
457 #define AHCI_SUCCESS (0) /* Successful return */ | |
458 #define AHCI_TIMEOUT (1) /* Timed out */ | |
459 #define AHCI_FAILURE (-1) /* Unsuccessful return */ | |
460 | |
461 /* Flags for ahcictl_flags */ | |
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462 #define AHCI_ATTACH 0x1 |
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463 #define AHCI_DETACH 0x2 |
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464 #define AHCI_SUSPEND 0x4 |
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465 #define AHCI_QUIESCE 0x8 |
3333 | 466 |
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467 /* Values for ahcictl_cap */ |
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468 /* PIO Multiple DRQ Block */ |
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469 #define AHCI_CAP_PIO_MDRQ 0x1 |
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470 /* |
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471 * Multiple command slots in the command list cannot be used for |
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472 * non-queued commands |
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473 */ |
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474 #define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2 |
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475 /* Native Command Queuing (NCQ) */ |
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476 #define AHCI_CAP_NCQ 0x4 |
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477 /* Power Management (PM) */ |
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478 #define AHCI_CAP_PM 0x8 |
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479 /* 32-bit DMA addressing for buffer block */ |
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480 #define AHCI_CAP_BUF_32BIT_DMA 0x10 |
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481 /* Supports Command List Override */ |
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482 #define AHCI_CAP_SCLO 0x20 |
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483 /* 32-bit DMA addressing for communication memory descriptors */ |
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484 #define AHCI_CAP_COMMU_32BIT_DMA 0x40 |
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485 /* Port reset is needed for initialization */ |
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486 #define AHCI_CAP_INIT_PORT_RESET 0x80 |
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487 /* Port Asychronous Notification */ |
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488 #define AHCI_CAP_SNTF 0x100 |
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489 /* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */ |
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490 #define AHCI_CAP_PMULT_CBSS 0x200 |
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491 /* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */ |
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492 #define AHCI_CAP_PMULT_FBSS 0x400 |
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493 /* Software Reset FIS cannot set pmport with 0xf for direct access device */ |
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494 #define AHCI_CAP_SRST_NO_HOSTPORT 0x800 |
3333 | 495 |
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496 /* Flags controlling the restart port behavior */ |
3333 | 497 #define AHCI_PORT_RESET 0x0001 /* Reset the port */ |
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498 #define AHCI_RESET_NO_EVENTS_UP 0x0002 /* Don't send reset events up */ |
3333 | 499 |
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500 #define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \ |
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501 (ahci_portp->ahciport_flags & \ |
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502 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT)) |
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503 |
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504 #define RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) \ |
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505 (ahci_portp->ahciport_flags & \ |
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506 AHCI_PORT_FLAG_RDWR_PMULT) |
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507 |
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508 #define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \ |
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509 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ |
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510 ahci_portp->ahciport_pending_tags != 0 && \ |
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511 ahci_portp->ahciport_pending_ncq_tags == 0) |
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512 |
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513 #define NCQ_CMD_IN_PROGRESS(ahci_portp) \ |
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514 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ |
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515 ahci_portp->ahciport_pending_ncq_tags != 0) |
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516 |
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517 /* Command type for ahci_claim_free_slot routine */ |
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518 #define AHCI_NON_NCQ_CMD 0x0 |
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519 #define AHCI_NCQ_CMD 0x1 |
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520 #define AHCI_ERR_RETRI_CMD 0x2 |
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521 #define AHCI_RDWR_PMULT_CMD 0x4 |
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522 |
3333 | 523 /* State values for ahci_attach */ |
524 #define AHCI_ATTACH_STATE_NONE (0x1 << 0) | |
525 #define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) | |
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526 #define AHCI_ATTACH_STATE_FMA (0x1 << 2) |
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527 #define AHCI_ATTACH_STATE_REG_MAP (0x1 << 3) |
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528 #define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 4) |
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529 #define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 5) |
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530 #define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 6) |
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531 #define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 7) |
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532 #define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8) |
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533 #define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9) |
3333 | 534 |
535 /* Interval used for delay */ | |
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536 #define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */ |
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537 #define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */ |
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538 #define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */ |
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539 #define AHCI_10MS_USECS (10000) /* microsecs in 10 millisec */ |
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540 #define AHCI_1MS_USECS (1000) /* microsecs in 1 millisec */ |
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541 #define AHCI_100US_USECS (100) |
3333 | 542 |
543 /* | |
544 * The following values are the numbers of times to retry polled requests. | |
545 */ | |
546 #define AHCI_POLLRATE_HBA_RESET 100 | |
547 #define AHCI_POLLRATE_PORT_SSTATUS 10 | |
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548 #define AHCI_POLLRATE_PORT_TFD_ERROR 1100 |
3333 | 549 #define AHCI_POLLRATE_PORT_IDLE 50 |
550 #define AHCI_POLLRATE_PORT_SOFTRESET 100 | |
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551 #define AHCI_POLLRATE_GET_SPKT 100 |
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552 #define AHCI_POLLRATE_PORT_IDLE_FR 500 |
3333 | 553 |
554 | |
555 /* Clearing & setting the n'th bit in a given tag */ | |
556 #define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) | |
557 #define SET_BIT(tag, bit) (tag |= (0x1<<bit)) | |
558 | |
559 | |
560 #if DEBUG | |
561 | |
562 #define AHCI_DEBUG 1 | |
563 | |
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564 #endif |
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565 |
3333 | 566 #define AHCIDBG_INIT 0x0001 |
567 #define AHCIDBG_ENTRY 0x0002 | |
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568 #define AHCIDBG_PRDT 0x0004 |
3333 | 569 #define AHCIDBG_EVENT 0x0008 |
570 #define AHCIDBG_POLL_LOOP 0x0010 | |
571 #define AHCIDBG_PKTCOMP 0x0020 | |
572 #define AHCIDBG_TIMEOUT 0x0040 | |
573 #define AHCIDBG_INFO 0x0080 | |
574 #define AHCIDBG_VERBOSE 0x0100 | |
575 #define AHCIDBG_INTR 0x0200 | |
576 #define AHCIDBG_ERRS 0x0400 | |
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577 #define AHCIDBG_ATACMD 0x0800 |
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578 #define AHCIDBG_ATAPICMD 0x1000 |
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579 #define AHCIDBG_SENSEDATA 0x2000 |
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6703522 ahci driver needs to support SATA tape
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580 #define AHCIDBG_NCQ 0x4000 |
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581 #define AHCIDBG_PM 0x8000 |
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582 #define AHCIDBG_UNDERFLOW 0x10000 |
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6768770 ahci driver should enable MSI interrupt mode by default
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583 #define AHCIDBG_MSI 0x20000 |
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PSARC/2009/394 SATA Framework Port Multiplier Support
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584 #define AHCIDBG_PMULT 0x40000 |
3333 | 585 |
9204
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6753962 ahci does not work with Asus M3N78 Pro/M3N-HT (nforce 780a) motherboard SATA interfaces
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586 extern uint32_t ahci_debug_flags; |
3333 | 587 |
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6713021 sata: provide a ring buffer for storing sata status messages to aid in debugging analysis
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588 #if DEBUG |
3333 | 589 |
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590 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ |
3333 | 591 if (ahci_debug_flags & (flag)) { \ |
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592 ahci_log(ahci_ctlp, CE_WARN, fmt, ## args); \ |
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593 if (ahci_ctlp == NULL) \ |
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594 sata_trace_debug(NULL, fmt, ## args); \ |
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595 else \ |
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596 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ |
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597 fmt, ## args); \ |
3333 | 598 } |
599 | |
600 #else | |
601 | |
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602 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ |
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603 if (ahci_debug_flags & (flag)) { \ |
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604 if (ahci_ctlp == NULL) \ |
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605 sata_trace_debug(NULL, fmt, ## args); \ |
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606 else \ |
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607 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ |
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608 fmt, ## args); \ |
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609 } |
3333 | 610 |
611 #endif /* DEBUG */ | |
612 | |
613 | |
614 #ifdef __cplusplus | |
615 } | |
616 #endif | |
617 | |
618 #endif /* _AHCIVAR_H */ |