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changeset 10226:bcd1cd454e93

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6855989 SB600 AHCI controller fails to configure SATA disk, regression to 111b
author ying tian - Beijing China <Ying.Tian@Sun.COM>
date Fri, 31 Jul 2009 16:00:44 +0800
parents c372315f6ac2
children e8e2c2e0ba7a
files usr/src/uts/common/io/sata/adapters/ahci/ahci.c usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h
diffstat 2 files changed, 11 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/common/io/sata/adapters/ahci/ahci.c	Fri Jul 31 15:35:13 2009 +0800
+++ b/usr/src/uts/common/io/sata/adapters/ahci/ahci.c	Fri Jul 31 16:00:44 2009 +0800
@@ -2923,7 +2923,10 @@
 
 	    /* Check interface status */
 	    port_task_file & AHCI_TFD_STS_BSY ||
-	    port_task_file & AHCI_TFD_STS_DRQ) {
+	    port_task_file & AHCI_TFD_STS_DRQ ||
+
+	    /* Check whether port reset must be executed */
+	    ahci_ctlp->ahcictl_cap & AHCI_CAP_INIT_PORT_RESET) {
 
 		/* Incorrect task file state, we need to reset port */
 		ret = ahci_port_reset(ahci_ctlp, ahci_portp, port);
@@ -3063,6 +3066,10 @@
 	 * AMD/ATI SB600 (1002,4380) AHCI chipset doesn't support 64-bit DMA
 	 * addressing for both data buffer and communication memory descriptors
 	 * though S64A bit of CAP register declares the support.
+	 *
+	 * We found this chipset must do port reset during initialization,
+	 * otherwise, when retrieving device signature, software reset will
+	 * get time out.
 	 */
 	if (venid == 0x1002 && devid == 0x4380) {
 		AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
@@ -3071,6 +3078,7 @@
 		    "support, so force it to use 32-bit DMA", NULL);
 		ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA;
 		ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
+		ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET;
 	}
 
 	/*
--- a/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h	Fri Jul 31 15:35:13 2009 +0800
+++ b/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h	Fri Jul 31 16:00:44 2009 +0800
@@ -289,6 +289,8 @@
 #define	AHCI_CAP_SCLO			0x20
 /* 32-bit DMA addressing for communication memory descriptors */
 #define	AHCI_CAP_COMMU_32BIT_DMA	0x40
+/* Port reset is needed for initialization */
+#define	AHCI_CAP_INIT_PORT_RESET	0x80
 
 
 /* Flags controlling the restart port behavior */