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comparison usr/src/uts/common/io/atge/atge_l1_reg.h @ 13768:ed21ea5d20cf

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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter Reviewed by: Garrett D'Amore <garrett@damore.org> Reviewed by: Milan Jurik <milan.jurik@xylab.cz> Approved by: Dan McDonald <danmcd@nexenta.com>
author Gary Mills <gary_mills@fastmail.fm>
date Fri, 10 Aug 2012 10:52:49 -0400
parents db56a54bf91c
children
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13767:8c906b14afbd 13768:ed21ea5d20cf
19 * CDDL HEADER END 19 * CDDL HEADER END
20 */ 20 */
21 /* 21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms. 23 * Use is subject to license terms.
24 * Copyright (c) 2012 Gary Mills
24 */ 25 */
25 26
26 #ifndef _ATGE_L1_REG_H 27 #ifndef _ATGE_L1_REG_H
27 #define _ATGE_L1_REG_H 28 #define _ATGE_L1_REG_H
28 29
179 #define DESC_RD_CNT_MASK 0x000007FF 180 #define DESC_RD_CNT_MASK 0x000007FF
180 181
181 /* 182 /*
182 * PHY registers. 183 * PHY registers.
183 */ 184 */
184 #define L1_CSMB_CTRL 0x15D0
185 #define PHY_CDTS_STAT_OK 0x0000 185 #define PHY_CDTS_STAT_OK 0x0000
186 #define PHY_CDTS_STAT_SHORT 0x0100 186 #define PHY_CDTS_STAT_SHORT 0x0100
187 #define PHY_CDTS_STAT_OPEN 0x0200 187 #define PHY_CDTS_STAT_OPEN 0x0200
188 #define PHY_CDTS_STAT_INVAL 0x0300 188 #define PHY_CDTS_STAT_INVAL 0x0300
189 #define PHY_CDTS_STAT_MASK 0x0300 189 #define PHY_CDTS_STAT_MASK 0x0300
195 #define DMA_CFG_WR_ENB 0x00000800 195 #define DMA_CFG_WR_ENB 0x00000800
196 #define DMA_CFG_RD_BURST_MASK 0x07 196 #define DMA_CFG_RD_BURST_MASK 0x07
197 #define DMA_CFG_RD_BURST_SHIFT 4 197 #define DMA_CFG_RD_BURST_SHIFT 4
198 #define DMA_CFG_WR_BURST_MASK 0x07 198 #define DMA_CFG_WR_BURST_MASK 0x07
199 #define DMA_CFG_WR_BURST_SHIFT 7 199 #define DMA_CFG_WR_BURST_SHIFT 7
200
201 #define RXQ_CFG_ENB 0x80000000
202 200
203 #define L1_RD_LEN_MASK 0x0000FFFF 201 #define L1_RD_LEN_MASK 0x0000FFFF
204 #define L1_RD_LEN_SHIFT 0 202 #define L1_RD_LEN_SHIFT 0
205 203
206 #define L1_SRAM_RD_ADDR 0x1500 204 #define L1_SRAM_RD_ADDR 0x1500
217 #define L1_SRAM_TX_FIFO_LEN 0x152C 215 #define L1_SRAM_TX_FIFO_LEN 0x152C
218 216
219 #define RXQ_CFG_RD_BURST_MASK 0x000000FF 217 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
220 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 218 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
221 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 219 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
222 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
223 #define RXQ_CFG_ENB 0x80000000
224 #define RXQ_CFG_RD_BURST_SHIFT 0 220 #define RXQ_CFG_RD_BURST_SHIFT 0
225 #define RXQ_CFG_RD_BURST_DEFAULT 8 221 #define RXQ_CFG_RD_BURST_DEFAULT 8
226 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 222 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
227 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 223 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
228 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 224 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
229 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 225 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
230 226
231 #define TXQ_CFG_ENB 0x00000020
232 #define TXQ_CFG_ENHANCED_MODE 0x00000040
233 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 227 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
234 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
235 #define TXQ_CFG_TPD_BURST_SHIFT 0
236 #define TXQ_CFG_TPD_BURST_DEFAULT 4
237 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 228 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
238 #define TXQ_CFG_TPD_FETCH_DEFAULT 16 229 #define TXQ_CFG_TPD_FETCH_DEFAULT 16
239 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
240 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
241 230
242 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584 231 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584
243 #define TX_JUMBO_TPD_TH_MASK 0x000007FF 232 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
244 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 233 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
245 #define TX_JUMBO_TPD_TH_SHIFT 0 234 #define TX_JUMBO_TPD_TH_SHIFT 0
262 #define CSMB_CTRL_CMB_KICK 0x00000001 251 #define CSMB_CTRL_CMB_KICK 0x00000001
263 #define CSMB_CTRL_SMB_KICK 0x00000002 252 #define CSMB_CTRL_SMB_KICK 0x00000002
264 #define CSMB_CTRL_CMB_ENB 0x00000004 253 #define CSMB_CTRL_CMB_ENB 0x00000004
265 #define CSMB_CTRL_SMB_ENB 0x00000008 254 #define CSMB_CTRL_SMB_ENB 0x00000008
266 255
267 #define INTR_TX_FIFO_UNDERRUN 0x00000040
268 #define INTR_RX_FIFO_OFLOW 0x00000008
269 #define INTR_TX_DMA 0x00040000
270 #define INTR_RX_DMA 0x00080000 256 #define INTR_RX_DMA 0x00080000
271 #define INTR_CMB_RX 0x00100000 257 #define INTR_CMB_RX 0x00100000
272 #define INTR_CMB_TX 0x00200000 258 #define INTR_CMB_TX 0x00200000
273 #define INTR_MAC_RX 0x00400000
274 #define INTR_MAC_TX 0x00800000
275 #define INTR_UNDERRUN 0x01000000
276 #define INTR_FRAME_ERROR 0x02000000
277 #define INTR_FRAME_OK 0x04000000
278 #define INTR_CSUM_ERROR 0x08000000
279 #define INTR_PHY_LINK_DOWN 0x10000000
280 #define INTR_DIS_SMB 0x20000000 259 #define INTR_DIS_SMB 0x20000000
281 #define INTR_DIS_DMA 0x40000000
282 #define INTR_DIS_INT 0x80000000
283 260
284 #define L1_INTRS \ 261 #define L1_INTRS \
285 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 262 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
286 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN) 263 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
287 264