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diff usr/src/uts/common/io/atge/atge_l1_reg.h @ 13768:ed21ea5d20cf

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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter Reviewed by: Garrett D'Amore <garrett@damore.org> Reviewed by: Milan Jurik <milan.jurik@xylab.cz> Approved by: Dan McDonald <danmcd@nexenta.com>
author Gary Mills <gary_mills@fastmail.fm>
date Fri, 10 Aug 2012 10:52:49 -0400
parents db56a54bf91c
children
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--- a/usr/src/uts/common/io/atge/atge_l1_reg.h	Tue Aug 07 21:36:09 2012 -0500
+++ b/usr/src/uts/common/io/atge/atge_l1_reg.h	Fri Aug 10 10:52:49 2012 -0400
@@ -21,6 +21,7 @@
 /*
  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
+ * Copyright (c) 2012 Gary Mills
  */
 
 #ifndef _ATGE_L1_REG_H
@@ -181,7 +182,6 @@
 /*
  * PHY registers.
  */
-#define	L1_CSMB_CTRL		0x15D0
 #define	PHY_CDTS_STAT_OK	0x0000
 #define	PHY_CDTS_STAT_SHORT	0x0100
 #define	PHY_CDTS_STAT_OPEN	0x0200
@@ -198,8 +198,6 @@
 #define	DMA_CFG_WR_BURST_MASK	0x07
 #define	DMA_CFG_WR_BURST_SHIFT	7
 
-#define	RXQ_CFG_ENB		0x80000000
-
 #define	L1_RD_LEN_MASK		0x0000FFFF
 #define	L1_RD_LEN_SHIFT	0
 
@@ -219,8 +217,6 @@
 #define	RXQ_CFG_RD_BURST_MASK		0x000000FF
 #define	RXQ_CFG_RRD_BURST_THRESH_MASK	0x0000FF00
 #define	RXQ_CFG_RD_PREF_MIN_IPG_MASK	0x001F0000
-#define	RXQ_CFG_CUT_THROUGH_ENB		0x40000000
-#define	RXQ_CFG_ENB			0x80000000
 #define	RXQ_CFG_RD_BURST_SHIFT		0
 #define	RXQ_CFG_RD_BURST_DEFAULT	8
 #define	RXQ_CFG_RRD_BURST_THRESH_SHIFT	8
@@ -228,16 +224,9 @@
 #define	RXQ_CFG_RD_PREF_MIN_IPG_SHIFT	16
 #define	RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT	1
 
-#define	TXQ_CFG_ENB			0x00000020
-#define	TXQ_CFG_ENHANCED_MODE		0x00000040
 #define	TXQ_CFG_TPD_FETCH_THRESH_MASK	0x00003F00
-#define	TXQ_CFG_TX_FIFO_BURST_MASK	0xFFFF0000
-#define	TXQ_CFG_TPD_BURST_SHIFT		0
-#define	TXQ_CFG_TPD_BURST_DEFAULT	4
 #define	TXQ_CFG_TPD_FETCH_THRESH_SHIFT	8
 #define	TXQ_CFG_TPD_FETCH_DEFAULT	16
-#define	TXQ_CFG_TX_FIFO_BURST_SHIFT	16
-#define	TXQ_CFG_TX_FIFO_BURST_DEFAULT	256
 
 #define	L1_TX_JUMBO_TPD_TH_IPG		0x1584
 #define	TX_JUMBO_TPD_TH_MASK		0x000007FF
@@ -264,22 +253,10 @@
 #define	CSMB_CTRL_CMB_ENB		0x00000004
 #define	CSMB_CTRL_SMB_ENB		0x00000008
 
-#define	INTR_TX_FIFO_UNDERRUN		0x00000040
-#define	INTR_RX_FIFO_OFLOW		0x00000008
-#define	INTR_TX_DMA			0x00040000
 #define	INTR_RX_DMA			0x00080000
 #define	INTR_CMB_RX			0x00100000
 #define	INTR_CMB_TX			0x00200000
-#define	INTR_MAC_RX			0x00400000
-#define	INTR_MAC_TX			0x00800000
-#define	INTR_UNDERRUN			0x01000000
-#define	INTR_FRAME_ERROR		0x02000000
-#define	INTR_FRAME_OK			0x04000000
-#define	INTR_CSUM_ERROR			0x08000000
-#define	INTR_PHY_LINK_DOWN		0x10000000
 #define	INTR_DIS_SMB			0x20000000
-#define	INTR_DIS_DMA			0x40000000
-#define	INTR_DIS_INT			0x80000000
 
 #define	L1_INTRS	\
 	(INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |	\