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comparison usr/src/uts/common/io/atge/atge_l1e_reg.h @ 13768:ed21ea5d20cf

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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter Reviewed by: Garrett D'Amore <garrett@damore.org> Reviewed by: Milan Jurik <milan.jurik@xylab.cz> Approved by: Dan McDonald <danmcd@nexenta.com>
author Gary Mills <gary_mills@fastmail.fm>
date Fri, 10 Aug 2012 10:52:49 -0400
parents db56a54bf91c
children
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13767:8c906b14afbd 13768:ed21ea5d20cf
17 * information: Portions Copyright [yyyy] [name of copyright owner] 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 * 18 *
19 * CDDL HEADER END 19 * CDDL HEADER END
20 */ 20 */
21 /* 21 /*
22 * Copyright (c) 2012 Gary Mills
23 *
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms. 25 * Use is subject to license terms.
24 */ 26 */
25 27
26 #ifndef _ATGE_L1E_REG_H 28 #ifndef _ATGE_L1E_REG_H
46 typedef struct rx_cmb { 48 typedef struct rx_cmb {
47 uint32_t cmb[L1E_RX_PAGES]; 49 uint32_t cmb[L1E_RX_PAGES];
48 } rx_cmb_t; 50 } rx_cmb_t;
49 #pragma pack() 51 #pragma pack()
50 52
53 /* Master configuration */
54 #define L1E_MASTER_CFG 0x1400
55 #define L1E_MASTER_RESET 0x00000001
56 #define L1E_MASTER_MTIMER_ENB 0x00000002
57 #define L1E_MASTER_IM_TX_TIMER_ENB 0x00000004
58 #define L1E_MASTER_MANUAL_INT_ENB 0x00000008
59 #define L1E_MASTER_IM_RX_TIMER_ENB 0x00000020
60 #define L1E_MASTER_CHIP_REV_MASK 0x00FF0000
61 #define L1E_MASTER_CHIP_ID_MASK 0xFF000000
62 #define L1E_MASTER_CHIP_REV_SHIFT 16
63 #define L1E_MASTER_CHIP_ID_SHIFT 24
64
65
51 /* 66 /*
52 * DMA CFG registers (L1E specific). 67 * DMA CFG registers (L1E specific).
53 */ 68 */
54 #define DMA_CFG_RD_REQ_PRI 0x00000400 69 #define DMA_CFG_RD_REQ_PRI 0x00000400
55 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
56 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
57 #define DMA_CFG_TXCMB_ENB 0x00100000 70 #define DMA_CFG_TXCMB_ENB 0x00100000
58 #define DMA_CFG_RXCMB_ENB 0x00200000
59 #define DMA_CFG_RD_BURST_MASK 0x07 71 #define DMA_CFG_RD_BURST_MASK 0x07
60 #define DMA_CFG_RD_BURST_SHIFT 4 72 #define DMA_CFG_RD_BURST_SHIFT 4
61 #define DMA_CFG_WR_BURST_MASK 0x07 73 #define DMA_CFG_WR_BURST_MASK 0x07
62 #define DMA_CFG_WR_BURST_SHIFT 7 74 #define DMA_CFG_WR_BURST_SHIFT 7
63 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
64 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
65 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
66 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
67 75
68 #define L1E_TX_RING_CNT_MIN 32 76 #define L1E_TX_RING_CNT_MIN 32
69 #define L1E_TX_RING_CNT_MAX 1020 77 #define L1E_TX_RING_CNT_MAX 1020
70 #define L1E_TX_RING_ALIGN 8 78 #define L1E_TX_RING_ALIGN 8
71 #define L1E_RX_PAGE_ALIGN 32 79 #define L1E_RX_PAGE_ALIGN 32