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changeset 13655:0461a7e94e53

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2412 Various CPU features aren't intel specific Reviewed by: Richard Lowe <richlowe@richlowe.net> Reviewed by: Robert Mustacchi <rm@joyent.com> Approved by: Albert Lee <trisk@nexenta.com>
author Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
date Sun, 01 Apr 2012 21:19:32 +0200
parents 05c013fc7a3f
children 57f5c4bc231c
files usr/src/uts/i86pc/os/cpuid.c
diffstat 1 files changed, 56 insertions(+), 59 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/i86pc/os/cpuid.c	Sat Mar 31 16:43:18 2012 -0700
+++ b/usr/src/uts/i86pc/os/cpuid.c	Sun Apr 01 21:19:32 2012 +0200
@@ -1218,30 +1218,28 @@
 		if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
 			add_x86_feature(featureset, X86FSET_SSE3);
 		}
-		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
-			if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
-				add_x86_feature(featureset, X86FSET_SSSE3);
-			}
-			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
-				add_x86_feature(featureset, X86FSET_SSE4_1);
-			}
-			if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
-				add_x86_feature(featureset, X86FSET_SSE4_2);
-			}
-			if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
-				add_x86_feature(featureset, X86FSET_AES);
-			}
-			if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
-				add_x86_feature(featureset, X86FSET_PCLMULQDQ);
-			}
-
-			if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
-				add_x86_feature(featureset, X86FSET_XSAVE);
-				/* We only test AVX when there is XSAVE */
-				if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
-					add_x86_feature(featureset,
-					    X86FSET_AVX);
-				}
+		if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
+			add_x86_feature(featureset, X86FSET_SSSE3);
+		}
+		if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
+			add_x86_feature(featureset, X86FSET_SSE4_1);
+		}
+		if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
+			add_x86_feature(featureset, X86FSET_SSE4_2);
+		}
+		if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
+			add_x86_feature(featureset, X86FSET_AES);
+		}
+		if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
+			add_x86_feature(featureset, X86FSET_PCLMULQDQ);
+		}
+
+		if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
+			add_x86_feature(featureset, X86FSET_XSAVE);
+			/* We only test AVX when there is XSAVE */
+			if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
+				add_x86_feature(featureset,
+				    X86FSET_AVX);
 			}
 		}
 	}
@@ -1797,7 +1795,7 @@
 	/*
 	 * XSAVE enumeration
 	 */
-	if (cpi->cpi_maxeax >= 0xD && cpi->cpi_vendor == X86_VENDOR_Intel) {
+	if (cpi->cpi_maxeax >= 0xD) {
 		struct cpuid_regs regs;
 		boolean_t cpuid_d_valid = B_TRUE;
 
@@ -2531,23 +2529,21 @@
 		if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
 			*ecx &= ~CPUID_INTC_ECX_SSE3;
 
-		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
-			if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
-				*ecx &= ~CPUID_INTC_ECX_SSSE3;
-			if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
-				*ecx &= ~CPUID_INTC_ECX_SSE4_1;
-			if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
-				*ecx &= ~CPUID_INTC_ECX_SSE4_2;
-			if (!is_x86_feature(x86_featureset, X86FSET_AES))
-				*ecx &= ~CPUID_INTC_ECX_AES;
-			if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
-				*ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
-			if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
-				*ecx &= ~(CPUID_INTC_ECX_XSAVE |
-				    CPUID_INTC_ECX_OSXSAVE);
-			if (!is_x86_feature(x86_featureset, X86FSET_AVX))
-				*ecx &= ~CPUID_INTC_ECX_AVX;
-		}
+		if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
+			*ecx &= ~CPUID_INTC_ECX_SSSE3;
+		if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
+			*ecx &= ~CPUID_INTC_ECX_SSE4_1;
+		if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
+			*ecx &= ~CPUID_INTC_ECX_SSE4_2;
+		if (!is_x86_feature(x86_featureset, X86FSET_AES))
+			*ecx &= ~CPUID_INTC_ECX_AES;
+		if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
+			*ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
+		if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
+			*ecx &= ~(CPUID_INTC_ECX_XSAVE |
+			    CPUID_INTC_ECX_OSXSAVE);
+		if (!is_x86_feature(x86_featureset, X86FSET_AVX))
+			*ecx &= ~CPUID_INTC_ECX_AVX;
 
 		/*
 		 * [no explicit support required beyond x87 fp context]
@@ -2567,23 +2563,21 @@
 			hwcap_flags |= AV_386_SSE2;
 		if (*ecx & CPUID_INTC_ECX_SSE3)
 			hwcap_flags |= AV_386_SSE3;
-		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
-			if (*ecx & CPUID_INTC_ECX_SSSE3)
-				hwcap_flags |= AV_386_SSSE3;
-			if (*ecx & CPUID_INTC_ECX_SSE4_1)
-				hwcap_flags |= AV_386_SSE4_1;
-			if (*ecx & CPUID_INTC_ECX_SSE4_2)
-				hwcap_flags |= AV_386_SSE4_2;
-			if (*ecx & CPUID_INTC_ECX_MOVBE)
-				hwcap_flags |= AV_386_MOVBE;
-			if (*ecx & CPUID_INTC_ECX_AES)
-				hwcap_flags |= AV_386_AES;
-			if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
-				hwcap_flags |= AV_386_PCLMULQDQ;
-			if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
-			    (*ecx & CPUID_INTC_ECX_OSXSAVE))
-				hwcap_flags |= AV_386_XSAVE;
-		}
+		if (*ecx & CPUID_INTC_ECX_SSSE3)
+			hwcap_flags |= AV_386_SSSE3;
+		if (*ecx & CPUID_INTC_ECX_SSE4_1)
+			hwcap_flags |= AV_386_SSE4_1;
+		if (*ecx & CPUID_INTC_ECX_SSE4_2)
+			hwcap_flags |= AV_386_SSE4_2;
+		if (*ecx & CPUID_INTC_ECX_MOVBE)
+			hwcap_flags |= AV_386_MOVBE;
+		if (*ecx & CPUID_INTC_ECX_AES)
+			hwcap_flags |= AV_386_AES;
+		if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
+			hwcap_flags |= AV_386_PCLMULQDQ;
+		if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
+		    (*ecx & CPUID_INTC_ECX_OSXSAVE))
+			hwcap_flags |= AV_386_XSAVE;
 		if (*ecx & CPUID_INTC_ECX_VMX)
 			hwcap_flags |= AV_386_VMX;
 		if (*ecx & CPUID_INTC_ECX_POPCNT)
@@ -4142,6 +4136,9 @@
 	case X86_VENDOR_Intel:
 		create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
 		break;
+	case X86_VENDOR_AMD:
+		create = cpi->cpi_family >= 0xf;
+		break;
 	default:
 		create = 0;
 		break;