Mercurial > illumos > illumos-gate
changeset 260:06b73b853c1f
6302652 Fire bypass access and translation access error handling in sun4u is wrong.
6302807 Some Fire FMA ereports are wrong
6303405 Minor code cleanup for pcie model
| author | et142600 |
|---|---|
| date | Fri, 29 Jul 2005 10:42:05 -0700 |
| parents | 0612b6e1662d |
| children | f2dfbad0c46b |
| files | usr/src/uts/common/io/pcie.c usr/src/uts/sun4u/io/px/px_err.c |
| diffstat | 2 files changed, 28 insertions(+), 7 deletions(-) [+] |
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--- a/usr/src/uts/common/io/pcie.c Fri Jul 29 09:36:18 2005 -0700 +++ b/usr/src/uts/common/io/pcie.c Fri Jul 29 10:42:05 2005 -0700 @@ -368,15 +368,12 @@ break; } -/* reg = pci_config_get32(config_handle, caps_ptr); */ -/* cap = reg & 0xFF; */ cap = pci_config_get8(config_handle, caps_ptr); if (cap == cap_id) { break; } -/* caps_ptr = (reg >> 8) & 0xFF; */ caps_ptr = P2ALIGN(pci_config_get8(config_handle, (caps_ptr + PCI_CAP_NEXT_PTR)), 4); }
--- a/usr/src/uts/sun4u/io/px/px_err.c Fri Jul 29 09:36:18 2005 -0700 +++ b/usr/src/uts/sun4u/io/px/px_err.c Fri Jul 29 10:42:05 2005 -0700 @@ -1450,8 +1450,10 @@ ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) { - uint64_t mmu_log_enable, mmu_intr_enable, mmu_tfa; + uint64_t mmu_log_enable, mmu_intr_enable; uint64_t mask = BITMASK(err_bit_descr->bit); + uint64_t mmu_tfa, mmu_ctrl; + uint64_t mmu_enable_bit = 0; int err = PX_NONFATAL; int ret; @@ -1459,8 +1461,26 @@ mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); + mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); - if (mmu_log_enable & mmu_intr_enable & mask) { + switch (err_bit_descr->bit) { + case MMU_INTERRUPT_STATUS_BYP_ERR_P: + mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); + break; + case MMU_INTERRUPT_STATUS_TRN_ERR_P: + mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); + break; + default: + mmu_enable_bit = 0; + break; + } + + /* + * If the interrupts are enabled and Translation/Bypass Enable bit + * was set, then panic. This error should not have occured. + */ + if (mmu_log_enable & mmu_intr_enable & + (mmu_ctrl & mmu_enable_bit)) { err = PX_FATAL_SW; } else { ret = px_handle_lookup( @@ -1474,6 +1494,10 @@ /* enable error & intr reporting for this bit */ CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); + + /* enable translation access/bypass enable */ + CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, + mmu_ctrl | mmu_enable_bit); } return (err); @@ -1606,7 +1630,7 @@ CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), - FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, + FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), NULL); @@ -1636,7 +1660,7 @@ CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), - FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, + FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), NULL);