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changeset 5079:2505799f46a8

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6601648 MPO changes should not have added reference to routine tsb_lgrp_affinity in common header file 6602344 Niagara1 machines think of themselves as NUMA 6602360 mdb, kstat updates needed post 6539930 6602440 physical processor view (psrinfo -vp) not supported on N1 post 6539930 6603355 MPO for sun4v platforms causes a panic when the number of mblocks > 1 and # of lgroups <= 1
author jc25722
date Mon, 17 Sep 2007 17:55:55 -0700
parents fd36ef94c1fc
children 047a93194dc4
files usr/src/cmd/mdb/common/modules/genunix/pg.c usr/src/uts/common/os/pghw.c usr/src/uts/common/sys/lgrp.h usr/src/uts/sun4v/cpu/generic.c usr/src/uts/sun4v/cpu/niagara2.c usr/src/uts/sun4v/os/cmp.c usr/src/uts/sun4v/os/mpo.c
diffstat 7 files changed, 37 insertions(+), 13 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/cmd/mdb/common/modules/genunix/pg.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/cmd/mdb/common/modules/genunix/pg.c	Mon Sep 17 17:55:55 2007 -0700
@@ -43,7 +43,8 @@
 	"ipipe",
 	"cache",
 	"fpu",
-	"mpipe/chip",
+	"mpipe",
+	"chip",
 	"memory",
 };
 
@@ -78,7 +79,7 @@
 
 	if (mdb_getopts(argc, argv,
 	    'q', MDB_OPT_SETBITS, TRUE, &opt_q,
-		NULL) != argc)
+	    NULL) != argc)
 		return (DCMD_USAGE);
 
 	if (flags & DCMD_PIPE_OUT)
@@ -111,7 +112,7 @@
 	}
 
 	if (mdb_vread(&pg_class, sizeof (struct pg_class),
-		(uintptr_t)pg.pg_class) == -1) {
+	    (uintptr_t)pg.pg_class) == -1) {
 		mdb_warn("unable to read 'pg_class' at %p", pg.pg_class);
 		return (DCMD_ERR);
 	}
--- a/usr/src/uts/common/os/pghw.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/common/os/pghw.c	Mon Sep 17 17:55:55 2007 -0700
@@ -365,6 +365,8 @@
 		return ("cache");
 	case PGHW_FPU:
 		return ("fpu");
+	case PGHW_MPIPE:
+		return ("mpipe");
 	case PGHW_CHIP:
 		return ("chip");
 	case PGHW_MEMORY:
--- a/usr/src/uts/common/sys/lgrp.h	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/common/sys/lgrp.h	Mon Sep 17 17:55:55 2007 -0700
@@ -605,7 +605,6 @@
 extern uint32_t		lgrp_loadavg_max_effect;
 extern uint32_t		lgrp_load_thresh;
 extern lgrp_mem_policy_t lgrp_mem_policy_root;
-extern int		tsb_lgrp_affinity;
 
 #endif	/* _KERNEL && _KMEMUSER */
 
--- a/usr/src/uts/sun4v/cpu/generic.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/sun4v/cpu/generic.c	Mon Sep 17 17:55:55 2007 -0700
@@ -168,6 +168,12 @@
 	if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND)
 		cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id);
 
+	/*
+	 * The cpu_chip field is initialized based on the information
+	 * in the MD and assume that all cpus within a chip
+	 * share the same L2 cache. If no such info is available, we
+	 * set the cpu to belong to the defacto chip 0.
+	 */
 	cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping;
 	if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND)
 		cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID;
--- a/usr/src/uts/sun4v/cpu/niagara2.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/sun4v/cpu/niagara2.c	Mon Sep 17 17:55:55 2007 -0700
@@ -201,6 +201,10 @@
 	cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping;
 	if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND)
 		cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID;
+
+	cp->cpu_m.cpu_chip = cpunodes[cp->cpu_id].l2_cache_mapping;
+	if (cp->cpu_m.cpu_chip == NO_L2_CACHE_MAPPING_FOUND)
+		cp->cpu_m.cpu_chip = CPU_CHIPID_INVALID;
 }
 
 static int cpucnt;
--- a/usr/src/uts/sun4v/os/cmp.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/sun4v/os/cmp.c	Mon Sep 17 17:55:55 2007 -0700
@@ -120,6 +120,8 @@
 	switch (hw) {
 	case PGHW_IPIPE:
 		return (cpu->cpu_m.cpu_ipipe);
+	case PGHW_CHIP:
+		return (cpu->cpu_m.cpu_chip);
 	case PGHW_MPIPE:
 		return (cpu->cpu_m.cpu_mpipe);
 	case PGHW_FPU:
--- a/usr/src/uts/sun4v/os/mpo.c	Mon Sep 17 17:10:05 2007 -0700
+++ b/usr/src/uts/sun4v/os/mpo.c	Mon Sep 17 17:55:55 2007 -0700
@@ -37,6 +37,7 @@
 #include <sys/mdesc.h>
 #include <sys/mpo.h>
 #include <vm/vm_dep.h>
+#include <vm/hat_sfmmu.h>
 
 /*
  * MPO and the sun4v memory representation
@@ -728,10 +729,12 @@
 	uint64_t stripe, frag, remove;
 	mem_stripe_t *ms;
 
-	/* Check for non-MPO sun4v platforms */
+	/* Pre-reserve space for plat_assign_lgrphand_to_mem_node */
+	max_mem_nodes = max_locality_groups;
 
+	/* Check for non-MPO sun4v platforms */
 	if (n_locality_groups <= 1) {
-		mpo_plat_assign_lgrphand_to_mem_node((lgrp_handle_t)0, 0);
+		mpo_plat_assign_lgrphand_to_mem_node(LGRP_DEFAULT_HANDLE, 0);
 		for (elem = 0; elem < nelems; elem += 2) {
 			base = list[elem];
 			len = list[elem+1];
@@ -742,11 +745,10 @@
 		mem_node_pfn_shift = 0;
 		mem_node_physalign = 0;
 		n_mem_stripes = 0;
-		return;
+		if (n_mblocks == 1)
+			return;
 	}
 
-	/* Pre-reserve space for plat_assign_lgrphand_to_mem_node */
-	max_mem_nodes = max_locality_groups;
 	bzero(mem_stripes, sizeof (mem_stripes));
 	stripe = ptob(mnode_pages);
 	stride = max_locality_groups * stripe;
@@ -808,9 +810,17 @@
 			ms->offset = btop(offset);
 			ms->exists = 1;
 
-			mpo_plat_assign_lgrphand_to_mem_node(lgrphand, mnode);
-			mpo_mem_node_add_slice(ms->physbase, ms->physmax);
-
+			/*
+			 * If we have only 1 lgroup and multiple mblocks,
+			 * then we have already established our lgrp handle
+			 * to mem_node and mem_node_config values above.
+			 */
+			if (n_locality_groups > 1) {
+				mpo_plat_assign_lgrphand_to_mem_node(lgrphand,
+				    mnode);
+				mpo_mem_node_add_slice(ms->physbase,
+				    ms->physmax);
+			}
 			base = stripe_end;
 			stripe_end += stripe;
 			offset = 0;
@@ -837,7 +847,7 @@
 	if (n_locality_groups > 1) {
 		return ((lgrp_handle_t)mpo_cpu[(int)id].home);
 	} else {
-		return ((lgrp_handle_t)0); /* Default */
+		return ((lgrp_handle_t)LGRP_DEFAULT_HANDLE); /* Default */
 	}
 }