Mercurial > illumos > illumos-gate

changeset 5146:27fbcf92f645

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
PSARC 2007/322 Batoka 4U Platform Support FWARC 2007/529 Victoria Falls Perf Regs HV API 6586280 ON platform support for SUNW,T5440 6577856 sun4v xt_sync changes to aid timeout debugging
author svemuri
date Fri, 28 Sep 2007 11:01:47 -0700
parents 197186deb5d4
children 5e950ccc9585
files usr/src/pkgdefs/SUNWcart200.v/prototype_com usr/src/pkgdefs/SUNWkvmt200.v/prototype_com usr/src/uts/sun4v/Makefile.sun4v.shared usr/src/uts/sun4v/cpu/niagara_perfctr.c usr/src/uts/sun4v/maramba/Makefile usr/src/uts/sun4v/os/mach_cpu_states.c usr/src/uts/sun4v/sys/niagara2regs.h
diffstat 7 files changed, 464 insertions(+), 24 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/pkgdefs/SUNWcart200.v/prototype_com	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/pkgdefs/SUNWcart200.v/prototype_com	Fri Sep 28 11:01:47 2007 -0700
@@ -63,6 +63,7 @@
 s none platform/SUNW,SPARC-Enterprise-T5120=sun4v
 s none platform/SUNW,T5140=sun4v
 s none platform/SUNW,T5240=sun4v
+s none platform/SUNW,T5440=sun4v
 s none platform/SUNW,SPARC-Enterprise-T2000=SUNW,Sun-Fire-T200
 s none platform/SUNW,SPARC-Enterprise-T1000=sun4v
 s none platform/SUNW,Sun-Blade-T6300=sun4v
--- a/usr/src/pkgdefs/SUNWkvmt200.v/prototype_com	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/pkgdefs/SUNWkvmt200.v/prototype_com	Fri Sep 28 11:01:47 2007 -0700
@@ -141,6 +141,10 @@
 #
 s none usr/platform/SUNW,T5240=SUNW,T5140
 #
+# add Batoka link
+#
+s none usr/platform/SUNW,T5440=SUNW,T5140
+#
 # add erie fujitsu link
 #
 s none usr/platform/SUNW,SPARC-Enterprise-T1000=SUNW,Sun-Fire-T200
--- a/usr/src/uts/sun4v/Makefile.sun4v.shared	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/uts/sun4v/Makefile.sun4v.shared	Fri Sep 28 11:01:47 2007 -0700
@@ -38,6 +38,7 @@
 LINKED_PLATFORMS += SUNW,SPARC-Enterprise-T5220
 LINKED_PLATFORMS += SUNW,T5140
 LINKED_PLATFORMS += SUNW,T5240
+LINKED_PLATFORMS += SUNW,T5440
 LINKED_PLATFORMS += SUNW,SPARC-Enterprise-T1000
 LINKED_PLATFORMS += SUNW,Sun-Blade-T6300
 LINKED_PLATFORMS += SUNW,Sun-Blade-T6320
--- a/usr/src/uts/sun4v/cpu/niagara_perfctr.c	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/uts/sun4v/cpu/niagara_perfctr.c	Fri Sep 28 11:01:47 2007 -0700
@@ -41,8 +41,6 @@
 
 extern char cpu_module_name[];
 
-#define	NUM_OF_PICS	2
-
 /*
  * Data structure used to build array of event-names and pcr-mask values
  */
@@ -70,7 +68,7 @@
 	uint64_t	pic_mask[NUM_OF_PICS];
 	kstat_t		*pic_name_ksp[NUM_OF_PICS];
 	kstat_t		*cntr_ksp;
-	uint32_t	pic_reg;
+	uint32_t	pic_reg[NUM_OF_PICS];
 	uint32_t	pcr_reg;
 	uint32_t	pic_overflow[NUM_OF_PICS];	/* overflow count */
 	uint32_t	pic_last_val[NUM_OF_PICS];	/* last PIC value */
@@ -92,8 +90,67 @@
 	{HV_NIAGARA_DRAM_CTL1, HV_NIAGARA_DRAM_COUNT1},
 	{HV_NIAGARA_DRAM_CTL2, HV_NIAGARA_DRAM_COUNT2},
 	{HV_NIAGARA_DRAM_CTL3, HV_NIAGARA_DRAM_COUNT3},
+#ifdef VFALLS_IMPL
+	{HV_NIAGARA_DRAM_CTL4, HV_NIAGARA_DRAM_COUNT4},
+	{HV_NIAGARA_DRAM_CTL5, HV_NIAGARA_DRAM_COUNT5},
+	{HV_NIAGARA_DRAM_CTL6, HV_NIAGARA_DRAM_COUNT6},
+	{HV_NIAGARA_DRAM_CTL7, HV_NIAGARA_DRAM_COUNT7}
+#endif
 };
 
+#ifdef VFALLS_IMPL
+/*
+ * Kstat data structure for Zambezi performance counters
+ * These performance counters are 64 bits wide.
+ */
+static ni_ksinfo_t	*zam_lpu_kstats[ZAMBEZI_LPU_COUNTERS];
+static ni_ksinfo_t	*zam_gpd_kstats[ZAMBEZI_GPD_COUNTERS];
+static ni_ksinfo_t	*zam_asu_kstats[ZAMBEZI_ASU_COUNTERS];
+
+typedef struct zam_perf_regs {
+	uint32_t	pcr_reg;
+	uint32_t	pic_reg[NUM_OF_PICS];
+} zam_perf_regs_t;
+
+static zam_perf_regs_t lpu_perf_regs[] = {
+	{HV_ZAM0_LPU_A_PCR, HV_ZAM0_LPU_A_PIC0, HV_ZAM0_LPU_A_PIC1},
+	{HV_ZAM0_LPU_B_PCR, HV_ZAM0_LPU_B_PIC0, HV_ZAM0_LPU_B_PIC1},
+	{HV_ZAM0_LPU_C_PCR, HV_ZAM0_LPU_C_PIC0, HV_ZAM0_LPU_C_PIC1},
+	{HV_ZAM0_LPU_D_PCR, HV_ZAM0_LPU_D_PIC0, HV_ZAM0_LPU_D_PIC1},
+
+	{HV_ZAM1_LPU_A_PCR, HV_ZAM1_LPU_A_PIC0, HV_ZAM1_LPU_A_PIC1},
+	{HV_ZAM1_LPU_B_PCR, HV_ZAM1_LPU_B_PIC0, HV_ZAM1_LPU_B_PIC1},
+	{HV_ZAM1_LPU_C_PCR, HV_ZAM1_LPU_C_PIC0, HV_ZAM1_LPU_C_PIC1},
+	{HV_ZAM1_LPU_D_PCR, HV_ZAM1_LPU_D_PIC0, HV_ZAM1_LPU_D_PIC1},
+
+	{HV_ZAM2_LPU_A_PCR, HV_ZAM2_LPU_A_PIC0, HV_ZAM2_LPU_A_PIC1},
+	{HV_ZAM2_LPU_B_PCR, HV_ZAM2_LPU_B_PIC0, HV_ZAM2_LPU_B_PIC1},
+	{HV_ZAM2_LPU_C_PCR, HV_ZAM2_LPU_C_PIC0, HV_ZAM2_LPU_C_PIC1},
+	{HV_ZAM2_LPU_D_PCR, HV_ZAM2_LPU_D_PIC0, HV_ZAM2_LPU_D_PIC1},
+
+	{HV_ZAM3_LPU_A_PCR, HV_ZAM3_LPU_A_PIC0, HV_ZAM3_LPU_A_PIC1},
+	{HV_ZAM3_LPU_B_PCR, HV_ZAM3_LPU_B_PIC0, HV_ZAM3_LPU_B_PIC1},
+	{HV_ZAM3_LPU_C_PCR, HV_ZAM3_LPU_C_PIC0, HV_ZAM3_LPU_C_PIC1},
+	{HV_ZAM3_LPU_D_PCR, HV_ZAM3_LPU_D_PIC0, HV_ZAM3_LPU_D_PIC1}
+};
+
+static zam_perf_regs_t gpd_perf_regs[] = {
+	{HV_ZAM0_GPD_PCR, HV_ZAM0_GPD_PIC0, HV_ZAM0_GPD_PIC1},
+	{HV_ZAM1_GPD_PCR, HV_ZAM1_GPD_PIC0, HV_ZAM1_GPD_PIC1},
+	{HV_ZAM2_GPD_PCR, HV_ZAM2_GPD_PIC0, HV_ZAM2_GPD_PIC1},
+	{HV_ZAM3_GPD_PCR, HV_ZAM3_GPD_PIC0, HV_ZAM3_GPD_PIC1}
+};
+
+static zam_perf_regs_t asu_perf_regs[] = {
+	{HV_ZAM0_ASU_PCR, HV_ZAM0_ASU_PIC0, HV_ZAM0_ASU_PIC1},
+	{HV_ZAM1_ASU_PCR, HV_ZAM1_ASU_PIC0, HV_ZAM1_ASU_PIC1},
+	{HV_ZAM2_ASU_PCR, HV_ZAM2_ASU_PIC0, HV_ZAM2_ASU_PIC1},
+	{HV_ZAM3_ASU_PCR, HV_ZAM3_ASU_PIC0, HV_ZAM3_ASU_PIC1}
+};
+
+static int zam_cntr_kstat_update(kstat_t *, int);
+#endif
+
 static void ni_create_name_kstat(char *, ni_ksinfo_t *, ni_kev_mask_t *);
 static void ni_delete_name_kstat(ni_ksinfo_t *);
 
@@ -122,9 +179,78 @@
 	{"wr_queue_latency",	0x5},
 	{"rw_queue_latency",	0x6},
 	{"wb_buf_hits",		0x7},
-	{"clear_pic", 0xf}
+	{"clear_pic",		0xf}
 };
 
+#if defined(VFALLS_IMPL)
+/*
+ * Zambezi Performance Events
+ */
+static ni_kev_mask_t
+zam_lpu_perf_events[] = {
+	{"none",		0x0},
+	{"clock_cycles",	0x1},
+	{"cycles_c2c_portX",	0x2},
+	{"cycles_mem_portX",	0x3},
+	{"cycles_WB_portX",	0x4},
+	{"cycles_NC_portX",	0x5},
+	{"cycles_c2c_portY",	0x6},
+	{"cycles_mem_portY",	0x7},
+	{"cycles_WB_portY",	0x8},
+	{"cycles_NC_portY",	0x9},
+	{"cycles_c2c_portZ",	0xa},
+	{"cycles_mem_portZ",	0xb},
+	{"cycles_WB_portZ",	0xc},
+	{"cycles_NC_portZ",	0xd},
+	{"cycles_TID_WB",	0xe},
+	{"cycles_TID_INV",	0xf},
+	{"cycles_TID_RTD",	0x10},
+	{"cycles_TID_RTO",	0x11},
+	{"cycles_TID_RTS",	0x12},
+	{"cycles_IO_WRM",	0x13},
+	{"cycles_IO_RD",	0x14},
+	{"cycles_WB_egress",	0x15},
+	{"cycles_INV_egress",	0x16},
+	{"cycles_RTO_egress",	0x17},
+	{"cycles_RTD_egress",	0x18},
+	{"cycles_RTS_egress",	0x19},
+	{"cycles_no_WB",	0x1a},
+	{"cycles_no_read/inv",	0x1b},
+	{"cycles_HIT_M",	0x1c},
+	{"cycles_HIT_O",	0x1d},
+	{"cycles_HIT_S",	0x1e},
+	{"cycles_WB_HIT",	0x1f},
+	{"cycles_MISS",		0x20},
+	{"cycles_READ_or_INV",	0x21},
+	{"cycles_WB",		0x22},
+	{"cycles_NDR",		0x23},
+	{"cycles_cache_miss",	0x24},
+	{"cycles_cache_hit",	0x25},
+	{"cycles_CRC_errors",	0x26},
+	{"cycles_replys_sent",	0x27},
+	{"cycles_replys_recev",	0x28},
+	{"cycles_link_retrain",	0x29},
+	{"clear_pic",		0xff}
+};
+
+static ni_kev_mask_t
+zam_gpd_perf_events[] = {
+	{"none",		0x0},
+	{"clock_cycles",	0x1},
+	{"clear_pic",		0xf}
+};
+
+static ni_kev_mask_t
+zam_asu_perf_events[] = {
+	{"none",		0x0},
+	{"clock_cycles",	0x1},
+	{"asu_in_pck",		0x2},
+	{"asu_out_pck",		0x3},
+	{"asu_CAM_hit",		0x4},
+	{"asu_wakeup",		0x5},
+	{"clear_pic",		0xf}
+};
+#endif
 
 #if defined(NIAGARA_IMPL)
 /*
@@ -148,14 +274,15 @@
 #endif
 
 /*
- * Create the picN kstats for DRAM and JBUS events
+ * Create the picN kstats for DRAM, JBUS and Zambezi events
  */
 void
 niagara_kstat_init()
 {
 	int i;
 	ni_ksinfo_t *ksinfop;
-	uint64_t pic;
+	uint64_t pcr;
+	uint64_t stat;
 
 #ifdef DEBUG
 	if (ni_perf_debug)
@@ -168,8 +295,8 @@
 	for (i = 0; i < NIAGARA_DRAM_BANKS; i++) {
 #ifdef VFALLS_IMPL
 		/* check if this dram instance is enabled in the HW */
-		if (hv_niagara_getperf(dram_perf_regs[i].pic_reg, &pic) !=
-		    H_EINVAL) {
+		stat = hv_niagara_getperf(dram_perf_regs[i].pcr_reg, &pcr);
+		if ((stat != H_EINVAL) && (stat != H_ENOTSUPPORTED)) {
 #endif
 			ksinfop = (ni_ksinfo_t *)kmem_zalloc(
 			    sizeof (ni_ksinfo_t), KM_NOSLEEP);
@@ -189,7 +316,7 @@
 			ksinfop->pic_sel_shift[1] = NIAGARA_DRAM_PIC1_SEL_SHIFT;
 			ksinfop->pic_shift[1] = NIAGARA_DRAM_PIC1_SHIFT;
 			ksinfop->pic_mask[1] = NIAGARA_DRAM_PIC1_MASK;
-			ksinfop->pic_reg = dram_perf_regs[i].pic_reg;
+			ksinfop->pic_reg[0] = dram_perf_regs[i].pic_reg;
 			ksinfop->pcr_reg = dram_perf_regs[i].pcr_reg;
 			ni_dram_kstats[i] = ksinfop;
 
@@ -206,6 +333,117 @@
 #endif
 	}
 
+#ifdef VFALLS_IMPL
+	/*
+	 * Create Zambezi LPU perf events kstat
+	 */
+	for (i = 0; i < ZAMBEZI_LPU_COUNTERS; i++) {
+		/* check if this Zambezi LPU instance is enabled in the HW */
+		stat = hv_niagara_getperf(lpu_perf_regs[i].pcr_reg, &pcr);
+		if ((stat != H_EINVAL) && (stat != H_ENOTSUPPORTED)) {
+			ksinfop = (ni_ksinfo_t *)kmem_zalloc(
+			    sizeof (ni_ksinfo_t), KM_NOSLEEP);
+
+			if (ksinfop == NULL) {
+				cmn_err(CE_WARN,
+				    "%s: no space for zambezi lpu kstat\n",
+				    cpu_module_name);
+				break;
+			}
+			ksinfop->pic_no_evs =
+			    sizeof (zam_lpu_perf_events) /
+			    sizeof (ni_kev_mask_t);
+			ksinfop->pic_sel_shift[0] = ZAMBEZI_PIC0_SEL_SHIFT;
+			ksinfop->pic_reg[0] = lpu_perf_regs[i].pic_reg[0];
+			ksinfop->pic_sel_shift[1] = ZAMBEZI_PIC1_SEL_SHIFT;
+			ksinfop->pic_reg[1] = lpu_perf_regs[i].pic_reg[1];
+			ksinfop->pcr_reg = lpu_perf_regs[i].pcr_reg;
+			zam_lpu_kstats[i] = ksinfop;
+
+			/* create basic pic event/mask pair (only once) */
+			if (i == 0)
+				ni_create_name_kstat("lpu", ksinfop,
+				    zam_lpu_perf_events);
+
+			/* create counter kstats */
+			zam_lpu_kstats[i]->cntr_ksp = ni_create_cntr_kstat(
+			    "lpu", i, zam_cntr_kstat_update, ksinfop);
+		}
+	}
+	/*
+	 * Create Zambezi GPD perf events kstat
+	 */
+	for (i = 0; i < ZAMBEZI_GPD_COUNTERS; i++) {
+		/* check if this Zambezi GPD instance is enabled in the HW */
+		stat = hv_niagara_getperf(gpd_perf_regs[i].pcr_reg, &pcr);
+		if ((stat != H_EINVAL) && (stat != H_ENOTSUPPORTED)) {
+			ksinfop = (ni_ksinfo_t *)kmem_zalloc(
+			    sizeof (ni_ksinfo_t), KM_NOSLEEP);
+
+			if (ksinfop == NULL) {
+				cmn_err(CE_WARN,
+				    "%s: no space for zambezi gpd kstat\n",
+				    cpu_module_name);
+				break;
+			}
+			ksinfop->pic_no_evs =
+			    sizeof (zam_gpd_perf_events) /
+			    sizeof (ni_kev_mask_t);
+			ksinfop->pic_sel_shift[0] = ZAMBEZI_PIC0_SEL_SHIFT;
+			ksinfop->pic_reg[0] = gpd_perf_regs[i].pic_reg[0];
+			ksinfop->pic_sel_shift[1] = ZAMBEZI_PIC1_SEL_SHIFT;
+			ksinfop->pic_reg[1] = gpd_perf_regs[i].pic_reg[1];
+			ksinfop->pcr_reg = gpd_perf_regs[i].pcr_reg;
+			zam_gpd_kstats[i] = ksinfop;
+
+			/* create basic pic event/mask pair (only once) */
+			if (i == 0)
+				ni_create_name_kstat("gpd", ksinfop,
+				    zam_gpd_perf_events);
+
+			/* create counter kstats */
+			zam_lpu_kstats[i]->cntr_ksp = ni_create_cntr_kstat(
+			    "gpd", i, zam_cntr_kstat_update, ksinfop);
+		}
+	}
+	/*
+	 * Create Zambezi ASU perf events kstat
+	 */
+	for (i = 0; i < ZAMBEZI_ASU_COUNTERS; i++) {
+		/* check if this Zambezi ASU instance is enabled in the HW */
+		stat = hv_niagara_getperf(asu_perf_regs[i].pcr_reg, &pcr);
+		if ((stat != H_EINVAL) && (stat != H_ENOTSUPPORTED)) {
+			ksinfop = (ni_ksinfo_t *)kmem_zalloc(
+			    sizeof (ni_ksinfo_t), KM_NOSLEEP);
+
+			if (ksinfop == NULL) {
+				cmn_err(CE_WARN,
+				    "%s: no space for zambezi asu kstat\n",
+				    cpu_module_name);
+				break;
+			}
+			ksinfop->pic_no_evs =
+			    sizeof (zam_asu_perf_events) /
+			    sizeof (ni_kev_mask_t);
+			ksinfop->pic_sel_shift[0] = ZAMBEZI_PIC0_SEL_SHIFT;
+			ksinfop->pic_reg[0] = asu_perf_regs[i].pic_reg[0];
+			ksinfop->pic_sel_shift[1] = ZAMBEZI_PIC1_SEL_SHIFT;
+			ksinfop->pic_reg[1] = asu_perf_regs[i].pic_reg[1];
+			ksinfop->pcr_reg = asu_perf_regs[i].pcr_reg;
+			zam_asu_kstats[i] = ksinfop;
+
+			/* create basic pic event/mask pair (only once) */
+			if (i == 0)
+				ni_create_name_kstat("asu", ksinfop,
+				    zam_asu_perf_events);
+
+			/* create counter kstats */
+			zam_lpu_kstats[i]->cntr_ksp = ni_create_cntr_kstat(
+			    "asu", i, zam_cntr_kstat_update, ksinfop);
+		}
+	}
+#endif
+
 #if defined(NIAGARA_IMPL)
 	/*
 	 * Create JBUS perf events kstat
@@ -225,7 +463,7 @@
 		ni_jbus_kstat->pic_sel_shift[1] = NIAGARA_JBUS_PIC1_SEL_SHIFT;
 		ni_jbus_kstat->pic_shift[1] = NIAGARA_JBUS_PIC1_SHIFT;
 		ni_jbus_kstat->pic_mask[1] = NIAGARA_JBUS_PIC1_MASK;
-		ni_jbus_kstat->pic_reg = HV_NIAGARA_JBUS_COUNT;
+		ni_jbus_kstat->pic_reg[0] = HV_NIAGARA_JBUS_COUNT;
 		ni_jbus_kstat->pcr_reg = HV_NIAGARA_JBUS_CTL;
 		ni_create_name_kstat("jbus", ni_jbus_kstat,
 		    niagara_jbus_events);
@@ -244,6 +482,7 @@
 	if (ni_perf_debug)
 		printf("ni_kstat_fini called\n");
 #endif
+
 	for (i = 0; i < NIAGARA_DRAM_BANKS; i++) {
 		if (ni_dram_kstats[i] != NULL) {
 			ni_delete_name_kstat(ni_dram_kstats[i]);
@@ -254,6 +493,38 @@
 		}
 	}
 
+#if defined(VFALLS_IMPL)
+	for (i = 0; i < ZAMBEZI_LPU_COUNTERS; i++) {
+		if (zam_lpu_kstats[i] != NULL) {
+			ni_delete_name_kstat(zam_lpu_kstats[i]);
+			if (zam_lpu_kstats[i]->cntr_ksp != NULL)
+				kstat_delete(zam_lpu_kstats[i]->cntr_ksp);
+			kmem_free(zam_lpu_kstats[i], sizeof (ni_ksinfo_t));
+			zam_lpu_kstats[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < ZAMBEZI_GPD_COUNTERS; i++) {
+		if (zam_gpd_kstats[i] != NULL) {
+			ni_delete_name_kstat(zam_gpd_kstats[i]);
+			if (zam_gpd_kstats[i]->cntr_ksp != NULL)
+				kstat_delete(zam_gpd_kstats[i]->cntr_ksp);
+			kmem_free(zam_gpd_kstats[i], sizeof (ni_ksinfo_t));
+			zam_gpd_kstats[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < ZAMBEZI_ASU_COUNTERS; i++) {
+		if (zam_asu_kstats[i] != NULL) {
+			ni_delete_name_kstat(zam_asu_kstats[i]);
+			if (zam_asu_kstats[i]->cntr_ksp != NULL)
+				kstat_delete(zam_asu_kstats[i]->cntr_ksp);
+			kmem_free(zam_asu_kstats[i], sizeof (ni_ksinfo_t));
+			zam_asu_kstats[i] = NULL;
+		}
+	}
+#endif
+
 #if defined(NIAGARA_IMPL)
 	if (ni_jbus_kstat != NULL) {
 		ni_delete_name_kstat(ni_jbus_kstat);
@@ -416,6 +687,63 @@
 	return (counters_ksp);
 }
 
+#if defined(VFALLS_IMPL)
+/*
+ * zambezi kstat update function. Handles reads/writes
+ * from/to kstat.
+ */
+static int
+zam_cntr_kstat_update(kstat_t *ksp, int rw)
+{
+	struct kstat_named	*data_p;
+	ni_ksinfo_t	*ksinfop = ksp->ks_private;
+	uint64_t	pic0, pic1, pcr;
+	int		stat = 0;
+	uint64_t	pic0_stat = 0, pic1_stat = 0, pcr_stat = 0;
+
+	data_p = (struct kstat_named *)ksp->ks_data;
+
+	if (rw == KSTAT_WRITE) {
+#ifdef DEBUG
+		if (ni_perf_debug)
+			printf("zam_cntr_kstat_update: wr pcr-%d: %lx\n",
+			    ksinfop->pcr_reg, data_p[0].value.ui64);
+#endif
+		if (hv_niagara_setperf(ksinfop->pcr_reg, data_p[0].value.ui64))
+			stat = EACCES;
+	} else {
+		do {
+			pic0_stat = hv_niagara_getperf(ksinfop->pic_reg[0],
+			    &pic0);
+		} while (pic0_stat == H_EWOULDBLOCK);
+		do {
+			pic1_stat = hv_niagara_getperf(ksinfop->pic_reg[1],
+			    &pic1);
+		} while (pic1_stat == H_EWOULDBLOCK);
+		do {
+			pcr_stat = hv_niagara_getperf(ksinfop->pcr_reg,
+			    &pcr);
+		} while (pcr_stat == H_EWOULDBLOCK);
+		if (pic0_stat != 0 || pic1_stat != 0 || pcr_stat != 0)
+			stat = EACCES;
+		else {
+			data_p[0].value.ui64 = pcr;
+			data_p[1].value.ui64 = pic0;
+			data_p[2].value.ui64 = pic1;
+		}
+#ifdef DEBUG
+		if (ni_perf_debug)
+			printf("zam_cntr_kstat_update: rd pcr%d: %lx  "
+			    "pic0: %16lx pic1: %16lx\n",
+			    ksinfop->pcr_reg, pcr,
+			    data_p[1].value.ui64, data_p[2].value.ui64);
+#endif
+	}
+
+	return (stat);
+}
+#endif
+
 /*
  * kstat update function. Handles reads/writes
  * from/to kstat.
@@ -440,7 +768,7 @@
 		if (hv_niagara_setperf(ksinfop->pcr_reg, data_p[0].value.ui64))
 			stat = EACCES;
 	} else {
-		if (hv_niagara_getperf(ksinfop->pic_reg, &pic) != 0 ||
+		if (hv_niagara_getperf(ksinfop->pic_reg[0], &pic) != 0 ||
 		    hv_niagara_getperf(ksinfop->pcr_reg, &pcr) != 0)
 			stat = EACCES;
 		else {
@@ -473,7 +801,7 @@
 		if (ni_perf_debug)
 			printf("ni_cntr_kstat_update: rd pcr%d: %lx  "
 			    "pic%d: %16lx pic0: %8lx pic1: %8lx\n",
-			    ksinfop->pcr_reg, pcr, ksinfop->pic_reg, pic,
+			    ksinfop->pcr_reg, pcr, ksinfop->pic_reg[0], pic,
 			    data_p[1].value.ui64, data_p[2].value.ui64);
 #endif
 	}
--- a/usr/src/uts/sun4v/maramba/Makefile	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/uts/sun4v/maramba/Makefile	Fri Sep 28 11:01:47 2007 -0700
@@ -71,6 +71,7 @@
 
 IMPLEMENTED_PLATFORM	= SUNW,T5140
 LINKED_PLATFORMS	= SUNW,T5240
+LINKED_PLATFORMS	+= SUNW,T5440
 
 $(LINKED_PLATFORMS:%=$(USR_PLAT_DIR)/%): $(USR_PLAT_DIR)
 	$(INS.slink3)
--- a/usr/src/uts/sun4v/os/mach_cpu_states.c	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/uts/sun4v/os/mach_cpu_states.c	Fri Sep 28 11:01:47 2007 -0700
@@ -258,7 +258,6 @@
 	} else {
 		mach_set_soft_state(SIS_TRANSITION,
 		    &SOLARIS_SOFT_STATE_REBOOT_MSG);
-
 		reboot_machine(bootstr);
 	}
 	/* MAYBE REACHED */
@@ -1191,7 +1190,7 @@
 		uint8_t volatile byte[NCPU];
 		uint64_t volatile xword[NCPU / 8];
 	} cpu_sync;
-	uint64_t starttick, endtick, tick, lasttick;
+	uint64_t starttick, endtick, tick, lasttick, traptrace_id;
 	uint_t largestid, smallestid;
 	int i, j;
 
@@ -1222,8 +1221,15 @@
 		cpu_sync.byte[largestid] = 1;
 	}
 
+	/*
+	 * To help debug xt_sync panic, each mondo is uniquely identified
+	 * by passing the tick value, traptrace_id as the second mondo
+	 * argument to xt_some which is logged in CPU's mondo queue,
+	 * traptrace buffer and the panic message.
+	 */
+	traptrace_id = gettick();
 	xt_some(cpuset, (xcfunc_t *)xt_sync_tl1,
-	    (uint64_t)cpu_sync.byte, 0);
+	    (uint64_t)cpu_sync.byte, traptrace_id);
 
 	starttick = lasttick = gettick();
 	endtick = starttick + xc_tick_limit;
@@ -1244,12 +1250,18 @@
 				if (panic_quiesce)
 					goto out;
 				cmn_err(CE_CONT, "Cross trap sync timeout:  "
-				    "cpuids:");
+				    "at cpu_sync.xword[%d]: 0x%lx "
+				    "cpu_sync.byte: 0x%lx "
+				    "starttick: 0x%lx endtick: 0x%lx "
+				    "traptrace_id = 0x%lx\n",
+				    i, cpu_sync.xword[i],
+				    (uint64_t)cpu_sync.byte,
+				    starttick, endtick, traptrace_id);
+				cmn_err(CE_CONT, "CPUIDs:");
 				for (j = (i * 8); j <= largestid; j++) {
 					if (cpu_sync.byte[j] != 0)
 						cmn_err(CE_CONT, " 0x%x", j);
 				}
-				cmn_err(CE_CONT, "\n");
 				cmn_err(CE_PANIC, "xt_sync: timeout");
 			}
 		}
@@ -1457,8 +1469,8 @@
 	if (soft_state_initialized && *string_ra) {
 		rc = hv_soft_state_set(state, *string_ra);
 		if (rc != H_EOK) {
-			cmn_err(CE_WARN, "hv_soft_state_set returned %ld\n",
-			    rc);
+			cmn_err(CE_WARN,
+			    "hv_soft_state_set returned %ld\n", rc);
 		}
 	}
 }
@@ -1471,8 +1483,8 @@
 	if (soft_state_initialized && *string_ra) {
 		rc = hv_soft_state_get(*string_ra, state);
 		if (rc != H_EOK) {
-			cmn_err(CE_WARN, "hv_soft_state_get returned %ld\n",
-			    rc);
+			cmn_err(CE_WARN,
+			    "hv_soft_state_get returned %ld\n", rc);
 			*state = -1;
 		}
 	}
--- a/usr/src/uts/sun4v/sys/niagara2regs.h	Fri Sep 28 09:20:49 2007 -0700
+++ b/usr/src/uts/sun4v/sys/niagara2regs.h	Fri Sep 28 11:01:47 2007 -0700
@@ -102,8 +102,6 @@
 /*
  * Niagara2 DRAM performance counters
  */
-#define	NIAGARA_DRAM_BANKS		0x4
-
 #define	NIAGARA_DRAM_PIC0_SEL_SHIFT	0x4
 #define	NIAGARA_DRAM_PIC1_SEL_SHIFT	0x0
 
@@ -117,6 +115,8 @@
  * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF
  * and HV_NIAGARA2_SETPERF for Niagara2
  */
+#define	NIAGARA_DRAM_BANKS		0x4
+
 #define	HV_NIAGARA_SPARC_CTL		0x0
 #define	HV_NIAGARA_DRAM_CTL0		0x1
 #define	HV_NIAGARA_DRAM_COUNT0		0x2
@@ -131,8 +131,10 @@
 /*
  * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF
  * and HV_VFALLS_SETPERF for Victoria Falls
- * Support for 2-node configuration
+ * Support for 4-node configuration
  */
+#define	NIAGARA_DRAM_BANKS		0x8
+
 #define	HV_NIAGARA_SPARC_CTL		0x0
 #define	HV_NIAGARA_L2_CTL		0x1
 #define	HV_NIAGARA_DRAM_CTL0		0x2
@@ -143,6 +145,97 @@
 #define	HV_NIAGARA_DRAM_COUNT2		0x7
 #define	HV_NIAGARA_DRAM_CTL3		0x8
 #define	HV_NIAGARA_DRAM_COUNT3		0x9
+#define	HV_NIAGARA_DRAM_CTL4		0xa
+#define	HV_NIAGARA_DRAM_COUNT4		0xb
+#define	HV_NIAGARA_DRAM_CTL5		0xc
+#define	HV_NIAGARA_DRAM_COUNT5		0xd
+#define	HV_NIAGARA_DRAM_CTL6		0xe
+#define	HV_NIAGARA_DRAM_COUNT6		0xf
+#define	HV_NIAGARA_DRAM_CTL7		0x10
+#define	HV_NIAGARA_DRAM_COUNT7		0x11
+
+#define	ZAMBEZI_PIC0_SEL_SHIFT		0x0
+#define	ZAMBEZI_PIC1_SEL_SHIFT		0x8
+
+#define	ZAMBEZI_LPU_COUNTERS		0x10
+#define	ZAMBEZI_GPD_COUNTERS		0x4
+#define	ZAMBEZI_ASU_COUNTERS		0x4
+
+#define	HV_ZAM0_LPU_A_PCR		0x12
+#define	HV_ZAM0_LPU_A_PIC0		0x13
+#define	HV_ZAM0_LPU_A_PIC1		0x14
+#define	HV_ZAM0_LPU_B_PCR		0x15
+#define	HV_ZAM0_LPU_B_PIC0		0x16
+#define	HV_ZAM0_LPU_B_PIC1		0x17
+#define	HV_ZAM0_LPU_C_PCR		0x18
+#define	HV_ZAM0_LPU_C_PIC0		0x19
+#define	HV_ZAM0_LPU_C_PIC1		0x1a
+#define	HV_ZAM0_LPU_D_PCR		0x1b
+#define	HV_ZAM0_LPU_D_PIC0		0x1c
+#define	HV_ZAM0_LPU_D_PIC1		0x1d
+#define	HV_ZAM0_GPD_PCR			0x1e
+#define	HV_ZAM0_GPD_PIC0		0x1f
+#define	HV_ZAM0_GPD_PIC1		0x20
+#define	HV_ZAM0_ASU_PCR			0x21
+#define	HV_ZAM0_ASU_PIC0		0x22
+#define	HV_ZAM0_ASU_PIC1		0x23
+
+#define	HV_ZAM1_LPU_A_PCR		0x24
+#define	HV_ZAM1_LPU_A_PIC0		0x25
+#define	HV_ZAM1_LPU_A_PIC1		0x26
+#define	HV_ZAM1_LPU_B_PCR		0x27
+#define	HV_ZAM1_LPU_B_PIC0		0x28
+#define	HV_ZAM1_LPU_B_PIC1		0x29
+#define	HV_ZAM1_LPU_C_PCR		0x2a
+#define	HV_ZAM1_LPU_C_PIC0		0x2b
+#define	HV_ZAM1_LPU_C_PIC1		0x2c
+#define	HV_ZAM1_LPU_D_PCR		0x2d
+#define	HV_ZAM1_LPU_D_PIC0		0x2e
+#define	HV_ZAM1_LPU_D_PIC1		0x2f
+#define	HV_ZAM1_GPD_PCR			0x30
+#define	HV_ZAM1_GPD_PIC0		0x31
+#define	HV_ZAM1_GPD_PIC1		0x32
+#define	HV_ZAM1_ASU_PCR			0x33
+#define	HV_ZAM1_ASU_PIC0		0x34
+#define	HV_ZAM1_ASU_PIC1		0x35
+
+#define	HV_ZAM2_LPU_A_PCR		0x36
+#define	HV_ZAM2_LPU_A_PIC0		0x37
+#define	HV_ZAM2_LPU_A_PIC1		0x38
+#define	HV_ZAM2_LPU_B_PCR		0x39
+#define	HV_ZAM2_LPU_B_PIC0		0x3a
+#define	HV_ZAM2_LPU_B_PIC1		0x3b
+#define	HV_ZAM2_LPU_C_PCR		0x3c
+#define	HV_ZAM2_LPU_C_PIC0		0x3d
+#define	HV_ZAM2_LPU_C_PIC1		0x3e
+#define	HV_ZAM2_LPU_D_PCR		0x3f
+#define	HV_ZAM2_LPU_D_PIC0		0x40
+#define	HV_ZAM2_LPU_D_PIC1		0x41
+#define	HV_ZAM2_GPD_PCR			0x42
+#define	HV_ZAM2_GPD_PIC0		0x43
+#define	HV_ZAM2_GPD_PIC1		0x44
+#define	HV_ZAM2_ASU_PCR			0x45
+#define	HV_ZAM2_ASU_PIC0		0x46
+#define	HV_ZAM2_ASU_PIC1		0x47
+
+#define	HV_ZAM3_LPU_A_PCR		0x48
+#define	HV_ZAM3_LPU_A_PIC0		0x49
+#define	HV_ZAM3_LPU_A_PIC1		0x4a
+#define	HV_ZAM3_LPU_B_PCR		0x4b
+#define	HV_ZAM3_LPU_B_PIC0		0x4c
+#define	HV_ZAM3_LPU_B_PIC1		0x4d
+#define	HV_ZAM3_LPU_C_PCR		0x4e
+#define	HV_ZAM3_LPU_C_PIC0		0x4f
+#define	HV_ZAM3_LPU_C_PIC1		0x50
+#define	HV_ZAM3_LPU_D_PCR		0x51
+#define	HV_ZAM3_LPU_D_PIC0		0x52
+#define	HV_ZAM3_LPU_D_PIC1		0x53
+#define	HV_ZAM3_GPD_PCR			0x54
+#define	HV_ZAM3_GPD_PIC0		0x55
+#define	HV_ZAM3_GPD_PIC1		0x56
+#define	HV_ZAM3_ASU_PCR			0x57
+#define	HV_ZAM3_ASU_PIC0		0x58
+#define	HV_ZAM3_ASU_PIC1		0x59
 
 #define	VFALLS_L2_CTL_MASK		0x3
 #define	VFALLS_SL3_MASK			0x300