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changeset 2017:3437ed99f780

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6423162 sun4u px driver should not set TLU Control Register's NPWR_EN bit
author jroberts
date Fri, 19 May 2006 10:25:13 -0700
parents 694146304566
children 97fd76adc7d3
files usr/src/uts/sun4u/io/px/px_hlib.c
diffstat 1 files changed, 3 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/sun4u/io/px/px_hlib.c	Fri May 19 07:34:55 2006 -0700
+++ b/usr/src/uts/sun4u/io/px/px_hlib.c	Fri May 19 10:25:13 2006 -0700
@@ -346,12 +346,12 @@
 	 * Link Control register?  Both are hardware dependent and likely
 	 * set by OBP.
 	 *
-	 * Disable non-posted write bit - ordering by setting
-	 * NPWR_EN bit to force serialization of writes.
+	 * NOTE: Do not set the NPWR_EN bit.  The desired value of this bit
+	 * will be set by OBP.
 	 */
 	val = CSR_XR(csr_base, TLU_CONTROL);
 	val |= (TLU_CONTROL_L0S_TIM_DEFAULT << TLU_CONTROL_L0S_TIM) |
-	    (1ull << TLU_CONTROL_NPWR_EN) | TLU_CONTROL_CONFIG_DEFAULT;
+	    TLU_CONTROL_CONFIG_DEFAULT;
 
 	/*
 	 * For Oberon, NPWR_EN is set to 0 to prevent PIO reads from blocking