Mercurial > illumos > illumos-gate
changeset 6864:50c1b31ccb24
6695050 hxge needs 32 bit (i386) version for boot net
6695773 hxge_rx_hw_blank may cause memory corruption
6706704 Driver workaround for "The hardware returns incorrect rbr blocks sometimes at driver startup"
6706708 Driver workaround for "RcrQlen value may not be consistent with the RCR memory state"
6707996 hxge needs to implement workaround for errant hardware rtab parity errors
6709118 kstat counters for VMAC need to be 64 bit
6709127 kstat counters for rx and tx jumbo frames need fix
6709138 rcr_to and rcr_thres crossing messages are not needed to be logged
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--- a/usr/src/pkgdefs/SUNWhxge/postinstall Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/pkgdefs/SUNWhxge/postinstall Thu Jun 12 13:25:54 2008 -0700 @@ -26,8 +26,6 @@ # ident "%Z%%M% %I% %E% SMI" # -set -u - PATH="/usr/bin:/usr/sbin:${PATH}" export PATH @@ -68,8 +66,7 @@ if [ $? -eq 1 ]; then ${ADD_DRV} -m "${DRVPERM}" -i "${DRVALIAS}" ${DRV} if [ $? -ne 0 ]; then - echo "\nFailed add_drv!\n" >&2 - exit 1 + echo "\nFailed add_drv!\n" fi fi
--- a/usr/src/pkgdefs/SUNWhxge/prototype_i386 Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/pkgdefs/SUNWhxge/prototype_i386 Thu Jun 12 13:25:54 2008 -0700 @@ -44,5 +44,6 @@ # # SUN 10Gb hxge NIC driver +f none kernel/drv/hxge 0755 root sys d none kernel/drv/amd64 0755 root sys f none kernel/drv/amd64/hxge 0755 root sys
--- a/usr/src/uts/common/io/hxge/hpi_pfc.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_pfc.c Thu Jun 12 13:25:54 2008 -0700 @@ -272,8 +272,13 @@ (void) hpi_pfc_get_config(handle, &config); - bit = 1 << slot; - config.bits.mac_addr_en = config.bits.mac_addr_en | bit; + if (slot < 24) { + bit = 1 << slot; + config.bits.mac_addr_en_l = config.bits.mac_addr_en_l | bit; + } else { + bit = 1 << (slot - 24); + config.bits.mac_addr_en = config.bits.mac_addr_en | bit; + } return (hpi_pfc_set_config(handle, config)); } @@ -290,8 +295,13 @@ (void) hpi_pfc_get_config(handle, &config); - bit = 1 << slot; - config.bits.mac_addr_en = config.bits.mac_addr_en & ~bit; + if (slot < 24) { + bit = 1 << slot; + config.bits.mac_addr_en_l = config.bits.mac_addr_en_l & ~bit; + } else { + bit = 1 << (slot - 24); + config.bits.mac_addr_en = config.bits.mac_addr_en & ~bit; + } return (hpi_pfc_set_config(handle, config)); } @@ -425,8 +435,10 @@ offset = PFC_MAC_ADDRESS(slot); moffset = PFC_MAC_ADDRESS_MASK(slot); - addr.bits.addr = address; + addr.bits.addr = address >> 32; + addr.bits.addr_l = address & 0xffffffff; mask.bits.mask = 0x0; + mask.bits.mask_l = 0x0; REG_PIO_WRITE64(handle, offset, addr.value); REG_PIO_WRITE64(handle, moffset, mask.value);
--- a/usr/src/uts/common/io/hxge/hpi_rxdma.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_rxdma.c Thu Jun 12 13:25:54 2008 -0700 @@ -27,6 +27,7 @@ #include <hpi_rxdma.h> #include <hxge_common.h> +#include <hxge_impl.h> #define RXDMA_RESET_TRY_COUNT 5 #define RXDMA_RESET_DELAY 5
--- a/usr/src/uts/common/io/hxge/hpi_rxdma.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_rxdma.h Thu Jun 12 13:25:54 2008 -0700 @@ -114,9 +114,9 @@ channel)), (data_p))\ } -#define RXDMA_REG_READ32(handle, reg, channel) \ - HXGE_HPI_PIO_READ32(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ - channel))) +#define RXDMA_REG_READ32(handle, reg, channel, data_p) \ + HXGE_REG_RD32(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ + channel)), (data_p)) #define RXDMA_REG_WRITE64(handle, reg, channel, data) {\ HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ @@ -157,7 +157,7 @@ (offset == SW_OFFSET_128)) #define RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64)) -#define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512)) +#define RXDMA_RCR_THRESH_VALID(thresh) ((thresh <= 0x8000)) #define hpi_rxdma_rdc_rcr_flush(handle, rdc) \ RXDMA_REG_WRITE64(handle, RDC_RCR_FLUSH, rdc, \
--- a/usr/src/uts/common/io/hxge/hpi_txdma.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_txdma.c Thu Jun 12 13:25:54 2008 -0700 @@ -26,14 +26,13 @@ #pragma ident "%Z%%M% %I% %E% SMI" #include <hpi_txdma.h> +#include <hxge_impl.h> #define TXDMA_WAIT_LOOP 10000 #define TXDMA_WAIT_MSEC 5 static hpi_status_t hpi_txdma_control_reset_wait(hpi_handle_t handle, uint8_t channel); -static hpi_status_t hpi_txdma_control_stop_wait(hpi_handle_t handle, - uint8_t channel); hpi_status_t hpi_txdma_log_page_handle_set(hpi_handle_t handle, uint8_t channel, @@ -347,7 +346,8 @@ desc_p->bits.tr_len, transfer_len)); } desc_p->bits.tr_len = transfer_len; - desc_p->bits.sad = dma_ioaddr; + desc_p->bits.sad = dma_ioaddr >> 32; + desc_p->bits.sad_l = dma_ioaddr & 0xffffffff; HPI_DEBUG_MSG((handle.function, HPI_TDC_CTL, "hpi_txdma_gather_set: xfer len %d to set (%d)", @@ -415,9 +415,10 @@ " desc_p $%p descriptor entry %d\n", desc_p, desc_index)); desc.value = 0; desp = ((desc_p != NULL) ? desc_p : (p_tx_desc_t)&desc); - desp->value = HXGE_MEM_PIO_READ64(handle); + HXGE_MEM_PIO_READ64(handle, &desp->value); #ifdef HXGE_DEBUG sad = desp->bits.sad; + sad = (sad << 32) | desp->bits.sad_l; xfer_len = desp->bits.tr_len; #endif HPI_DEBUG_MSG((handle.function, HPI_TDC_CTL, "\n\t: value 0x%llx\n" @@ -461,7 +462,7 @@ return (HPI_SUCCESS); } -static hpi_status_t +hpi_status_t hpi_txdma_control_stop_wait(hpi_handle_t handle, uint8_t channel) { tdc_tdr_cfg_t txcs;
--- a/usr/src/uts/common/io/hxge/hpi_txdma.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_txdma.h Thu Jun 12 13:25:54 2008 -0700 @@ -125,6 +125,8 @@ p_tx_desc_t desc_p, uint8_t gather_index, boolean_t mark, uint8_t ngathers, uint64_t dma_ioaddr, uint32_t transfer_len); +hpi_status_t hpi_txdma_control_stop_wait(hpi_handle_t handle, + uint8_t channel); hpi_status_t hpi_txdma_desc_set_xfer_len(hpi_handle_t handle, p_tx_desc_t desc_p, uint32_t transfer_len);
--- a/usr/src/uts/common/io/hxge/hpi_vir.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_vir.c Thu Jun 12 13:25:54 2008 -0700 @@ -27,6 +27,7 @@ #include <hpi_vir.h> #include <hxge_defs.h> +#include <hxge_impl.h> /* * Set up a logical group number that a logical device belongs to.
--- a/usr/src/uts/common/io/hxge/hpi_vmac.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hpi_vmac.c Thu Jun 12 13:25:54 2008 -0700 @@ -25,6 +25,7 @@ #pragma ident "%Z%%M% %I% %E% SMI" +#include <hxge_impl.h> #include <hpi_vmac.h> #define HXGE_VMAC_RX_STAT_CLEAR 0x1ffULL
--- a/usr/src/uts/common/io/hxge/hxge.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge.h Thu Jun 12 13:25:54 2008 -0700 @@ -350,6 +350,8 @@ uint32_t hxge_port_rcr_size; uint32_t hxge_port_tx_ring_size; hxge_mmac_t hxge_mmac_info; + + kmutex_t pio_lock; }; /*
--- a/usr/src/uts/common/io/hxge/hxge_common_impl.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_common_impl.h Thu Jun 12 13:25:54 2008 -0700 @@ -105,7 +105,11 @@ typedef ddi_acc_handle_t hxge_os_acc_handle_t; typedef hxge_os_acc_handle_t hpi_reg_handle_t; +#if defined(__i386) +typedef uint32_t hpi_reg_ptr_t; +#else typedef uint64_t hpi_reg_ptr_t; +#endif typedef ddi_dma_handle_t hxge_os_dma_handle_t; typedef struct _hxge_dma_common_t hxge_os_dma_common_t; @@ -132,140 +136,100 @@ #define HXGE_DELAY(microseconds) (drv_usecwait(microseconds)) -#define HXGE_PIO_READ8(handle, devaddr, offset) \ - (ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset))) - -#define HXGE_PIO_READ16(handle, devaddr, offset) \ - (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset))) - -#define HXGE_PIO_READ32(handle, devaddr, offset) \ - (ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset))) - -#define HXGE_PIO_READ64(handle, devaddr, offset) \ - (ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset))) - -#define HXGE_PIO_WRITE8(handle, devaddr, offset, data) \ - (ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data)) - -#define HXGE_PIO_WRITE16(handle, devaddr, offset, data) \ - (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data)) - -#define HXGE_PIO_WRITE32(handle, devaddr, offset, data) \ - (ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data)) - -#define HXGE_PIO_WRITE64(handle, devaddr, offset, data) \ - (ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data)) - -#define HXGE_HPI_PIO_READ8(hpi_handle, offset) \ - (ddi_get8(HPI_REGH(hpi_handle), \ - (uint8_t *)(HPI_REGP(hpi_handle) + offset))) - -#define HXGE_HPI_PIO_READ16(hpi_handle, offset) \ - (ddi_get16(HPI_REGH(hpi_handle), \ - (uint16_t *)(HPI_REGP(hpi_handle) + offset))) - +/* + * HXGE_HPI_PIO_READ32 and HXGE_HPI_PIO_READ64 should not be called directly + * on 32 bit platforms + */ #define HXGE_HPI_PIO_READ32(hpi_handle, offset) \ (ddi_get32(HPI_REGH(hpi_handle), \ (uint32_t *)(HPI_REGP(hpi_handle) + offset))) +#if defined(__i386) +#define HXGE_HPI_PIO_READ64(hpi_handle, offset) \ + (ddi_get64(HPI_REGH(hpi_handle), \ + (uint64_t *)(HPI_REGP(hpi_handle) + (uint32_t)offset))) +#else #define HXGE_HPI_PIO_READ64(hpi_handle, offset) \ (ddi_get64(HPI_REGH(hpi_handle), \ (uint64_t *)(HPI_REGP(hpi_handle) + offset))) - -#define HXGE_HPI_PIO_WRITE8(hpi_handle, offset, data) \ - (ddi_put8(HPI_REGH(hpi_handle), \ - (uint8_t *)(HPI_REGP(hpi_handle) + offset), data)) - -#define HXGE_HPI_PIO_WRITE16(hpi_handle, offset, data) \ - (ddi_put16(HPI_REGH(hpi_handle), \ - (uint16_t *)(HPI_REGP(hpi_handle) + offset), data)) - -#define HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) \ - (ddi_put32(HPI_REGH(hpi_handle), \ - (uint32_t *)(HPI_REGP(hpi_handle) + offset), data)) - -#define HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) \ - (ddi_put64(HPI_REGH(hpi_handle), \ - (uint64_t *)(HPI_REGP(hpi_handle) + offset), data)) - -#define HXGE_MEM_PIO_READ8(hpi_handle) \ - (ddi_get8(HPI_REGH(hpi_handle), (uint8_t *)HPI_REGP(hpi_handle))) +#endif -#define HXGE_MEM_PIO_READ16(hpi_handle) \ - (ddi_get16(HPI_REGH(hpi_handle), (uint16_t *)HPI_REGP(hpi_handle))) - -#define HXGE_MEM_PIO_READ32(hpi_handle) \ - (ddi_get32(HPI_REGH(hpi_handle), (uint32_t *)HPI_REGP(hpi_handle))) - -#define HXGE_MEM_PIO_READ64(hpi_handle) \ - (ddi_get64(HPI_REGH(hpi_handle), (uint64_t *)HPI_REGP(hpi_handle))) - -#define HXGE_MEM_PIO_WRITE8(hpi_handle, data) \ - (ddi_put8(HPI_REGH(hpi_handle), (uint8_t *)HPI_REGP(hpi_handle), data)) - -#define HXGE_MEM_PIO_WRITE16(hpi_handle, data) \ - (ddi_put16(HPI_REGH(hpi_handle), \ - (uint16_t *)HPI_REGP(hpi_handle), data)) - -#define HXGE_MEM_PIO_WRITE32(hpi_handle, data) \ - (ddi_put32(HPI_REGH(hpi_handle), \ - (uint32_t *)HPI_REGP(hpi_handle), data)) +#if defined(__i386) -#define HXGE_MEM_PIO_WRITE64(hpi_handle, data) \ - (ddi_put64(HPI_REGH(hpi_handle), \ - (uint64_t *)HPI_REGP(hpi_handle), data)) - -#define FM_SERVICE_RESTORED(hxgep) \ - if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ - ddi_fm_service_impact(hxgep->dip, DDI_SERVICE_RESTORED) -#define HXGE_FM_REPORT_ERROR(hxgep, chan, ereport_id) \ - if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ - hxge_fm_report_error(hxgep, chan, ereport_id) - - -#if defined(REG_TRACE) -#define HXGE_REG_RD64(handle, offset, val_p) {\ - *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ - hpi_rtrace_update(handle, B_FALSE, &hpi_rtracebuf, (uint32_t)offset, \ - (uint64_t)(*(val_p)));\ +#define HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) { \ + MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ + ddi_put32(HPI_REGH(hpi_handle), \ + (uint32_t *)(HPI_REGP(hpi_handle) + \ + (uint32_t)offset), data); \ + MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ +} +#define HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) { \ + MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ + ddi_put64(HPI_REGH(hpi_handle), \ + (uint64_t *)(HPI_REGP(hpi_handle) + \ + (uint32_t)offset), data); \ + MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ } -#define HXGE_REG_WR64(handle, offset, val) {\ - HXGE_HPI_PIO_WRITE64(handle, (offset), (val));\ - hpi_rtrace_update(handle, B_TRUE, &hpi_rtracebuf, (uint32_t)offset,\ - (uint64_t)(val));\ +#define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ + MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ + *(val_p) = ddi_get64(HPI_REGH(hpi_handle), \ + (uint64_t *)HPI_REGP(hpi_handle)); \ + MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ +} +#define HXGE_MEM_PIO_WRITE64(hpi_handle, data) { \ + MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ + ddi_put64(HPI_REGH(hpi_handle), \ + (uint64_t *)HPI_REGP(hpi_handle), data); \ + MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock); \ } -#elif defined(REG_SHOW) - /* - * Send 0xbadbad to tell rs_show_reg that we do not have - * a valid RTBUF index to pass - */ -#define HXGE_REG_RD64(handle, offset, val_p) {\ - *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ - rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\ +#define HXGE_REG_RD64(handle, offset, val_p) { \ + MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock); \ + *(val_p) = HXGE_HPI_PIO_READ64(handle, offset); \ + MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock); \ } -/* - * Send 0xbadbad to tell rs_show_reg that we do not have - * a valid RTBUF index to pass - */ -#define HXGE_REG_WR64(handle, offset, val) {\ - HXGE_HPI_PIO_WRITE64(handle, offset, (val));\ - rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\ +#define HXGE_REG_RD32(handle, offset, val_p) { \ + MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock); \ + *(val_p) = HXGE_HPI_PIO_READ32(handle, offset); \ + MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock); \ } + #else -#define HXGE_REG_RD64(handle, offset, val_p) {\ - *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ +#define HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) \ + (ddi_put32(HPI_REGH(hpi_handle), \ + (uint32_t *)(HPI_REGP(hpi_handle) + offset), data)) +#define HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) \ + (ddi_put64(HPI_REGH(hpi_handle), \ + (uint64_t *)(HPI_REGP(hpi_handle) + offset), data)) +#define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ + *(val_p) = ddi_get64(HPI_REGH(hpi_handle), \ + (uint64_t *)HPI_REGP(hpi_handle)); \ } -#define HXGE_REG_RD32(handle, offset, val_p) {\ - *(val_p) = HXGE_HPI_PIO_READ32(handle, offset);\ +#define HXGE_MEM_PIO_WRITE64(hpi_handle, data) \ + (ddi_put64(HPI_REGH(hpi_handle), \ + (uint64_t *)HPI_REGP(hpi_handle), data)) +#define HXGE_REG_RD64(handle, offset, val_p) { \ + *(val_p) = HXGE_HPI_PIO_READ64(handle, offset); \ } -#define HXGE_REG_WR64(handle, offset, val) {\ - HXGE_HPI_PIO_WRITE64(handle, (offset), (val));\ +#define HXGE_REG_RD32(handle, offset, val_p) { \ + *(val_p) = HXGE_HPI_PIO_READ32(handle, offset); \ +} + +#endif + +#define HXGE_REG_WR64(handle, offset, val) { \ + HXGE_HPI_PIO_WRITE64(handle, (offset), (val)); \ } -#define HXGE_REG_WR32(handle, offset, val) {\ - HXGE_HPI_PIO_WRITE32(handle, (offset), (val));\ +#define HXGE_REG_WR32(handle, offset, val) { \ + HXGE_HPI_PIO_WRITE32(handle, (offset), (val)); \ } -#endif + +#define FM_SERVICE_RESTORED(hxgep) \ + if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ + ddi_fm_service_impact(hxgep->dip, DDI_SERVICE_RESTORED) +#define HXGE_FM_REPORT_ERROR(hxgep, chan, ereport_id) \ + if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ + hxge_fm_report_error(hxgep, chan, ereport_id) #ifdef __cplusplus }
--- a/usr/src/uts/common/io/hxge/hxge_hw.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_hw.c Thu Jun 12 13:25:54 2008 -0700 @@ -390,8 +390,6 @@ if (estat.bits.tdc_err0 || estat.bits.tdc_err1) { /* TDMC */ - HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, - "==> hxge_syserr_intr: device error - TDMC")); (void) hxge_txdma_handle_sys_errors(hxgep); } else if (estat.bits.rdc_err0 || estat.bits.rdc_err1) { /* RDMC */
--- a/usr/src/uts/common/io/hxge/hxge_kstats.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_kstats.c Thu Jun 12 13:25:54 2008 -0700 @@ -209,18 +209,19 @@ } hxge_vmac_stat_index_t; hxge_kstat_index_t hxge_vmac_stats[] = { - {VMAC_STAT_TX_FRAME_CNT, KSTAT_DATA_ULONG, "vmac_tx_frame_cnt"}, - {VMAC_STAT_TX_BYTE_CNT, KSTAT_DATA_ULONG, "vmac_tx_byte_cnt"}, + {VMAC_STAT_TX_FRAME_CNT, KSTAT_DATA_UINT64, "vmac_tx_frame_cnt"}, + {VMAC_STAT_TX_BYTE_CNT, KSTAT_DATA_UINT64, "vmac_tx_byte_cnt"}, - {VMAC_STAT_RX_FRAME_CNT, KSTAT_DATA_ULONG, "vmac_rx_frame_cnt"}, - {VMAC_STAT_RX_BYTE_CNT, KSTAT_DATA_ULONG, "vmac_rx_byte_cnt"}, - {VMAC_STAT_RX_DROP_FRAME_CNT, KSTAT_DATA_ULONG, + {VMAC_STAT_RX_FRAME_CNT, KSTAT_DATA_UINT64, "vmac_rx_frame_cnt"}, + {VMAC_STAT_RX_BYTE_CNT, KSTAT_DATA_UINT64, "vmac_rx_byte_cnt"}, + {VMAC_STAT_RX_DROP_FRAME_CNT, KSTAT_DATA_UINT64, "vmac_rx_drop_frame_cnt"}, - {VMAC_STAT_RX_DROP_BYTE_CNT, KSTAT_DATA_ULONG, "vmac_rx_drop_byte_cnt"}, - {VMAC_STAT_RX_CRC_CNT, KSTAT_DATA_ULONG, "vmac_rx_crc_cnt"}, - {VMAC_STAT_RX_PAUSE_CNT, KSTAT_DATA_ULONG, "vmac_rx_pause_cnt"}, - {VMAC_STAT_RX_BCAST_FR_CNT, KSTAT_DATA_ULONG, "vmac_rx_bcast_fr_cnt"}, - {VMAC_STAT_RX_MCAST_FR_CNT, KSTAT_DATA_ULONG, "vmac_rx_mcast_fr_cnt"}, + {VMAC_STAT_RX_DROP_BYTE_CNT, KSTAT_DATA_UINT64, + "vmac_rx_drop_byte_cnt"}, + {VMAC_STAT_RX_CRC_CNT, KSTAT_DATA_UINT64, "vmac_rx_crc_cnt"}, + {VMAC_STAT_RX_PAUSE_CNT, KSTAT_DATA_UINT64, "vmac_rx_pause_cnt"}, + {VMAC_STAT_RX_BCAST_FR_CNT, KSTAT_DATA_UINT64, "vmac_rx_bcast_fr_cnt"}, + {VMAC_STAT_RX_MCAST_FR_CNT, KSTAT_DATA_UINT64, "vmac_rx_mcast_fr_cnt"}, {VMAC_STAT_END, NULL, NULL} };
--- a/usr/src/uts/common/io/hxge/hxge_main.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_main.c Thu Jun 12 13:25:54 2008 -0700 @@ -623,9 +623,6 @@ /* Tear down the kstat setup. */ hxge_destroy_kstats(hxgep); - /* Destroy all mutexes. */ - hxge_destroy_mutexes(hxgep); - /* * Remove the list of ndd parameters which were setup during attach. */ @@ -636,6 +633,13 @@ } /* + * Reset RDC, TDC, PFC, and VMAC blocks from PEU to clear any + * previous state before unmapping the registers. + */ + HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E); + HXGE_DELAY(1000); + + /* * Unmap the register setup. */ hxge_unmap_regs(hxgep); @@ -647,6 +651,9 @@ */ ddi_soft_state_free(hxge_list, hxgep->instance); + /* Destroy all mutexes. */ + hxge_destroy_mutexes(hxgep); + HXGE_DEBUG_MSG((NULL, DDI_CTL, "<== hxge_unattach")); } @@ -829,6 +836,8 @@ MUTEX_DRIVER, (void *) hxgep->interrupt_cookie); RW_INIT(&hxgep->filter_lock, NULL, RW_DRIVER, (void *) hxgep->interrupt_cookie); + MUTEX_INIT(&hxgep->pio_lock, NULL, + MUTEX_DRIVER, (void *) hxgep->interrupt_cookie); hxge_setup_mutexes_exit: HXGE_DEBUG_MSG((hxgep, DDI_CTL, @@ -847,6 +856,7 @@ RW_DESTROY(&hxgep->filter_lock); MUTEX_DESTROY(&hxgep->ouraddr_lock); MUTEX_DESTROY(hxgep->genlock); + MUTEX_DESTROY(&hxgep->pio_lock); if (hxge_debug_init == 1) { MUTEX_DESTROY(&hxgedebuglock); @@ -2503,9 +2513,10 @@ mrf.mrf_type = MAC_RX_FIFO; mrf.mrf_blank = hxge_rx_hw_blank; - - mrf.mrf_normal_blank_time = RXDMA_RCR_PTHRES_DEFAULT; - mrf.mrf_normal_pkt_count = RXDMA_RCR_TO_DEFAULT; + mrf.mrf_arg = (void *)hxgep; + + mrf.mrf_normal_blank_time = RXDMA_RCR_TO_DEFAULT; + mrf.mrf_normal_pkt_count = RXDMA_RCR_PTHRES_DEFAULT; rcr_rings = hxgep->rx_rcr_rings; rcr_p = rcr_rings->rcr_rings; @@ -2516,7 +2527,6 @@ */ for (i = 0; i < ndmas; i++) { rcrp = (void *)(p_rx_rcr_ring_t)rcr_p[i]; - mrf.mrf_arg = rcrp; rcrp->rcr_mac_handle = mac_resource_add(hxgep->mach, (mac_resource_t *)&mrf);
--- a/usr/src/uts/common/io/hxge/hxge_pfc.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_pfc.c Thu Jun 12 13:25:54 2008 -0700 @@ -200,10 +200,12 @@ key->blade_id = hxge_get_blade_id(hxgep); - mask->class_code = 0x1f; + mask->class_code = 0xf; + mask->class_code_l = 0x1; mask->blade_id = 0; mask->wild1 = 0x7ffffff; - mask->wild = ~0x0; + mask->wild = 0xffffffff; + mask->wild_l = 0xffffffff; location = class; @@ -687,7 +689,8 @@ static hxge_status_t hxge_pfc_config_init(p_hxge_t hxgep) { - hpi_handle_t handle; + hpi_handle_t handle; + block_reset_t reset_reg; handle = hxgep->hpi_reg_handle; if (hxgep->hxge_hw_p == NULL) { @@ -696,6 +699,12 @@ return (HXGE_ERROR); } + /* Reset PFC block from PEU to clear any previous state */ + reset_reg.value = 0; + reset_reg.bits.pfc_rst = 1; + HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); + HXGE_DELAY(1000); + (void) hpi_pfc_set_tcam_enable(handle, B_FALSE); (void) hpi_pfc_set_l2_hash(handle, B_FALSE); (void) hpi_pfc_set_tcp_cksum(handle, B_FALSE);
--- a/usr/src/uts/common/io/hxge/hxge_pfc.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_pfc.h Thu Jun 12 13:25:54 2008 -0700 @@ -87,27 +87,29 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t padding:34; - uint64_t reserved:15; - uint64_t parity:1; - uint64_t hit_count:4; - uint64_t channel_d:2; - uint64_t channel_c:2; - uint64_t channel_b:2; - uint64_t channel_a:2; - uint64_t source_hash:1; - uint64_t discard:1; + uint32_t padding:32; + uint32_t padding_l:2; + uint32_t reserved:15; + uint32_t parity:1; + uint32_t hit_count:4; + uint32_t channel_d:2; + uint32_t channel_c:2; + uint32_t channel_b:2; + uint32_t channel_a:2; + uint32_t source_hash:1; + uint32_t discard:1; #else - uint64_t discard:1; - uint64_t source_hash:1; - uint64_t channel_a:2; - uint64_t channel_b:2; - uint64_t channel_c:2; - uint64_t channel_d:2; - uint64_t hit_count:4; - uint64_t parity:1; - uint64_t reserved:15; - uint64_t padding:34; + uint32_t discard:1; + uint32_t source_hash:1; + uint32_t channel_a:2; + uint32_t channel_b:2; + uint32_t channel_c:2; + uint32_t channel_d:2; + uint32_t hit_count:4; + uint32_t parity:1; + uint32_t reserved:15; + uint32_t padding_l:2; + uint32_t padding:32; #endif } bits; } hxge_tcam_res_t, *p_hxge_tcam_res_t; @@ -124,47 +126,58 @@ typedef struct hxge_tcam_ipv4_S { #if defined(_BIG_ENDIAN) - uint32_t class_code:5; /* 99:95 */ + uint32_t class_code:4; /* 99:96 */ + uint32_t class_code_l:1; /* 95:95 */ uint32_t blade_id:4; /* 94:91 */ uint32_t rsrvd2:2; /* 90:89 */ uint32_t noport:1; /* 88 */ uint32_t protocol:8; /* 87:80 */ - uint32_t l4_hdr; /* 79:48 */ + uint32_t l4_hdr:16; /* 79:64 */ + uint32_t l4_hdr_l:16; /* 63:48 */ uint32_t rsrvd:16; /* 47:32 */ uint32_t ip_daddr; /* 31:0 */ #else uint32_t ip_daddr; /* 31:0 */ uint32_t rsrvd:16; /* 47:32 */ - uint32_t l4_hdr; /* 79:48 */ + uint32_t l4_hdr_l:16; /* 63:48 */ + uint32_t l4_hdr:16; /* 79:64 */ uint32_t protocol:8; /* 87:80 */ uint32_t noport:1; /* 88 */ uint32_t rsrvd2:2; /* 90:89 */ uint32_t blade_id:4; /* 94:91 */ - uint32_t class_code:5; /* 99:95 */ + uint32_t class_code_l:1; /* 95:95 */ + uint32_t class_code:4; /* 99:96 */ #endif } hxge_tcam_ipv4_t; typedef struct hxge_tcam_ipv6_S { #if defined(_BIG_ENDIAN) - uint32_t class_code:5; /* 99:95 */ + uint32_t class_code:4; /* 99:96 */ + uint32_t class_code_l:1; /* 95:95 */ uint32_t blade_id:4; /* 94:91 */ - uint64_t rsrvd2:3; /* 90:88 */ - uint64_t protocol:8; /* 87:80 */ - uint64_t l4_hdr:32; /* 79:48 */ - uint64_t rsrvd:48; /* 47:0 */ + uint32_t rsrvd2:3; /* 90:88 */ + uint32_t protocol:8; /* 87:80 */ + uint32_t l4_hdr:16; /* 79:64 */ + uint32_t l4_hdr_l:16; /* 63:48 */ + uint32_t rsrvd:16; /* 47:32 */ + uint32_t rsrvd_l:32; /* 31:0 */ #else - uint64_t rsrvd:48; /* 47:0 */ - uint64_t l4_hdr:32; /* 79:48 */ - uint64_t protocol:8; /* 87:80 */ - uint64_t rsrvd2:3; /* 90:88 */ + uint32_t rsrvd_l:32; /* 31:0 */ + uint32_t rsrvd:16; /* 47:32 */ + uint32_t l4_hdr_l:16; /* 63:48 */ + uint32_t l4_hdr:16; /* 79:64 */ + uint32_t protocol:8; /* 87:80 */ + uint32_t rsrvd2:3; /* 90:88 */ uint32_t blade_id:4; /* 94:91 */ - uint32_t class_code:5; /* 99:95 */ + uint32_t class_code_l:1; /* 95:95 */ + uint32_t class_code:4; /* 99:96 */ #endif } hxge_tcam_ipv6_t; typedef struct hxge_tcam_enet_S { #if defined(_BIG_ENDIAN) - uint8_t class_code:5; /* 99:95 */ + uint8_t class_code:4; /* 99:96 */ + uint8_t class_code_l:1; /* 95:95 */ uint8_t blade_id:4; /* 94:91 */ uint8_t rsrvd:3; /* 90:88 */ uint8_t eframe[11]; /* 87:0 */ @@ -172,23 +185,28 @@ uint8_t eframe[11]; /* 87:0 */ uint8_t rsrvd:3; /* 90:88 */ uint8_t blade_id:4; /* 94:91 */ - uint8_t class_code:5; /* 99:95 */ + uint8_t class_code_l:1; /* 95:95 */ + uint8_t class_code:4; /* 99:96 */ #endif } hxge_tcam_ether_t; typedef struct hxge_tcam_spread_S { #if defined(_BIG_ENDIAN) - uint64_t unused:28; /* 127:100 */ - uint64_t class_code:5; /* 99:95 */ - uint64_t blade_id:4; /* 94:91 */ - uint64_t wild1:27; /* 90:64 */ - uint64_t wild; /* 63:0 */ + uint32_t unused:28; /* 127:100 */ + uint32_t class_code:4; /* 99:96 */ + uint32_t class_code_l:1; /* 95:95 */ + uint32_t blade_id:4; /* 94:91 */ + uint32_t wild1:27; /* 90:64 */ + uint32_t wild; /* 63:32 */ + uint32_t wild_l; /* 31:0 */ #else - uint64_t wild; /* 63:0 */ - uint64_t wild1:27; /* 90:64 */ - uint64_t blade_id:4; /* 94:91 */ - uint64_t class_code:5; /* 99:95 */ - uint64_t unused:28; /* 127:100 */ + uint32_t wild_l; /* 31:0 */ + uint32_t wild; /* 63:32 */ + uint32_t wild1:27; /* 90:64 */ + uint32_t blade_id:4; /* 94:91 */ + uint32_t class_code_l:1; /* 95:95 */ + uint32_t class_code:4; /* 99:96 */ + uint32_t unused:28; /* 127:100 */ #endif } hxge_tcam_spread_t; @@ -215,34 +233,44 @@ #define mask1 mask.regs.reg1 #define ip4_class_key key.ipv4.class_code +#define ip4_class_key_l key.ipv4.class_code_l #define ip4_blade_id_key key.ipv4.blade_id #define ip4_noport_key key.ipv4.noport #define ip4_proto_key key.ipv4.protocol #define ip4_l4_hdr_key key.ipv4.l4_hdr +#define ip4_l4_hdr_key_l key.ipv4.l4_hdr_l #define ip4_dest_key key.ipv4.ip_daddr #define ip4_class_mask mask.ipv4.class_code +#define ip4_class_mask_l mask.ipv4.class_code_l #define ip4_blade_id_mask mask.ipv4.blade_id #define ip4_noport_mask mask.ipv4.noport #define ip4_proto_mask mask.ipv4.protocol #define ip4_l4_hdr_mask mask.ipv4.l4_hdr +#define ip4_l4_hdr_mask_l mask.ipv4.l4_hdr_l #define ip4_dest_mask mask.ipv4.ip_daddr #define ip6_class_key key.ipv6.class_code +#define ip6_class_key_l key.ipv6.class_code_l #define ip6_blade_id_key key.ipv6.blade_id #define ip6_proto_key key.ipv6.protocol #define ip6_l4_hdr_key key.ipv6.l4_hdr +#define ip6_l4_hdr_key_l key.ipv6.l4_hdr_l #define ip6_class_mask mask.ipv6.class_code +#define ip6_class_mask_l mask.ipv6.class_code_l #define ip6_blade_id_mask mask.ipv6.blade_id #define ip6_proto_mask mask.ipv6.protocol #define ip6_l4_hdr_mask mask.ipv6.l4_hdr +#define ip6_l4_hdr_mask_l mask.ipv6.l4_hdr_l #define ether_class_key key.enet.class_code +#define ether_class_key_l key.enet.class_code_l #define ether_blade_id_key key.enet.blade_id #define ether_ethframe_key key.enet.eframe #define ether_class_mask mask.enet.class_code +#define ether_class_mask_l mask.enet.class_code_l #define ether_blade_id_mask mask.enet.blade_id #define ether_ethframe_mask mask.enet.eframe
--- a/usr/src/uts/common/io/hxge/hxge_pfc_hw.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_pfc_hw.h Thu Jun 12 13:25:54 2008 -0700 @@ -80,13 +80,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:28; - uint64_t parity:4; - uint64_t member:32; + uint32_t rsrvd:28; + uint32_t parity:4; + uint32_t member:32; #else - uint64_t member:32; - uint64_t parity:4; - uint64_t rsrvd:28; + uint32_t member:32; + uint32_t parity:4; + uint32_t rsrvd:28; #endif } bits; } pfc_vlan_table_t; @@ -110,15 +110,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:50; - uint64_t par_en:1; - uint64_t valid:1; - uint64_t id:12; + uint32_t rsrvd:32; + uint32_t rsrvd_l:18; + uint32_t par_en:1; + uint32_t valid:1; + uint32_t id:12; #else - uint64_t id:12; - uint64_t valid:1; - uint64_t par_en:1; - uint64_t rsrvd:50; + uint32_t id:12; + uint32_t valid:1; + uint32_t par_en:1; + uint32_t rsrvd_l:18; + uint32_t rsrvd:32; #endif } bits; } pfc_vlan_ctrl_t; @@ -142,11 +144,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:16; - uint64_t addr:48; + uint32_t rsrvd:16; + uint32_t addr:16; + uint32_t addr_l:32; #else - uint64_t addr:48; - uint64_t rsrvd:16; + uint32_t addr_l:32; + uint32_t addr:16; + uint32_t rsrvd:16; #endif } bits; } pfc_mac_addr_t; @@ -167,11 +171,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:16; - uint64_t mask:48; + uint32_t rsrvd:16; + uint32_t mask:16; + uint32_t mask_l:32; #else - uint64_t mask:48; - uint64_t rsrvd:16; + uint32_t mask_l:32; + uint32_t mask:16; + uint32_t rsrvd:16; #endif } bits; } pfc_mac_addr_mask_t; @@ -193,11 +199,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t hash_val:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t hash_val:16; #else - uint64_t hash_val:16; - uint64_t rsrvd:48; + uint32_t hash_val:16; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } pfc_hash_table_t; @@ -217,13 +225,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:47; - uint64_t valid:1; - uint64_t etype:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:15; + uint32_t valid:1; + uint32_t etype:16; #else - uint64_t etype:16; - uint64_t valid:1; - uint64_t rsrvd:47; + uint32_t etype:16; + uint32_t valid:1; + uint32_t rsrvd_l:15; + uint32_t rsrvd:32; #endif } bits; } pfc_l2_class_config_t; @@ -244,15 +254,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:60; - uint64_t discard:1; - uint64_t tsel:1; - uint64_t rsrvd1:2; + uint32_t rsrvd:32; + uint32_t rsrvd_l:28; + uint32_t discard:1; + uint32_t tsel:1; + uint32_t rsrvd1:2; #else - uint64_t rsrvd1:2; - uint64_t tsel:1; - uint64_t discard:1; - uint64_t rsrvd:60; + uint32_t rsrvd1:2; + uint32_t tsel:1; + uint32_t discard:1; + uint32_t rsrvd_l:28; + uint32_t rsrvd:32; #endif } bits; } pfc_l3_class_config_t; @@ -269,9 +281,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t key:64; + uint32_t key:32; + uint32_t key_l:32; #else - uint64_t key:64; + uint32_t key_l:32; + uint32_t key:32; #endif } bits; } pfc_tcam_key0_t; @@ -288,11 +302,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:28; - uint64_t key:36; + uint32_t rsrvd:28; + uint32_t key:4; + uint32_t key_l:32; #else - uint64_t key:36; - uint64_t rsrvd:28; + uint32_t key_l:32; + uint32_t key:4; + uint32_t rsrvd:28; #endif } bits; } pfc_tcam_key1_t; @@ -309,9 +325,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t mask:64; + uint32_t mask:32; + uint32_t mask_l:32; #else - uint64_t mask:64; + uint32_t mask_l:32; + uint32_t mask:32; #endif } bits; } pfc_tcam_mask0_t; @@ -328,11 +346,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:28; - uint64_t mask:36; + uint32_t rsrvd:28; + uint32_t mask:4; + uint32_t mask_l:32; #else - uint64_t mask:36; - uint64_t rsrvd:28; + uint32_t mask_l:32; + uint32_t mask:4; + uint32_t rsrvd:28; #endif } bits; } pfc_tcam_mask1_t; @@ -370,21 +390,23 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:45; - uint64_t par_en:1; - uint64_t cmd:3; - uint64_t status:1; - uint64_t match:1; - uint64_t rsrvd1:5; - uint64_t addr:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:13; + uint32_t par_en:1; + uint32_t cmd:3; + uint32_t status:1; + uint32_t match:1; + uint32_t rsrvd1:5; + uint32_t addr:8; #else - uint64_t addr:8; - uint64_t rsrvd1:5; - uint64_t match:1; - uint64_t status:1; - uint64_t cmd:3; - uint64_t par_en:1; - uint64_t rsrvd:45; + uint32_t addr:8; + uint32_t rsrvd1:5; + uint32_t match:1; + uint32_t status:1; + uint32_t cmd:3; + uint32_t par_en:1; + uint32_t rsrvd_l:13; + uint32_t rsrvd:32; #endif } bits; } pfc_tcam_ctrl_t; @@ -411,21 +433,23 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:24; - uint64_t mac_addr_en:32; - uint64_t default_dma:4; - uint64_t force_cs_en:1; - uint64_t tcp_cs_en:1; - uint64_t tcam_en:1; - uint64_t l2_hash_en:1; + uint32_t rsrvd:24; + uint32_t mac_addr_en:8; + uint32_t mac_addr_en_l:24; + uint32_t default_dma:4; + uint32_t force_cs_en:1; + uint32_t tcp_cs_en:1; + uint32_t tcam_en:1; + uint32_t l2_hash_en:1; #else - uint64_t l2_hash_en:1; - uint64_t tcam_en:1; - uint64_t tcp_cs_en:1; - uint64_t force_cs_en:1; - uint64_t default_dma:4; - uint64_t mac_addr_en:32; - uint64_t rsrvd:24; + uint32_t l2_hash_en:1; + uint32_t tcam_en:1; + uint32_t tcp_cs_en:1; + uint32_t force_cs_en:1; + uint32_t default_dma:4; + uint32_t mac_addr_en_l:24; + uint32_t mac_addr_en:8; + uint32_t rsrvd:24; #endif } bits; } pfc_config_t; @@ -454,23 +478,25 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:57; - uint64_t discard:1; - uint64_t fin:1; - uint64_t syn:1; - uint64_t rst:1; - uint64_t psh:1; - uint64_t ack:1; - uint64_t urg:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:25; + uint32_t discard:1; + uint32_t fin:1; + uint32_t syn:1; + uint32_t rst:1; + uint32_t psh:1; + uint32_t ack:1; + uint32_t urg:1; #else - uint64_t urg:1; - uint64_t ack:1; - uint64_t psh:1; - uint64_t rst:1; - uint64_t syn:1; - uint64_t fin:1; - uint64_t discard:1; - uint64_t rsrvd:57; + uint32_t urg:1; + uint32_t ack:1; + uint32_t psh:1; + uint32_t rst:1; + uint32_t syn:1; + uint32_t fin:1; + uint32_t discard:1; + uint32_t rsrvd_l:25; + uint32_t rsrvd:32; #endif } bits; } tcp_ctrl_mask_t; @@ -485,11 +511,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t seed:32; + uint32_t rsrvd:32; + uint32_t seed:32; #else - uint64_t seed:32; - uint64_t rsrvd:32; + uint32_t seed:32; + uint32_t rsrvd:32; #endif } bits; } src_hash_val_t; @@ -510,15 +536,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t pkt_drop:1; - uint64_t tcam_parity_err:1; - uint64_t vlan_parity_err:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t pkt_drop:1; + uint32_t tcam_parity_err:1; + uint32_t vlan_parity_err:1; #else - uint64_t vlan_parity_err:1; - uint64_t tcam_parity_err:1; - uint64_t pkt_drop:1; - uint64_t rsrvd:61; + uint32_t vlan_parity_err:1; + uint32_t tcam_parity_err:1; + uint32_t pkt_drop:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } pfc_int_status_t; @@ -540,15 +568,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t pkt_drop:1; - uint64_t tcam_parity_err:1; - uint64_t vlan_parity_err:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t pkt_drop:1; + uint32_t tcam_parity_err:1; + uint32_t vlan_parity_err:1; #else - uint64_t vlan_parity_err:1; - uint64_t tcam_parity_err:1; - uint64_t pkt_drop:1; - uint64_t rsrvd:61; + uint32_t vlan_parity_err:1; + uint32_t tcam_parity_err:1; + uint32_t pkt_drop:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } pfc_dbg_int_status_t; @@ -567,15 +597,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t pkt_drop_mask:1; - uint64_t tcam_parity_err_mask:1; - uint64_t vlan_parity_err_mask:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t pkt_drop_mask:1; + uint32_t tcam_parity_err_mask:1; + uint32_t vlan_parity_err_mask:1; #else - uint64_t vlan_parity_err_mask:1; - uint64_t tcam_parity_err_mask:1; - uint64_t pkt_drop_mask:1; - uint64_t rsrvd:61; + uint32_t vlan_parity_err_mask:1; + uint32_t tcam_parity_err_mask:1; + uint32_t pkt_drop_mask:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } pfc_int_mask_t; @@ -597,19 +629,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:59; - uint64_t tcp_ctrl_drop:1; - uint64_t l2_addr_drop:1; - uint64_t class_code_drop:1; - uint64_t tcam_drop:1; - uint64_t vlan_drop:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:27; + uint32_t tcp_ctrl_drop:1; + uint32_t l2_addr_drop:1; + uint32_t class_code_drop:1; + uint32_t tcam_drop:1; + uint32_t vlan_drop:1; #else - uint64_t vlan_drop:1; - uint64_t tcam_drop:1; - uint64_t class_code_drop:1; - uint64_t l2_addr_drop:1; - uint64_t tcp_ctrl_drop:1; - uint64_t rsrvd:59; + uint32_t vlan_drop:1; + uint32_t tcam_drop:1; + uint32_t class_code_drop:1; + uint32_t l2_addr_drop:1; + uint32_t tcp_ctrl_drop:1; + uint32_t rsrvd_l:27; + uint32_t rsrvd:32; #endif } bits; } pfc_drop_log_t; @@ -633,19 +667,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:59; - uint64_t tcp_ctrl_drop_mask:1; - uint64_t l2_addr_drop_mask:1; - uint64_t class_code_drop_mask:1; - uint64_t tcam_drop_mask:1; - uint64_t vlan_drop_mask:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:27; + uint32_t tcp_ctrl_drop_mask:1; + uint32_t l2_addr_drop_mask:1; + uint32_t class_code_drop_mask:1; + uint32_t tcam_drop_mask:1; + uint32_t vlan_drop_mask:1; #else - uint64_t vlan_drop_mask:1; - uint64_t tcam_drop_mask:1; - uint64_t class_code_drop_mask:1; - uint64_t l2_addr_drop_mask:1; - uint64_t tcp_ctrl_drop_mask:1; - uint64_t rsrvd:59; + uint32_t vlan_drop_mask:1; + uint32_t tcam_drop_mask:1; + uint32_t class_code_drop_mask:1; + uint32_t l2_addr_drop_mask:1; + uint32_t tcp_ctrl_drop_mask:1; + uint32_t rsrvd_l:27; + uint32_t rsrvd:32; #endif } bits; } pfc_drop_log_mask_t; @@ -663,11 +699,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:52; - uint64_t addr:12; + uint32_t rsrvd:32; + uint32_t rsrvd_l:20; + uint32_t addr:12; #else - uint64_t addr:12; - uint64_t rsrvd:52; + uint32_t addr:12; + uint32_t rsrvd_l:20; + uint32_t rsrvd:32; #endif } bits; } pfc_vlan_par_err_log_t; @@ -685,11 +723,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:56; - uint64_t addr:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:24; + uint32_t addr:8; #else - uint64_t addr:8; - uint64_t rsrvd:56; + uint32_t addr:8; + uint32_t rsrvd_l:24; + uint32_t rsrvd:32; #endif } bits; } pfc_tcam_par_err_log_t; @@ -708,11 +748,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t bad_cs_count:32; + uint32_t rsrvd:32; + uint32_t bad_cs_count:32; #else - uint64_t bad_cs_count:32; - uint64_t rsrvd:32; + uint32_t bad_cs_count:32; + uint32_t rsrvd:32; #endif } bits; } pfc_bad_cs_counter_t; @@ -732,11 +772,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t drop_count:32; + uint32_t rsrvd:32; + uint32_t drop_count:32; #else - uint64_t drop_count:32; - uint64_t rsrvd:32; + uint32_t drop_count:32; + uint32_t rsrvd:32; #endif } bits; } pfc_drop_counter_t; @@ -756,11 +796,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:63; - uint64_t auto_init_status:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:31; + uint32_t auto_init_status:1; #else - uint64_t auto_init_status:1; - uint64_t rsrvd:63; + uint32_t auto_init_status:1; + uint32_t rsrvd_l:31; + uint32_t rsrvd:32; #endif } bits; } pfc_auto_init_t;
--- a/usr/src/uts/common/io/hxge/hxge_rdc_hw.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_rdc_hw.h Thu Jun 12 13:25:54 2008 -0700 @@ -94,11 +94,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:44; - uint64_t handle:20; + uint32_t rsrvd:32; + uint32_t rsrvd_l:12; + uint32_t handle:20; #else - uint64_t handle:20; - uint64_t rsrvd:44; + uint32_t handle:20; + uint32_t rsrvd_l:12; + uint32_t rsrvd:32; #endif } bits; } rdc_page_handle_t; @@ -139,19 +141,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t enable:1; - uint64_t reset:1; - uint64_t qst:1; - uint64_t rsrvd1:17; - uint64_t mbaddr_h:12; + uint32_t rsrvd:32; + uint32_t enable:1; + uint32_t reset:1; + uint32_t qst:1; + uint32_t rsrvd1:17; + uint32_t mbaddr_h:12; #else - uint64_t mbaddr_h:12; - uint64_t rsrvd1:17; - uint64_t qst:1; - uint64_t reset:1; - uint64_t enable:1; - uint64_t rsrvd:32; + uint32_t mbaddr_h:12; + uint32_t rsrvd1:17; + uint32_t qst:1; + uint32_t reset:1; + uint32_t enable:1; + uint32_t rsrvd:32; #endif } bits; } rdc_rx_cfg1_t; @@ -174,17 +176,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t mbaddr_l:26; - uint64_t rsrvd1:3; - uint64_t offset:2; - uint64_t full_hdr:1; + uint32_t rsrvd:32; + uint32_t mbaddr_l:26; + uint32_t rsrvd1:3; + uint32_t offset:2; + uint32_t full_hdr:1; #else - uint64_t full_hdr:1; - uint64_t offset:2; - uint64_t rsrvd1:3; - uint64_t mbaddr_l:26; - uint64_t rsrvd:32; + uint32_t full_hdr:1; + uint32_t offset:2; + uint32_t rsrvd1:3; + uint32_t mbaddr_l:26; + uint32_t rsrvd:32; #endif } bits; } rdc_rx_cfg2_t; @@ -221,19 +223,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t len:10; - uint64_t len_lo:6; - uint64_t rsrvd:4; - uint64_t staddr_base:26; - uint64_t staddr:12; - uint64_t rsrvd1:6; + uint32_t len:10; + uint32_t len_lo:6; + uint32_t rsrvd:4; + uint32_t staddr_base:12; + uint32_t staddr_base_l:14; + uint32_t staddr:12; + uint32_t rsrvd1:6; #else - uint64_t rsrvd1:6; - uint64_t staddr:12; - uint64_t staddr_base:26; - uint64_t rsrvd:4; - uint64_t len_lo:6; - uint64_t len:10; + uint32_t rsrvd1:6; + uint32_t staddr:12; + uint32_t staddr_base_l:14; + uint32_t staddr_base:12; + uint32_t rsrvd:4; + uint32_t len_lo:6; + uint32_t len:10; #endif } bits; } rdc_rbr_cfg_a_t; @@ -268,29 +272,31 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:39; - uint64_t bksize:1; - uint64_t vld2:1; - uint64_t rsrvd1:6; - uint64_t bufsz2:1; - uint64_t vld1:1; - uint64_t rsrvd2:6; - uint64_t bufsz1:1; - uint64_t vld0:1; - uint64_t rsrvd3:5; - uint64_t bufsz0:2; + uint32_t rsrvd:32; + uint32_t rsrvd_l:7; + uint32_t bksize:1; + uint32_t vld2:1; + uint32_t rsrvd1:6; + uint32_t bufsz2:1; + uint32_t vld1:1; + uint32_t rsrvd2:6; + uint32_t bufsz1:1; + uint32_t vld0:1; + uint32_t rsrvd3:5; + uint32_t bufsz0:2; #else - uint64_t bufsz0:2; - uint64_t rsrvd3:5; - uint64_t vld0:1; - uint64_t bufsz1:1; - uint64_t rsrvd2:6; - uint64_t vld1:1; - uint64_t bufsz2:1; - uint64_t rsrvd1:6; - uint64_t vld2:1; - uint64_t bksize:1; - uint64_t rsrvd:39; + uint32_t bufsz0:2; + uint32_t rsrvd3:5; + uint32_t vld0:1; + uint32_t bufsz1:1; + uint32_t rsrvd2:6; + uint32_t vld1:1; + uint32_t bufsz2:1; + uint32_t rsrvd1:6; + uint32_t vld2:1; + uint32_t bksize:1; + uint32_t rsrvd_l:7; + uint32_t rsrvd:32; #endif } bits; } rdc_rbr_cfg_b_t; @@ -314,11 +320,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t bkadd:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t bkadd:16; #else - uint64_t bkadd:16; - uint64_t rsrvd:48; + uint32_t bkadd:16; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } rdc_rbr_kick_t; @@ -335,11 +343,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t qlen:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t qlen:16; #else - uint64_t qlen:16; - uint64_t rsrvd:48; + uint32_t qlen:16; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } rdc_rbr_qlen_t; @@ -359,13 +369,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:46; - uint64_t head:16; - uint64_t rsrvd1:2; + uint32_t rsrvd:32; + uint32_t rsrvd_l:14; + uint32_t head:16; + uint32_t rsrvd1:2; #else - uint64_t rsrvd1:2; - uint64_t head:16; - uint64_t rsrvd:46; + uint32_t rsrvd1:2; + uint32_t head:16; + uint32_t rsrvd_l:14; + uint32_t rsrvd:32; #endif } bits; } rdc_rbr_head_t; @@ -396,19 +408,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t len:11; - uint64_t len_lo:5; - uint64_t rsrvd:4; - uint64_t staddr_base:25; - uint64_t staddr:13; - uint64_t rsrvd1:6; + uint32_t len:11; + uint32_t len_lo:5; + uint32_t rsrvd:4; + uint32_t staddr_base:12; + uint32_t staddr_base_l:13; + uint32_t staddr:13; + uint32_t rsrvd1:6; #else - uint64_t rsrvd1:6; - uint64_t staddr:13; - uint64_t staddr_base:25; - uint64_t rsrvd:4; - uint64_t len_lo:5; - uint64_t len:11; + uint32_t rsrvd1:6; + uint32_t staddr:13; + uint32_t staddr_base_l:13; + uint32_t staddr_base:12; + uint32_t rsrvd:4; + uint32_t len_lo:5; + uint32_t len:11; #endif } bits; } rdc_rcr_cfg_a_t; @@ -433,17 +447,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t pthres:16; - uint64_t entout:1; - uint64_t rsrvd1:9; - uint64_t timeout:6; + uint32_t rsrvd:32; + uint32_t pthres:16; + uint32_t entout:1; + uint32_t rsrvd1:9; + uint32_t timeout:6; #else - uint64_t timeout:6; - uint64_t rsrvd1:9; - uint64_t entout:1; - uint64_t pthres:16; - uint64_t rsrvd:32; + uint32_t timeout:6; + uint32_t rsrvd1:9; + uint32_t entout:1; + uint32_t pthres:16; + uint32_t rsrvd:32; #endif } bits; } rdc_rcr_cfg_b_t; @@ -461,11 +475,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t qlen:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t qlen:16; #else - uint64_t qlen:16; - uint64_t rsrvd:48; + uint32_t qlen:16; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } rdc_rcr_qlen_t; @@ -485,13 +501,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:45; - uint64_t tail:16; - uint64_t rsrvd1:3; + uint32_t rsrvd:32; + uint32_t rsrvd_l:13; + uint32_t tail:16; + uint32_t rsrvd1:3; #else - uint64_t rsrvd1:3; - uint64_t tail:16; - uint64_t rsrvd:45; + uint32_t rsrvd1:3; + uint32_t tail:16; + uint32_t rsrvd_l:13; + uint32_t rsrvd:32; #endif } bits; } rdc_rcr_tail_t; @@ -512,11 +530,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:63; - uint64_t flush:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:31; + uint32_t flush:1; #else - uint64_t flush:1; - uint64_t rsrvd:63; + uint32_t flush:1; + uint32_t rsrvd_l:31; + uint32_t rsrvd:32; #endif } bits; } rdc_rcr_flush_t; @@ -537,11 +557,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t count:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t count:16; #else - uint64_t count:16; - uint64_t rsrvd:48; + uint32_t count:16; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } rdc_clock_div_t; @@ -585,41 +607,41 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:10; - uint64_t rbr_cpl_to:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd1:5; - uint64_t rcr_thres:1; - uint64_t rcr_to:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rbr_prefetch_par_err:1; - uint64_t rsrvd2:2; - uint64_t rbr_pre_empty:1; - uint64_t rcr_shadow_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_full:1; - uint64_t rbr_empty:1; - uint64_t rbr_full:1; - uint64_t rsrvd4:2; - uint64_t rsrvd5:32; + uint32_t rsrvd:10; + uint32_t rbr_cpl_to:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd1:5; + uint32_t rcr_thres:1; + uint32_t rcr_to:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rbr_prefetch_par_err:1; + uint32_t rsrvd2:2; + uint32_t rbr_pre_empty:1; + uint32_t rcr_shadow_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_full:1; + uint32_t rbr_empty:1; + uint32_t rbr_full:1; + uint32_t rsrvd4:2; + uint32_t rsrvd5:32; #else - uint64_t rsrvd5:32; - uint64_t rsrvd4:2; - uint64_t rbr_full:1; - uint64_t rbr_empty:1; - uint64_t rcr_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_shadow_full:1; - uint64_t rbr_pre_empty:1; - uint64_t rsrvd2:2; - uint64_t rbr_prefetch_par_err:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rcr_to:1; - uint64_t rcr_thres:1; - uint64_t rsrvd1:5; - uint64_t peu_resp_err:1; - uint64_t rbr_cpl_to:1; - uint64_t rsrvd:10; + uint32_t rsrvd5:32; + uint32_t rsrvd4:2; + uint32_t rbr_full:1; + uint32_t rbr_empty:1; + uint32_t rcr_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_shadow_full:1; + uint32_t rbr_pre_empty:1; + uint32_t rsrvd2:2; + uint32_t rbr_prefetch_par_err:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rcr_to:1; + uint32_t rcr_thres:1; + uint32_t rsrvd1:5; + uint32_t peu_resp_err:1; + uint32_t rbr_cpl_to:1; + uint32_t rsrvd:10; #endif } bits; } rdc_int_mask_t; @@ -683,45 +705,45 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:10; - uint64_t rbr_cpl_to:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd1:4; - uint64_t mex:1; - uint64_t rcr_thres:1; - uint64_t rcr_to:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rbr_prefetch_par_err:1; - uint64_t rsrvd2:2; - uint64_t rbr_pre_empty:1; - uint64_t rcr_shadow_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_full:1; - uint64_t rbr_empty:1; - uint64_t rbr_full:1; - uint64_t rsrvd4:2; - uint64_t ptrread:16; - uint64_t pktread:16; + uint32_t rsrvd:10; + uint32_t rbr_cpl_to:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd1:4; + uint32_t mex:1; + uint32_t rcr_thres:1; + uint32_t rcr_to:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rbr_prefetch_par_err:1; + uint32_t rsrvd2:2; + uint32_t rbr_pre_empty:1; + uint32_t rcr_shadow_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_full:1; + uint32_t rbr_empty:1; + uint32_t rbr_full:1; + uint32_t rsrvd4:2; + uint32_t ptrread:16; + uint32_t pktread:16; #else - uint64_t pktread:16; - uint64_t ptrread:16; - uint64_t rsrvd4:2; - uint64_t rbr_full:1; - uint64_t rbr_empty:1; - uint64_t rcr_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_shadow_full:1; - uint64_t rbr_pre_empty:1; - uint64_t rsrvd2:2; - uint64_t rbr_prefetch_par_err:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rcr_to:1; - uint64_t rcr_thres:1; - uint64_t mex:1; - uint64_t rsrvd1:4; - uint64_t peu_resp_err:1; - uint64_t rbr_cpl_to:1; - uint64_t rsrvd:10; + uint32_t pktread:16; + uint32_t ptrread:16; + uint32_t rsrvd4:2; + uint32_t rbr_full:1; + uint32_t rbr_empty:1; + uint32_t rcr_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_shadow_full:1; + uint32_t rbr_pre_empty:1; + uint32_t rsrvd2:2; + uint32_t rbr_prefetch_par_err:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rcr_to:1; + uint32_t rcr_thres:1; + uint32_t mex:1; + uint32_t rsrvd1:4; + uint32_t peu_resp_err:1; + uint32_t rbr_cpl_to:1; + uint32_t rsrvd:10; #endif } bits; } rdc_stat_t; @@ -741,11 +763,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t syn_pkt_count:32; - uint64_t pkt_count:32; + uint32_t syn_pkt_count:32; + uint32_t pkt_count:32; #else - uint64_t pkt_count:32; - uint64_t syn_pkt_count:32; + uint32_t pkt_count:32; + uint32_t syn_pkt_count:32; #endif } bits; } rdc_pkt_count_t; @@ -772,21 +794,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:16; - uint64_t too_long:8; - uint64_t no_rbr_avail:8; - uint64_t rvm_error:8; - uint64_t frame_error:8; - uint64_t rxram_error:8; - uint64_t rsrvd1:8; + uint32_t rsrvd:16; + uint32_t too_long:8; + uint32_t no_rbr_avail:8; + uint32_t rvm_error:8; + uint32_t frame_error:8; + uint32_t rxram_error:8; + uint32_t rsrvd1:8; #else - uint64_t rsrvd1:8; - uint64_t rxram_error:8; - uint64_t frame_error:8; - uint64_t rvm_error:8; - uint64_t no_rbr_avail:8; - uint64_t too_long:8; - uint64_t rsrvd:16; + uint32_t rsrvd1:8; + uint32_t rxram_error:8; + uint32_t frame_error:8; + uint32_t rvm_error:8; + uint32_t no_rbr_avail:8; + uint32_t too_long:8; + uint32_t rsrvd:16; #endif } bits; } rdc_drop_count_t; @@ -804,11 +826,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t count:32; + uint32_t rsrvd:32; + uint32_t count:32; #else - uint64_t count:32; - uint64_t rsrvd:32; + uint32_t count:32; + uint32_t rsrvd:32; #endif } bits; } rdc_byte_count_t; @@ -837,21 +859,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t par_en:1; - uint64_t rsrvd1:22; - uint64_t dmc:2; - uint64_t entry:5; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t par_en:1; + uint32_t rsrvd1:22; + uint32_t dmc:2; + uint32_t entry:5; #else - uint64_t entry:5; - uint64_t dmc:2; - uint64_t rsrvd1:22; - uint64_t par_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:5; + uint32_t dmc:2; + uint32_t rsrvd1:22; + uint32_t par_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } rdc_pref_cmd_t; @@ -871,13 +893,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:28; - uint64_t par:4; - uint64_t data:32; + uint32_t rsrvd:28; + uint32_t par:4; + uint32_t data:32; #else - uint64_t data:32; - uint64_t par:4; - uint64_t rsrvd:28; + uint32_t data:32; + uint32_t par:4; + uint32_t rsrvd:28; #endif } bits; } rdc_pref_data_t; @@ -905,21 +927,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t par_en:1; - uint64_t rsrvd1:23; - uint64_t dmc:2; - uint64_t entry:4; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t par_en:1; + uint32_t rsrvd1:23; + uint32_t dmc:2; + uint32_t entry:4; #else - uint64_t entry:4; - uint64_t dmc:2; - uint64_t rsrvd1:23; - uint64_t par_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:4; + uint32_t dmc:2; + uint32_t rsrvd1:23; + uint32_t par_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } rdc_shadow_cmd_t; @@ -937,9 +959,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } rdc_shadow_data_t; @@ -957,13 +981,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:24; - uint64_t parity_data:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:24; + uint32_t parity_data:8; #else - uint64_t parity_data:8; - uint64_t rsrvd1:24; - uint64_t rsrvd:32; + uint32_t parity_data:8; + uint32_t rsrvd1:24; + uint32_t rsrvd:32; #endif } bits; } rdc_shadow_par_data_t; @@ -991,19 +1015,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t ecc_en:1; - uint64_t rsrvd1:20; - uint64_t entry:9; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t ecc_en:1; + uint32_t rsrvd1:20; + uint32_t entry:9; #else - uint64_t entry:9; - uint64_t rsrvd1:20; - uint64_t ecc_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:9; + uint32_t rsrvd1:20; + uint32_t ecc_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } rdc_ctrl_fifo_cmd_t; @@ -1022,9 +1046,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } rdc_ctrl_fifo_data_lo_t; @@ -1043,9 +1069,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } rdc_ctrl_fifo_data_hi_t; @@ -1066,15 +1094,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:16; - uint64_t ecc_data_hi:8; - uint64_t ecc_data_lo:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:16; + uint32_t ecc_data_hi:8; + uint32_t ecc_data_lo:8; #else - uint64_t ecc_data_lo:8; - uint64_t ecc_data_hi:8; - uint64_t rsrvd1:16; - uint64_t rsrvd:32; + uint32_t ecc_data_lo:8; + uint32_t ecc_data_hi:8; + uint32_t rsrvd1:16; + uint32_t rsrvd:32; #endif } bits; } rdc_ctrl_fifo_data_ecc_t; @@ -1102,19 +1130,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t ecc_en:1; - uint64_t rsrvd1:18; - uint64_t entry:11; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t ecc_en:1; + uint32_t rsrvd1:18; + uint32_t entry:11; #else - uint64_t entry:11; - uint64_t rsrvd1:18; - uint64_t ecc_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:11; + uint32_t rsrvd1:18; + uint32_t ecc_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } rdc_data_fifo_cmd_t; @@ -1133,9 +1161,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } rdc_data_fifo_data_lo_t; @@ -1154,9 +1184,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } rdc_data_fifo_data_hi_t; @@ -1177,15 +1209,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:16; - uint64_t ecc_data_hi:8; - uint64_t ecc_data_lo:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:16; + uint32_t ecc_data_hi:8; + uint32_t ecc_data_lo:8; #else - uint64_t ecc_data_lo:8; - uint64_t ecc_data_hi:8; - uint64_t rsrvd1:16; - uint64_t rsrvd:32; + uint32_t ecc_data_lo:8; + uint32_t ecc_data_hi:8; + uint32_t rsrvd1:16; + uint32_t rsrvd:32; #endif } bits; } rdc_data_fifo_data_ecc_t; @@ -1214,41 +1246,41 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:10; - uint64_t rbr_cpl_to:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd1:5; - uint64_t rcr_thres:1; - uint64_t rcr_to:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rbr_prefetch_par_err:1; - uint64_t rsrvd2:2; - uint64_t rbr_pre_empty:1; - uint64_t rcr_shadow_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_full:1; - uint64_t rbr_empty:1; - uint64_t rbr_full:1; - uint64_t rsrvd4:2; - uint64_t rsrvd5:32; + uint32_t rsrvd:10; + uint32_t rbr_cpl_to:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd1:5; + uint32_t rcr_thres:1; + uint32_t rcr_to:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rbr_prefetch_par_err:1; + uint32_t rsrvd2:2; + uint32_t rbr_pre_empty:1; + uint32_t rcr_shadow_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_full:1; + uint32_t rbr_empty:1; + uint32_t rbr_full:1; + uint32_t rsrvd4:2; + uint32_t rsrvd5:32; #else - uint64_t rsrvd5:32; - uint64_t rsrvd4:2; - uint64_t rbr_full:1; - uint64_t rbr_empty:1; - uint64_t rcr_full:1; - uint64_t rsrvd3:2; - uint64_t rcr_shadow_full:1; - uint64_t rbr_pre_empty:1; - uint64_t rsrvd2:2; - uint64_t rbr_prefetch_par_err:1; - uint64_t rcr_shadow_par_err:1; - uint64_t rcr_to:1; - uint64_t rcr_thres:1; - uint64_t rsrvd1:5; - uint64_t peu_resp_err:1; - uint64_t rbr_cpl_to:1; - uint64_t rsrvd:10; + uint32_t rsrvd5:32; + uint32_t rsrvd4:2; + uint32_t rbr_full:1; + uint32_t rbr_empty:1; + uint32_t rcr_full:1; + uint32_t rsrvd3:2; + uint32_t rcr_shadow_full:1; + uint32_t rbr_pre_empty:1; + uint32_t rsrvd2:2; + uint32_t rbr_prefetch_par_err:1; + uint32_t rcr_shadow_par_err:1; + uint32_t rcr_to:1; + uint32_t rcr_thres:1; + uint32_t rsrvd1:5; + uint32_t peu_resp_err:1; + uint32_t rbr_cpl_to:1; + uint32_t rsrvd:10; #endif } bits; } rdc_stat_int_dbg_t; @@ -1267,11 +1299,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:57; - uint64_t address:7; + uint32_t rsrvd:32; + uint32_t rsrvd_l:25; + uint32_t address:7; #else - uint64_t address:7; - uint64_t rsrvd:57; + uint32_t address:7; + uint32_t rsrvd_l:25; + uint32_t rsrvd:32; #endif } bits; } rdc_pref_par_log_t; @@ -1290,13 +1324,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:26; - uint64_t address:6; + uint32_t rsrvd:32; + uint32_t rsrvd1:26; + uint32_t address:6; #else - uint64_t address:6; - uint64_t rsrvd1:26; - uint64_t rsrvd:32; + uint32_t address:6; + uint32_t rsrvd1:26; + uint32_t rsrvd:32; #endif } bits; } rdc_shadow_par_log_t; @@ -1326,23 +1360,23 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:7; - uint64_t address_hi:9; - uint64_t rsrvd1:7; - uint64_t address_lo:9; - uint64_t rsrvd2:8; - uint64_t syndrome_hi:8; - uint64_t rsrvd3:8; - uint64_t syndrome_lo:8; + uint32_t rsrvd:7; + uint32_t address_hi:9; + uint32_t rsrvd1:7; + uint32_t address_lo:9; + uint32_t rsrvd2:8; + uint32_t syndrome_hi:8; + uint32_t rsrvd3:8; + uint32_t syndrome_lo:8; #else - uint64_t syndrome_lo:8; - uint64_t rsrvd3:8; - uint64_t syndrome_hi:8; - uint64_t rsrvd2:8; - uint64_t address_lo:9; - uint64_t rsrvd1:7; - uint64_t address_hi:9; - uint64_t rsrvd:7; + uint32_t syndrome_lo:8; + uint32_t rsrvd3:8; + uint32_t syndrome_hi:8; + uint32_t rsrvd2:8; + uint32_t address_lo:9; + uint32_t rsrvd1:7; + uint32_t address_hi:9; + uint32_t rsrvd:7; #endif } bits; } rdc_ctrl_fifo_ecc_log_t; @@ -1372,23 +1406,23 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:5; - uint64_t address_hi:11; - uint64_t rsrvd1:5; - uint64_t address_lo:11; - uint64_t rsrvd2:8; - uint64_t syndrome_hi:8; - uint64_t rsrvd3:8; - uint64_t syndrome_lo:8; + uint32_t rsrvd:5; + uint32_t address_hi:11; + uint32_t rsrvd1:5; + uint32_t address_lo:11; + uint32_t rsrvd2:8; + uint32_t syndrome_hi:8; + uint32_t rsrvd3:8; + uint32_t syndrome_lo:8; #else - uint64_t syndrome_lo:8; - uint64_t rsrvd3:8; - uint64_t syndrome_hi:8; - uint64_t rsrvd2:8; - uint64_t address_lo:11; - uint64_t rsrvd1:5; - uint64_t address_hi:11; - uint64_t rsrvd:5; + uint32_t syndrome_lo:8; + uint32_t rsrvd3:8; + uint32_t syndrome_hi:8; + uint32_t rsrvd2:8; + uint32_t address_lo:11; + uint32_t rsrvd1:5; + uint32_t address_hi:11; + uint32_t rsrvd:5; #endif } bits; } rdc_data_fifo_ecc_log_t; @@ -1414,19 +1448,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:24; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_data_fifo_ded:2; + uint32_t rsrvd:32; + uint32_t rsrvd1:24; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_data_fifo_ded:2; #else - uint64_t rx_data_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rsrvd1:24; - uint64_t rsrvd:32; + uint32_t rx_data_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rsrvd1:24; + uint32_t rsrvd:32; #endif } bits; } rdc_fifo_err_int_mask_t; @@ -1460,17 +1494,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:56; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_data_fifo_ded:2; + uint32_t rsrvd:32; + uint32_t rsrvd_l:24; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_data_fifo_ded:2; #else - uint64_t rx_data_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rsrvd:56; + uint32_t rx_data_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rsrvd_l:24; + uint32_t rsrvd:32; #endif } bits; } rdc_fifo_err_stat_t; @@ -1491,19 +1527,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:24; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_data_fifo_ded:2; + uint32_t rsrvd:32; + uint32_t rsrvd1:24; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_data_fifo_ded:2; #else - uint64_t rx_data_fifo_ded:2; - uint64_t rx_data_fifo_sec:2; - uint64_t rx_ctrl_fifo_ded:2; - uint64_t rx_ctrl_fifo_sec:2; - uint64_t rsrvd1:24; - uint64_t rsrvd:32; + uint32_t rx_data_fifo_ded:2; + uint32_t rx_data_fifo_sec:2; + uint32_t rx_ctrl_fifo_ded:2; + uint32_t rx_ctrl_fifo_sec:2; + uint32_t rsrvd1:24; + uint32_t rsrvd:32; #endif } bits; } rdc_fifo_err_int_dbg_t; @@ -1524,15 +1560,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:16; - uint64_t peu_mem_wr_count:8; - uint64_t peu_mem_rd_count:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:16; + uint32_t peu_mem_wr_count:8; + uint32_t peu_mem_rd_count:8; #else - uint64_t peu_mem_rd_count:8; - uint64_t peu_mem_wr_count:8; - uint64_t rsrvd1:16; - uint64_t rsrvd:32; + uint32_t peu_mem_rd_count:8; + uint32_t peu_mem_wr_count:8; + uint32_t rsrvd1:16; + uint32_t rsrvd:32; #endif } bits; } rdc_peu_txn_log_t; @@ -1558,21 +1594,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t dbgx_msb:1; - uint64_t dbgx_bld_num:3; - uint64_t dbgx_training_vec:12; - uint64_t dbgy_msb:1; - uint64_t dbgy_bld_num:3; - uint64_t dbgy_training_vec:12; + uint32_t rsrvd:32; + uint32_t dbgx_msb:1; + uint32_t dbgx_bld_num:3; + uint32_t dbgx_training_vec:12; + uint32_t dbgy_msb:1; + uint32_t dbgy_bld_num:3; + uint32_t dbgy_training_vec:12; #else - uint64_t dbgy_training_vec:12; - uint64_t dbgy_bld_num:3; - uint64_t dbgy_msb:1; - uint64_t dbgx_training_vec:12; - uint64_t dbgx_bld_num:3; - uint64_t dbgx_msb:1; - uint64_t rsrvd:32; + uint32_t dbgy_training_vec:12; + uint32_t dbgy_bld_num:3; + uint32_t dbgy_msb:1; + uint32_t dbgx_training_vec:12; + uint32_t dbgx_bld_num:3; + uint32_t dbgx_msb:1; + uint32_t rsrvd:32; #endif } bits; } rdc_dbg_training_vec_t; @@ -1592,13 +1628,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t dbg_h32_sub_sel:8; - uint64_t dbg_l32_sub_sel:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t dbg_h32_sub_sel:8; + uint32_t dbg_l32_sub_sel:8; #else - uint64_t dbg_l32_sub_sel:8; - uint64_t dbg_h32_sub_sel:8; - uint64_t rsrvd:48; + uint32_t dbg_l32_sub_sel:8; + uint32_t dbg_h32_sub_sel:8; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } rdc_dbg_grp_sel_t;
--- a/usr/src/uts/common/io/hxge/hxge_rxdma.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_rxdma.c Thu Jun 12 13:25:54 2008 -0700 @@ -84,7 +84,7 @@ p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, - mblk_t ** mp, mblk_t ** mp_cont); + mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel); static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); @@ -102,10 +102,17 @@ hxge_status_t hxge_init_rxdma_channels(p_hxge_t hxgep) { - hxge_status_t status = HXGE_OK; + hxge_status_t status = HXGE_OK; + block_reset_t reset_reg; HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); + /* Reset RDC block from PEU to clear any previous state */ + reset_reg.value = 0; + reset_reg.bits.rdc_rst = 1; + HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); + HXGE_DELAY(1000); + status = hxge_map_rxdma(hxgep); if (status != HXGE_OK) { HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, @@ -330,7 +337,11 @@ "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", pkt_buf_addr_pp, pktbufsz_type)); +#if defined(__i386) + pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; +#else pktbuf_pp = (uint64_t)pkt_buf_addr_pp; +#endif switch (pktbufsz_type) { case 0: @@ -523,8 +534,13 @@ "block_index %d ", total_index, dvma_addr, offset, block_size, block_index)); +#if defined(__i386) + *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + + (uint32_t)offset); +#else *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + offset); +#endif HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp: " @@ -695,7 +711,7 @@ entry_p->bits.l2_len, entry_p->bits.pktbufsz, bptr, - entry_p->bits.pkt_buf_addr)); + entry_p->bits.pkt_buf_addr_l)); pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT; @@ -1231,8 +1247,11 @@ p_mblk_t nmp, mp_cont, head_mp, *tail_mp; uint16_t qlen, nrcr_read, npkt_read; uint32_t qlen_hw; + uint32_t invalid_rcr_entry; boolean_t multi; rdc_rcr_cfg_b_t rcr_cfg_b; + p_rx_mbox_t rx_mboxp; + p_rxdma_mailbox_t mboxp; #if defined(_BIG_ENDIAN) hpi_status_t rs = HPI_SUCCESS; #endif @@ -1261,17 +1280,10 @@ channel, rcr_p->rcr_desc_rd_head_p, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); -#if !defined(_BIG_ENDIAN) - qlen = RXDMA_REG_READ32(handle, RDC_RCR_QLEN, channel) & 0xffff; -#else - rs = hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); - if (rs != HPI_SUCCESS) { - HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " - "channel %d, get qlen failed 0x%08x", - vindex, ldvp->channel, rs)); - return (NULL); - } -#endif + rx_mboxp = hxgep->rx_mbox_areas_p->rxmbox_areas[channel]; + mboxp = (p_rxdma_mailbox_t)rx_mboxp->rx_mbox.kaddrp; + qlen = mboxp->rcrstat_a.bits.qlen; + if (!qlen) { HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", @@ -1306,8 +1318,16 @@ /* * Process one completion ring entry. */ + invalid_rcr_entry = 0; hxge_receive_packet(hxgep, - rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); + rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, + &invalid_rcr_entry); + if (invalid_rcr_entry != 0) { + HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, + "Channel %d could only read 0x%x packets, " + "but 0x%x pending\n", channel, npkt_read, qlen_hw)); + break; + } /* * message chaining modes (nemo msg chaining) @@ -1370,6 +1390,9 @@ rcr_p->comp_rd_index = comp_rd_index; rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; + /* Adjust the mailbox queue length for a hardware bug workaround */ + mboxp->rcrstat_a.bits.qlen -= npkt_read; + if ((hxgep->intr_timeout != rcr_p->intr_timeout) || (hxgep->intr_threshold != rcr_p->intr_threshold)) { rcr_p->intr_timeout = hxgep->intr_timeout; @@ -1403,11 +1426,14 @@ return (head_mp); } +#define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL + /*ARGSUSED*/ void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, - boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) + boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, + uint32_t *invalid_rcr_entry) { p_mblk_t nmp = NULL; uint64_t multi; @@ -1439,11 +1465,23 @@ uint64_t pkt_type; + channel = rcr_p->rdc; + HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); + /* Verify the content of the rcr_entry for a hardware bug workaround */ + if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { + *invalid_rcr_entry = 1; + HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " + "Channel %d invalid RCR entry 0x%llx found, returning\n", + channel, (long long) rcr_entry)); + return; + } + *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; + multi = (rcr_entry & RCR_MULTI_MASK); pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); @@ -1458,10 +1496,13 @@ pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> RCR_PKTBUFSZ_SHIFT); +#if defined(__i386) + pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & + RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); +#else pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); - - channel = rcr_p->rdc; +#endif HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet: entryp $%p entry 0x%0llx " @@ -1484,6 +1525,8 @@ /* get the stats ptr */ rdc_stats = rcr_p->rdc_stats; + if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) + rdc_stats->jumbo_pkts++; if (!l2_len) { HXGE_DEBUG_MSG((hxgep, RX_CTL, @@ -1492,8 +1535,13 @@ } /* shift 6 bits to get the full io address */ +#if defined(__i386) + pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << + RCR_PKT_BUF_ADDR_SHIFT_FULL); +#else pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << RCR_PKT_BUF_ADDR_SHIFT_FULL); +#endif HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> (rbr) hxge_receive_packet: entry 0x%0llx " "full pkt_buf_addr_pp $%p l2_len %d", @@ -1914,18 +1962,10 @@ if (cs.bits.rcr_thres) { rdc_stats->rcr_thres++; - if (rdc_stats->rcr_thres == 1) - HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, - "==> hxge_rx_err_evnts(channel %d): rcr_thres", - channel)); } if (cs.bits.rcr_to) { rdc_stats->rcr_to++; - if (rdc_stats->rcr_to == 1) - HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, - "==> hxge_rx_err_evnts(channel %d): rcr_to", - channel)); } if (cs.bits.rcr_shadow_full) { @@ -2446,8 +2486,13 @@ rcrp->comp_wt_index = 0; rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); +#if defined(__i386) + rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = + (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); +#else rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); +#endif rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + (hxge_port_rcr_size - 1); rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + @@ -2660,11 +2705,19 @@ for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { bsize = dma_bufp->block_size; nblocks = dma_bufp->nblocks; +#if defined(__i386) + ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; +#else ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; +#endif ring_info->buffer[i].buf_index = i; ring_info->buffer[i].buf_size = dma_bufp->alength; ring_info->buffer[i].start_index = index; +#if defined(__i386) + ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; +#else ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; +#endif HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: map channel %d " @@ -3343,8 +3396,13 @@ rcrp->comp_wt_index = 0; rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); +#if defined(__i386) + rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = + (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); +#else rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); +#endif rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + (hxge_port_rcr_size - 1);
--- a/usr/src/uts/common/io/hxge/hxge_rxdma.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_rxdma.h Thu Jun 12 13:25:54 2008 -0700 @@ -170,21 +170,23 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t multi:1; - uint64_t pkt_type:2; - uint64_t reserved:3; - uint64_t error:4; - uint64_t l2_len:14; - uint64_t pktbufsz:2; - uint64_t pkt_buf_addr:38; + uint32_t multi:1; + uint32_t pkt_type:2; + uint32_t reserved:3; + uint32_t error:4; + uint32_t l2_len:14; + uint32_t pktbufsz:2; + uint32_t pkt_buf_addr:6; + uint32_t pkt_buf_addr_l:32; #else - uint64_t pkt_buf_addr:38; - uint64_t pktbufsz:2; - uint64_t l2_len:14; - uint64_t error:4; - uint64_t reserved:3; - uint64_t pkt_type:2; - uint64_t multi:1; + uint32_t pkt_buf_addr_l:32; + uint32_t pkt_buf_addr:6; + uint32_t pktbufsz:2; + uint32_t l2_len:14; + uint32_t error:4; + uint32_t reserved:3; + uint32_t pkt_type:2; + uint32_t multi:1; #endif } bits; } rcr_entry_t, *p_rcr_entry_t;
--- a/usr/src/uts/common/io/hxge/hxge_send.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_send.c Thu Jun 12 13:25:54 2008 -0700 @@ -206,10 +206,15 @@ hpi_handle = desc_area.hpi_handle; hpi_desc_handle.regh = (hxge_os_acc_handle_t) DMA_COMMON_ACC_HANDLE(desc_area); + hpi_desc_handle.hxgep = hxgep; tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area); #ifdef HXGE_DEBUG +#if defined(__i386) + tx_desc_ring_pp = (p_tx_desc_t)(uint32_t)DMA_COMMON_IOADDR(desc_area); +#else tx_desc_ring_pp = (p_tx_desc_t)DMA_COMMON_IOADDR(desc_area); #endif +#endif tx_desc_dma_handle = (hxge_os_dma_handle_t)DMA_COMMON_HANDLE(desc_area); tx_msg_ring = tx_ring_p->tx_msg_ring; @@ -507,7 +512,8 @@ sop_tx_desc_p = &sop_tx_desc; sop_tx_desc_p->value = 0; sop_tx_desc_p->bits.tr_len = clen; - sop_tx_desc_p->bits.sad = dma_ioaddr; + sop_tx_desc_p->bits.sad = dma_ioaddr >> 32; + sop_tx_desc_p->bits.sad_l = dma_ioaddr & 0xffffffff; } else { #ifdef HXGE_DEBUG save_desc_p = &tx_desc; @@ -515,7 +521,8 @@ tmp_desc_p = &tx_desc; tmp_desc_p->value = 0; tmp_desc_p->bits.tr_len = clen; - tmp_desc_p->bits.sad = dma_ioaddr; + tmp_desc_p->bits.sad = dma_ioaddr >> 32; + tmp_desc_p->bits.sad_l = dma_ioaddr & 0xffffffff; tx_desc_p->value = tmp_desc_p->value; } @@ -534,6 +541,7 @@ hpi_desc_handle.function.function = 0; hpi_desc_handle.function.instance = hxgep->instance; sad = save_desc_p->bits.sad; + sad = (sad << 32) | save_desc_p->bits.sad_l; xfer_len = save_desc_p->bits.tr_len; HXGE_DEBUG_MSG((hxgep, TX_CTL, "\n\t: value 0x%llx\n" @@ -578,7 +586,12 @@ hdrp->value = 0; (void) hxge_fill_tx_hdr(mp, B_FALSE, cksum_on, (pkt_len - TX_PKT_HEADER_SIZE), npads, pkthdrp); - if (pkt_len > STD_FRAME_SIZE) { + + /* + * Hardware header should not be counted as part of the frame + * when determining the frame size + */ + if ((pkt_len - TX_PKT_HEADER_SIZE) > (STD_FRAME_SIZE - ETHERFCSL)) { tdc_stats->tx_jumbo_pkts++; }
--- a/usr/src/uts/common/io/hxge/hxge_tdc_hw.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_tdc_hw.h Thu Jun 12 13:25:54 2008 -0700 @@ -86,11 +86,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:44; - uint64_t page_handle:20; + uint32_t rsrvd:32; + uint32_t rsrvd_l:12; + uint32_t page_handle:20; #else - uint64_t page_handle:20; - uint64_t rsrvd:44; + uint32_t page_handle:20; + uint32_t rsrvd_l:12; + uint32_t rsrvd:32; #endif } bits; } tdc_page_handle_t; @@ -145,25 +147,27 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t len:11; - uint64_t rsrvd:5; - uint64_t enable:1; - uint64_t reset:1; - uint64_t qst:1; - uint64_t rsrvd1:1; - uint64_t staddr_base:25; - uint64_t staddr:13; - uint64_t rsrvd2:6; + uint32_t len:11; + uint32_t rsrvd:5; + uint32_t enable:1; + uint32_t reset:1; + uint32_t qst:1; + uint32_t rsrvd1:1; + uint32_t staddr_base:12; + uint32_t staddr_base_l:13; + uint32_t staddr:13; + uint32_t rsrvd2:6; #else - uint64_t rsrvd2:6; - uint64_t staddr:13; - uint64_t staddr_base:25; - uint64_t rsrvd1:1; - uint64_t qst:1; - uint64_t reset:1; - uint64_t enable:1; - uint64_t rsrvd:5; - uint64_t len:11; + uint32_t rsrvd2:6; + uint32_t staddr:13; + uint32_t staddr_base_l:13; + uint32_t staddr_base:12; + uint32_t rsrvd1:1; + uint32_t qst:1; + uint32_t reset:1; + uint32_t enable:1; + uint32_t rsrvd:5; + uint32_t len:11; #endif } bits; } tdc_tdr_cfg_t; @@ -190,13 +194,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:47; - uint64_t wrap:1; - uint64_t head:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:15; + uint32_t wrap:1; + uint32_t head:16; #else - uint64_t head:16; - uint64_t wrap:1; - uint64_t rsrvd:47; + uint32_t head:16; + uint32_t wrap:1; + uint32_t rsrvd_l:15; + uint32_t rsrvd:32; #endif } bits; } tdc_tdr_head_t; @@ -220,13 +226,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:47; - uint64_t wrap:1; - uint64_t head:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:15; + uint32_t wrap:1; + uint32_t head:16; #else - uint64_t head:16; - uint64_t wrap:1; - uint64_t rsrvd:47; + uint32_t head:16; + uint32_t wrap:1; + uint32_t rsrvd_l:15; + uint32_t rsrvd:32; #endif } bits; } tdc_tdr_pre_head_t; @@ -252,13 +260,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:47; - uint64_t wrap:1; - uint64_t tail:16; + uint32_t rsrvd:32; + uint32_t rsrvd_l:15; + uint32_t wrap:1; + uint32_t tail:16; #else - uint64_t tail:16; - uint64_t wrap:1; - uint64_t rsrvd:47; + uint32_t tail:16; + uint32_t wrap:1; + uint32_t rsrvd_l:15; + uint32_t rsrvd:32; #endif } bits; } tdc_tdr_kick_t; @@ -307,33 +317,35 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t marked:1; - uint64_t rsrvd1:5; - uint64_t peu_resp_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pref_par_err:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pkt_cpl_to:1; - uint64_t invalid_sop:1; - uint64_t unexpected_sop:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t marked:1; + uint32_t rsrvd1:5; + uint32_t peu_resp_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pref_par_err:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pkt_cpl_to:1; + uint32_t invalid_sop:1; + uint32_t unexpected_sop:1; #else - uint64_t unexpected_sop:1; - uint64_t invalid_sop:1; - uint64_t pkt_cpl_to:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pref_par_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pkt_size_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd1:5; - uint64_t marked:1; - uint64_t rsrvd:48; + uint32_t unexpected_sop:1; + uint32_t invalid_sop:1; + uint32_t pkt_cpl_to:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pref_par_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pkt_size_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd1:5; + uint32_t marked:1; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } tdc_int_mask_t; @@ -433,47 +445,47 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:4; - uint64_t pkt_cnt:12; - uint64_t rsrvd1:4; - uint64_t lastmark:12; - uint64_t rsrvd2:2; - uint64_t mb:1; - uint64_t rsrvd3:13; - uint64_t marked:1; - uint64_t m_marked:1; - uint64_t rsrvd4:4; - uint64_t peu_resp_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pref_par_err:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pkt_cpl_to:1; - uint64_t invalid_sop:1; - uint64_t unexpected_sop:1; + uint32_t rsrvd:4; + uint32_t pkt_cnt:12; + uint32_t rsrvd1:4; + uint32_t lastmark:12; + uint32_t rsrvd2:2; + uint32_t mb:1; + uint32_t rsrvd3:13; + uint32_t marked:1; + uint32_t m_marked:1; + uint32_t rsrvd4:4; + uint32_t peu_resp_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pref_par_err:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pkt_cpl_to:1; + uint32_t invalid_sop:1; + uint32_t unexpected_sop:1; #else - uint64_t unexpected_sop:1; - uint64_t invalid_sop:1; - uint64_t pkt_cpl_to:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pref_par_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pkt_size_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd4:4; - uint64_t m_marked:1; - uint64_t marked:1; - uint64_t rsrvd3:13; - uint64_t mb:1; - uint64_t rsrvd2:2; - uint64_t lastmark:12; - uint64_t rsrvd1:4; - uint64_t pkt_cnt:12; - uint64_t rsrvd:4; + uint32_t unexpected_sop:1; + uint32_t invalid_sop:1; + uint32_t pkt_cpl_to:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pref_par_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pkt_size_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd4:4; + uint32_t m_marked:1; + uint32_t marked:1; + uint32_t rsrvd3:13; + uint32_t mb:1; + uint32_t rsrvd2:2; + uint32_t lastmark:12; + uint32_t rsrvd1:4; + uint32_t pkt_cnt:12; + uint32_t rsrvd:4; #endif } bits; } tdc_stat_t; @@ -492,11 +504,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:52; - uint64_t mbaddr:12; + uint32_t rsrvd:32; + uint32_t rsrvd_l:20; + uint32_t mbaddr:12; #else - uint64_t mbaddr:12; - uint64_t rsrvd:52; + uint32_t mbaddr:12; + uint32_t rsrvd_l:20; + uint32_t rsrvd:32; #endif } bits; } tdc_mbh_t; @@ -516,13 +530,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t mbaddr:26; - uint64_t rsrvd1:6; + uint32_t rsrvd:32; + uint32_t mbaddr:26; + uint32_t rsrvd1:6; #else - uint64_t rsrvd1:6; - uint64_t mbaddr:26; - uint64_t rsrvd:32; + uint32_t rsrvd1:6; + uint32_t mbaddr:26; + uint32_t rsrvd:32; #endif } bits; } tdc_mbl_t; @@ -542,11 +556,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t byte_count:32; + uint32_t rsrvd:32; + uint32_t byte_count:32; #else - uint64_t byte_count:32; - uint64_t rsrvd:32; + uint32_t byte_count:32; + uint32_t rsrvd:32; #endif } bits; } tdc_byte_cnt_t; @@ -569,13 +583,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t tdr_qlen:16; - uint64_t tdr_pref_qlen:16; + uint32_t rsrvd:32; + uint32_t tdr_qlen:16; + uint32_t tdr_pref_qlen:16; #else - uint64_t tdr_pref_qlen:16; - uint64_t tdr_qlen:16; - uint64_t rsrvd:32; + uint32_t tdr_pref_qlen:16; + uint32_t tdr_qlen:16; + uint32_t rsrvd:32; #endif } bits; } tdc_tdr_qlen_t; @@ -602,19 +616,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:24; - uint64_t pkt_rtab_head:8; - uint64_t rsrvd1:7; - uint64_t rtab_head:9; - uint64_t rsrvd2:7; - uint64_t rtab_tail:9; + uint32_t rsrvd:24; + uint32_t pkt_rtab_head:8; + uint32_t rsrvd1:7; + uint32_t rtab_head:9; + uint32_t rsrvd2:7; + uint32_t rtab_tail:9; #else - uint64_t rtab_tail:9; - uint64_t rsrvd2:7; - uint64_t rtab_head:9; - uint64_t rsrvd1:7; - uint64_t pkt_rtab_head:8; - uint64_t rsrvd:24; + uint32_t rtab_tail:9; + uint32_t rsrvd2:7; + uint32_t rtab_head:9; + uint32_t rsrvd1:7; + uint32_t pkt_rtab_head:8; + uint32_t rsrvd:24; #endif } bits; } tdc_rtab_ptr_t; @@ -656,15 +670,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:40; - uint64_t hdr_size_error_count:8; - uint64_t abort_count:8; - uint64_t runt_count:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:8; + uint32_t hdr_size_error_count:8; + uint32_t abort_count:8; + uint32_t runt_count:8; #else - uint64_t runt_count:8; - uint64_t abort_count:8; - uint64_t hdr_size_error_count:8; - uint64_t rsrvd:40; + uint32_t runt_count:8; + uint32_t abort_count:8; + uint32_t hdr_size_error_count:8; + uint32_t rsrvd_l:8; + uint32_t rsrvd:32; #endif } bits; } tdc_drop_cnt_t; @@ -683,15 +699,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:36; - uint64_t rbuf_tail_ptr:12; - uint64_t rsrvd1:4; - uint64_t rbuf_head_ptr:12; + uint32_t rsrvd:32; + uint32_t rsrvd_l:4; + uint32_t rbuf_tail_ptr:12; + uint32_t rsrvd1:4; + uint32_t rbuf_head_ptr:12; #else - uint64_t rbuf_head_ptr:12; - uint64_t rsrvd1:4; - uint64_t rbuf_tail_ptr:12; - uint64_t rsrvd:36; + uint32_t rbuf_head_ptr:12; + uint32_t rsrvd1:4; + uint32_t rbuf_tail_ptr:12; + uint32_t rsrvd_l:4; + uint32_t rsrvd:32; #endif } bits; } tdc_last_pkt_rbuf_ptrs_t; @@ -718,21 +736,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t par_en:1; - uint64_t rsrvd1:23; - uint64_t dmc:2; - uint64_t entry:4; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t par_en:1; + uint32_t rsrvd1:23; + uint32_t dmc:2; + uint32_t entry:4; #else - uint64_t entry:4; - uint64_t dmc:2; - uint64_t rsrvd1:23; - uint64_t par_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:4; + uint32_t dmc:2; + uint32_t rsrvd1:23; + uint32_t par_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } tdc_pref_cmd_t; @@ -750,9 +768,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } tdc_pref_data_t; @@ -770,11 +790,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:56; - uint64_t par_data:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:24; + uint32_t par_data:8; #else - uint64_t par_data:8; - uint64_t rsrvd:56; + uint32_t par_data:8; + uint32_t rsrvd_l:24; + uint32_t rsrvd:32; #endif } bits; } tdc_pref_par_data_t; @@ -800,19 +822,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t ecc_en:1; - uint64_t rsrvd1:17; - uint64_t entry:12; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t ecc_en:1; + uint32_t rsrvd1:17; + uint32_t entry:12; #else - uint64_t entry:12; - uint64_t rsrvd1:17; - uint64_t ecc_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:12; + uint32_t rsrvd1:17; + uint32_t ecc_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_buf_cmd_t; @@ -830,9 +852,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } tdc_reord_buf_data_t; @@ -850,11 +874,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:56; - uint64_t ecc_data:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:24; + uint32_t ecc_data:8; #else - uint64_t ecc_data:8; - uint64_t rsrvd:56; + uint32_t ecc_data:8; + uint32_t rsrvd_l:24; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_buf_ecc_data_t; @@ -880,19 +906,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t status:1; - uint64_t cmd:1; - uint64_t par_en:1; - uint64_t rsrvd1:21; - uint64_t entry:8; + uint32_t rsrvd:32; + uint32_t status:1; + uint32_t cmd:1; + uint32_t par_en:1; + uint32_t rsrvd1:21; + uint32_t entry:8; #else - uint64_t entry:8; - uint64_t rsrvd1:21; - uint64_t par_en:1; - uint64_t cmd:1; - uint64_t status:1; - uint64_t rsrvd:32; + uint32_t entry:8; + uint32_t rsrvd1:21; + uint32_t par_en:1; + uint32_t cmd:1; + uint32_t status:1; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_tbl_cmd_t; @@ -910,9 +936,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t data:64; + uint32_t data:32; + uint32_t data_l:32; #else - uint64_t data:64; + uint32_t data_l:32; + uint32_t data:32; #endif } bits; } tdc_reord_tbl_data_lo_t; @@ -932,13 +960,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:47; - uint64_t par_data:9; - uint64_t hi_data:8; + uint32_t rsrvd:32; + uint32_t rsrvd_l:15; + uint32_t par_data:9; + uint32_t hi_data:8; #else - uint64_t hi_data:8; - uint64_t par_data:9; - uint64_t rsrvd:47; + uint32_t hi_data:8; + uint32_t par_data:9; + uint32_t rsrvd_l:15; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_tbl_data_hi_t; @@ -958,13 +988,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:26; - uint64_t address:6; + uint32_t rsrvd:32; + uint32_t rsrvd1:26; + uint32_t address:6; #else - uint64_t address:6; - uint64_t rsrvd1:26; - uint64_t rsrvd:32; + uint32_t address:6; + uint32_t rsrvd1:26; + uint32_t rsrvd:32; #endif } bits; } tdc_pref_par_log_t; @@ -985,17 +1015,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:4; - uint64_t address:12; - uint64_t rsrvd2:8; - uint64_t syndrome:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:4; + uint32_t address:12; + uint32_t rsrvd2:8; + uint32_t syndrome:8; #else - uint64_t syndrome:8; - uint64_t rsrvd2:8; - uint64_t address:12; - uint64_t rsrvd1:4; - uint64_t rsrvd:32; + uint32_t syndrome:8; + uint32_t rsrvd2:8; + uint32_t address:12; + uint32_t rsrvd1:4; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_buf_ecc_log_t; @@ -1015,13 +1045,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:24; - uint64_t address:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:24; + uint32_t address:8; #else - uint64_t address:8; - uint64_t rsrvd1:24; - uint64_t rsrvd:32; + uint32_t address:8; + uint32_t rsrvd1:24; + uint32_t rsrvd:32; #endif } bits; } tdc_reord_tbl_par_log_t; @@ -1047,15 +1077,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t reord_tbl_par_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_buf_sec_err:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t reord_tbl_par_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_buf_sec_err:1; #else - uint64_t reord_buf_sec_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_tbl_par_err:1; - uint64_t rsrvd:61; + uint32_t reord_buf_sec_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_tbl_par_err:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } tdc_fifo_err_mask_t; @@ -1084,15 +1116,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t reord_tbl_par_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_buf_sec_err:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t reord_tbl_par_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_buf_sec_err:1; #else - uint64_t reord_buf_sec_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_tbl_par_err:1; - uint64_t rsrvd:61; + uint32_t reord_buf_sec_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_tbl_par_err:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } tdc_fifo_err_stat_t; @@ -1122,15 +1156,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t reord_tbl_par_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_buf_sec_err:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t reord_tbl_par_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_buf_sec_err:1; #else - uint64_t reord_buf_sec_err:1; - uint64_t reord_buf_ded_err:1; - uint64_t reord_tbl_par_err:1; - uint64_t rsrvd:61; + uint32_t reord_buf_sec_err:1; + uint32_t reord_buf_ded_err:1; + uint32_t reord_tbl_par_err:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } tdc_fifo_err_int_dbg_t; @@ -1180,33 +1216,35 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t marked:1; - uint64_t rsrvd1:5; - uint64_t peu_resp_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pref_par_err:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pkt_cpl_to:1; - uint64_t invalid_sop:1; - uint64_t unexpected_sop:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t marked:1; + uint32_t rsrvd1:5; + uint32_t peu_resp_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pref_par_err:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pkt_cpl_to:1; + uint32_t invalid_sop:1; + uint32_t unexpected_sop:1; #else - uint64_t unexpected_sop:1; - uint64_t invalid_sop:1; - uint64_t pkt_cpl_to:1; - uint64_t tdr_pref_cpl_to:1; - uint64_t pref_par_err:1; - uint64_t tx_rng_oflow:1; - uint64_t pkt_size_err:1; - uint64_t runt_pkt_drop_err:1; - uint64_t pkt_size_hdr_err:1; - uint64_t peu_resp_err:1; - uint64_t rsrvd1:5; - uint64_t marked:1; - uint64_t rsrvd:48; + uint32_t unexpected_sop:1; + uint32_t invalid_sop:1; + uint32_t pkt_cpl_to:1; + uint32_t tdr_pref_cpl_to:1; + uint32_t pref_par_err:1; + uint32_t tx_rng_oflow:1; + uint32_t pkt_size_err:1; + uint32_t runt_pkt_drop_err:1; + uint32_t pkt_size_hdr_err:1; + uint32_t peu_resp_err:1; + uint32_t rsrvd1:5; + uint32_t marked:1; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } tdc_stat_int_dbg_t; @@ -1224,13 +1262,13 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t pkt_req_tid_tag:24; - uint64_t rsrvd1:8; + uint32_t rsrvd:32; + uint32_t pkt_req_tid_tag:24; + uint32_t rsrvd1:8; #else - uint64_t rsrvd1:8; - uint64_t pkt_req_tid_tag:24; - uint64_t rsrvd:32; + uint32_t rsrvd1:8; + uint32_t pkt_req_tid_tag:24; + uint32_t rsrvd:32; #endif } bits; } tdc_pkt_req_tid_tag_t; @@ -1253,9 +1291,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t sop_pref_desc_log:64; + uint32_t sop_pref_desc_log:32; + uint32_t sop_pref_desc_log_l:32; #else - uint64_t sop_pref_desc_log:64; + uint32_t sop_pref_desc_log_l:32; + uint32_t sop_pref_desc_log:32; #endif } bits; } tdc_sop_pref_desc_log_t; @@ -1280,9 +1320,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t pref_desc_log:64; + uint32_t pref_desc_log:32; + uint32_t pref_desc_log_l:32; #else - uint64_t pref_desc_log:64; + uint32_t pref_desc_log_l:32; + uint32_t pref_desc_log:32; #endif } bits; } tdc_pref_desc_log_t; @@ -1303,15 +1345,15 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rsrvd1:16; - uint64_t peu_mem_wr_count:8; - uint64_t peu_mem_rd_count:8; + uint32_t rsrvd:32; + uint32_t rsrvd1:16; + uint32_t peu_mem_wr_count:8; + uint32_t peu_mem_rd_count:8; #else - uint64_t peu_mem_rd_count:8; - uint64_t peu_mem_wr_count:8; - uint64_t rsrvd1:16; - uint64_t rsrvd:32; + uint32_t peu_mem_rd_count:8; + uint32_t peu_mem_wr_count:8; + uint32_t rsrvd1:16; + uint32_t rsrvd:32; #endif } bits; } tdc_peu_txn_log_t; @@ -1337,21 +1379,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t dbgx_msb:1; - uint64_t dbgx_bld_num:3; - uint64_t dbgx_training_vec:12; - uint64_t dbgy_msb:1; - uint64_t dbgy_bld_num:3; - uint64_t dbgy_training_vec:12; + uint32_t rsrvd:32; + uint32_t dbgx_msb:1; + uint32_t dbgx_bld_num:3; + uint32_t dbgx_training_vec:12; + uint32_t dbgy_msb:1; + uint32_t dbgy_bld_num:3; + uint32_t dbgy_training_vec:12; #else - uint64_t dbgy_training_vec:12; - uint64_t dbgy_bld_num:3; - uint64_t dbgy_msb:1; - uint64_t dbgx_training_vec:12; - uint64_t dbgx_bld_num:3; - uint64_t dbgx_msb:1; - uint64_t rsrvd:32; + uint32_t dbgy_training_vec:12; + uint32_t dbgy_bld_num:3; + uint32_t dbgy_msb:1; + uint32_t dbgx_training_vec:12; + uint32_t dbgx_bld_num:3; + uint32_t dbgx_msb:1; + uint32_t rsrvd:32; #endif } bits; } tdc_dbg_training_vec_t; @@ -1371,17 +1413,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:48; - uint64_t rsrvd1:1; - uint64_t dbg_h32_sub_sel:7; - uint64_t rsrvd2:1; - uint64_t dbg_l32_sub_sel:7; + uint32_t rsrvd:32; + uint32_t rsrvd_l:16; + uint32_t rsrvd1:1; + uint32_t dbg_h32_sub_sel:7; + uint32_t rsrvd2:1; + uint32_t dbg_l32_sub_sel:7; #else - uint64_t dbg_l32_sub_sel:7; - uint64_t rsrvd2:1; - uint64_t dbg_h32_sub_sel:7; - uint64_t rsrvd1:1; - uint64_t rsrvd:48; + uint32_t dbg_l32_sub_sel:7; + uint32_t rsrvd2:1; + uint32_t dbg_h32_sub_sel:7; + uint32_t rsrvd1:1; + uint32_t rsrvd_l:16; + uint32_t rsrvd:32; #endif } bits; } tdc_dbg_grp_sel_t;
--- a/usr/src/uts/common/io/hxge/hxge_txdma.c Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_txdma.c Thu Jun 12 13:25:54 2008 -0700 @@ -2117,12 +2117,14 @@ HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "PANIC ReordTbl " "unexpected data (hi), entry: %x, value: 0x%0llx\n", i, (unsigned long long)tmp)); + status = HXGE_ERROR; } HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, &tmp); if (tmp != 0) { HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "PANIC ReordTbl " "unexpected data (lo), entry: %x\n", i)); + status = HXGE_ERROR; } HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp); @@ -2130,15 +2132,20 @@ HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "PANIC ReordTbl " "parity error, entry: %x, val 0x%llx\n", i, (unsigned long long)tmp)); + status = HXGE_ERROR; } HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp); if (tmp != 0) { HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "PANIC ReordTbl " "parity error, entry: %x\n", i)); + status = HXGE_ERROR; } } + if (status != HXGE_OK) + goto hxge_txdma_hw_start_exit; + /* * Reset FIFO Error Status for the TDC and enable FIFO error events. */ @@ -2154,6 +2161,9 @@ "<== hxge_txdma_hw_start: NULL ring pointer")); return (HXGE_ERROR); } + + tx_rings->dma_to_reenable = 0; + tx_desc_rings = tx_rings->rings; if (tx_desc_rings == NULL) { HXGE_DEBUG_MSG((hxgep, TX_CTL, @@ -2619,6 +2629,58 @@ return (status); } +static hxge_status_t +hxge_txdma_wait_for_qst(p_hxge_t hxgep, int channel) +{ + hpi_status_t rs; + hxge_status_t status = HXGE_OK; + hpi_handle_t handle; + + handle = HXGE_DEV_HPI_HANDLE(hxgep); + + /* + * Wait for QST state of the DMA. + */ + rs = hpi_txdma_control_stop_wait(handle, channel); + if (rs != HPI_SUCCESS) + status = HXGE_ERROR; + + return (status); +} + +static hxge_status_t +hxge_txdma_handle_rtab_error(p_hxge_t hxgep) +{ + hxge_status_t status = HXGE_OK; + int ndmas, i; + uint16_t chnl; + + ndmas = hxgep->tx_rings->ndmas; + + /* + * Make sure each DMA is in the QST state. + */ + for (i = 0; i < ndmas; i++) { + status = hxge_txdma_wait_for_qst(hxgep, i); + if (status != HXGE_OK) + goto hxge_txdma_handle_rtab_error_exit; + } + + /* + * Enable the DMAs. + */ + for (i = 0; i < ndmas; i++) { + chnl = (hxgep->tx_rings->dma_to_reenable + i) % ndmas; + hxge_txdma_enable_channel(hxgep, chnl); + } + + hxgep->tx_rings->dma_to_reenable = + (hxgep->tx_rings->dma_to_reenable + 1) % ndmas; + +hxge_txdma_handle_rtab_error_exit: + return (status); +} + hxge_status_t hxge_txdma_handle_sys_errors(p_hxge_t hxgep) { @@ -2646,11 +2708,7 @@ tdc_sys_stats = &hxgep->statsp->tdc_sys_stats; if (fifo_stat.bits.reord_tbl_par_err) { tdc_sys_stats->reord_tbl_par_err++; - HXGE_FM_REPORT_ERROR(hxgep, NULL, - HXGE_FM_EREPORT_TDMC_REORD_TBL_PAR); - HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, - "==> hxge_txdma_handle_sys_errors: fatal error: " - "reord_tbl_par_err")); + status = hxge_txdma_handle_rtab_error(hxgep); } if (fifo_stat.bits.reord_buf_ded_err) { @@ -2670,8 +2728,7 @@ "reord_buf_sec_err")); } - if (fifo_stat.bits.reord_tbl_par_err || - fifo_stat.bits.reord_buf_ded_err) { + if (fifo_stat.bits.reord_buf_ded_err) { status = hxge_tx_port_fatal_err_recover(hxgep); if (status == HXGE_OK) { FM_SERVICE_RESTORED(hxgep);
--- a/usr/src/uts/common/io/hxge/hxge_txdma.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_txdma.h Thu Jun 12 13:25:54 2008 -0700 @@ -187,6 +187,7 @@ p_tx_ring_t *rings; boolean_t txdesc_allocated; uint32_t ndmas; + uint32_t dma_to_reenable; hxge_os_dma_common_t tdc_dma; hxge_os_dma_common_t tdc_mbox; } tx_rings_t, *p_tx_rings_t;
--- a/usr/src/uts/common/io/hxge/hxge_txdma_hw.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_txdma_hw.h Thu Jun 12 13:25:54 2008 -0700 @@ -44,19 +44,21 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t sop:1; - uint64_t mark:1; - uint64_t num_ptr:4; - uint64_t rsvd:1; - uint64_t tr_len:13; - uint64_t sad:44; + uint32_t sop:1; + uint32_t mark:1; + uint32_t num_ptr:4; + uint32_t rsvd:1; + uint32_t tr_len:13; + uint32_t sad:12; + uint32_t sad_l:32; #else - uint64_t sad:44; - uint64_t tr_len:13; - uint64_t rsvd:1; - uint64_t num_ptr:4; - uint64_t mark:1; - uint64_t sop:1; + uint32_t sad_l:32; + uint32_t sad:12; + uint32_t tr_len:13; + uint32_t rsvd:1; + uint32_t num_ptr:4; + uint32_t mark:1; + uint32_t sop:1; #endif } bits; } tx_desc_t, *p_tx_desc_t; @@ -161,35 +163,35 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t cksum_en_pkt_type:2; - uint64_t ip_ver:1; - uint64_t rsrvd:4; - uint64_t vlan:1; - uint64_t ihl:4; - uint64_t l3start:4; - uint64_t rsvrvd1:2; - uint64_t l4start:6; - uint64_t rsvrvd2:2; - uint64_t l4stuff:6; - uint64_t rsvrvd3:2; - uint64_t tot_xfer_len:14; - uint64_t rsrrvd4:13; - uint64_t pad:3; + uint32_t cksum_en_pkt_type:2; + uint32_t ip_ver:1; + uint32_t rsrvd:4; + uint32_t vlan:1; + uint32_t ihl:4; + uint32_t l3start:4; + uint32_t rsvrvd1:2; + uint32_t l4start:6; + uint32_t rsvrvd2:2; + uint32_t l4stuff:6; + uint32_t rsvrvd3:2; + uint32_t tot_xfer_len:14; + uint32_t rsrrvd4:13; + uint32_t pad:3; #else - uint64_t pad:3; - uint64_t rsrrvd4:13; - uint64_t tot_xfer_len:14; - uint64_t rsvrvd3:2; - uint64_t l4stuff:6; - uint64_t rsvrvd2:2; - uint64_t l4start:6; - uint64_t rsvrvd1:2; - uint64_t l3start:4; - uint64_t ihl:4; - uint64_t vlan:1; - uint64_t rsrvd:4; - uint64_t ip_ver:1; - uint64_t cksum_en_pkt_type:2; + uint32_t pad:3; + uint32_t rsrrvd4:13; + uint32_t tot_xfer_len:14; + uint32_t rsvrvd3:2; + uint32_t l4stuff:6; + uint32_t rsvrvd2:2; + uint32_t l4start:6; + uint32_t rsvrvd1:2; + uint32_t l3start:4; + uint32_t ihl:4; + uint32_t vlan:1; + uint32_t rsrvd:4; + uint32_t ip_ver:1; + uint32_t cksum_en_pkt_type:2; #endif } bits; } tx_pkt_header_t, *p_tx_pkt_header_t;
--- a/usr/src/uts/common/io/hxge/hxge_vmac_hw.h Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/common/io/hxge/hxge_vmac_hw.h Thu Jun 12 13:25:54 2008 -0700 @@ -69,15 +69,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:55; - uint64_t rx_reset:1; - uint64_t rsrvd1:7; - uint64_t tx_reset:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:23; + uint32_t rx_reset:1; + uint32_t rsrvd1:7; + uint32_t tx_reset:1; #else - uint64_t tx_reset:1; - uint64_t rsrvd1:7; - uint64_t rx_reset:1; - uint64_t rsrvd:55; + uint32_t tx_reset:1; + uint32_t rsrvd1:7; + uint32_t rx_reset:1; + uint32_t rsrvd_l:23; + uint32_t rsrvd:32; #endif } bits; } vmac_rst_t; @@ -114,19 +116,19 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t tx_max_frame_length:14; - uint64_t rsrvd1:15; - uint64_t tx_pad:1; - uint64_t crc_insert:1; - uint64_t tx_en:1; + uint32_t rsrvd:32; + uint32_t tx_max_frame_length:14; + uint32_t rsrvd1:15; + uint32_t tx_pad:1; + uint32_t crc_insert:1; + uint32_t tx_en:1; #else - uint64_t tx_en:1; - uint64_t crc_insert:1; - uint64_t tx_pad:1; - uint64_t rsrvd1:15; - uint64_t tx_max_frame_length:14; - uint64_t rsrvd:32; + uint32_t tx_en:1; + uint32_t crc_insert:1; + uint32_t tx_pad:1; + uint32_t rsrvd1:15; + uint32_t tx_max_frame_length:14; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_cfg_t; @@ -162,27 +164,27 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_max_frame_length:14; - uint64_t reserved:11; - uint64_t loopback:1; - uint64_t promiscuous_mode:1; - uint64_t promiscuous_group:1; - uint64_t pass_flow_ctrl_fr:1; - uint64_t strip_crc:1; - uint64_t crc_check_disable:1; - uint64_t rx_en:1; + uint32_t rsrvd:32; + uint32_t rx_max_frame_length:14; + uint32_t reserved:11; + uint32_t loopback:1; + uint32_t promiscuous_mode:1; + uint32_t promiscuous_group:1; + uint32_t pass_flow_ctrl_fr:1; + uint32_t strip_crc:1; + uint32_t crc_check_disable:1; + uint32_t rx_en:1; #else - uint64_t rx_en:1; - uint64_t crc_check_disable:1; - uint64_t strip_crc:1; - uint64_t pass_flow_ctrl_fr:1; - uint64_t promiscuous_group:1; - uint64_t promiscuous_mode:1; - uint64_t loopback:1; - uint64_t reserved:11; - uint64_t rx_max_frame_length:14; - uint64_t rsrvd:32; + uint32_t rx_en:1; + uint32_t crc_check_disable:1; + uint32_t strip_crc:1; + uint32_t pass_flow_ctrl_fr:1; + uint32_t promiscuous_group:1; + uint32_t promiscuous_mode:1; + uint32_t loopback:1; + uint32_t reserved:11; + uint32_t rx_max_frame_length:14; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_cfg_t; @@ -206,15 +208,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t tx_byte_cnt_overflow:1; - uint64_t tx_frame_cnt_overflow:1; - uint64_t frame_tx:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t tx_byte_cnt_overflow:1; + uint32_t tx_frame_cnt_overflow:1; + uint32_t frame_tx:1; #else - uint64_t frame_tx:1; - uint64_t tx_frame_cnt_overflow:1; - uint64_t tx_byte_cnt_overflow:1; - uint64_t rsrvd:61; + uint32_t frame_tx:1; + uint32_t tx_frame_cnt_overflow:1; + uint32_t tx_byte_cnt_overflow:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_stat_t; @@ -235,15 +239,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t tx_byte_cnt_overflow_msk:1; - uint64_t tx_frame_cnt_overflow_msk:1; - uint64_t frame_tx_msk:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t tx_byte_cnt_overflow_msk:1; + uint32_t tx_frame_cnt_overflow_msk:1; + uint32_t frame_tx_msk:1; #else - uint64_t frame_tx_msk:1; - uint64_t tx_frame_cnt_overflow_msk:1; - uint64_t tx_byte_cnt_overflow_msk:1; - uint64_t rsrvd:61; + uint32_t frame_tx_msk:1; + uint32_t tx_frame_cnt_overflow_msk:1; + uint32_t tx_byte_cnt_overflow_msk:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_msk_t; @@ -280,27 +286,29 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:55; - uint64_t bcast_cnt_overflow:1; - uint64_t mcast_cnt_overflow:1; - uint64_t pause_cnt_overflow:1; - uint64_t crc_err_cnt_overflow:1; - uint64_t rx_drop_byte_cnt_overflow:1; - uint64_t rx_drop_frame_cnt_overflow:1; - uint64_t rx_byte_cnt_overflow:1; - uint64_t rx_frame_cnt_overflow:1; - uint64_t frame_rx:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:23; + uint32_t bcast_cnt_overflow:1; + uint32_t mcast_cnt_overflow:1; + uint32_t pause_cnt_overflow:1; + uint32_t crc_err_cnt_overflow:1; + uint32_t rx_drop_byte_cnt_overflow:1; + uint32_t rx_drop_frame_cnt_overflow:1; + uint32_t rx_byte_cnt_overflow:1; + uint32_t rx_frame_cnt_overflow:1; + uint32_t frame_rx:1; #else - uint64_t frame_rx:1; - uint64_t rx_frame_cnt_overflow:1; - uint64_t rx_byte_cnt_overflow:1; - uint64_t rx_drop_frame_cnt_overflow:1; - uint64_t rx_drop_byte_cnt_overflow:1; - uint64_t crc_err_cnt_overflow:1; - uint64_t pause_cnt_overflow:1; - uint64_t mcast_cnt_overflow:1; - uint64_t bcast_cnt_overflow:1; - uint64_t rsrvd:55; + uint32_t frame_rx:1; + uint32_t rx_frame_cnt_overflow:1; + uint32_t rx_byte_cnt_overflow:1; + uint32_t rx_drop_frame_cnt_overflow:1; + uint32_t rx_drop_byte_cnt_overflow:1; + uint32_t crc_err_cnt_overflow:1; + uint32_t pause_cnt_overflow:1; + uint32_t mcast_cnt_overflow:1; + uint32_t bcast_cnt_overflow:1; + uint32_t rsrvd_l:23; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_stat_t; @@ -330,27 +338,29 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:55; - uint64_t bcast_cnt_overflow_msk:1; - uint64_t mcast_cnt_overflow_msk:1; - uint64_t pause_cnt_overflow_msk:1; - uint64_t crc_err_cnt_overflow_msk:1; - uint64_t rx_drop_byte_cnt_overflow_msk:1; - uint64_t rx_drop_frame_cnt_overflow_msk:1; - uint64_t rx_byte_cnt_overflow_msk:1; - uint64_t rx_frame_cnt_overflow_msk:1; - uint64_t frame_rx_msk:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:23; + uint32_t bcast_cnt_overflow_msk:1; + uint32_t mcast_cnt_overflow_msk:1; + uint32_t pause_cnt_overflow_msk:1; + uint32_t crc_err_cnt_overflow_msk:1; + uint32_t rx_drop_byte_cnt_overflow_msk:1; + uint32_t rx_drop_frame_cnt_overflow_msk:1; + uint32_t rx_byte_cnt_overflow_msk:1; + uint32_t rx_frame_cnt_overflow_msk:1; + uint32_t frame_rx_msk:1; #else - uint64_t frame_rx_msk:1; - uint64_t rx_frame_cnt_overflow_msk:1; - uint64_t rx_byte_cnt_overflow_msk:1; - uint64_t rx_drop_frame_cnt_overflow_msk:1; - uint64_t rx_drop_byte_cnt_overflow_msk:1; - uint64_t crc_err_cnt_overflow_msk:1; - uint64_t pause_cnt_overflow_msk:1; - uint64_t mcast_cnt_overflow_msk:1; - uint64_t bcast_cnt_overflow_msk:1; - uint64_t rsrvd:55; + uint32_t frame_rx_msk:1; + uint32_t rx_frame_cnt_overflow_msk:1; + uint32_t rx_byte_cnt_overflow_msk:1; + uint32_t rx_drop_frame_cnt_overflow_msk:1; + uint32_t rx_drop_byte_cnt_overflow_msk:1; + uint32_t crc_err_cnt_overflow_msk:1; + uint32_t pause_cnt_overflow_msk:1; + uint32_t mcast_cnt_overflow_msk:1; + uint32_t bcast_cnt_overflow_msk:1; + uint32_t rsrvd_l:23; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_msk_t; @@ -375,15 +385,17 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:61; - uint64_t force_tx_byte_cnt_overflow:1; - uint64_t force_tx_frame_cnt_overflow:1; - uint64_t force_frame_tx:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:29; + uint32_t force_tx_byte_cnt_overflow:1; + uint32_t force_tx_frame_cnt_overflow:1; + uint32_t force_frame_tx:1; #else - uint64_t force_frame_tx:1; - uint64_t force_tx_frame_cnt_overflow:1; - uint64_t force_tx_byte_cnt_overflow:1; - uint64_t rsrvd:61; + uint32_t force_frame_tx:1; + uint32_t force_tx_frame_cnt_overflow:1; + uint32_t force_tx_byte_cnt_overflow:1; + uint32_t rsrvd_l:29; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_stat_mirror_t; @@ -416,27 +428,29 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:55; - uint64_t force_bcast_cnt_overflow:1; - uint64_t force_mcast_cnt_overflow:1; - uint64_t force_pause_cnt_overflow:1; - uint64_t force_crc_err_cnt_overflow:1; - uint64_t force_rx_drop_byte_cnt_overflow:1; - uint64_t force_rx_drop_frame_cnt_overflow:1; - uint64_t force_rx_byte_cnt_overflow:1; - uint64_t force_rx_frame_cnt_overflow:1; - uint64_t force_frame_rx:1; + uint32_t rsrvd:32; + uint32_t rsrvd_l:23; + uint32_t force_bcast_cnt_overflow:1; + uint32_t force_mcast_cnt_overflow:1; + uint32_t force_pause_cnt_overflow:1; + uint32_t force_crc_err_cnt_overflow:1; + uint32_t force_rx_drop_byte_cnt_overflow:1; + uint32_t force_rx_drop_frame_cnt_overflow:1; + uint32_t force_rx_byte_cnt_overflow:1; + uint32_t force_rx_frame_cnt_overflow:1; + uint32_t force_frame_rx:1; #else - uint64_t force_frame_rx:1; - uint64_t force_rx_frame_cnt_overflow:1; - uint64_t force_rx_byte_cnt_overflow:1; - uint64_t force_rx_drop_frame_cnt_overflow:1; - uint64_t force_rx_drop_byte_cnt_overflow:1; - uint64_t force_crc_err_cnt_overflow:1; - uint64_t force_pause_cnt_overflow:1; - uint64_t force_mcast_cnt_overflow:1; - uint64_t force_bcast_cnt_overflow:1; - uint64_t rsrvd:55; + uint32_t force_frame_rx:1; + uint32_t force_rx_frame_cnt_overflow:1; + uint32_t force_rx_byte_cnt_overflow:1; + uint32_t force_rx_drop_frame_cnt_overflow:1; + uint32_t force_rx_drop_byte_cnt_overflow:1; + uint32_t force_crc_err_cnt_overflow:1; + uint32_t force_pause_cnt_overflow:1; + uint32_t force_mcast_cnt_overflow:1; + uint32_t force_bcast_cnt_overflow:1; + uint32_t rsrvd_l:23; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_stat_mirror_t; @@ -455,11 +469,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t tx_frame_cnt:32; + uint32_t rsrvd:32; + uint32_t tx_frame_cnt:32; #else - uint64_t tx_frame_cnt:32; - uint64_t rsrvd:32; + uint32_t tx_frame_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_frame_cnt_t; @@ -480,11 +494,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t tx_byte_cnt:32; + uint32_t rsrvd:32; + uint32_t tx_byte_cnt:32; #else - uint64_t tx_byte_cnt:32; - uint64_t rsrvd:32; + uint32_t tx_byte_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_tx_byte_cnt_t; @@ -503,11 +517,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_frame_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_frame_cnt:32; #else - uint64_t rx_frame_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_frame_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_frame_cnt_t; @@ -527,11 +541,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_byte_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_byte_cnt:32; #else - uint64_t rx_byte_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_byte_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_byte_cnt_t; @@ -554,11 +568,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_drop_frame_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_drop_frame_cnt:32; #else - uint64_t rx_drop_frame_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_drop_frame_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_drop_fr_cnt_t; @@ -581,11 +595,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_drop_byte_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_drop_byte_cnt:32; #else - uint64_t rx_drop_byte_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_drop_byte_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_drop_byte_cnt_t; @@ -609,11 +623,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_crc_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_crc_cnt:32; #else - uint64_t rx_crc_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_crc_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_crc_cnt_t; @@ -632,11 +646,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_pause_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_pause_cnt:32; #else - uint64_t rx_pause_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_pause_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_pause_cnt_t; @@ -654,11 +668,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_bcast_fr_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_bcast_fr_cnt:32; #else - uint64_t rx_bcast_fr_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_bcast_fr_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_bcast_fr_cnt_t; @@ -676,11 +690,11 @@ uint64_t value; struct { #if defined(_BIG_ENDIAN) - uint64_t rsrvd:32; - uint64_t rx_mcast_fr_cnt:32; + uint32_t rsrvd:32; + uint32_t rx_mcast_fr_cnt:32; #else - uint64_t rx_mcast_fr_cnt:32; - uint64_t rsrvd:32; + uint32_t rx_mcast_fr_cnt:32; + uint32_t rsrvd:32; #endif } bits; } vmac_rx_mcast_fr_cnt_t;
--- a/usr/src/uts/intel/Makefile.intel.shared Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/intel/Makefile.intel.shared Thu Jun 12 13:25:54 2008 -0700 @@ -233,6 +233,7 @@ DRV_KMODS += fd DRV_KMODS += fdc DRV_KMODS += fssnap +DRV_KMODS += hxge DRV_KMODS += i8042 DRV_KMODS += i915 DRV_KMODS += icmp @@ -328,7 +329,6 @@ DRV_KMODS += zcons DRV_KMODS += chxge DRV_KMODS += nsmb -DRV_KMODS += hxge # # Don't build some of these for OpenSolaris, since they will be
--- a/usr/src/uts/intel/hxge/Makefile Thu Jun 12 13:12:05 2008 -0700 +++ b/usr/src/uts/intel/hxge/Makefile Thu Jun 12 13:25:54 2008 -0700 @@ -83,12 +83,6 @@ # # CFLAGS += -DHXGE_DEBUG -DHPI_DEBUG # -# 64 bit only -# -ALL_BUILDS = $(ALL_BUILDS64) -DEF_BUILDS = $(DEF_BUILDS64) -CLEANLINTFILES += $(LINT64_FILES) -# LINTFLAGS += -DSOLARIS # # STREAMS, DDI API limitations and other ON header file definitions such as ethernet.h @@ -117,7 +111,7 @@ lint: $(LINT_DEPS) -modlintlib: $(MODLINTLIB_DEPS) lint32 +modlintlib: $(MODLINTLIB_DEPS) clean.lint: $(CLEAN_LINT_DEPS) @@ -127,11 +121,3 @@ # Include common targets. # include $(UTSBASE)/intel/Makefile.targ - -# -# This is a hack to avoid a lint warning in the nightly build due to -# lack of a 32 bit version of the hxge driver. This will be removed -# when the 32 bit driver is available. -# -LINT32_DIRS=$(LINT32_BUILDS:%=$(UTSBASE)/intel/lint-libs/%) -LINT32_FILES=$(LINT32_DIRS:%=%/llib-l$(MODULE).ln)