changeset 10136:511580c70e26

6840236 AMD errata 91 needs more work
author George Wilson <George.Wilson@Sun.COM>
date Mon, 20 Jul 2009 14:51:44 -0700
parents 5163295a46a3
children bdbc0ef4c18b
files usr/src/uts/i86pc/os/trap.c
diffstat 1 files changed, 5 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/i86pc/os/trap.c	Mon Jul 20 17:13:57 2009 -0400
+++ b/usr/src/uts/i86pc/os/trap.c	Mon Jul 20 14:51:44 2009 -0700
@@ -420,7 +420,9 @@
  *
  * The first byte of prefetch instructions is always 0x0F.
  * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
- * The third byte is between 0 and 3 inclusive.
+ * The third byte (ModRM) contains the register field bits (bits 3-5).
+ * These bits must be between 0 and 3 inclusive for regular prefetch and
+ * 0 and 1 inclusive for AMD 3dnow prefetch.
  *
  * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
  */
@@ -432,7 +434,8 @@
 	if ((p[0] & 0xF0) == 0x40)	/* 64-bit REX prefix */
 		p++;
 #endif
-	return (p[0] == 0x0F && (p[1] == 0x18 || p[1] == 0x0D) && p[2] <= 3);
+	return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
+	    (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
 }
 
 static int