Mercurial > illumos > illumos-gate
changeset 4919:b6b235c6e23b
6535620 e1000g needs to support ICH9 devices
6572330 e1000g: integrate the latest Intel refactored shared code
6573381 e1000g receiving VLAN tagged frames does not do hardware checksumming
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/deleted_files/usr/src/uts/common/io/e1000g/e1000_hw.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,9309 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * e1000_hw.c + * Shared functions for accessing and configuring the MAC + * IntelVersion: 1.428.2.1 + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#include "e1000_hw.h" + +#define STATIC static + +static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); +static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); +static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); +static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); +static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); +static void e1000_release_software_semaphore(struct e1000_hw *hw); + +static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); +static int32_t e1000_check_downshift(struct e1000_hw *hw); +static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); +static void e1000_clear_vfta(struct e1000_hw *hw); +static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); +static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); +static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); +static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); +static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); +static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); +static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); +static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); +static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); +static int32_t e1000_get_software_flag(struct e1000_hw *hw); +static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); +static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); +static int32_t e1000_id_led_init(struct e1000_hw *hw); +static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); +static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); +static void e1000_init_rx_addrs(struct e1000_hw *hw); +static void e1000_initialize_hardware_bits(struct e1000_hw *hw); +static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); +static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); +static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); +static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); +static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); +static int32_t e1000_mng_write_commit(struct e1000_hw *hw); +static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); +static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); +static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); +static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); +static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); +static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); +static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); +static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); +static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); +static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); +static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); +static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); +static void e1000_release_software_flag(struct e1000_hw *hw); +static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); +static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); +static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); +static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); +static int32_t e1000_wait_autoneg(struct e1000_hw *hw); +static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); +static int32_t e1000_set_phy_type(struct e1000_hw *hw); +static void e1000_phy_init_script(struct e1000_hw *hw); +static int32_t e1000_setup_copper_link(struct e1000_hw *hw); +static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); +static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); +static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); +static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); +static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); +static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); +static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, + uint16_t count); +static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); +static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); +static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, + uint16_t words, uint16_t *data); +static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, + uint16_t offset, uint16_t words, + uint16_t *data); +static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); +static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, + uint16_t count); +static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data); +static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, + uint16_t *phy_data); +static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); +static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); +static void e1000_release_eeprom(struct e1000_hw *hw); +static void e1000_standby_eeprom(struct e1000_hw *hw); +static int32_t e1000_set_vco_speed(struct e1000_hw *hw); +static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); +static int32_t e1000_set_phy_mode(struct e1000_hw *hw); +static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); +static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); +static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, + uint16_t duplex); +static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); + +/* IGP cable length table */ +static const +uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = + { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, + 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, + 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, + 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, + 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, + 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; + +static const +uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, + 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, + 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, + 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, + 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, + 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, + 104, 109, 114, 118, 121, 124}; + +/****************************************************************************** + * Set the phy type member in the hw struct. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +STATIC int32_t +e1000_set_phy_type(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_set_phy_type"); + + if (hw->mac_type == e1000_undefined) + return -E1000_ERR_PHY_TYPE; + + switch (hw->phy_id) { + case M88E1000_E_PHY_ID: + case M88E1000_I_PHY_ID: + case M88E1011_I_PHY_ID: + case M88E1111_I_PHY_ID: + hw->phy_type = e1000_phy_m88; + break; + case IGP01E1000_I_PHY_ID: + if (hw->mac_type == e1000_82541 || + hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547 || + hw->mac_type == e1000_82547_rev_2) { + hw->phy_type = e1000_phy_igp; + break; + } + case IGP03E1000_E_PHY_ID: + hw->phy_type = e1000_phy_igp_3; + break; + case IFE_E_PHY_ID: + case IFE_PLUS_E_PHY_ID: + case IFE_C_E_PHY_ID: + hw->phy_type = e1000_phy_ife; + break; + case GG82563_E_PHY_ID: + if (hw->mac_type == e1000_80003es2lan) { + hw->phy_type = e1000_phy_gg82563; + break; + } + /* Fall Through */ + default: + /* Should never have loaded on this device */ + hw->phy_type = e1000_phy_undefined; + return -E1000_ERR_PHY_TYPE; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * IGP phy init script - initializes the GbE PHY + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_phy_init_script(struct e1000_hw *hw) +{ + uint32_t ret_val; + uint16_t phy_saved_data; + + DEBUGFUNC("e1000_phy_init_script"); + + if (hw->phy_init_script) { + msec_delay(20); + + /* Save off the current value of register 0x2F5B to be restored at + * the end of this routine. */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + + /* Disabled the PHY transmitter */ + e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + + msec_delay(20); + + e1000_write_phy_reg(hw,0x0000,0x0140); + + msec_delay(5); + + switch (hw->mac_type) { + case e1000_82541: + case e1000_82547: + e1000_write_phy_reg(hw, 0x1F95, 0x0001); + + e1000_write_phy_reg(hw, 0x1F71, 0xBD21); + + e1000_write_phy_reg(hw, 0x1F79, 0x0018); + + e1000_write_phy_reg(hw, 0x1F30, 0x1600); + + e1000_write_phy_reg(hw, 0x1F31, 0x0014); + + e1000_write_phy_reg(hw, 0x1F32, 0x161C); + + e1000_write_phy_reg(hw, 0x1F94, 0x0003); + + e1000_write_phy_reg(hw, 0x1F96, 0x003F); + + e1000_write_phy_reg(hw, 0x2010, 0x0008); + break; + + case e1000_82541_rev_2: + case e1000_82547_rev_2: + e1000_write_phy_reg(hw, 0x1F73, 0x0099); + break; + default: + break; + } + + e1000_write_phy_reg(hw, 0x0000, 0x3300); + + msec_delay(20); + + /* Now enable the transmitter */ + e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (hw->mac_type == e1000_82547) { + uint16_t fused, fine, coarse; + + /* Move to analog registers page */ + e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); + + if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { + e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); + + fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; + coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; + + if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { + coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; + fine -= IGP01E1000_ANALOG_FUSE_FINE_1; + } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) + fine -= IGP01E1000_ANALOG_FUSE_FINE_10; + + fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | + (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | + (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); + + e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); + e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, + IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); + } + } + } +} + +/****************************************************************************** + * Set the mac type member in the hw struct. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_set_mac_type(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_set_mac_type"); + + switch (hw->device_id) { + case E1000_DEV_ID_82542: + switch (hw->revision_id) { + case E1000_82542_2_0_REV_ID: + hw->mac_type = e1000_82542_rev2_0; + break; + case E1000_82542_2_1_REV_ID: + hw->mac_type = e1000_82542_rev2_1; + break; + default: + /* Invalid 82542 revision ID */ + return -E1000_ERR_MAC_TYPE; + } + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + hw->mac_type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + hw->mac_type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + case E1000_DEV_ID_82540EP: + case E1000_DEV_ID_82540EP_LOM: + case E1000_DEV_ID_82540EP_LP: + hw->mac_type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + hw->mac_type = e1000_82545; + break; + case E1000_DEV_ID_82545GM_COPPER: + case E1000_DEV_ID_82545GM_FIBER: + case E1000_DEV_ID_82545GM_SERDES: + hw->mac_type = e1000_82545_rev_3; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546EB_QUAD_COPPER: + hw->mac_type = e1000_82546; + break; + case E1000_DEV_ID_82546GB_COPPER: + case E1000_DEV_ID_82546GB_FIBER: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82546GB_PCIE: + case E1000_DEV_ID_82546GB_QUAD_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: + hw->mac_type = e1000_82546_rev_3; + break; + case E1000_DEV_ID_82541EI: + case E1000_DEV_ID_82541EI_MOBILE: + case E1000_DEV_ID_82541ER_LOM: + hw->mac_type = e1000_82541; + break; + case E1000_DEV_ID_82541ER: + case E1000_DEV_ID_82541GI: + case E1000_DEV_ID_82541GI_LF: + case E1000_DEV_ID_82541GI_MOBILE: + hw->mac_type = e1000_82541_rev_2; + break; + case E1000_DEV_ID_82547EI: + case E1000_DEV_ID_82547EI_MOBILE: + hw->mac_type = e1000_82547; + break; + case E1000_DEV_ID_82547GI: + hw->mac_type = e1000_82547_rev_2; + break; + case E1000_DEV_ID_82571EB_COPPER: + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_QUAD_COPPER: + case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: + case E1000_DEV_ID_82571PT_QUAD_COPPER: + hw->mac_type = e1000_82571; + break; + case E1000_DEV_ID_82572EI_COPPER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82572EI_SERDES: + case E1000_DEV_ID_82572EI: + hw->mac_type = e1000_82572; + break; + case E1000_DEV_ID_82573E: + case E1000_DEV_ID_82573E_IAMT: + case E1000_DEV_ID_82573L: + hw->mac_type = e1000_82573; + break; + case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: + case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + hw->mac_type = e1000_80003es2lan; + break; + case E1000_DEV_ID_ICH8_IGP_M_AMT: + case E1000_DEV_ID_ICH8_IGP_AMT: + case E1000_DEV_ID_ICH8_IGP_C: + case E1000_DEV_ID_ICH8_IFE: + case E1000_DEV_ID_ICH8_IFE_GT: + case E1000_DEV_ID_ICH8_IFE_G: + case E1000_DEV_ID_ICH8_IGP_M: + hw->mac_type = e1000_ich8lan; + break; + default: + /* Should never have loaded on this device */ + return -E1000_ERR_MAC_TYPE; + } + + switch (hw->mac_type) { + case e1000_ich8lan: + hw->swfwhw_semaphore_present = TRUE; + hw->asf_firmware_present = TRUE; + break; + case e1000_80003es2lan: + hw->swfw_sync_present = TRUE; + /* fall through */ + case e1000_82571: + case e1000_82572: + case e1000_82573: + hw->eeprom_semaphore_present = TRUE; + /* fall through */ + case e1000_82541: + case e1000_82547: + case e1000_82541_rev_2: + case e1000_82547_rev_2: + hw->asf_firmware_present = TRUE; + break; + default: + break; + } + + return E1000_SUCCESS; +} + +/***************************************************************************** + * Set media type and TBI compatibility. + * + * hw - Struct containing variables accessed by shared code + * **************************************************************************/ +void +e1000_set_media_type(struct e1000_hw *hw) +{ + uint32_t status; + + DEBUGFUNC("e1000_set_media_type"); + + if (hw->mac_type != e1000_82543) { + /* tbi_compatibility is only valid on 82543 */ + hw->tbi_compatibility_en = FALSE; + } + + switch (hw->device_id) { + case E1000_DEV_ID_82545GM_SERDES: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82572EI_SERDES: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + hw->media_type = e1000_media_type_internal_serdes; + break; + default: + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + hw->media_type = e1000_media_type_fiber; + break; + case e1000_ich8lan: + case e1000_82573: + /* The STATUS_TBIMODE bit is reserved or reused for the this + * device. + */ + hw->media_type = e1000_media_type_copper; + break; + default: + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_TBIMODE) { + hw->media_type = e1000_media_type_fiber; + /* tbi_compatibility not valid on fiber */ + hw->tbi_compatibility_en = FALSE; + } else { + hw->media_type = e1000_media_type_copper; + } + break; + } + } +} + +/****************************************************************************** + * Reset the transmit and receive units; mask and clear all interrupts. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_reset_hw(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + uint32_t icr; + uint32_t manc; + uint32_t led_ctrl; + uint32_t timeout; + uint32_t extcnf_ctrl; + int32_t ret_val; + + DEBUGFUNC("e1000_reset_hw"); + + /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + e1000_pci_clear_mwi(hw); + } + + if (hw->bus_type == e1000_bus_type_pci_express) { + /* Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ + if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { + DEBUGOUT("PCI-E Master disable polling has failed.\n"); + } + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Disable the Transmit and Receive units. Then delay to allow + * any pending transactions to complete before we hit the MAC with + * the global reset. + */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); +#ifndef FIFO_WORKAROUND + hw->tx_fifo_head = 0; +#endif + + /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ + hw->tbi_compatibility_on = FALSE; + + /* Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + msec_delay(10); + + ctrl = E1000_READ_REG(hw, CTRL); + + /* Must reset the PHY before resetting the MAC */ + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); + msec_delay(5); + } + + /* Must acquire the MDIO ownership before MAC reset. + * Ownership defaults to firmware after a reset. */ + if (hw->mac_type == e1000_82573) { + timeout = 10; + + extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; + + do { + E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); + extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); + + if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) + break; + else + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; + + msec_delay(2); + timeout--; + } while (timeout); + } + + /* Workaround for ICH8 bit corruption issue in FIFO memory */ + if (hw->mac_type == e1000_ich8lan) { + /* Set Tx and Rx buffer allocation to 8k apiece. */ + E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); + /* Set Packet Buffer Size to 16k. */ + E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); + } + + /* Issue a global reset to the MAC. This will reset the chip's + * transmit, receive, DMA, and link units. It will not effect + * the current PCI configuration. The global reset bit is self- + * clearing, and should clear within a microsecond. + */ + DEBUGOUT("Issuing a global reset to MAC\n"); + + switch (hw->mac_type) { + case e1000_82544: + case e1000_82540: + case e1000_82545: + case e1000_82546: + case e1000_82541: + case e1000_82541_rev_2: + /* These controllers can't ack the 64-bit write when issuing the + * reset, so use IO-mapping as a workaround to issue the reset */ + E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); + break; + case e1000_82545_rev_3: + case e1000_82546_rev_3: + /* Reset is performed on a shadow of the control register */ + E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); + break; + case e1000_ich8lan: + if (!hw->phy_reset_disable && + e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { + /* e1000_ich8lan PHY HW reset requires MAC CORE reset + * at the same time to make sure the interface between + * MAC and the external PHY is reset. + */ + ctrl |= E1000_CTRL_PHY_RST; + } + + e1000_get_software_flag(hw); + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); + msec_delay(5); + break; + default: + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); + break; + } + + /* After MAC reset, force reload of EEPROM to restore power-on settings to + * device. Later controllers reload the EEPROM automatically, so just wait + * for reload to complete. + */ + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + case e1000_82544: + /* Wait for reset to complete */ + usec_delay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + /* Wait for EEPROM reload */ + msec_delay(2); + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + /* Wait for EEPROM reload */ + msec_delay(20); + break; + case e1000_82573: + if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + usec_delay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + /* fall through */ + default: + /* Auto read done will delay 5ms or poll based on mac type */ + ret_val = e1000_get_auto_rd_done(hw); + if (ret_val) + return ret_val; + break; + } + + /* Disable HW ARPs on ASF enabled adapters */ + if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { + manc = E1000_READ_REG(hw, MANC); + manc &= ~(E1000_MANC_ARP_EN); + E1000_WRITE_REG(hw, MANC, manc); + } + + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + e1000_phy_init_script(hw); + + /* Configure activity LED after PHY reset */ + led_ctrl = E1000_READ_REG(hw, LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, LEDCTL, led_ctrl); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Clear any pending interrupt events. */ + icr = E1000_READ_REG(hw, ICR); + + /* If MWI was previously enabled, reenable it. */ + if (hw->mac_type == e1000_82542_rev2_0) { + if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + e1000_pci_set_mwi(hw); + } + + if (hw->mac_type == e1000_ich8lan) { + uint32_t kab = E1000_READ_REG(hw, KABGTXD); + kab |= E1000_KABGTXD_BGSQLBIAS; + E1000_WRITE_REG(hw, KABGTXD, kab); + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * + * Initialize a number of hardware-dependent bits + * + * hw: Struct containing variables accessed by shared code + * + *****************************************************************************/ +STATIC void +e1000_initialize_hardware_bits(struct e1000_hw *hw) +{ + if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { + /* Settings common to all silicon */ + uint32_t reg_ctrl, reg_ctrl_ext; + uint32_t reg_tarc0, reg_tarc1; + uint32_t reg_tctl; + uint32_t reg_txdctl, reg_txdctl1; + + reg_tarc0 = E1000_READ_REG(hw, TARC0); + reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 27 */ + + reg_txdctl = E1000_READ_REG(hw, TXDCTL); + reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ + E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); + + reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); + reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ + E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); + + switch (hw->mac_type) { + case e1000_82571: + case e1000_82572: + reg_tarc1 = E1000_READ_REG(hw, TARC1); + reg_tctl = E1000_READ_REG(hw, TCTL); + + /* Set the phy Tx compatible mode bits */ + reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ + + reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ + reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ + + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ + else + reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + case e1000_82573: + reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + reg_ctrl = E1000_READ_REG(hw, CTRL); + + reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ + reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ + reg_ctrl &= ~0x20000000; /* Clear bit 29 */ + + E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); + E1000_WRITE_REG(hw, CTRL, reg_ctrl); + break; + case e1000_80003es2lan: + if ((hw->media_type == e1000_media_type_fiber) || + (hw->media_type == e1000_media_type_internal_serdes)) { + reg_tarc0 &= ~0x00100000; /* Clear bit 20 */ + } + + reg_tctl = E1000_READ_REG(hw, TCTL); + reg_tarc1 = E1000_READ_REG(hw, TARC1); + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ + else + reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + case e1000_ich8lan: + if ((hw->revision_id < 3) || + ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && + (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) + reg_tarc0 |= 0x30000000; /* Set TARC0 bits 29 and 28 */ + reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ + E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); + + reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 24, 26, 27 */ + + reg_tarc1 = E1000_READ_REG(hw, TARC1); + reg_tctl = E1000_READ_REG(hw, TCTL); + + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ + else + reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ + + reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 30 */ + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + default: + break; + } + + E1000_WRITE_REG(hw, TARC0, reg_tarc0); + } +} + +/****************************************************************************** + * Performs basic configuration of the adapter. + * + * hw - Struct containing variables accessed by shared code + * + * Assumes that the controller has previously been reset and is in a + * post-reset uninitialized state. Initializes the receive address registers, + * multicast table, and VLAN filter table. Calls routines to setup link + * configuration and flow control settings. Clears all on-chip counters. Leaves + * the transmit and receive units disabled and uninitialized. + *****************************************************************************/ +int32_t +e1000_init_hw(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t i; + int32_t ret_val; + uint16_t pcix_cmd_word; + uint16_t pcix_stat_hi_word; + uint16_t cmd_mmrbc; + uint16_t stat_mmrbc; + uint32_t mta_size; +#ifndef FIFO_WORKAROUND + uint32_t pba_reg; +#endif + uint32_t reg_data; + uint32_t ctrl_ext; + + DEBUGFUNC("e1000_init_hw"); + + /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ + if ((hw->mac_type == e1000_ich8lan) && + ((hw->revision_id < 3) || + ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && + (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { + reg_data = E1000_READ_REG(hw, STATUS); + reg_data &= ~0x80000000; + E1000_WRITE_REG(hw, STATUS, reg_data); + } + + /* Initialize Identification LED */ + ret_val = e1000_id_led_init(hw); + if (ret_val) { + DEBUGOUT("Error Initializing Identification LED\n"); + return ret_val; + } + + /* Set the media type and TBI compatibility */ + e1000_set_media_type(hw); + +#ifndef FIFO_WORKAROUND + pba_reg = E1000_READ_REG(hw, PBA); + hw->tx_fifo_start = (pba_reg & 0x0000FFFF) * E1000_FIFO_MULTIPLIER; + hw->tx_fifo_size = (pba_reg & 0xFFFF0000) >> 6; + +#endif + /* Disabling VLAN filtering. */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ + if (hw->mac_type != e1000_ich8lan) { + if (hw->mac_type < e1000_82545_rev_3) + E1000_WRITE_REG(hw, VET, 0); + e1000_clear_vfta(hw); + } + + /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + e1000_pci_clear_mwi(hw); + E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); + E1000_WRITE_FLUSH(hw); + msec_delay(5); + } + + /* Setup the receive address. This involves initializing all of the Receive + * Address Registers (RARs 0 - 15). + */ + e1000_init_rx_addrs(hw); + + /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ + if (hw->mac_type == e1000_82542_rev2_0) { + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_FLUSH(hw); + msec_delay(1); + if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + e1000_pci_set_mwi(hw); + } + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + mta_size = E1000_MC_TBL_SIZE; + if (hw->mac_type == e1000_ich8lan) + mta_size = E1000_MC_TBL_SIZE_ICH8LAN; + for (i = 0; i < mta_size; i++) { + E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); + /* use write flush to prevent Memory Write Block (MWB) from + * occuring when accessing our register space */ + E1000_WRITE_FLUSH(hw); + } + + /* Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. Valid only on + * 82542 and 82543 silicon. + */ + if (hw->dma_fairness && hw->mac_type <= e1000_82543) { + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); + } + + switch (hw->mac_type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + break; + default: + /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ + if (hw->bus_type == e1000_bus_type_pcix) { + e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); + e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); + cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> + PCIX_COMMAND_MMRBC_SHIFT; + stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> + PCIX_STATUS_HI_MMRBC_SHIFT; + if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) + stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; + if (cmd_mmrbc > stat_mmrbc) { + pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; + pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; + e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + } + } + break; + } + + /* More time needed for PHY to initialize */ + if (hw->mac_type == e1000_ich8lan) + msec_delay(15); + + /* Call a subroutine to configure the link and setup flow control. */ + ret_val = e1000_setup_link(hw); + + /* Set the transmit descriptor write-back policy */ + if (hw->mac_type > e1000_82544) { + ctrl = E1000_READ_REG(hw, TXDCTL); + ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL, ctrl); + } + + if (hw->mac_type == e1000_82573) { + e1000_enable_tx_pkt_filtering(hw); + } + + switch (hw->mac_type) { + default: + break; + case e1000_80003es2lan: + /* Enable retransmit on late collisions */ + reg_data = E1000_READ_REG(hw, TCTL); + reg_data |= E1000_TCTL_RTLC; + E1000_WRITE_REG(hw, TCTL, reg_data); + + /* Configure Gigabit Carry Extend Padding */ + reg_data = E1000_READ_REG(hw, TCTL_EXT); + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; + reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; + E1000_WRITE_REG(hw, TCTL_EXT, reg_data); + + /* Configure Transmit Inter-Packet Gap */ + reg_data = E1000_READ_REG(hw, TIPG); + reg_data &= ~E1000_TIPG_IPGT_MASK; + reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; + E1000_WRITE_REG(hw, TIPG, reg_data); + + reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); + reg_data &= ~0x00100000; + E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); + /* Fall through */ + case e1000_82571: + case e1000_82572: + case e1000_ich8lan: + ctrl = E1000_READ_REG(hw, TXDCTL1); + ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL1, ctrl); + break; + } + + + if (hw->mac_type == e1000_82573) { + uint32_t gcr = E1000_READ_REG(hw, GCR); + gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + E1000_WRITE_REG(hw, GCR, gcr); + } + + /* Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs(hw); + + /* ICH8 No-snoop bits are opposite polarity. + * Set to snoop by default after reset. */ + if (hw->mac_type == e1000_ich8lan) + e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); + + if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || + hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + /* Relaxed ordering must be disabled to avoid a parity + * error crash in a PCI slot. */ + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + /* Must be called after e1000_set_media_type because media_type is used */ + e1000_initialize_hardware_bits(hw); + + return ret_val; +} + +/****************************************************************************** + * Adjust SERDES output amplitude based on EEPROM setting. + * + * hw - Struct containing variables accessed by shared code. + *****************************************************************************/ +static int32_t +e1000_adjust_serdes_amplitude(struct e1000_hw *hw) +{ + uint16_t eeprom_data; + int32_t ret_val; + + DEBUGFUNC("e1000_adjust_serdes_amplitude"); + + if (hw->media_type != e1000_media_type_internal_serdes) + return E1000_SUCCESS; + + switch (hw->mac_type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + break; + default: + return E1000_SUCCESS; + } + + ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); + if (ret_val) { + return ret_val; + } + + if (eeprom_data != EEPROM_RESERVED_WORD) { + /* Adjust SERDES output amplitude only. */ + eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Configures flow control and link settings. + * + * hw - Struct containing variables accessed by shared code + * + * Determines which flow control settings to use. Calls the apropriate media- + * specific link configuration function. Configures the flow control settings. + * Assuming the adapter has a valid link partner, a valid link should be + * established. Assumes the hardware has previously been reset and the + * transmitter and receiver are not enabled. + *****************************************************************************/ +int32_t +e1000_setup_link(struct e1000_hw *hw) +{ + uint32_t ctrl_ext; + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC("e1000_setup_link"); + + /* In the case of the phy reset being blocked, we already have a link. + * We do not have to set it up again. */ + if (e1000_check_phy_reset_block(hw)) + return E1000_SUCCESS; + + /* Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, + * a bit that determines whether the HW defaults to enabling or + * disabling auto-negotiation, and the direction of the + * SW defined pins. If there is no SW over-ride of the flow + * control setting, then the variable hw->fc will + * be initialized based on a value in the EEPROM. + */ + if (hw->fc == E1000_FC_DEFAULT) { + switch (hw->mac_type) { + case e1000_ich8lan: + case e1000_82573: + hw->fc = E1000_FC_FULL; + break; + default: + ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, + 1, &eeprom_data); + if (ret_val) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) + hw->fc = E1000_FC_NONE; + else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == + EEPROM_WORD0F_ASM_DIR) + hw->fc = E1000_FC_TX_PAUSE; + else + hw->fc = E1000_FC_FULL; + break; + } + } + + /* We want to save off the original Flow Control configuration just + * in case we get disconnected and then reconnected into a different + * hub or switch with different Flow Control capabilities. + */ + if (hw->mac_type == e1000_82542_rev2_0) + hw->fc &= (~E1000_FC_TX_PAUSE); + + if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) + hw->fc &= (~E1000_FC_RX_PAUSE); + + hw->original_fc = hw->fc; + + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); + + /* Take the 4 bits from EEPROM word 0x0F that determine the initial + * polarity value for the SW controlled pins, and setup the + * Extended Device Control reg with that info. + * This is needed because one of the SW controlled pins is used for + * signal detection. So this should be done before e1000_setup_pcs_link() + * or e1000_phy_setup() is called. + */ + if (hw->mac_type == e1000_82543) { + ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, + 1, &eeprom_data); + if (ret_val) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << + SWDPIO__EXT_SHIFT); + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + /* Call the necessary subroutine to configure the link. */ + ret_val = (hw->media_type == e1000_media_type_copper) ? + e1000_setup_copper_link(hw) : + e1000_setup_fiber_serdes_link(hw); + + /* Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); + + /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ + if (hw->mac_type != e1000_ich8lan) { + E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); + E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); + } + + E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); + + /* Set the flow control receive threshold registers. Normally, + * these registers will be set to a default threshold that may be + * adjusted later by the driver's runtime code. However, if the + * ability to transmit pause frames in not enabled, then these + * registers will be set to 0. + */ + if (!(hw->fc & E1000_FC_TX_PAUSE)) { + E1000_WRITE_REG(hw, FCRTL, 0); + E1000_WRITE_REG(hw, FCRTH, 0); + } else { + /* We need to set up the Receive Threshold high and low water marks + * as well as (optionally) enabling the transmission of XON frames. + */ + if (hw->fc_send_xon) { + E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } else { + E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } + } + return ret_val; +} + +/****************************************************************************** + * Sets up link for a fiber based or serdes based adapter + * + * hw - Struct containing variables accessed by shared code + * + * Manipulates Physical Coding Sublayer functions in order to configure + * link. Assumes the hardware has been previously reset and the transmitter + * and receiver are not enabled. + *****************************************************************************/ +static int32_t +e1000_setup_fiber_serdes_link(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t status; + uint32_t txcw = 0; + uint32_t i; + uint32_t signal = 0; + int32_t ret_val; + + DEBUGFUNC("e1000_setup_fiber_serdes_link"); + + /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists + * until explicitly turned off or a power cycle is performed. A read to + * the register does not indicate its status. Therefore, we ensure + * loopback mode is disabled during initialization. + */ + if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) + E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); + + /* On adapters with a MAC newer than 82544, SWDP 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal. This applies to fiber media only. + * If we're on serdes media, adjust the output amplitude to value + * set in the EEPROM. + */ + ctrl = E1000_READ_REG(hw, CTRL); + if (hw->media_type == e1000_media_type_fiber) + signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; + + ret_val = e1000_adjust_serdes_amplitude(hw); + if (ret_val) + return ret_val; + + /* Take the link out of reset */ + ctrl &= ~(E1000_CTRL_LRST); + + /* Adjust VCO speed to improve BER performance */ + ret_val = e1000_set_vco_speed(hw); + if (ret_val) + return ret_val; + + e1000_config_collision_dist(hw); + + /* Check for a software override of the flow control settings, and setup + * the device accordingly. If auto-negotiation is enabled, then software + * will have to set the "PAUSE" bits to the correct value in the Tranmsit + * Config Word Register (TXCW) and re-start auto-negotiation. However, if + * auto-negotiation is disabled, then software will have to manually + * configure the two flow control enable bits in the CTRL register. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, but + * not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but we do + * not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + */ + switch (hw->fc) { + case E1000_FC_NONE: + /* Flow control is completely disabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); + break; + case E1000_FC_RX_PAUSE: + /* RX Flow control is enabled and TX Flow control is disabled by a + * software over-ride. Since there really isn't a way to advertise + * that we are capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + case E1000_FC_TX_PAUSE: + /* TX Flow control is enabled, and RX Flow control is disabled, by a + * software over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); + break; + case E1000_FC_FULL: + /* Flow control (both RX and TX) is enabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + /* Since auto-negotiation is enabled, take the link out of reset (the link + * will be in reset, because we previously reset the chip). This will + * restart auto-negotiation. If auto-neogtiation is successful then the + * link-up status bit will be set and the flow control enable bits (RFCE + * and TFCE) will be set according to their negotiated value. + */ + DEBUGOUT("Auto-negotiation enabled\n"); + + E1000_WRITE_REG(hw, TXCW, txcw); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + hw->txcw = txcw; + msec_delay(1); + + /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" + * indication in the Device Status Register. Time-out if a link isn't + * seen in 500 milliseconds seconds (Auto-negotiation should complete in + * less than 500 milliseconds even if the other end is doing it in SW). + * For internal serdes, we just assume a signal is present, then poll. + */ + if (hw->media_type == e1000_media_type_internal_serdes || + (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { + DEBUGOUT("Looking for Link\n"); + for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { + msec_delay(10); + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_LU) break; + } + if (i == (LINK_UP_TIMEOUT / 10)) { + DEBUGOUT("Never got a valid link from auto-neg!!!\n"); + hw->autoneg_failed = 1; + /* AutoNeg failed to achieve a link, so we'll call + * e1000_check_for_link. This routine will force the link up if + * we detect a signal. This will allow us to communicate with + * non-autonegotiating link partners. + */ + ret_val = e1000_check_for_link(hw); + if (ret_val) { + DEBUGOUT("Error while checking for link\n"); + return ret_val; + } + hw->autoneg_failed = 0; + } else { + hw->autoneg_failed = 0; + DEBUGOUT("Valid Link Found\n"); + } + } else { + DEBUGOUT("No Signal Detected\n"); + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Make sure we have a valid PHY and change PHY mode before link setup. +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_copper_link_preconfig(struct e1000_hw *hw) +{ + uint32_t ctrl; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_copper_link_preconfig"); + + ctrl = E1000_READ_REG(hw, CTRL); + /* With 82543, we need to force speed and duplex on the MAC equal to what + * the PHY speed and duplex configuration is. In addition, we need to + * perform a hardware reset on the PHY to take it out of reset. + */ + if (hw->mac_type > e1000_82543) { + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, CTRL, ctrl); + } else { + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); + E1000_WRITE_REG(hw, CTRL, ctrl); + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) + return ret_val; + } + + /* Make sure we have a valid PHY */ + ret_val = e1000_detect_gig_phy(hw); + if (ret_val) { + DEBUGOUT("Error, did not detect valid phy.\n"); + return ret_val; + } + DEBUGOUT1("Phy ID = %x \n", hw->phy_id); + + /* Set PHY to class A mode (if necessary) */ + ret_val = e1000_set_phy_mode(hw); + if (ret_val) + return ret_val; + + if ((hw->mac_type == e1000_82545_rev_3) || + (hw->mac_type == e1000_82546_rev_3)) { + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + phy_data |= 0x00000008; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + } + + if (hw->mac_type <= e1000_82543 || + hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || + hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) + hw->phy_reset_disable = FALSE; + + return E1000_SUCCESS; +} + + +/******************************************************************** +* Copper link setup for e1000_phy_igp series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_igp_setup(struct e1000_hw *hw) +{ + uint32_t led_ctrl; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_copper_link_igp_setup"); + + if (hw->phy_reset_disable) + return E1000_SUCCESS; + + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + /* Wait 15ms for MAC to configure PHY from eeprom settings */ + msec_delay(15); + if (hw->mac_type != e1000_ich8lan) { + /* Configure activity LED after PHY reset */ + led_ctrl = E1000_READ_REG(hw, LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, LEDCTL, led_ctrl); + } + + /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ + if (hw->phy_type == e1000_phy_igp) { + /* disable lplu d3 during driver init */ + ret_val = e1000_set_d3_lplu_state(hw, FALSE); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D3\n"); + return ret_val; + } + } + + /* disable lplu d0 during driver init */ + ret_val = e1000_set_d0_lplu_state(hw, FALSE); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D0\n"); + return ret_val; + } + /* Configure mdi-mdix settings */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) + return ret_val; + + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + hw->dsp_config_state = e1000_dsp_config_disabled; + /* Force MDI for earlier revs of the IGP PHY */ + phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); + hw->mdix = 1; + + } else { + hw->dsp_config_state = e1000_dsp_config_enabled; + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + + switch (hw->mdix) { + case 1: + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 2: + phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 0: + default: + phy_data |= IGP01E1000_PSCR_AUTO_MDIX; + break; + } + } + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* set auto-master slave resolution settings */ + if (hw->autoneg) { + e1000_ms_type phy_ms_setting = hw->master_slave; + + if (hw->ffe_config_state == e1000_ffe_config_active) + hw->ffe_config_state = e1000_ffe_config_enabled; + + if (hw->dsp_config_state == e1000_dsp_config_activated) + hw->dsp_config_state = e1000_dsp_config_enabled; + + /* when autonegotiation advertisment is only 1000Mbps then we + * should disable SmartSpeed and enable Auto MasterSlave + * resolution as hardware default. */ + if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { + /* Disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + /* Set auto Master/Slave resolution process */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); + if (ret_val) + return ret_val; + phy_data &= ~CR_1000T_MS_ENABLE; + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); + if (ret_val) + return ret_val; + } + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); + if (ret_val) + return ret_val; + + /* load defaults for future use */ + hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? + ((phy_data & CR_1000T_MS_VALUE) ? + e1000_ms_force_master : + e1000_ms_force_slave) : + e1000_ms_auto; + + switch (phy_ms_setting) { + case e1000_ms_force_master: + phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); + break; + case e1000_ms_force_slave: + phy_data |= CR_1000T_MS_ENABLE; + phy_data &= ~(CR_1000T_MS_VALUE); + break; + case e1000_ms_auto: + phy_data &= ~CR_1000T_MS_ENABLE; + default: + break; + } + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/******************************************************************** +* Copper link setup for e1000_phy_gg82563 series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_ggp_setup(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + uint32_t reg_data; + + DEBUGFUNC("e1000_copper_link_ggp_setup"); + + if (!hw->phy_reset_disable) { + + /* Enable CRS on TX for half-duplex operation. */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + &phy_data); + if (ret_val) + return ret_val; + + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ + phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + phy_data); + if (ret_val) + return ret_val; + + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; + + switch (hw->mdix) { + case 1: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; + break; + case 2: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; + break; + case 0: + default: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; + break; + } + + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; + if (hw->disable_polarity_correction == 1) + phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); + + if (ret_val) + return ret_val; + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + } /* phy_reset_disable */ + + if (hw->mac_type == e1000_80003es2lan) { + /* Bypass RX and TX FIFO's */ + ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, + E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | + E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); + + if (ret_val) + return ret_val; + + reg_data = E1000_READ_REG(hw, CTRL_EXT); + reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); + E1000_WRITE_REG(hw, CTRL_EXT, reg_data); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, + &phy_data); + if (ret_val) + return ret_val; + + /* Do not init these registers when the HW is in IAMT mode, since the + * firmware will have already initialized them. We only initialize + * them if the HW is not in IAMT mode. + */ + if (e1000_check_mng_mode(hw) == FALSE) { + /* Enable Electrical Idle on the PHY */ + phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, + phy_data); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + phy_data); + + if (ret_val) + return ret_val; + } + + /* Workaround: Disable padding in Kumeran interface in the MAC + * and in the PHY to avoid CRC errors. + */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, + &phy_data); + if (ret_val) + return ret_val; + phy_data |= GG82563_ICR_DIS_PADDING; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, + phy_data); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/******************************************************************** +* Copper link setup for e1000_phy_m88 series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_mgp_setup(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_copper_link_mgp_setup"); + + if (hw->phy_reset_disable) + return E1000_SUCCESS; + + /* Enable CRS on TX. This must be set for half-duplex operation. */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + + switch (hw->mdix) { + case 1: + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; + break; + case 2: + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; + break; + case 3: + phy_data |= M88E1000_PSCR_AUTO_X_1000T; + break; + case 0: + default: + phy_data |= M88E1000_PSCR_AUTO_X_MODE; + break; + } + + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; + if (hw->disable_polarity_correction == 1) + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + if (hw->phy_revision < M88E1011_I_REV_4) { + /* Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_EPSCR_TX_CLK_25; + + if ((hw->phy_revision == E1000_REVISION_2) && + (hw->phy_id == M88E1111_I_PHY_ID)) { + /* Vidalia Phy, set the downshift counter to 5x */ + phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; + ret_val = e1000_write_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + } else { + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + ret_val = e1000_write_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + } + } + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + return E1000_SUCCESS; +} + +/******************************************************************** +* Setup auto-negotiation and flow control advertisements, +* and then perform auto-negotiation. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_autoneg(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_copper_link_autoneg"); + + /* Perform some bounds checking on the hw->autoneg_advertised + * parameter. If this variable is zero, then set it to the default. + */ + hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* If autoneg_advertised is zero, we assume it was not defaulted + * by the calling code so we set to advertise full capability. + */ + if (hw->autoneg_advertised == 0) + hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* IFE phy only supports 10/100 */ + if (hw->phy_type == e1000_phy_ife) + hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; + + DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error Setting up Auto-Negotiation\n"); + return ret_val; + } + DEBUGOUT("Restarting Auto-Neg\n"); + + /* Restart auto-negotiation by setting the Auto Neg Enable bit and + * the Auto Neg Restart bit in the PHY control register. + */ + ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* Does the user want to wait for Auto-Neg to complete here, or + * check at a later time (for example, callback routine). + */ + if (hw->wait_autoneg_complete) { + ret_val = e1000_wait_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error while waiting for autoneg to complete\n"); + return ret_val; + } + } + + hw->get_link_status = TRUE; + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Config the MAC and the PHY after link is up. +* 1) Set up the MAC to the current PHY speed/duplex +* if we are on 82543. If we +* are on newer silicon, we only need to configure +* collision distance in the Transmit Control Register. +* 2) Set up flow control on the MAC to that established with +* the link partner. +* 3) Config DSP to improve Gigabit link quality for some PHY revisions. +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_copper_link_postconfig(struct e1000_hw *hw) +{ + int32_t ret_val; + DEBUGFUNC("e1000_copper_link_postconfig"); + + if (hw->mac_type >= e1000_82544) { + e1000_config_collision_dist(hw); + } else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val) { + DEBUGOUT("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + DEBUGOUT("Error Configuring Flow Control\n"); + return ret_val; + } + + /* Config DSP to improve Giga link quality */ + if (hw->phy_type == e1000_phy_igp) { + ret_val = e1000_config_dsp_after_link_change(hw, TRUE); + if (ret_val) { + DEBUGOUT("Error Configuring DSP after link up\n"); + return ret_val; + } + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Detects which PHY is present and setup the speed and duplex +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_setup_copper_link(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t i; + uint16_t phy_data; + uint16_t reg_data; + + DEBUGFUNC("e1000_setup_copper_link"); + + switch (hw->mac_type) { + case e1000_80003es2lan: + case e1000_ich8lan: + /* Set the mac to wait the maximum time between each + * iteration and increase the max iterations when + * polling the phy; this fixes erroneous timeouts at 10Mbps. */ + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + return ret_val; + ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) + return ret_val; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) + return ret_val; + default: + break; + } + + /* Check if it is a valid PHY and set PHY mode if necessary. */ + ret_val = e1000_copper_link_preconfig(hw); + if (ret_val) + return ret_val; + + switch (hw->mac_type) { + case e1000_80003es2lan: + /* Kumeran registers are written-only */ + reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; + reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; + ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, + reg_data); + if (ret_val) + return ret_val; + break; + default: + break; + } + + if (hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) { + ret_val = e1000_copper_link_igp_setup(hw); + if (ret_val) + return ret_val; + } else if (hw->phy_type == e1000_phy_m88) { + ret_val = e1000_copper_link_mgp_setup(hw); + if (ret_val) + return ret_val; + } else if (hw->phy_type == e1000_phy_gg82563) { + ret_val = e1000_copper_link_ggp_setup(hw); + if (ret_val) + return ret_val; + } + + if (hw->autoneg) { + /* Setup autoneg and flow control advertisement + * and perform autonegotiation */ + ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) + return ret_val; + } else { + /* PHY will be set to 10H, 10F, 100H,or 100F + * depending on value from forced_speed_duplex. */ + DEBUGOUT("Forcing speed and duplex\n"); + ret_val = e1000_phy_force_speed_duplex(hw); + if (ret_val) { + DEBUGOUT("Error Forcing Speed and Duplex\n"); + return ret_val; + } + } + + /* Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + for (i = 0; i < 10; i++) { + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if (phy_data & MII_SR_LINK_STATUS) { + /* Config the MAC and PHY after link is up */ + ret_val = e1000_copper_link_postconfig(hw); + if (ret_val) + return ret_val; + + DEBUGOUT("Valid link established!!!\n"); + return E1000_SUCCESS; + } + usec_delay(10); + } + + DEBUGOUT("Unable to establish link!!!\n"); + return E1000_SUCCESS; +} + +/****************************************************************************** +* Configure the MAC-to-PHY interface for 10/100Mbps +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) +{ + int32_t ret_val = E1000_SUCCESS; + uint32_t tipg; + uint16_t reg_data; + + DEBUGFUNC("e1000_configure_kmrn_for_10_100"); + + reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) + return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; + E1000_WRITE_REG(hw, TIPG, tipg); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + + if (ret_val) + return ret_val; + + if (duplex == HALF_DUPLEX) + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; + else + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + + return ret_val; +} + +static int32_t +e1000_configure_kmrn_for_1000(struct e1000_hw *hw) +{ + int32_t ret_val = E1000_SUCCESS; + uint16_t reg_data; + uint32_t tipg; + + DEBUGFUNC("e1000_configure_kmrn_for_1000"); + + reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) + return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; + E1000_WRITE_REG(hw, TIPG, tipg); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + + if (ret_val) + return ret_val; + + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + + return ret_val; +} + +/****************************************************************************** +* Configures PHY autoneg and flow control advertisement settings +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +int32_t +e1000_phy_setup_autoneg(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_autoneg_adv_reg; + uint16_t mii_1000t_ctrl_reg; + + DEBUGFUNC("e1000_phy_setup_autoneg"); + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); + if (ret_val) + return ret_val; + + if (hw->phy_type != e1000_phy_ife) { + /* Read the MII 1000Base-T Control Register (Address 9). */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); + if (ret_val) + return ret_val; + } else + mii_1000t_ctrl_reg=0; + + /* Need to parse both autoneg_advertised and fc and set up + * the appropriate PHY registers. First we will parse for + * autoneg_advertised software override. Since we can advertise + * a plethora of combinations, we need to check each bit + * individually. + */ + + /* First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; + mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; + + DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_HALF) { + DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_FULL) { + DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_HALF) { + DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_FULL) { + DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { + DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); + } + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { + DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + if (hw->phy_type == e1000_phy_ife) { + DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); + } + } + + /* Check for a software override of the flow control settings, and + * setup the PHY advertisement registers accordingly. If + * auto-negotiation is enabled, then software will have to set the + * "PAUSE" bits to the correct value in the Auto-Negotiation + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ + switch (hw->fc) { + case E1000_FC_NONE: /* 0 */ + /* Flow control (RX & TX) is completely disabled by a + * software over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case E1000_FC_RX_PAUSE: /* 1 */ + /* RX Flow control is enabled, and TX Flow control is + * disabled, by a software over-ride. + */ + /* Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later + * (in e1000_config_fc_after_link_up) we will disable the + *hw's ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case E1000_FC_TX_PAUSE: /* 2 */ + /* TX Flow control is enabled, and RX Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; + break; + case E1000_FC_FULL: /* 3 */ + /* Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); + if (ret_val) + return ret_val; + + DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (hw->phy_type != e1000_phy_ife) { + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Force PHY speed and duplex settings to hw->forced_speed_duplex +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_phy_force_speed_duplex(struct e1000_hw *hw) +{ + uint32_t ctrl; + int32_t ret_val; + uint16_t mii_ctrl_reg; + uint16_t mii_status_reg; + uint16_t phy_data; + uint16_t i; + + DEBUGFUNC("e1000_phy_force_speed_duplex"); + + /* Turn off Flow control if we are forcing speed and duplex. */ + hw->fc = E1000_FC_NONE; + + DEBUGOUT1("hw->fc = %d\n", hw->fc); + + /* Read the Device Control Register. */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(DEVICE_SPEED_MASK); + + /* Clear the Auto Speed Detect Enable bit. */ + ctrl &= ~E1000_CTRL_ASDE; + + /* Read the MII Control Register. */ + ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); + if (ret_val) + return ret_val; + + /* We need to disable autoneg in order to force link and duplex. */ + + mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; + + /* Are we forcing Full or Half Duplex? */ + if (hw->forced_speed_duplex == e1000_100_full || + hw->forced_speed_duplex == e1000_10_full) { + /* We want to force full duplex so we SET the full duplex bits in the + * Device and MII Control Registers. + */ + ctrl |= E1000_CTRL_FD; + mii_ctrl_reg |= MII_CR_FULL_DUPLEX; + DEBUGOUT("Full Duplex\n"); + } else { + /* We want to force half duplex so we CLEAR the full duplex bits in + * the Device and MII Control Registers. + */ + ctrl &= ~E1000_CTRL_FD; + mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; + DEBUGOUT("Half Duplex\n"); + } + + /* Are we forcing 100Mbps??? */ + if (hw->forced_speed_duplex == e1000_100_full || + hw->forced_speed_duplex == e1000_100_half) { + /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ + ctrl |= E1000_CTRL_SPD_100; + mii_ctrl_reg |= MII_CR_SPEED_100; + mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); + DEBUGOUT("Forcing 100mb "); + } else { + /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); + mii_ctrl_reg |= MII_CR_SPEED_10; + mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); + DEBUGOUT("Forcing 10mb "); + } + + e1000_config_collision_dist(hw); + + /* Write the configured values back to the Device Control Reg. */ + E1000_WRITE_REG(hw, CTRL, ctrl); + + if ((hw->phy_type == e1000_phy_m88) || + (hw->phy_type == e1000_phy_gg82563)) { + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI + * forced whenever speed are duplex are forced. + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); + + /* Need to reset the PHY or these changes will be ignored */ + mii_ctrl_reg |= MII_CR_RESET; + + /* Disable MDI-X support for 10/100 */ + } else if (hw->phy_type == e1000_phy_ife) { + ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IFE_PMC_AUTO_MDIX; + phy_data &= ~IFE_PMC_FORCE_MDIX; + + ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); + if (ret_val) + return ret_val; + + } else { + /* Clear Auto-Crossover to force MDI manually. IGP requires MDI + * forced whenever speed or duplex are forced. + */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) + return ret_val; + } + + /* Write back the modified PHY MII control register. */ + ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); + if (ret_val) + return ret_val; + + usec_delay(1); + + /* The wait_autoneg_complete flag may be a little misleading here. + * Since we are forcing speed and duplex, Auto-Neg is not enabled. + * But we do want to delay for a period while forcing only so we + * don't generate false No Link messages. So we will wait here + * only if the user has set wait_autoneg_complete to 1, which is + * the default. + */ + if (hw->wait_autoneg_complete) { + /* We will wait for autoneg to complete. */ + DEBUGOUT("Waiting for forced speed/duplex link.\n"); + mii_status_reg = 0; + + /* We will wait for autoneg to complete or 4.5 seconds to expire. */ + for (i = PHY_FORCE_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Auto-Neg Complete bit + * to be set. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + if (mii_status_reg & MII_SR_LINK_STATUS) break; + msec_delay(100); + } + if ((i == 0) && + ((hw->phy_type == e1000_phy_m88) || + (hw->phy_type == e1000_phy_gg82563))) { + /* We didn't get link. Reset the DSP and wait again for link. */ + ret_val = e1000_phy_reset_dsp(hw); + if (ret_val) { + DEBUGOUT("Error Resetting PHY DSP\n"); + return ret_val; + } + } + /* This loop will early-out if the link condition has been met. */ + for (i = PHY_FORCE_TIME; i > 0; i--) { + if (mii_status_reg & MII_SR_LINK_STATUS) break; + msec_delay(100); + /* Read the MII Status Register and wait for Auto-Neg Complete bit + * to be set. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + } + } + + if (hw->phy_type == e1000_phy_m88) { + /* Because we reset the PHY above, we need to re-force TX_CLK in the + * Extended PHY Specific Control Register to 25MHz clock. This value + * defaults back to a 2.5MHz clock when the PHY is reset. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_EPSCR_TX_CLK_25; + ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* In addition, because of the s/w reset above, we need to enable CRS on + * TX. This must be set for both full and half duplex operation. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && + (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || + hw->forced_speed_duplex == e1000_10_half)) { + ret_val = e1000_polarity_reversal_workaround(hw); + if (ret_val) + return ret_val; + } + } else if (hw->phy_type == e1000_phy_gg82563) { + /* The TX_CLK of the Extended PHY Specific Control Register defaults + * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if + * we're not in a forced 10/duplex configuration. */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_MSCR_TX_CLK_MASK; + if ((hw->forced_speed_duplex == e1000_10_full) || + (hw->forced_speed_duplex == e1000_10_half)) + phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; + else + phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; + + /* Also due to the reset, we need to enable CRS on Tx. */ + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Sets the collision distance in the Transmit Control register +* +* hw - Struct containing variables accessed by shared code +* +* Link should have been established previously. Reads the speed and duplex +* information from the Device Status register. +******************************************************************************/ +void +e1000_config_collision_dist(struct e1000_hw *hw) +{ + uint32_t tctl, coll_dist; + + DEBUGFUNC("e1000_config_collision_dist"); + + if (hw->mac_type < e1000_82543) + coll_dist = E1000_COLLISION_DISTANCE_82542; + else + coll_dist = E1000_COLLISION_DISTANCE; + + tctl = E1000_READ_REG(hw, TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= coll_dist << E1000_COLD_SHIFT; + + E1000_WRITE_REG(hw, TCTL, tctl); + E1000_WRITE_FLUSH(hw); +} + +/****************************************************************************** +* Sets MAC speed and duplex settings to reflect the those in the PHY +* +* hw - Struct containing variables accessed by shared code +* mii_reg - data to write to the MII control register +* +* The contents of the PHY register containing the needed information need to +* be passed in. +******************************************************************************/ +static int32_t +e1000_config_mac_to_phy(struct e1000_hw *hw) +{ + uint32_t ctrl; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_config_mac_to_phy"); + + /* 82544 or newer MAC, Auto Speed Detection takes care of + * MAC speed/duplex configuration.*/ + if (hw->mac_type >= e1000_82544) + return E1000_SUCCESS; + + /* Read the Device Control Register and set the bits to Force Speed + * and Duplex. + */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + + /* Set up duplex in the Device Control and Transmit Control + * registers depending on negotiated values. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if (phy_data & M88E1000_PSSR_DPLX) + ctrl |= E1000_CTRL_FD; + else + ctrl &= ~E1000_CTRL_FD; + + e1000_config_collision_dist(hw); + + /* Set up speed in the Device Control register depending on + * negotiated values. + */ + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) + ctrl |= E1000_CTRL_SPD_1000; + else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) + ctrl |= E1000_CTRL_SPD_100; + + /* Write the configured values back to the Device Control Reg. */ + E1000_WRITE_REG(hw, CTRL, ctrl); + return E1000_SUCCESS; +} + +/****************************************************************************** + * Forces the MAC's flow control settings. + * + * hw - Struct containing variables accessed by shared code + * + * Sets the TFCE and RFCE bits in the device control register to reflect + * the adapter settings. TFCE and RFCE need to be explicitly set by + * software when a Copper PHY is used because autonegotiation is managed + * by the PHY rather than the MAC. Software must also configure these + * bits when link is forced on a fiber connection. + *****************************************************************************/ +int32_t +e1000_force_mac_fc(struct e1000_hw *hw) +{ + uint32_t ctrl; + + DEBUGFUNC("e1000_force_mac_fc"); + + /* Get the current configuration of the Device Control Register */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Because we didn't get link via the internal auto-negotiation + * mechanism (we either forced link or we got link via PHY + * auto-neg), we have to manually enable/disable transmit an + * receive flow control. + * + * The "Case" statement below enables/disable flow control + * according to the "hw->fc" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). + * 3: Both Rx and TX flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ + + switch (hw->fc) { + case E1000_FC_NONE: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; + case E1000_FC_RX_PAUSE: + ctrl &= (~E1000_CTRL_TFCE); + ctrl |= E1000_CTRL_RFCE; + break; + case E1000_FC_TX_PAUSE: + ctrl &= (~E1000_CTRL_RFCE); + ctrl |= E1000_CTRL_TFCE; + break; + case E1000_FC_FULL: + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + /* Disable TX Flow Control for 82542 (rev 2.0) */ + if (hw->mac_type == e1000_82542_rev2_0) + ctrl &= (~E1000_CTRL_TFCE); + + E1000_WRITE_REG(hw, CTRL, ctrl); + return E1000_SUCCESS; +} + +/****************************************************************************** + * Configures flow control settings after link is established + * + * hw - Struct containing variables accessed by shared code + * + * Should be called immediately after a valid link has been established. + * Forces MAC flow control settings if link was forced. When in MII/GMII mode + * and autonegotiation is enabled, the MAC flow control settings will be set + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE + * and RFCE bits will be automaticaly set to the negotiated flow control mode. + *****************************************************************************/ +STATIC int32_t +e1000_config_fc_after_link_up(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_status_reg; + uint16_t mii_nway_adv_reg; + uint16_t mii_nway_lp_ability_reg; + uint16_t speed; + uint16_t duplex; + + DEBUGFUNC("e1000_config_fc_after_link_up"); + + /* Check for the case where we have fiber media and auto-neg failed + * so we had to force link. In this case, we need to force the + * configuration of the MAC to match the "fc" parameter. + */ + if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || + ((hw->media_type == e1000_media_type_internal_serdes) && + (hw->autoneg_failed)) || + ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { + ret_val = e1000_force_mac_fc(hw); + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + + /* Check for the case where we have copper media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { + /* Read the MII Status Register and check to see if AutoNeg + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement Register + * (Address 4) and the Auto_Negotiation Base Page Ability + * Register (Address 5) to determine how flow control was + * negotiated. + */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, + &mii_nway_adv_reg); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, + &mii_nway_lp_ability_reg); + if (ret_val) + return ret_val; + + /* Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base + * Page Ability Register (Address 5) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + /* Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* Now we need to check if the user selected RX ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->original_fc == E1000_FC_FULL) { + hw->fc = E1000_FC_FULL; + DEBUGOUT("Flow Control = FULL.\n"); + } else { + hw->fc = E1000_FC_RX_PAUSE; + DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { + hw->fc = E1000_FC_TX_PAUSE; + DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { + hw->fc = E1000_FC_RX_PAUSE; + DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); + } + /* Per the IEEE spec, at this point flow control should be + * disabled. However, we want to consider that we could + * be connected to a legacy switch that doesn't advertise + * desired flow control, but can be forced on the link + * partner. So if we advertised no flow control, that is + * what we will resolve to. If we advertised some kind of + * receive capability (Rx Pause Only or Full Flow Control) + * and the link partner advertised none, we will configure + * ourselves to enable Rx Flow Control only. We can do + * this safely for two reasons: If the link partner really + * didn't want flow control enabled, and we enable Rx, no + * harm done since we won't be receiving any PAUSE frames + * anyway. If the intent on the link partner was to have + * flow control enabled, then by us enabling RX only, we + * can at least receive pause frames and process them. + * This is a good idea because in most cases, since we are + * predominantly a server NIC, more times than not we will + * be asked to delay transmission of packets than asking + * our link partner to pause transmission of frames. + */ + else if ((hw->original_fc == E1000_FC_NONE|| + hw->original_fc == E1000_FC_TX_PAUSE) || + hw->fc_strict_ieee) { + hw->fc = E1000_FC_NONE; + DEBUGOUT("Flow Control = NONE.\n"); + } else { + hw->fc = E1000_FC_RX_PAUSE; + DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); + } + + /* Now we need to do one last check... If we auto- + * negotiated to HALF DUPLEX, flow control should not be + * enabled per IEEE 802.3 spec. + */ + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + return ret_val; + } + + if (duplex == HALF_DUPLEX) + hw->fc = E1000_FC_NONE; + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + ret_val = e1000_force_mac_fc(hw); + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } else { + DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); + } + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Checks to see if the link status of the hardware has changed. + * + * hw - Struct containing variables accessed by shared code + * + * Called by any function that needs to check the link status of the adapter. + *****************************************************************************/ +int32_t +e1000_check_for_link(struct e1000_hw *hw) +{ + uint32_t rxcw = 0; + uint32_t ctrl; + uint32_t status; + uint32_t rctl; + uint32_t icr; + uint32_t signal = 0; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_check_for_link"); + + ctrl = E1000_READ_REG(hw, CTRL); + status = E1000_READ_REG(hw, STATUS); + + /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal. This applies to fiber media only. + */ + if ((hw->media_type == e1000_media_type_fiber) || + (hw->media_type == e1000_media_type_internal_serdes)) { + rxcw = E1000_READ_REG(hw, RXCW); + + if (hw->media_type == e1000_media_type_fiber) { + signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; + if (status & E1000_STATUS_LU) + hw->get_link_status = FALSE; + } + } + + /* If we have a copper PHY then we only want to go out to the PHY + * registers to see if Auto-Neg has completed and/or if our link + * status has changed. The get_link_status flag will be set if we + * receive a Link Status Change interrupt or we have Rx Sequence + * Errors. + */ + if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { + /* First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex + * of the PHY. + * Read the register twice since the link bit is sticky. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if (phy_data & MII_SR_LINK_STATUS) { + hw->get_link_status = FALSE; + /* Check if there was DownShift, must be checked immediately after + * link-up */ + e1000_check_downshift(hw); + + /* If we are on 82544 or 82543 silicon and speed/duplex + * are forced to 10H or 10F, then we will implement the polarity + * reversal workaround. We disable interrupts first, and upon + * returning, place the devices interrupt state to its previous + * value except for the link status change interrupt which will + * happen due to the execution of this workaround. + */ + + if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && + (!hw->autoneg) && + (hw->forced_speed_duplex == e1000_10_full || + hw->forced_speed_duplex == e1000_10_half)) { + E1000_WRITE_REG(hw, IMC, 0xffffffff); + ret_val = e1000_polarity_reversal_workaround(hw); + icr = E1000_READ_REG(hw, ICR); + E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); + E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); + } + + } else { + /* No link detected */ + e1000_config_dsp_after_link_change(hw, FALSE); + return 0; + } + + /* If we are forcing speed/duplex, then we simply return since + * we have already determined whether we have link or not. + */ + if (!hw->autoneg) return -E1000_ERR_CONFIG; + + /* optimize the dsp settings for the igp phy */ + e1000_config_dsp_after_link_change(hw, TRUE); + + /* We have a M88E1000 PHY and Auto-Neg is enabled. If we + * have Si on board that is 82544 or newer, Auto + * Speed Detection takes care of MAC speed/duplex + * configuration. So we only need to configure Collision + * Distance in the MAC. Otherwise, we need to force + * speed/duplex on the MAC to the current PHY speed/duplex + * settings. + */ + if (hw->mac_type >= e1000_82544) + e1000_config_collision_dist(hw); + else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val) { + DEBUGOUT("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + + /* Configure Flow Control now that Auto-Neg has completed. First, we + * need to restore the desired flow control settings because we may + * have had to re-autoneg with a different link partner. + */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + + /* At this point we know that we are on copper and we have + * auto-negotiated link. These are conditions for checking the link + * partner capability register. We use the link speed to determine if + * TBI compatibility needs to be turned on or off. If the link is not + * at gigabit speed, then TBI compatibility is not needed. If we are + * at gigabit speed, we turn on TBI compatibility. + */ + if (hw->tbi_compatibility_en) { + uint16_t speed, duplex; + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + return ret_val; + } + if (speed != SPEED_1000) { + /* If link speed is not set to gigabit speed, we do not need + * to enable TBI compatibility. + */ + if (hw->tbi_compatibility_on) { + /* If we previously were in the mode, turn it off. */ + rctl = E1000_READ_REG(hw, RCTL); + rctl &= ~E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + hw->tbi_compatibility_on = FALSE; + } + } else { + /* If TBI compatibility is was previously off, turn it on. For + * compatibility with a TBI link partner, we will store bad + * packets. Some frames have an additional byte on the end and + * will look like CRC errors to to the hardware. + */ + if (!hw->tbi_compatibility_on) { + hw->tbi_compatibility_on = TRUE; + rctl = E1000_READ_REG(hw, RCTL); + rctl |= E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + } + } + } + } + /* If we don't have link (auto-negotiation failed or link partner cannot + * auto-negotiate), the cable is plugged in (we have signal), and our + * link partner is not trying to auto-negotiate with us (we are receiving + * idles or data), we need to force link up. We also need to give + * auto-negotiation time to complete, in case the cable was just plugged + * in. The autoneg_failed flag does this. + */ + else if ((((hw->media_type == e1000_media_type_fiber) && + ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || + (hw->media_type == e1000_media_type_internal_serdes)) && + (!(status & E1000_STATUS_LU)) && + (!(rxcw & E1000_RXCW_C))) { + if (hw->autoneg_failed == 0) { + hw->autoneg_failed = 1; + return 0; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + } + /* If we are forcing link and we are receiving /C/ ordered sets, re-enable + * auto-negotiation in the TXCW register and disable forced link in the + * Device Control register in an attempt to auto-negotiate with our link + * partner. + */ + else if (((hw->media_type == e1000_media_type_fiber) || + (hw->media_type == e1000_media_type_internal_serdes)) && + (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); + E1000_WRITE_REG(hw, TXCW, hw->txcw); + E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); + + hw->serdes_link_down = FALSE; + } + /* If we force link for non-auto-negotiation switch, check link status + * based on MAC synchronization for internal serdes media type. + */ + else if ((hw->media_type == e1000_media_type_internal_serdes) && + !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { + /* SYNCH bit and IV bit are sticky. */ + usec_delay(10); + if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { + if (!(rxcw & E1000_RXCW_IV)) { + hw->serdes_link_down = FALSE; + DEBUGOUT("SERDES: Link is up.\n"); + } + } else { + hw->serdes_link_down = TRUE; + DEBUGOUT("SERDES: Link is down.\n"); + } + } + if ((hw->media_type == e1000_media_type_internal_serdes) && + (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { + hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Detects the current speed and duplex settings of the hardware. + * + * hw - Struct containing variables accessed by shared code + * speed - Speed of the connection + * duplex - Duplex setting of the connection + *****************************************************************************/ +int32_t +e1000_get_speed_and_duplex(struct e1000_hw *hw, + uint16_t *speed, + uint16_t *duplex) +{ + uint32_t status; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_get_speed_and_duplex"); + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; + DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; + DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; + DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; + DEBUGOUT("Full Duplex\n"); + } else { + *duplex = HALF_DUPLEX; + DEBUGOUT(" Half Duplex\n"); + } + } else { + DEBUGOUT("1000 Mbs, Full Duplex\n"); + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + } + + /* IGP01 PHY may advertise full duplex operation after speed downgrade even + * if it is operating at half duplex. Here we set the duplex settings to + * match the duplex in the link partner's capabilities. + */ + if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); + if (ret_val) + return ret_val; + + if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) + *duplex = HALF_DUPLEX; + else { + ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); + if (ret_val) + return ret_val; + if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || + (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) + *duplex = HALF_DUPLEX; + } + } + + if ((hw->mac_type == e1000_80003es2lan) && + (hw->media_type == e1000_media_type_copper)) { + if (*speed == SPEED_1000) + ret_val = e1000_configure_kmrn_for_1000(hw); + else + ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); + if (ret_val) + return ret_val; + } + + if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { + ret_val = e1000_kumeran_lock_loss_workaround(hw); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Blocks until autoneg completes or times out (~4.5 seconds) +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +STATIC int32_t +e1000_wait_autoneg(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC("e1000_wait_autoneg"); + DEBUGOUT("Waiting for Auto-Neg to complete.\n"); + + /* We will wait for autoneg to complete or 4.5 seconds to expire. */ + for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Auto-Neg + * Complete bit to be set. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + if (phy_data & MII_SR_AUTONEG_COMPLETE) { + return E1000_SUCCESS; + } + msec_delay(100); + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Raises the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_raise_mdi_clk(struct e1000_hw *hw, + uint32_t *ctrl) +{ + /* Raise the clock input to the Management Data Clock (by setting the MDC + * bit), and then delay 10 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + usec_delay(10); +} + +/****************************************************************************** +* Lowers the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_lower_mdi_clk(struct e1000_hw *hw, + uint32_t *ctrl) +{ + /* Lower the clock input to the Management Data Clock (by clearing the MDC + * bit), and then delay 10 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + usec_delay(10); +} + +/****************************************************************************** +* Shifts data bits out to the PHY +* +* hw - Struct containing variables accessed by shared code +* data - Data to send out to the PHY +* count - Number of bits to shift out +* +* Bits are shifted out in MSB to LSB order. +******************************************************************************/ +static void +e1000_shift_out_mdi_bits(struct e1000_hw *hw, + uint32_t data, + uint16_t count) +{ + uint32_t ctrl; + uint32_t mask; + + /* We need to shift "count" number of bits out to the PHY. So, the value + * in the "data" parameter will be shifted out to the PHY one bit at a + * time. In order to do this, "data" must be broken down into bits. + */ + mask = 0x01; + mask <<= (count - 1); + + ctrl = E1000_READ_REG(hw, CTRL); + + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ + ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); + + while (mask) { + /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and + * then raising and lowering the Management Data Clock. A "0" is + * shifted out to the PHY by setting the MDIO bit to "0" and then + * raising and lowering the clock. + */ + if (data & mask) + ctrl |= E1000_CTRL_MDIO; + else + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + usec_delay(10); + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + mask = mask >> 1; + } +} + +/****************************************************************************** +* Shifts data bits in from the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Bits are shifted in in MSB to LSB order. +******************************************************************************/ +static uint16_t +e1000_shift_in_mdi_bits(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t data = 0; + uint8_t i; + + /* In order to read a register from the PHY, we need to shift in a total + * of 18 bits from the PHY. The first two bit (turnaround) times are used + * to avoid contention on the MDIO pin when a read operation is performed. + * These two bits are ignored by us and thrown away. Bits are "shifted in" + * by raising the input to the Management Data Clock (setting the MDC bit), + * and then reading the value of the MDIO bit. + */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ + ctrl &= ~E1000_CTRL_MDIO_DIR; + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + /* Raise and Lower the clock before reading in the data. This accounts for + * the turnaround bits. The first clock occurred when we clocked out the + * last bit of the Register Address. + */ + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + for (data = 0, i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_mdi_clk(hw, &ctrl); + ctrl = E1000_READ_REG(hw, CTRL); + /* Check to see if we shifted in a "1". */ + if (ctrl & E1000_CTRL_MDIO) + data |= 1; + e1000_lower_mdi_clk(hw, &ctrl); + } + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + return data; +} + +STATIC int32_t +e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) +{ + uint32_t swfw_sync = 0; + uint32_t swmask = mask; + uint32_t fwmask = mask << 16; + int32_t timeout = 200; + + DEBUGFUNC("e1000_swfw_sync_acquire"); + + if (hw->swfwhw_semaphore_present) + return e1000_get_software_flag(hw); + + if (!hw->swfw_sync_present) + return e1000_get_hw_eeprom_semaphore(hw); + + while (timeout) { + if (e1000_get_hw_eeprom_semaphore(hw)) + return -E1000_ERR_SWFW_SYNC; + + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + if (!(swfw_sync & (fwmask | swmask))) { + break; + } + + /* firmware currently using resource (fwmask) */ + /* or other software thread currently using resource (swmask) */ + e1000_put_hw_eeprom_semaphore(hw); + msec_delay_irq(5); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); + return -E1000_ERR_SWFW_SYNC; + } + + swfw_sync |= swmask; + E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); + + e1000_put_hw_eeprom_semaphore(hw); + return E1000_SUCCESS; +} + +STATIC void +e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) +{ + uint32_t swfw_sync; + uint32_t swmask = mask; + + DEBUGFUNC("e1000_swfw_sync_release"); + + if (hw->swfwhw_semaphore_present) { + e1000_release_software_flag(hw); + return; + } + + if (!hw->swfw_sync_present) { + e1000_put_hw_eeprom_semaphore(hw); + return; + } + + /* if (e1000_get_hw_eeprom_semaphore(hw)) + * return -E1000_ERR_SWFW_SYNC; */ + while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); + /* empty */ + + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + swfw_sync &= ~swmask; + E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); + + e1000_put_hw_eeprom_semaphore(hw); +} + +/***************************************************************************** +* Reads the value from a PHY register, if the value is on a specific non zero +* page, sets the page first. +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to read +******************************************************************************/ +int32_t +e1000_read_phy_reg(struct e1000_hw *hw, + uint32_t reg_addr, + uint16_t *phy_data) +{ + uint32_t ret_val; + uint16_t swfw; + + DEBUGFUNC("e1000_read_phy_reg"); + + if ((hw->mac_type == e1000_80003es2lan) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + swfw = E1000_SWFW_PHY1_SM; + } else { + swfw = E1000_SWFW_PHY0_SM; + } + if (e1000_swfw_sync_acquire(hw, swfw)) + return -E1000_ERR_SWFW_SYNC; + + if ((hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) && + (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { + ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, + (uint16_t)reg_addr); + if (ret_val) { + e1000_swfw_sync_release(hw, swfw); + return ret_val; + } + } else if (hw->phy_type == e1000_phy_gg82563) { + if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || + (hw->mac_type == e1000_80003es2lan)) { + /* Select Configuration Page */ + if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { + ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, + (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + } else { + /* Use Alternative Page Select register to access + * registers 30 and 31 + */ + ret_val = e1000_write_phy_reg_ex(hw, + GG82563_PHY_PAGE_SELECT_ALT, + (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + } + + if (ret_val) { + e1000_swfw_sync_release(hw, swfw); + return ret_val; + } + } + } + + ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, + phy_data); + + e1000_swfw_sync_release(hw, swfw); + return ret_val; +} + +STATIC int32_t +e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t *phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + DEBUGFUNC("e1000_read_phy_reg_ex"); + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, and register address in the MDI + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ + mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + usec_delay(50); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Read did not complete\n"); + return -E1000_ERR_PHY; + } + if (mdic & E1000_MDIC_ERROR) { + DEBUGOUT("MDI Error\n"); + return -E1000_ERR_PHY; + } + *phy_data = (uint16_t) mdic; + } else { + /* We must first send a preamble through the MDIO pin to signal the + * beginning of an MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the next few fields that are required for a read + * operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine five different times. The format of + * a MII read instruction consists of a shift out of 14 bits and is + * defined as follows: + * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> + * followed by a shift in of 18 bits. This first two bits shifted in + * are TurnAround bits used to avoid contention on the MDIO pin when a + * READ operation is performed. These two bits are thrown away + * followed by a shift in of 16 bits which contains the desired data. + */ + mdic = ((reg_addr) | (phy_addr << 5) | + (PHY_OP_READ << 10) | (PHY_SOF << 12)); + + e1000_shift_out_mdi_bits(hw, mdic, 14); + + /* Now that we've shifted out the read command to the MII, we need to + * "shift in" the 16-bit value (18 total bits) of the requested PHY + * register address. + */ + *phy_data = e1000_shift_in_mdi_bits(hw); + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Writes a value to a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to write +* data - data to write to the PHY +******************************************************************************/ +int32_t +e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data) +{ + uint32_t ret_val; + uint16_t swfw; + + DEBUGFUNC("e1000_write_phy_reg"); + + if ((hw->mac_type == e1000_80003es2lan) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + swfw = E1000_SWFW_PHY1_SM; + } else { + swfw = E1000_SWFW_PHY0_SM; + } + if (e1000_swfw_sync_acquire(hw, swfw)) + return -E1000_ERR_SWFW_SYNC; + + if ((hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) && + (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { + ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, + (uint16_t)reg_addr); + if (ret_val) { + e1000_swfw_sync_release(hw, swfw); + return ret_val; + } + } else if (hw->phy_type == e1000_phy_gg82563) { + if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || + (hw->mac_type == e1000_80003es2lan)) { + /* Select Configuration Page */ + if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { + ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, + (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + } else { + /* Use Alternative Page Select register to access + * registers 30 and 31 + */ + ret_val = e1000_write_phy_reg_ex(hw, + GG82563_PHY_PAGE_SELECT_ALT, + (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + } + + if (ret_val) { + e1000_swfw_sync_release(hw, swfw); + return ret_val; + } + } + } + + ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, + phy_data); + + e1000_swfw_sync_release(hw, swfw); + return ret_val; +} + +STATIC int32_t +e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + DEBUGFUNC("e1000_write_phy_reg_ex"); + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, register address, and data intended + * for the PHY register in the MDI Control register. The MAC will take + * care of interfacing with the PHY to send the desired data. + */ + mdic = (((uint32_t) phy_data) | + (reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 641; i++) { + usec_delay(5); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Write did not complete\n"); + return -E1000_ERR_PHY; + } + } else { + /* We'll need to use the SW defined pins to shift the write command + * out to the PHY. We first send a preamble to the PHY to signal the + * beginning of the MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the remaining required fields that will indicate a + * write operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine for each field in the command. The + * format of a MII write instruction is as follows: + * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. + */ + mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | + (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); + mdic <<= 16; + mdic |= (uint32_t) phy_data; + + e1000_shift_out_mdi_bits(hw, mdic, 32); + } + + return E1000_SUCCESS; +} + +STATIC int32_t +e1000_read_kmrn_reg(struct e1000_hw *hw, + uint32_t reg_addr, + uint16_t *data) +{ + uint32_t reg_val; + uint16_t swfw; + DEBUGFUNC("e1000_read_kmrn_reg"); + + if ((hw->mac_type == e1000_80003es2lan) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + swfw = E1000_SWFW_PHY1_SM; + } else { + swfw = E1000_SWFW_PHY0_SM; + } + if (e1000_swfw_sync_acquire(hw, swfw)) + return -E1000_ERR_SWFW_SYNC; + + /* Write register address */ + reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & + E1000_KUMCTRLSTA_OFFSET) | + E1000_KUMCTRLSTA_REN; + E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); + usec_delay(2); + + /* Read the data returned */ + reg_val = E1000_READ_REG(hw, KUMCTRLSTA); + *data = (uint16_t)reg_val; + + e1000_swfw_sync_release(hw, swfw); + return E1000_SUCCESS; +} + +STATIC int32_t +e1000_write_kmrn_reg(struct e1000_hw *hw, + uint32_t reg_addr, + uint16_t data) +{ + uint32_t reg_val; + uint16_t swfw; + DEBUGFUNC("e1000_write_kmrn_reg"); + + if ((hw->mac_type == e1000_80003es2lan) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + swfw = E1000_SWFW_PHY1_SM; + } else { + swfw = E1000_SWFW_PHY0_SM; + } + if (e1000_swfw_sync_acquire(hw, swfw)) + return -E1000_ERR_SWFW_SYNC; + + reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & + E1000_KUMCTRLSTA_OFFSET) | data; + E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); + usec_delay(2); + + e1000_swfw_sync_release(hw, swfw); + return E1000_SUCCESS; +} + +/****************************************************************************** +* Returns the PHY to the power-on reset state +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +int32_t +e1000_phy_hw_reset(struct e1000_hw *hw) +{ + uint32_t ctrl, ctrl_ext; + uint32_t led_ctrl; + int32_t ret_val; + uint16_t swfw; + + DEBUGFUNC("e1000_phy_hw_reset"); + + /* In the case of the phy reset being blocked, it's not an error, we + * simply return success without performing the reset. */ + ret_val = e1000_check_phy_reset_block(hw); + if (ret_val) + return E1000_SUCCESS; + + DEBUGOUT("Resetting Phy...\n"); + + if (hw->mac_type > e1000_82543) { + if ((hw->mac_type == e1000_80003es2lan) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + swfw = E1000_SWFW_PHY1_SM; + } else { + swfw = E1000_SWFW_PHY0_SM; + } + if (e1000_swfw_sync_acquire(hw, swfw)) { + DEBUGOUT("Unable to acquire swfw sync\n"); + return -E1000_ERR_SWFW_SYNC; + } + /* Read the device control register and assert the E1000_CTRL_PHY_RST + * bit. Then, take it out of reset. + * For pre-e1000_82571 hardware, we delay for 10ms between the assert + * and deassert. For e1000_82571 hardware and later, we instead delay + * for 50us between and 10ms after the deassertion. + */ + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + + if (hw->mac_type < e1000_82571) + msec_delay(10); + else + usec_delay(100); + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + if (hw->mac_type >= e1000_82571) + msec_delay_irq(10); + + e1000_swfw_sync_release(hw, swfw); + } else { + /* Read the Extended Device Control Register, assert the PHY_RESET_DIR + * bit to put the PHY into reset. Then, take it out of reset. + */ + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; + ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + msec_delay(10); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + usec_delay(150); + + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + /* Configure activity LED after PHY reset */ + led_ctrl = E1000_READ_REG(hw, LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, LEDCTL, led_ctrl); + } + + /* Wait for FW to finish PHY configuration. */ + ret_val = e1000_get_phy_cfg_done(hw); + if (ret_val != E1000_SUCCESS) + return ret_val; + e1000_release_software_semaphore(hw); + + if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) + ret_val = e1000_init_lcd_from_nvm(hw); + + return ret_val; +} + +/****************************************************************************** +* Resets the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Sets bit 15 of the MII Control regiser +******************************************************************************/ +int32_t +e1000_phy_reset(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_phy_reset"); + + /* In the case of the phy reset being blocked, it's not an error, we + * simply return success without performing the reset. */ + ret_val = e1000_check_phy_reset_block(hw); + if (ret_val) + return E1000_SUCCESS; + + switch (hw->phy_type) { + case e1000_phy_igp: + case e1000_phy_igp_2: + case e1000_phy_igp_3: + case e1000_phy_ife: + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) + return ret_val; + break; + default: + ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= MII_CR_RESET; + ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); + if (ret_val) + return ret_val; + + usec_delay(1); + break; + } + + if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) + e1000_phy_init_script(hw); + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Work-around for 82566 power-down: on D3 entry- +* 1) disable gigabit link +* 2) write VR power-down enable +* 3) read it back +* if successful continue, else issue LCD reset and repeat +* +* hw - struct containing variables accessed by shared code +******************************************************************************/ +void +e1000_phy_powerdown_workaround(struct e1000_hw *hw) +{ + int32_t reg; + uint16_t phy_data; + int32_t retry = 0; + + DEBUGFUNC("e1000_phy_powerdown_workaround"); + + if (hw->phy_type != e1000_phy_igp_3) + return; + + do { + /* Disable link */ + reg = E1000_READ_REG(hw, PHY_CTRL); + E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | + E1000_PHY_CTRL_NOND0A_GBE_DISABLE); + + /* Write VR power-down enable - bits 9:8 should be 10b */ + e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); + phy_data |= (1 << 9); + phy_data &= ~(1 << 8); + e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); + + /* Read it back and test */ + e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); + if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) + break; + + /* Issue PHY reset and repeat at most one more time */ + reg = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); + retry++; + } while (retry); + + return; + +} + +/****************************************************************************** +* Work-around for 82566 Kumeran PCS lock loss: +* On link status change (i.e. PCI reset, speed change) and link is up and +* speed is gigabit- +* 0) if workaround is optionally disabled do nothing +* 1) wait 1ms for Kumeran link to come up +* 2) check Kumeran Diagnostic register PCS lock loss bit +* 3) if not set the link is locked (all is good), otherwise... +* 4) reset the PHY +* 5) repeat up to 10 times +* Note: this is only called for IGP3 copper when speed is 1gb. +* +* hw - struct containing variables accessed by shared code +******************************************************************************/ +STATIC int32_t +e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) +{ + int32_t ret_val; + int32_t reg; + int32_t cnt; + uint16_t phy_data; + + if (hw->kmrn_lock_loss_workaround_disabled) + return E1000_SUCCESS; + + /* Make sure link is up before proceeding. If not just return. + * Attempting this while link is negotiating fouled up link + * stability */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + + if (phy_data & MII_SR_LINK_STATUS) { + for (cnt = 0; cnt < 10; cnt++) { + /* read once to clear */ + ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); + if (ret_val) + return ret_val; + /* and again to get new status */ + ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); + if (ret_val) + return ret_val; + + /* check for PCS lock */ + if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) + return E1000_SUCCESS; + + /* Issue PHY reset */ + e1000_phy_hw_reset(hw); + msec_delay_irq(5); + } + /* Disable GigE link negotiation */ + reg = E1000_READ_REG(hw, PHY_CTRL); + E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | + E1000_PHY_CTRL_NOND0A_GBE_DISABLE); + + /* unable to acquire PCS lock */ + return E1000_ERR_PHY; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Probes the expected PHY address for known PHY IDs +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +STATIC int32_t +e1000_detect_gig_phy(struct e1000_hw *hw) +{ + int32_t phy_init_status, ret_val; + uint16_t phy_id_high, phy_id_low; + boolean_t match = FALSE; + + DEBUGFUNC("e1000_detect_gig_phy"); + + if (hw->phy_id != 0) + return E1000_SUCCESS; + + /* The 82571 firmware may still be configuring the PHY. In this + * case, we cannot access the PHY until the configuration is done. So + * we explicitly set the PHY values. */ + if (hw->mac_type == e1000_82571 || + hw->mac_type == e1000_82572) { + hw->phy_id = IGP01E1000_I_PHY_ID; + hw->phy_type = e1000_phy_igp_2; + return E1000_SUCCESS; + } + + /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- + * around that forces PHY page 0 to be set or the reads fail. The rest of + * the code in this routine uses e1000_read_phy_reg to read the PHY ID. + * So for ESB-2 we need to have this set so our reads won't fail. If the + * attached PHY is not a e1000_phy_gg82563, the routines below will figure + * this out as well. */ + if (hw->mac_type == e1000_80003es2lan) + hw->phy_type = e1000_phy_gg82563; + + /* Read the PHY ID Registers to identify which PHY is onboard. */ + ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); + if (ret_val) + return ret_val; + + hw->phy_id = (uint32_t) (phy_id_high << 16); + usec_delay(20); + ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); + if (ret_val) + return ret_val; + + hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); + hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; + + switch (hw->mac_type) { + case e1000_82543: + if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; + break; + case e1000_82544: + if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; + break; + case e1000_82573: + if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; + break; + case e1000_80003es2lan: + if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; + break; + case e1000_ich8lan: + if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; + if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; + if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; + if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; + break; + default: + DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); + return -E1000_ERR_CONFIG; + } + phy_init_status = e1000_set_phy_type(hw); + + if ((match) && (phy_init_status == E1000_SUCCESS)) { + DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); + return E1000_SUCCESS; + } + DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); + return -E1000_ERR_PHY; +} + +/****************************************************************************** +* Resets the PHY's DSP +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_phy_reset_dsp(struct e1000_hw *hw) +{ + int32_t ret_val; + DEBUGFUNC("e1000_phy_reset_dsp"); + + do { + if (hw->phy_type != e1000_phy_gg82563) { + ret_val = e1000_write_phy_reg(hw, 29, 0x001d); + if (ret_val) break; + } + ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); + if (ret_val) break; + ret_val = e1000_write_phy_reg(hw, 30, 0x0000); + if (ret_val) break; + ret_val = E1000_SUCCESS; + } while (0); + + return ret_val; +} + +/****************************************************************************** +* Get PHY information from various PHY registers for igp PHY only. +* +* hw - Struct containing variables accessed by shared code +* phy_info - PHY information structure +******************************************************************************/ +STATIC int32_t +e1000_phy_igp_get_info(struct e1000_hw *hw, + struct e1000_phy_info *phy_info) +{ + int32_t ret_val; + uint16_t phy_data, min_length, max_length, average; + e1000_rev_polarity polarity; + + DEBUGFUNC("e1000_phy_igp_get_info"); + + /* The downshift status is checked only once, after link is established, + * and it stored in the hw->speed_downgraded parameter. */ + phy_info->downshift = (e1000_downshift)hw->speed_downgraded; + + /* IGP01E1000 does not need to support it. */ + phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; + + /* IGP01E1000 always correct polarity reversal */ + phy_info->polarity_correction = e1000_polarity_reversal_enabled; + + /* Check polarity status */ + ret_val = e1000_check_polarity(hw, &polarity); + if (ret_val) + return ret_val; + + phy_info->cable_polarity = polarity; + + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); + if (ret_val) + return ret_val; + + phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> + IGP01E1000_PSSR_MDIX_SHIFT); + + if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == + IGP01E1000_PSSR_SPEED_1000MBPS) { + /* Local/Remote Receiver Information are only valid at 1000 Mbps */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) + return ret_val; + + phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> + SR_1000T_LOCAL_RX_STATUS_SHIFT) ? + e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; + phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> + SR_1000T_REMOTE_RX_STATUS_SHIFT) ? + e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; + + /* Get cable length */ + ret_val = e1000_get_cable_length(hw, &min_length, &max_length); + if (ret_val) + return ret_val; + + /* Translate to old method */ + average = (max_length + min_length) / 2; + + if (average <= e1000_igp_cable_length_50) + phy_info->cable_length = e1000_cable_length_50; + else if (average <= e1000_igp_cable_length_80) + phy_info->cable_length = e1000_cable_length_50_80; + else if (average <= e1000_igp_cable_length_110) + phy_info->cable_length = e1000_cable_length_80_110; + else if (average <= e1000_igp_cable_length_140) + phy_info->cable_length = e1000_cable_length_110_140; + else + phy_info->cable_length = e1000_cable_length_140; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Get PHY information from various PHY registers for ife PHY only. +* +* hw - Struct containing variables accessed by shared code +* phy_info - PHY information structure +******************************************************************************/ +STATIC int32_t +e1000_phy_ife_get_info(struct e1000_hw *hw, + struct e1000_phy_info *phy_info) +{ + int32_t ret_val; + uint16_t phy_data; + e1000_rev_polarity polarity; + + DEBUGFUNC("e1000_phy_ife_get_info"); + + phy_info->downshift = (e1000_downshift)hw->speed_downgraded; + phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; + + ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); + if (ret_val) + return ret_val; + phy_info->polarity_correction = + ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> + IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? + e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; + + if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { + ret_val = e1000_check_polarity(hw, &polarity); + if (ret_val) + return ret_val; + } else { + /* Polarity is forced. */ + polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> + IFE_PSC_FORCE_POLARITY_SHIFT) ? + e1000_rev_polarity_reversed : e1000_rev_polarity_normal; + } + phy_info->cable_polarity = polarity; + + ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); + if (ret_val) + return ret_val; + + phy_info->mdix_mode = (e1000_auto_x_mode) + ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> + IFE_PMC_MDIX_MODE_SHIFT); + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Get PHY information from various PHY registers fot m88 PHY only. +* +* hw - Struct containing variables accessed by shared code +* phy_info - PHY information structure +******************************************************************************/ +STATIC int32_t +e1000_phy_m88_get_info(struct e1000_hw *hw, + struct e1000_phy_info *phy_info) +{ + int32_t ret_val; + uint16_t phy_data; + e1000_rev_polarity polarity; + + DEBUGFUNC("e1000_phy_m88_get_info"); + + /* The downshift status is checked only once, after link is established, + * and it stored in the hw->speed_downgraded parameter. */ + phy_info->downshift = (e1000_downshift)hw->speed_downgraded; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_info->extended_10bt_distance = + ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> + M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? + e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; + + phy_info->polarity_correction = + ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> + M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? + e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; + + /* Check polarity status */ + ret_val = e1000_check_polarity(hw, &polarity); + if (ret_val) + return ret_val; + phy_info->cable_polarity = polarity; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + return ret_val; + + phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> + M88E1000_PSSR_MDIX_SHIFT); + + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { + /* Cable Length Estimation and Local/Remote Receiver Information + * are only valid at 1000 Mbps. + */ + if (hw->phy_type != e1000_phy_gg82563) { + phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> + M88E1000_PSSR_CABLE_LENGTH_SHIFT); + } else { + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, + &phy_data); + if (ret_val) + return ret_val; + + phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); + } + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) + return ret_val; + + phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> + SR_1000T_LOCAL_RX_STATUS_SHIFT) ? + e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; + phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> + SR_1000T_REMOTE_RX_STATUS_SHIFT) ? + e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; + + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Get PHY information from various PHY registers +* +* hw - Struct containing variables accessed by shared code +* phy_info - PHY information structure +******************************************************************************/ +int32_t +e1000_phy_get_info(struct e1000_hw *hw, + struct e1000_phy_info *phy_info) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_phy_get_info"); + + phy_info->cable_length = e1000_cable_length_undefined; + phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; + phy_info->cable_polarity = e1000_rev_polarity_undefined; + phy_info->downshift = e1000_downshift_undefined; + phy_info->polarity_correction = e1000_polarity_reversal_undefined; + phy_info->mdix_mode = e1000_auto_x_mode_undefined; + phy_info->local_rx = e1000_1000t_rx_status_undefined; + phy_info->remote_rx = e1000_1000t_rx_status_undefined; + + if (hw->media_type != e1000_media_type_copper) { + DEBUGOUT("PHY info is only valid for copper media\n"); + return -E1000_ERR_CONFIG; + } + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { + DEBUGOUT("PHY info is only valid if link is up\n"); + return -E1000_ERR_CONFIG; + } + + if (hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) + return e1000_phy_igp_get_info(hw, phy_info); + else if (hw->phy_type == e1000_phy_ife) + return e1000_phy_ife_get_info(hw, phy_info); + else + return e1000_phy_m88_get_info(hw, phy_info); +} + +int32_t +e1000_validate_mdi_setting(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_validate_mdi_settings"); + + if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { + DEBUGOUT("Invalid MDI setting detected\n"); + hw->mdix = 1; + return -E1000_ERR_CONFIG; + } + return E1000_SUCCESS; +} + + +/****************************************************************************** + * Sets up eeprom variables in the hw struct. Must be called after mac_type + * is configured. Additionally, if this is ICH8, the flash controller GbE + * registers must be mapped, or this will crash. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_init_eeprom_params(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd = E1000_READ_REG(hw, EECD); + int32_t ret_val = E1000_SUCCESS; + uint16_t eeprom_size; + + DEBUGFUNC("e1000_init_eeprom_params"); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + case e1000_82544: + eeprom->type = e1000_eeprom_microwire; + eeprom->word_size = 64; + eeprom->opcode_bits = 3; + eeprom->address_bits = 6; + eeprom->delay_usec = 50; + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + eeprom->type = e1000_eeprom_microwire; + eeprom->opcode_bits = 3; + eeprom->delay_usec = 50; + if (eecd & E1000_EECD_SIZE) { + eeprom->word_size = 256; + eeprom->address_bits = 8; + } else { + eeprom->word_size = 64; + eeprom->address_bits = 6; + } + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + if (eecd & E1000_EECD_TYPE) { + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + } else { + eeprom->type = e1000_eeprom_microwire; + eeprom->opcode_bits = 3; + eeprom->delay_usec = 50; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->word_size = 256; + eeprom->address_bits = 8; + } else { + eeprom->word_size = 64; + eeprom->address_bits = 6; + } + } + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + break; + case e1000_82571: + case e1000_82572: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + break; + case e1000_82573: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = TRUE; + eeprom->use_eewr = TRUE; + if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + eeprom->type = e1000_eeprom_flash; + eeprom->word_size = 2048; + + /* Ensure that the Autonomous FLASH update bit is cleared due to + * Flash update issue on parts which use a FLASH for NVM. */ + eecd &= ~E1000_EECD_AUPDEN; + E1000_WRITE_REG(hw, EECD, eecd); + } + break; + case e1000_80003es2lan: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = TRUE; + eeprom->use_eewr = FALSE; + break; + case e1000_ich8lan: + { + int32_t i = 0; + uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); + + eeprom->type = e1000_eeprom_ich8; + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + eeprom->word_size = E1000_SHADOW_RAM_WORDS; + + /* Zero the shadow RAM structure. But don't load it from NVM + * so as to save time for driver init */ + if (hw->eeprom_shadow_ram != NULL) { + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; + } + } + + hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * + ICH_FLASH_SECTOR_SIZE; + + hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; + hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); + + hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; + + hw->flash_bank_size /= 2 * sizeof(uint16_t); + + break; + } + default: + break; + } + + if (eeprom->type == e1000_eeprom_spi) { + /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to + * 32KB (incremented by powers of 2). + */ + if (hw->mac_type <= e1000_82547_rev_2) { + /* Set to default value for initial eeprom read. */ + eeprom->word_size = 64; + ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); + if (ret_val) + return ret_val; + eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; + /* 256B eeprom size was not supported in earlier hardware, so we + * bump eeprom_size up one to ensure that "1" (which maps to 256B) + * is never the result used in the shifting logic below. */ + if (eeprom_size) + eeprom_size++; + } else { + eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + } + + eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); + } + return ret_val; +} + +/****************************************************************************** + * Raises the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_raise_ee_clk(struct e1000_hw *hw, + uint32_t *eecd) +{ + /* Raise the clock input to the EEPROM (by setting the SK bit), and then + * wait <delay> microseconds. + */ + *eecd = *eecd | E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->eeprom.delay_usec); +} + +/****************************************************************************** + * Lowers the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_lower_ee_clk(struct e1000_hw *hw, + uint32_t *eecd) +{ + /* Lower the clock input to the EEPROM (by clearing the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd & ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->eeprom.delay_usec); +} + +/****************************************************************************** + * Shift data bits out to the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * data - data to send to the EEPROM + * count - number of bits to shift out + *****************************************************************************/ +static void +e1000_shift_out_ee_bits(struct e1000_hw *hw, + uint16_t data, + uint16_t count) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd; + uint32_t mask; + + /* We need to shift "count" bits out to the EEPROM. So, value in the + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ + mask = 0x01 << (count - 1); + eecd = E1000_READ_REG(hw, EECD); + if (eeprom->type == e1000_eeprom_microwire) { + eecd &= ~E1000_EECD_DO; + } else if (eeprom->type == e1000_eeprom_spi) { + eecd |= E1000_EECD_DO; + } + do { + /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", + * and then raising and then lowering the clock (the SK bit controls + * the clock input to the EEPROM). A "0" is shifted out to the EEPROM + * by setting "DI" to "0" and then raising and then lowering the clock. + */ + eecd &= ~E1000_EECD_DI; + + if (data & mask) + eecd |= E1000_EECD_DI; + + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + + usec_delay(eeprom->delay_usec); + + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); + + mask = mask >> 1; + + } while (mask); + + /* We leave the "DI" bit set to "0" when we leave this routine. */ + eecd &= ~E1000_EECD_DI; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Shift data bits in from the EEPROM + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static uint16_t +e1000_shift_in_ee_bits(struct e1000_hw *hw, + uint16_t count) +{ + uint32_t eecd; + uint32_t i; + uint16_t data; + + /* In order to read a register from the EEPROM, we need to shift 'count' + * bits in from the EEPROM. Bits are "shifted in" by raising the clock + * input to the EEPROM (setting the SK bit), and then reading the value of + * the "DO" bit. During this "shifting in" process the "DI" bit should + * always be clear. + */ + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < count; i++) { + data = data << 1; + e1000_raise_ee_clk(hw, &eecd); + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DI); + if (eecd & E1000_EECD_DO) + data |= 1; + + e1000_lower_ee_clk(hw, &eecd); + } + + return data; +} + +/****************************************************************************** + * Prepares EEPROM for access + * + * hw - Struct containing variables accessed by shared code + * + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This + * function should be called before issuing a command to the EEPROM. + *****************************************************************************/ +static int32_t +e1000_acquire_eeprom(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd, i=0; + + DEBUGFUNC("e1000_acquire_eeprom"); + + if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) + return -E1000_ERR_SWFW_SYNC; + eecd = E1000_READ_REG(hw, EECD); + + if (hw->mac_type != e1000_82573) { + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && + (i < E1000_EEPROM_GRANT_ATTEMPTS)) { + i++; + usec_delay(5); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); + return -E1000_ERR_EEPROM; + } + } + } + + /* Setup EEPROM for Read/Write */ + + if (eeprom->type == e1000_eeprom_microwire) { + /* Clear SK and DI */ + eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + + /* Set CS */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + } else if (eeprom->type == e1000_eeprom_spi) { + /* Clear SK and CS */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + usec_delay(1); + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Returns EEPROM to a "standby" state + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_standby_eeprom(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + if (eeprom->type == e1000_eeprom_microwire) { + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + + /* Clock high */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + + /* Select EEPROM */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + + /* Clock low */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + } else if (eeprom->type == e1000_eeprom_spi) { + /* Toggle CS to flush commands */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + eecd &= ~E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(eeprom->delay_usec); + } +} + +/****************************************************************************** + * Terminates a command by inverting the EEPROM's chip select pin + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_release_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + DEBUGFUNC("e1000_release_eeprom"); + + eecd = E1000_READ_REG(hw, EECD); + + if (hw->eeprom.type == e1000_eeprom_spi) { + eecd |= E1000_EECD_CS; /* Pull CS high */ + eecd &= ~E1000_EECD_SK; /* Lower SCK */ + + E1000_WRITE_REG(hw, EECD, eecd); + + usec_delay(hw->eeprom.delay_usec); + } else if (hw->eeprom.type == e1000_eeprom_microwire) { + /* cleanup eeprom */ + + /* CS on Microwire is active-high */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); + + E1000_WRITE_REG(hw, EECD, eecd); + + /* Rising edge of clock */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->eeprom.delay_usec); + + /* Falling edge of clock */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->eeprom.delay_usec); + } + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + + e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +STATIC int32_t +e1000_spi_eeprom_ready(struct e1000_hw *hw) +{ + uint16_t retry_count = 0; + uint8_t spi_stat_reg; + + DEBUGFUNC("e1000_spi_eeprom_ready"); + + /* Read "Status Register" repeatedly until the LSB is cleared. The + * EEPROM will signal that the command has been completed by clearing + * bit 0 of the internal status register. If it's not cleared within + * 5 milliseconds, then error out. + */ + retry_count = 0; + do { + e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, + hw->eeprom.opcode_bits); + spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); + if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) + break; + + usec_delay(5); + retry_count += 5; + + e1000_standby_eeprom(hw); + } while (retry_count < EEPROM_MAX_RETRY_SPI); + + /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and + * only 0-5mSec on 5V devices) + */ + if (retry_count >= EEPROM_MAX_RETRY_SPI) { + DEBUGOUT("SPI EEPROM Status error\n"); + return -E1000_ERR_EEPROM; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +int32_t +e1000_read_eeprom(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t i = 0; + + DEBUGFUNC("e1000_read_eeprom"); + + /* If eeprom is not yet detected, do so now */ + if (eeprom->word_size == 0) + e1000_init_eeprom_params(hw); + + /* A check for invalid values: offset too large, too many words, and not + * enough words. + */ + if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || + (words == 0)) { + DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); + return -E1000_ERR_EEPROM; + } + + /* EEPROM's that don't use EERD to read require us to bit-bang the SPI + * directly. In this case, we need to acquire the EEPROM so that + * FW or other port software does not interrupt. + */ + if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && + hw->eeprom.use_eerd == FALSE) { + /* Prepare the EEPROM for bit-bang reading */ + if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) + return -E1000_ERR_EEPROM; + } + + /* Eerd register EEPROM access requires no eeprom aquire/release */ + if (eeprom->use_eerd == TRUE) + return e1000_read_eeprom_eerd(hw, offset, words, data); + + /* ICH EEPROM access is done via the ICH flash controller */ + if (eeprom->type == e1000_eeprom_ich8) + return e1000_read_eeprom_ich8(hw, offset, words, data); + + /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have + * acquired the EEPROM at this point, so any returns should relase it */ + if (eeprom->type == e1000_eeprom_spi) { + uint16_t word_in; + uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; + + if (e1000_spi_eeprom_ready(hw)) { + e1000_release_eeprom(hw); + return -E1000_ERR_EEPROM; + } + + e1000_standby_eeprom(hw); + + /* Some SPI eeproms use the 8th address bit embedded in the opcode */ + if ((eeprom->address_bits == 8) && (offset >= 128)) + read_opcode |= EEPROM_A8_OPCODE_SPI; + + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); + e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); + + /* Read the data. The address of the eeprom internally increments with + * each byte (spi) being read, saving on the overhead of eeprom setup + * and tear-down. The address counter will roll over if reading beyond + * the size of the eeprom, thus allowing the entire memory to be read + * starting from any offset. */ + for (i = 0; i < words; i++) { + word_in = e1000_shift_in_ee_bits(hw, 16); + data[i] = (word_in >> 8) | (word_in << 8); + } + } else if (eeprom->type == e1000_eeprom_microwire) { + for (i = 0; i < words; i++) { + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, + eeprom->opcode_bits); + e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), + eeprom->address_bits); + + /* Read the data. For microwire, each word requires the overhead + * of eeprom setup and tear-down. */ + data[i] = e1000_shift_in_ee_bits(hw, 16); + e1000_standby_eeprom(hw); + } + } + + /* End this read operation */ + e1000_release_eeprom(hw); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM using the EERD register. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +STATIC int32_t +e1000_read_eeprom_eerd(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + uint32_t i, eerd = 0; + int32_t error = 0; + + for (i = 0; i < words; i++) { + eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + + E1000_EEPROM_RW_REG_START; + + E1000_WRITE_REG(hw, EERD, eerd); + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); + + if (error) { + break; + } + data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); + + } + + return error; +} + +/****************************************************************************** + * Writes a 16 bit word from the EEPROM using the EEWR register. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +STATIC int32_t +e1000_write_eeprom_eewr(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + uint32_t register_value = 0; + uint32_t i = 0; + int32_t error = 0; + + if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) + return -E1000_ERR_SWFW_SYNC; + + for (i = 0; i < words; i++) { + register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | + ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | + E1000_EEPROM_RW_REG_START; + + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); + if (error) { + break; + } + + E1000_WRITE_REG(hw, EEWR, register_value); + + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); + + if (error) { + break; + } + } + + e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); + return error; +} + +/****************************************************************************** + * Polls the status bit (bit 1) of the EERD to determine when the read is done. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +STATIC int32_t +e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) +{ + uint32_t attempts = 100000; + uint32_t i, reg = 0; + int32_t done = E1000_ERR_EEPROM; + + for (i = 0; i < attempts; i++) { + if (eerd == E1000_EEPROM_POLL_READ) + reg = E1000_READ_REG(hw, EERD); + else + reg = E1000_READ_REG(hw, EEWR); + + if (reg & E1000_EEPROM_RW_REG_DONE) { + done = E1000_SUCCESS; + break; + } + usec_delay(5); + } + + return done; +} + +/*************************************************************************** +* Description: Determines if the onboard NVM is FLASH or EEPROM. +* +* hw - Struct containing variables accessed by shared code +****************************************************************************/ +STATIC boolean_t +e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd = 0; + + DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); + + if (hw->mac_type == e1000_ich8lan) + return FALSE; + + if (hw->mac_type == e1000_82573) { + eecd = E1000_READ_REG(hw, EECD); + + /* Isolate bits 15 & 16 */ + eecd = ((eecd >> 15) & 0x03); + + /* If both bits are set, device is Flash type */ + if (eecd == 0x03) { + return FALSE; + } + } + return TRUE; +} + +/****************************************************************************** + * Verifies that the EEPROM has a valid checksum + * + * hw - Struct containing variables accessed by shared code + * + * Reads the first 64 16 bit words of the EEPROM and sums the values read. + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is + * valid. + *****************************************************************************/ +int32_t +e1000_validate_eeprom_checksum(struct e1000_hw *hw) +{ + uint16_t checksum = 0; + uint16_t i, eeprom_data; + + DEBUGFUNC("e1000_validate_eeprom_checksum"); + + if ((hw->mac_type == e1000_82573) && + (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { + /* Check bit 4 of word 10h. If it is 0, firmware is done updating + * 10h-12h. Checksum may need to be fixed. */ + e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); + if ((eeprom_data & 0x10) == 0) { + /* Read 0x23 and check bit 15. This bit is a 1 when the checksum + * has already been fixed. If the checksum is still wrong and this + * bit is a 1, we need to return bad checksum. Otherwise, we need + * to set this bit to a 1 and update the checksum. */ + e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); + if ((eeprom_data & 0x8000) == 0) { + eeprom_data |= 0x8000; + e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); + e1000_update_eeprom_checksum(hw); + } + } + } + + if (hw->mac_type == e1000_ich8lan) { + /* Drivers must allocate the shadow ram structure for the + * EEPROM checksum to be updated. Otherwise, this bit as well + * as the checksum must both be set correctly for this + * validation to pass. + */ + e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); + if ((eeprom_data & 0x40) == 0) { + eeprom_data |= 0x40; + e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); + e1000_update_eeprom_checksum(hw); + } + } + + for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { + if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + checksum += eeprom_data; + } + + if (checksum == (uint16_t) EEPROM_SUM) + return E1000_SUCCESS; + else { + DEBUGOUT("EEPROM Checksum Invalid\n"); + return -E1000_ERR_EEPROM; + } +} + +/****************************************************************************** + * Calculates the EEPROM checksum and writes it to the EEPROM + * + * hw - Struct containing variables accessed by shared code + * + * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. + * Writes the difference to word offset 63 of the EEPROM. + *****************************************************************************/ +int32_t +e1000_update_eeprom_checksum(struct e1000_hw *hw) +{ + uint32_t ctrl_ext; + uint16_t checksum = 0; + uint16_t i, eeprom_data; + + DEBUGFUNC("e1000_update_eeprom_checksum"); + + for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { + if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + checksum += eeprom_data; + } + checksum = (uint16_t) EEPROM_SUM - checksum; + if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { + DEBUGOUT("EEPROM Write Error\n"); + return -E1000_ERR_EEPROM; + } else if (hw->eeprom.type == e1000_eeprom_flash) { + e1000_commit_shadow_ram(hw); + } else if (hw->eeprom.type == e1000_eeprom_ich8) { + e1000_commit_shadow_ram(hw); + /* Reload the EEPROM, or else modifications will not appear + * until after next adapter reset. */ + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + msec_delay(10); + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Parent function for writing words to the different EEPROM types. + * + * hw - Struct containing variables accessed by shared code + * offset - offset within the EEPROM to be written to + * words - number of words to write + * data - 16 bit word to be written to the EEPROM + * + * If e1000_update_eeprom_checksum is not called after this function, the + * EEPROM will most likely contain an invalid checksum. + *****************************************************************************/ +int32_t +e1000_write_eeprom(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + int32_t status = 0; + + DEBUGFUNC("e1000_write_eeprom"); + + /* If eeprom is not yet detected, do so now */ + if (eeprom->word_size == 0) + e1000_init_eeprom_params(hw); + + /* A check for invalid values: offset too large, too many words, and not + * enough words. + */ + if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || + (words == 0)) { + DEBUGOUT("\"words\" parameter out of bounds\n"); + return -E1000_ERR_EEPROM; + } + + /* 82573 writes only through eewr */ + if (eeprom->use_eewr == TRUE) + return e1000_write_eeprom_eewr(hw, offset, words, data); + + if (eeprom->type == e1000_eeprom_ich8) + return e1000_write_eeprom_ich8(hw, offset, words, data); + + /* Prepare the EEPROM for writing */ + if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) + return -E1000_ERR_EEPROM; + + if (eeprom->type == e1000_eeprom_microwire) { + status = e1000_write_eeprom_microwire(hw, offset, words, data); + } else { + status = e1000_write_eeprom_spi(hw, offset, words, data); + msec_delay(10); + } + + /* Done with writing */ + e1000_release_eeprom(hw); + + return status; +} + +/****************************************************************************** + * Writes a 16 bit word to a given offset in an SPI EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset within the EEPROM to be written to + * words - number of words to write + * data - pointer to array of 8 bit words to be written to the EEPROM + * + *****************************************************************************/ +STATIC int32_t +e1000_write_eeprom_spi(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint16_t widx = 0; + + DEBUGFUNC("e1000_write_eeprom_spi"); + + while (widx < words) { + uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; + + if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; + + e1000_standby_eeprom(hw); + + /* Send the WRITE ENABLE command (8 bit opcode ) */ + e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, + eeprom->opcode_bits); + + e1000_standby_eeprom(hw); + + /* Some SPI eeproms use the 8th address bit embedded in the opcode */ + if ((eeprom->address_bits == 8) && (offset >= 128)) + write_opcode |= EEPROM_A8_OPCODE_SPI; + + /* Send the Write command (8-bit opcode + addr) */ + e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); + + e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), + eeprom->address_bits); + + /* Send the data */ + + /* Loop to allow for up to whole page write (32 bytes) of eeprom */ + while (widx < words) { + uint16_t word_out = data[widx]; + word_out = (word_out >> 8) | (word_out << 8); + e1000_shift_out_ee_bits(hw, word_out, 16); + widx++; + + /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE + * operation, while the smaller eeproms are capable of an 8-byte + * PAGE WRITE operation. Break the inner loop to pass new address + */ + if ((((offset + widx)*2) % eeprom->page_size) == 0) { + e1000_standby_eeprom(hw); + break; + } + } + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Writes a 16 bit word to a given offset in a Microwire EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset within the EEPROM to be written to + * words - number of words to write + * data - pointer to array of 16 bit words to be written to the EEPROM + * + *****************************************************************************/ +STATIC int32_t +e1000_write_eeprom_microwire(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd; + uint16_t words_written = 0; + uint16_t i = 0; + + DEBUGFUNC("e1000_write_eeprom_microwire"); + + /* Send the write enable command to the EEPROM (3-bit opcode plus + * 6/8-bit dummy address beginning with 11). It's less work to include + * the 11 of the dummy address as part of the opcode than it is to shift + * it over the correct number of bits for the address. This puts the + * EEPROM into write/erase mode. + */ + e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, + (uint16_t)(eeprom->opcode_bits + 2)); + + e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); + + /* Prepare the EEPROM */ + e1000_standby_eeprom(hw); + + while (words_written < words) { + /* Send the Write command (3-bit opcode + addr) */ + e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, + eeprom->opcode_bits); + + e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), + eeprom->address_bits); + + /* Send the data */ + e1000_shift_out_ee_bits(hw, data[words_written], 16); + + /* Toggle the CS line. This in effect tells the EEPROM to execute + * the previous command. + */ + e1000_standby_eeprom(hw); + + /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will + * signal that the command has been completed by raising the DO signal. + * If DO does not go high in 10 milliseconds, then error out. + */ + for (i = 0; i < 200; i++) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_DO) break; + usec_delay(50); + } + if (i == 200) { + DEBUGOUT("EEPROM Write did not complete\n"); + return -E1000_ERR_EEPROM; + } + + /* Recover from write */ + e1000_standby_eeprom(hw); + + words_written++; + } + + /* Send the write disable command to the EEPROM (3-bit opcode plus + * 6/8-bit dummy address beginning with 10). It's less work to include + * the 10 of the dummy address as part of the opcode than it is to shift + * it over the correct number of bits for the address. This takes the + * EEPROM out of write/erase mode. + */ + e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, + (uint16_t)(eeprom->opcode_bits + 2)); + + e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Flushes the cached eeprom to NVM. This is done by saving the modified values + * in the eeprom cache and the non modified values in the currently active bank + * to the new bank. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +STATIC int32_t +e1000_commit_shadow_ram(struct e1000_hw *hw) +{ + uint32_t attempts = 100000; + uint32_t eecd = 0; + uint32_t flop = 0; + uint32_t i = 0; + int32_t error = E1000_SUCCESS; + uint32_t old_bank_offset = 0; + uint32_t new_bank_offset = 0; + uint8_t low_byte = 0; + uint8_t high_byte = 0; + boolean_t sector_write_failed = FALSE; + + if (hw->mac_type == e1000_82573) { + /* The flop register will be used to determine if flash type is STM */ + flop = E1000_READ_REG(hw, FLOP); + for (i=0; i < attempts; i++) { + eecd = E1000_READ_REG(hw, EECD); + if ((eecd & E1000_EECD_FLUPD) == 0) { + break; + } + usec_delay(5); + } + + if (i == attempts) { + return -E1000_ERR_EEPROM; + } + + /* If STM opcode located in bits 15:8 of flop, reset firmware */ + if ((flop & 0xFF00) == E1000_STM_OPCODE) { + E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); + } + + /* Perform the flash update */ + E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); + + for (i=0; i < attempts; i++) { + eecd = E1000_READ_REG(hw, EECD); + if ((eecd & E1000_EECD_FLUPD) == 0) { + break; + } + usec_delay(5); + } + + if (i == attempts) { + return -E1000_ERR_EEPROM; + } + } + + if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { + /* We're writing to the opposite bank so if we're on bank 1, + * write to bank 0 etc. We also need to erase the segment that + * is going to be written */ + if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { + new_bank_offset = hw->flash_bank_size * 2; + old_bank_offset = 0; + e1000_erase_ich8_4k_segment(hw, 1); + } else { + old_bank_offset = hw->flash_bank_size * 2; + new_bank_offset = 0; + e1000_erase_ich8_4k_segment(hw, 0); + } + + sector_write_failed = FALSE; + /* Loop for every byte in the shadow RAM, + * which is in units of words. */ + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + /* Determine whether to write the value stored + * in the other NVM bank or a modified value stored + * in the shadow RAM */ + if (hw->eeprom_shadow_ram[i].modified == TRUE) { + low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; + usec_delay(100); + error = e1000_verify_write_ich8_byte(hw, + (i << 1) + new_bank_offset, low_byte); + + if (error != E1000_SUCCESS) + sector_write_failed = TRUE; + else { + high_byte = + (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); + usec_delay(100); + } + } else { + e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, + &low_byte); + usec_delay(100); + error = e1000_verify_write_ich8_byte(hw, + (i << 1) + new_bank_offset, low_byte); + + if (error != E1000_SUCCESS) + sector_write_failed = TRUE; + else { + e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, + &high_byte); + usec_delay(100); + } + } + + /* If the write of the low byte was successful, go ahread and + * write the high byte while checking to make sure that if it + * is the signature byte, then it is handled properly */ + if (sector_write_failed == FALSE) { + /* If the word is 0x13, then make sure the signature bits + * (15:14) are 11b until the commit has completed. + * This will allow us to write 10b which indicates the + * signature is valid. We want to do this after the write + * has completed so that we don't mark the segment valid + * while the write is still in progress */ + if (i == E1000_ICH_NVM_SIG_WORD) + high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; + + error = e1000_verify_write_ich8_byte(hw, + (i << 1) + new_bank_offset + 1, high_byte); + if (error != E1000_SUCCESS) + sector_write_failed = TRUE; + + } else { + /* If the write failed then break from the loop and + * return an error */ + break; + } + } + + /* Don't bother writing the segment valid bits if sector + * programming failed. */ + if (sector_write_failed == FALSE) { + /* Finally validate the new segment by setting bit 15:14 + * to 10b in word 0x13 , this can be done without an + * erase as well since these bits are 11 to start with + * and we need to change bit 14 to 0b */ + e1000_read_ich8_byte(hw, + E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, + &high_byte); + high_byte &= 0xBF; + error = e1000_verify_write_ich8_byte(hw, + E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); + /* And invalidate the previously valid segment by setting + * its signature word (0x13) high_byte to 0b. This can be + * done without an erase because flash erase sets all bits + * to 1's. We can write 1's to 0's without an erase */ + if (error == E1000_SUCCESS) { + error = e1000_verify_write_ich8_byte(hw, + E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); + } + + /* Clear the now not used entry in the cache */ + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; + } + } + } + + return error; +} + +/****************************************************************************** + * Reads the adapter's part number from the EEPROM + * + * hw - Struct containing variables accessed by shared code + * part_num - Adapter's part number + *****************************************************************************/ +int32_t +e1000_read_part_num(struct e1000_hw *hw, + uint32_t *part_num) +{ + uint16_t offset = EEPROM_PBA_BYTE_1; + uint16_t eeprom_data; + + DEBUGFUNC("e1000_read_part_num"); + + /* Get word 0 from EEPROM */ + if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + /* Save word 0 in upper half of part_num */ + *part_num = (uint32_t) (eeprom_data << 16); + + /* Get word 1 from EEPROM */ + if (e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + /* Save word 1 in lower half of part_num */ + *part_num |= eeprom_data; + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the + * second function of dual function devices + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_read_mac_addr(struct e1000_hw * hw) +{ + uint16_t offset; + uint16_t eeprom_data, i; + + DEBUGFUNC("e1000_read_mac_addr"); + + for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { + offset = i >> 1; + if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); + hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); + } + + switch (hw->mac_type) { + default: + break; + case e1000_82546: + case e1000_82546_rev_3: + case e1000_82571: + case e1000_80003es2lan: + if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + hw->perm_mac_addr[5] ^= 0x01; + break; + } + + for (i = 0; i < NODE_ADDRESS_SIZE; i++) + hw->mac_addr[i] = hw->perm_mac_addr[i]; + return E1000_SUCCESS; +} + +/****************************************************************************** + * Initializes receive address filters. + * + * hw - Struct containing variables accessed by shared code + * + * Places the MAC address in receive address register 0 and clears the rest + * of the receive addresss registers. Clears the multicast table. Assumes + * the receiver is in reset when the routine is called. + *****************************************************************************/ +STATIC void +e1000_init_rx_addrs(struct e1000_hw *hw) +{ + uint32_t i; + uint32_t rar_num; + + DEBUGFUNC("e1000_init_rx_addrs"); + + /* Setup the receive address. */ + DEBUGOUT("Programming MAC Address into RAR[0]\n"); + + e1000_rar_set(hw, hw->mac_addr, 0); + + rar_num = E1000_RAR_ENTRIES; + + /* Reserve a spot for the Locally Administered Address to work around + * an 82571 issue in which a reset on one port will reload the MAC on + * the other port. */ + if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) + rar_num -= 1; + if (hw->mac_type == e1000_ich8lan) + rar_num = E1000_RAR_ENTRIES_ICH8LAN; + + /* Zero out the other 15 receive addresses. */ + DEBUGOUT("Clearing RAR[1-15]\n"); + for (i = 1; i < rar_num; i++) { + E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); + E1000_WRITE_FLUSH(hw); + } +} + +/****************************************************************************** + * Updates the MAC's list of multicast addresses. + * + * hw - Struct containing variables accessed by shared code + * mc_addr_list - the list of new multicast addresses + * mc_addr_count - number of addresses + * pad - number of bytes between addresses in the list + * rar_used_count - offset where to start adding mc addresses into the RAR's + * + * The given list replaces any existing list. Clears the last 15 receive + * address registers and the multicast table. Uses receive address registers + * for the first 15 multicast addresses, and hashes the rest into the + * multicast table. + *****************************************************************************/ +void +e1000_mc_addr_list_update(struct e1000_hw *hw, + uint8_t *mc_addr_list, + uint32_t mc_addr_count, + uint32_t pad, + uint32_t rar_used_count) +{ + uint32_t hash_value; + uint32_t i; + uint32_t num_rar_entry; + uint32_t num_mta_entry; + + DEBUGFUNC("e1000_mc_addr_list_update"); + + /* Set the new number of MC addresses that we are being requested to use. */ + hw->num_mc_addrs = mc_addr_count; + + /* Clear RAR[1-15] */ + DEBUGOUT(" Clearing RAR[1-15]\n"); + num_rar_entry = E1000_RAR_ENTRIES; + if (hw->mac_type == e1000_ich8lan) + num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; + + /* Reserve a spot for the Locally Administered Address to work around + * an 82571 issue in which a reset on one port will reload the MAC on + * the other port. */ + if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) + num_rar_entry -= 1; + + for (i = rar_used_count; i < num_rar_entry; i++) { + E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); + E1000_WRITE_FLUSH(hw); + } + + /* Clear the MTA */ + DEBUGOUT(" Clearing MTA\n"); + num_mta_entry = E1000_NUM_MTA_REGISTERS; + if (hw->mac_type == e1000_ich8lan) + num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; + + for (i = 0; i < num_mta_entry; i++) { + E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); + E1000_WRITE_FLUSH(hw); + } + + /* Add the new addresses */ + for (i = 0; i < mc_addr_count; i++) { + DEBUGOUT(" Adding the multicast addresses:\n"); + DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], + mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); + + hash_value = e1000_hash_mc_addr(hw, + mc_addr_list + + (i * (ETH_LENGTH_OF_ADDRESS + pad))); + + DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); + + /* Place this multicast address in the RAR if there is room, * + * else put it in the MTA + */ + if (rar_used_count < num_rar_entry) { + e1000_rar_set(hw, + mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), + rar_used_count); + rar_used_count++; + } else { + e1000_mta_set(hw, hash_value); + } + } + DEBUGOUT("MC Update Complete\n"); +} + +/****************************************************************************** + * Hashes an address to determine its location in the multicast table + * + * hw - Struct containing variables accessed by shared code + * mc_addr - the multicast address to hash + *****************************************************************************/ +uint32_t +e1000_hash_mc_addr(struct e1000_hw *hw, + uint8_t *mc_addr) +{ + uint32_t hash_value = 0; + + /* The portion of the address that is used for the hash table is + * determined by the mc_filter_type setting. + */ + switch (hw->mc_filter_type) { + /* [0] [1] [2] [3] [4] [5] + * 01 AA 00 12 34 56 + * LSB MSB + */ + case 0: + if (hw->mac_type == e1000_ich8lan) { + /* [47:38] i.e. 0x158 for above example address */ + hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); + } else { + /* [47:36] i.e. 0x563 for above example address */ + hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); + } + break; + case 1: + if (hw->mac_type == e1000_ich8lan) { + /* [46:37] i.e. 0x2B1 for above example address */ + hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); + } else { + /* [46:35] i.e. 0xAC6 for above example address */ + hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); + } + break; + case 2: + if (hw->mac_type == e1000_ich8lan) { + /*[45:36] i.e. 0x163 for above example address */ + hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); + } else { + /* [45:34] i.e. 0x5D8 for above example address */ + hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); + } + break; + case 3: + if (hw->mac_type == e1000_ich8lan) { + /* [43:34] i.e. 0x18D for above example address */ + hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); + } else { + /* [43:32] i.e. 0x634 for above example address */ + hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); + } + break; + } + + hash_value &= 0xFFF; + if (hw->mac_type == e1000_ich8lan) + hash_value &= 0x3FF; + + return hash_value; +} + +/****************************************************************************** + * Sets the bit in the multicast table corresponding to the hash value. + * + * hw - Struct containing variables accessed by shared code + * hash_value - Multicast address hash value + *****************************************************************************/ +void +e1000_mta_set(struct e1000_hw *hw, + uint32_t hash_value) +{ + uint32_t hash_bit, hash_reg; + uint32_t mta; + uint32_t temp; + + /* The MTA is a register array of 128 32-bit registers. + * It is treated like an array of 4096 bits. We want to set + * bit BitArray[hash_value]. So we figure out what register + * the bit is in, read it, OR in the new bit, then write + * back the new value. The register is determined by the + * upper 7 bits of the hash value and the bit within that + * register are determined by the lower 5 bits of the value. + */ + hash_reg = (hash_value >> 5) & 0x7F; + if (hw->mac_type == e1000_ich8lan) + hash_reg &= 0x1F; + + hash_bit = hash_value & 0x1F; + + mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); + + mta |= (1 << hash_bit); + + /* If we are on an 82544 and we are trying to write an odd offset + * in the MTA, save off the previous entry before writing and + * restore the old value after writing. + */ + if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { + temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); + E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); + E1000_WRITE_FLUSH(hw); + } else { + E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); + E1000_WRITE_FLUSH(hw); + } +} + +/****************************************************************************** + * Puts an ethernet address into a receive address register. + * + * hw - Struct containing variables accessed by shared code + * addr - Address to put into receive address register + * index - Receive address register to write + *****************************************************************************/ +void +e1000_rar_set(struct e1000_hw *hw, + uint8_t *addr, + uint32_t index) +{ + uint32_t rar_low, rar_high; + + /* HW expects these in little endian so we reverse the byte order + * from network order (big endian) to little endian + */ + rar_low = ((uint32_t) addr[0] | + ((uint32_t) addr[1] << 8) | + ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); + rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); + + /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx + * unit hang. + * + * Description: + * If there are any Rx frames queued up or otherwise present in the HW + * before RSS is enabled, and then we enable RSS, the HW Rx unit will + * hang. To work around this issue, we have to disable receives and + * flush out all Rx frames before we enable RSS. To do so, we modify we + * redirect all Rx traffic to manageability and then reset the HW. + * This flushes away Rx frames, and (since the redirections to + * manageability persists across resets) keeps new ones from coming in + * while we work. Then, we clear the Address Valid AV bit for all MAC + * addresses and undo the re-direction to manageability. + * Now, frames are coming in again, but the MAC won't accept them, so + * far so good. We now proceed to initialize RSS (if necessary) and + * configure the Rx unit. Last, we re-enable the AV bits and continue + * on our merry way. + */ + switch (hw->mac_type) { + case e1000_82571: + case e1000_82572: + case e1000_80003es2lan: + if (hw->leave_av_bit_off == TRUE) + break; + default: + /* Indicate to hardware the Address is Valid. */ + rar_high |= E1000_RAH_AV; + break; + } + + E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); + E1000_WRITE_FLUSH(hw); +} + +/****************************************************************************** + * Writes a value to the specified offset in the VLAN filter table. + * + * hw - Struct containing variables accessed by shared code + * offset - Offset in VLAN filer table to write + * value - Value to write into VLAN filter table + *****************************************************************************/ +void +e1000_write_vfta(struct e1000_hw *hw, + uint32_t offset, + uint32_t value) +{ + uint32_t temp; + + if (hw->mac_type == e1000_ich8lan) + return; + + if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { + temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); + E1000_WRITE_FLUSH(hw); + } else { + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); + E1000_WRITE_FLUSH(hw); + } +} + +/****************************************************************************** + * Clears the VLAN filer table + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +STATIC void +e1000_clear_vfta(struct e1000_hw *hw) +{ + uint32_t offset; + uint32_t vfta_value = 0; + uint32_t vfta_offset = 0; + uint32_t vfta_bit_in_reg = 0; + + if (hw->mac_type == e1000_ich8lan) + return; + + if (hw->mac_type == e1000_82573) { + if (hw->mng_cookie.vlan_id != 0) { + /* The VFTA is a 4096b bit-field, each identifying a single VLAN + * ID. The following operations determine which 32b entry + * (i.e. offset) into the array we want to set the VLAN ID + * (i.e. bit) of the manageability unit. */ + vfta_offset = (hw->mng_cookie.vlan_id >> + E1000_VFTA_ENTRY_SHIFT) & + E1000_VFTA_ENTRY_MASK; + vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & + E1000_VFTA_ENTRY_BIT_SHIFT_MASK); + } + } + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { + /* If the offset we want to clear is the same offset of the + * manageability VLAN ID, then clear all bits except that of the + * manageability unit */ + vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); + E1000_WRITE_FLUSH(hw); + } +} + +STATIC int32_t +e1000_id_led_init(struct e1000_hw * hw) +{ + uint32_t ledctl; + const uint32_t ledctl_mask = 0x000000FF; + const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; + const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; + uint16_t eeprom_data, i, temp; + const uint16_t led_mask = 0x0F; + + DEBUGFUNC("e1000_id_led_init"); + + if (hw->mac_type < e1000_82540) { + /* Nothing to do */ + return E1000_SUCCESS; + } + + ledctl = E1000_READ_REG(hw, LEDCTL); + hw->ledctl_default = ledctl; + hw->ledctl_mode1 = hw->ledctl_default; + hw->ledctl_mode2 = hw->ledctl_default; + + if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + + if ((hw->mac_type == e1000_82573) && + (eeprom_data == ID_LED_RESERVED_82573)) + eeprom_data = ID_LED_DEFAULT_82573; + else if ((eeprom_data == ID_LED_RESERVED_0000) || + (eeprom_data == ID_LED_RESERVED_FFFF)) { + if (hw->mac_type == e1000_ich8lan) + eeprom_data = ID_LED_DEFAULT_ICH8LAN; + else + eeprom_data = ID_LED_DEFAULT; + } + + for (i = 0; i < 4; i++) { + temp = (eeprom_data >> (i << 2)) & led_mask; + switch (temp) { + case ID_LED_ON1_DEF2: + case ID_LED_ON1_ON2: + case ID_LED_ON1_OFF2: + hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); + hw->ledctl_mode1 |= ledctl_on << (i << 3); + break; + case ID_LED_OFF1_DEF2: + case ID_LED_OFF1_ON2: + case ID_LED_OFF1_OFF2: + hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); + hw->ledctl_mode1 |= ledctl_off << (i << 3); + break; + default: + /* Do nothing */ + break; + } + switch (temp) { + case ID_LED_DEF1_ON2: + case ID_LED_ON1_ON2: + case ID_LED_OFF1_ON2: + hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); + hw->ledctl_mode2 |= ledctl_on << (i << 3); + break; + case ID_LED_DEF1_OFF2: + case ID_LED_ON1_OFF2: + case ID_LED_OFF1_OFF2: + hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); + hw->ledctl_mode2 |= ledctl_off << (i << 3); + break; + default: + /* Do nothing */ + break; + } + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Prepares SW controlable LED for use and saves the current state of the LED. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_setup_led(struct e1000_hw *hw) +{ + uint32_t ledctl; + int32_t ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_led"); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + case e1000_82544: + /* No setup necessary */ + break; + case e1000_82541: + case e1000_82547: + case e1000_82541_rev_2: + case e1000_82547_rev_2: + /* Turn off PHY Smart Power Down (if enabled) */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, + &hw->phy_spd_default); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, + (uint16_t)(hw->phy_spd_default & + ~IGP01E1000_GMII_SPD)); + if (ret_val) + return ret_val; + /* Fall Through */ + default: + if (hw->media_type == e1000_media_type_fiber) { + ledctl = E1000_READ_REG(hw, LEDCTL); + /* Save current LEDCTL settings */ + hw->ledctl_default = ledctl; + /* Turn off LED0 */ + ledctl &= ~(E1000_LEDCTL_LED0_IVRT | + E1000_LEDCTL_LED0_BLINK | + E1000_LEDCTL_LED0_MODE_MASK); + ledctl |= (E1000_LEDCTL_MODE_LED_OFF << + E1000_LEDCTL_LED0_MODE_SHIFT); + E1000_WRITE_REG(hw, LEDCTL, ledctl); + } else if (hw->media_type == e1000_media_type_copper) + E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); + break; + } + + return E1000_SUCCESS; +} + + +/****************************************************************************** + * Used on 82571 and later Si that has LED blink bits. + * Callers must use their own timer and should have already called + * e1000_id_led_init() + * Call e1000_cleanup led() to stop blinking + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_blink_led_start(struct e1000_hw *hw) +{ + int16_t i; + uint32_t ledctl_blink = 0; + + DEBUGFUNC("e1000_id_led_blink_on"); + + if (hw->mac_type < e1000_82571) { + /* Nothing to do */ + return E1000_SUCCESS; + } + if (hw->media_type == e1000_media_type_fiber) { + /* always blink LED0 for PCI-E fiber */ + ledctl_blink = E1000_LEDCTL_LED0_BLINK | + (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); + } else { + /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ + ledctl_blink = hw->ledctl_mode2; + for (i=0; i < 4; i++) + if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == + E1000_LEDCTL_MODE_LED_ON) + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); + } + + E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Restores the saved state of the SW controlable LED. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_cleanup_led(struct e1000_hw *hw) +{ + int32_t ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_cleanup_led"); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + case e1000_82544: + /* No cleanup necessary */ + break; + case e1000_82541: + case e1000_82547: + case e1000_82541_rev_2: + case e1000_82547_rev_2: + /* Turn on PHY Smart Power Down (if previously enabled) */ + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, + hw->phy_spd_default); + if (ret_val) + return ret_val; + /* Fall Through */ + default: + if (hw->phy_type == e1000_phy_ife) { + e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); + break; + } + /* Restore LEDCTL settings */ + E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); + break; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Turns on the software controllable LED + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_led_on(struct e1000_hw *hw) +{ + uint32_t ctrl = E1000_READ_REG(hw, CTRL); + + DEBUGFUNC("e1000_led_on"); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + /* Set SW Defineable Pin 0 to turn on the LED */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + break; + case e1000_82544: + if (hw->media_type == e1000_media_type_fiber) { + /* Set SW Defineable Pin 0 to turn on the LED */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else { + /* Clear SW Defineable Pin 0 to turn on the LED */ + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } + break; + default: + if (hw->media_type == e1000_media_type_fiber) { + /* Clear SW Defineable Pin 0 to turn on the LED */ + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else if (hw->phy_type == e1000_phy_ife) { + e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); + } else if (hw->media_type == e1000_media_type_copper) { + E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); + return E1000_SUCCESS; + } + break; + } + + E1000_WRITE_REG(hw, CTRL, ctrl); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Turns off the software controllable LED + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_led_off(struct e1000_hw *hw) +{ + uint32_t ctrl = E1000_READ_REG(hw, CTRL); + + DEBUGFUNC("e1000_led_off"); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + /* Clear SW Defineable Pin 0 to turn off the LED */ + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + break; + case e1000_82544: + if (hw->media_type == e1000_media_type_fiber) { + /* Clear SW Defineable Pin 0 to turn off the LED */ + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else { + /* Set SW Defineable Pin 0 to turn off the LED */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } + break; + default: + if (hw->media_type == e1000_media_type_fiber) { + /* Set SW Defineable Pin 0 to turn off the LED */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else if (hw->phy_type == e1000_phy_ife) { + e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); + } else if (hw->media_type == e1000_media_type_copper) { + E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); + return E1000_SUCCESS; + } + break; + } + + E1000_WRITE_REG(hw, CTRL, ctrl); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Clears all hardware statistics counters. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void +e1000_clear_hw_cntrs(struct e1000_hw *hw) +{ + volatile uint32_t temp; + + temp = E1000_READ_REG(hw, CRCERRS); + temp = E1000_READ_REG(hw, SYMERRS); + temp = E1000_READ_REG(hw, MPC); + temp = E1000_READ_REG(hw, SCC); + temp = E1000_READ_REG(hw, ECOL); + temp = E1000_READ_REG(hw, MCC); + temp = E1000_READ_REG(hw, LATECOL); + temp = E1000_READ_REG(hw, COLC); + temp = E1000_READ_REG(hw, DC); + temp = E1000_READ_REG(hw, SEC); + temp = E1000_READ_REG(hw, RLEC); + temp = E1000_READ_REG(hw, XONRXC); + temp = E1000_READ_REG(hw, XONTXC); + temp = E1000_READ_REG(hw, XOFFRXC); + temp = E1000_READ_REG(hw, XOFFTXC); + temp = E1000_READ_REG(hw, FCRUC); + + if (hw->mac_type != e1000_ich8lan) { + temp = E1000_READ_REG(hw, PRC64); + temp = E1000_READ_REG(hw, PRC127); + temp = E1000_READ_REG(hw, PRC255); + temp = E1000_READ_REG(hw, PRC511); + temp = E1000_READ_REG(hw, PRC1023); + temp = E1000_READ_REG(hw, PRC1522); + } + + temp = E1000_READ_REG(hw, GPRC); + temp = E1000_READ_REG(hw, BPRC); + temp = E1000_READ_REG(hw, MPRC); + temp = E1000_READ_REG(hw, GPTC); + temp = E1000_READ_REG(hw, GORCL); + temp = E1000_READ_REG(hw, GORCH); + temp = E1000_READ_REG(hw, GOTCL); + temp = E1000_READ_REG(hw, GOTCH); + temp = E1000_READ_REG(hw, RNBC); + temp = E1000_READ_REG(hw, RUC); + temp = E1000_READ_REG(hw, RFC); + temp = E1000_READ_REG(hw, ROC); + temp = E1000_READ_REG(hw, RJC); + temp = E1000_READ_REG(hw, TORL); + temp = E1000_READ_REG(hw, TORH); + temp = E1000_READ_REG(hw, TOTL); + temp = E1000_READ_REG(hw, TOTH); + temp = E1000_READ_REG(hw, TPR); + temp = E1000_READ_REG(hw, TPT); + + if (hw->mac_type != e1000_ich8lan) { + temp = E1000_READ_REG(hw, PTC64); + temp = E1000_READ_REG(hw, PTC127); + temp = E1000_READ_REG(hw, PTC255); + temp = E1000_READ_REG(hw, PTC511); + temp = E1000_READ_REG(hw, PTC1023); + temp = E1000_READ_REG(hw, PTC1522); + } + + temp = E1000_READ_REG(hw, MPTC); + temp = E1000_READ_REG(hw, BPTC); + + if (hw->mac_type < e1000_82543) return; + + temp = E1000_READ_REG(hw, ALGNERRC); + temp = E1000_READ_REG(hw, RXERRC); + temp = E1000_READ_REG(hw, TNCRS); + temp = E1000_READ_REG(hw, CEXTERR); + temp = E1000_READ_REG(hw, TSCTC); + temp = E1000_READ_REG(hw, TSCTFC); + + if (hw->mac_type <= e1000_82544) return; + + temp = E1000_READ_REG(hw, MGTPRC); + temp = E1000_READ_REG(hw, MGTPDC); + temp = E1000_READ_REG(hw, MGTPTC); + + if (hw->mac_type <= e1000_82547_rev_2) return; + + temp = E1000_READ_REG(hw, IAC); + temp = E1000_READ_REG(hw, ICRXOC); + + if (hw->mac_type == e1000_ich8lan) return; + + temp = E1000_READ_REG(hw, ICRXPTC); + temp = E1000_READ_REG(hw, ICRXATC); + temp = E1000_READ_REG(hw, ICTXPTC); + temp = E1000_READ_REG(hw, ICTXATC); + temp = E1000_READ_REG(hw, ICTXQEC); + temp = E1000_READ_REG(hw, ICTXQMTC); + temp = E1000_READ_REG(hw, ICRXDMTC); + +} + +/****************************************************************************** + * Resets Adaptive IFS to its default state. + * + * hw - Struct containing variables accessed by shared code + * + * Call this after e1000_init_hw. You may override the IFS defaults by setting + * hw->ifs_params_forced to TRUE. However, you must initialize hw-> + * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio + * before calling this function. + *****************************************************************************/ +void +e1000_reset_adaptive(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_reset_adaptive"); + + if (hw->adaptive_ifs) { + if (!hw->ifs_params_forced) { + hw->current_ifs_val = 0; + hw->ifs_min_val = IFS_MIN; + hw->ifs_max_val = IFS_MAX; + hw->ifs_step_size = IFS_STEP; + hw->ifs_ratio = IFS_RATIO; + } + hw->in_ifs_mode = FALSE; + E1000_WRITE_REG(hw, AIT, 0); + } else { + DEBUGOUT("Not in Adaptive IFS mode!\n"); + } +} + +/****************************************************************************** + * Called during the callback/watchdog routine to update IFS value based on + * the ratio of transmits to collisions. + * + * hw - Struct containing variables accessed by shared code + * tx_packets - Number of transmits since last callback + * total_collisions - Number of collisions since last callback + *****************************************************************************/ +void +e1000_update_adaptive(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_update_adaptive"); + + if (hw->adaptive_ifs) { + if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { + if (hw->tx_packet_delta > MIN_NUM_XMITS) { + hw->in_ifs_mode = TRUE; + if (hw->current_ifs_val < hw->ifs_max_val) { + if (hw->current_ifs_val == 0) + hw->current_ifs_val = hw->ifs_min_val; + else + hw->current_ifs_val += hw->ifs_step_size; + E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); + } + } + } else { + if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { + hw->current_ifs_val = 0; + hw->in_ifs_mode = FALSE; + E1000_WRITE_REG(hw, AIT, 0); + } + } + } else { + DEBUGOUT("Not in Adaptive IFS mode!\n"); + } +} + +/****************************************************************************** + * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT + * + * hw - Struct containing variables accessed by shared code + * frame_len - The length of the frame in question + * mac_addr - The Ethernet destination address of the frame in question + *****************************************************************************/ +void +e1000_tbi_adjust_stats(struct e1000_hw *hw, + struct e1000_hw_stats *stats, + uint32_t frame_len, + uint8_t *mac_addr) +{ + uint64_t carry_bit; + + /* First adjust the frame length. */ + frame_len--; + /* We need to adjust the statistics counters, since the hardware + * counters overcount this packet as a CRC error and undercount + * the packet as a good packet + */ + /* This packet should not be counted as a CRC error. */ + stats->crcerrs--; + /* This packet does count as a Good Packet Received. */ + stats->gprc++; + + /* Adjust the Good Octets received counters */ + carry_bit = 0x80000000 & stats->gorcl; + stats->gorcl += frame_len; + /* If the high bit of Gorcl (the low 32 bits of the Good Octets + * Received Count) was one before the addition, + * AND it is zero after, then we lost the carry out, + * need to add one to Gorch (Good Octets Received Count High). + * This could be simplified if all environments supported + * 64-bit integers. + */ + if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) + stats->gorch++; + /* Is this a broadcast or multicast? Check broadcast first, + * since the test for a multicast frame will test positive on + * a broadcast frame. + */ + if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) + /* Broadcast packet */ + stats->bprc++; + else if (*mac_addr & 0x01) + /* Multicast packet */ + stats->mprc++; + + if (frame_len == hw->max_frame_size) { + /* In this case, the hardware has overcounted the number of + * oversize frames. + */ + if (stats->roc > 0) + stats->roc--; + } + + /* Adjust the bin counters when the extra byte put the frame in the + * wrong bin. Remember that the frame_len was adjusted above. + */ + if (frame_len == 64) { + stats->prc64++; + stats->prc127--; + } else if (frame_len == 127) { + stats->prc127++; + stats->prc255--; + } else if (frame_len == 255) { + stats->prc255++; + stats->prc511--; + } else if (frame_len == 511) { + stats->prc511++; + stats->prc1023--; + } else if (frame_len == 1023) { + stats->prc1023++; + stats->prc1522--; + } else if (frame_len == 1522) { + stats->prc1522++; + } +} + +/****************************************************************************** + * Gets the current PCI bus type, speed, and width of the hardware + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void +e1000_get_bus_info(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t pci_ex_link_status; + uint32_t status; + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + hw->bus_type = e1000_bus_type_unknown; + hw->bus_speed = e1000_bus_speed_unknown; + hw->bus_width = e1000_bus_width_unknown; + break; + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_80003es2lan: + hw->bus_type = e1000_bus_type_pci_express; + hw->bus_speed = e1000_bus_speed_2500; + ret_val = e1000_read_pcie_cap_reg(hw, + PCI_EX_LINK_STATUS, + &pci_ex_link_status); + if (ret_val) + hw->bus_width = e1000_bus_width_unknown; + else + hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> + PCI_EX_LINK_WIDTH_SHIFT; + break; + case e1000_ich8lan: + hw->bus_type = e1000_bus_type_pci_express; + hw->bus_speed = e1000_bus_speed_2500; + hw->bus_width = e1000_bus_width_pciex_1; + break; + default: + status = E1000_READ_REG(hw, STATUS); + hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? + e1000_bus_type_pcix : e1000_bus_type_pci; + + if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { + hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? + e1000_bus_speed_66 : e1000_bus_speed_120; + } else if (hw->bus_type == e1000_bus_type_pci) { + hw->bus_speed = (status & E1000_STATUS_PCI66) ? + e1000_bus_speed_66 : e1000_bus_speed_33; + } else { + switch (status & E1000_STATUS_PCIX_SPEED) { + case E1000_STATUS_PCIX_SPEED_66: + hw->bus_speed = e1000_bus_speed_66; + break; + case E1000_STATUS_PCIX_SPEED_100: + hw->bus_speed = e1000_bus_speed_100; + break; + case E1000_STATUS_PCIX_SPEED_133: + hw->bus_speed = e1000_bus_speed_133; + break; + default: + hw->bus_speed = e1000_bus_speed_reserved; + break; + } + } + hw->bus_width = (status & E1000_STATUS_BUS64) ? + e1000_bus_width_64 : e1000_bus_width_32; + break; + } +} + +#ifndef __sparc +/****************************************************************************** + * Writes a value to one of the devices registers using port I/O (as opposed to + * memory mapped I/O). Only 82544 and newer devices support port I/O. + * + * hw - Struct containing variables accessed by shared code + * offset - offset to write to + * value - value to write + *****************************************************************************/ +STATIC void +e1000_write_reg_io(struct e1000_hw *hw, + uint32_t offset, + uint32_t value) +{ + unsigned long io_addr = hw->io_base; + unsigned long io_data = hw->io_base + 4; + + e1000_io_write(hw, io_addr, offset); + e1000_io_write(hw, io_data, value); +} +#endif + +/****************************************************************************** + * Estimates the cable length. + * + * hw - Struct containing variables accessed by shared code + * min_length - The estimated minimum length + * max_length - The estimated maximum length + * + * returns: - E1000_ERR_XXX + * E1000_SUCCESS + * + * This function always returns a ranged length (minimum & maximum). + * So for M88 phy's, this function interprets the one value returned from the + * register to the minimum and maximum range. + * For IGP phy's, the function calculates the range by the AGC registers. + *****************************************************************************/ +STATIC int32_t +e1000_get_cable_length(struct e1000_hw *hw, + uint16_t *min_length, + uint16_t *max_length) +{ + int32_t ret_val; + uint16_t agc_value = 0; + uint16_t i, phy_data; + uint16_t cable_length; + + DEBUGFUNC("e1000_get_cable_length"); + + *min_length = *max_length = 0; + + /* Use old method for Phy older than IGP */ + if (hw->phy_type == e1000_phy_m88) { + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, + &phy_data); + if (ret_val) + return ret_val; + cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> + M88E1000_PSSR_CABLE_LENGTH_SHIFT; + + /* Convert the enum value to ranged values */ + switch (cable_length) { + case e1000_cable_length_50: + *min_length = 0; + *max_length = e1000_igp_cable_length_50; + break; + case e1000_cable_length_50_80: + *min_length = e1000_igp_cable_length_50; + *max_length = e1000_igp_cable_length_80; + break; + case e1000_cable_length_80_110: + *min_length = e1000_igp_cable_length_80; + *max_length = e1000_igp_cable_length_110; + break; + case e1000_cable_length_110_140: + *min_length = e1000_igp_cable_length_110; + *max_length = e1000_igp_cable_length_140; + break; + case e1000_cable_length_140: + *min_length = e1000_igp_cable_length_140; + *max_length = e1000_igp_cable_length_170; + break; + default: + return -E1000_ERR_PHY; + } + } else if (hw->phy_type == e1000_phy_gg82563) { + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, + &phy_data); + if (ret_val) + return ret_val; + cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; + + switch (cable_length) { + case e1000_gg_cable_length_60: + *min_length = 0; + *max_length = e1000_igp_cable_length_60; + break; + case e1000_gg_cable_length_60_115: + *min_length = e1000_igp_cable_length_60; + *max_length = e1000_igp_cable_length_115; + break; + case e1000_gg_cable_length_115_150: + *min_length = e1000_igp_cable_length_115; + *max_length = e1000_igp_cable_length_150; + break; + case e1000_gg_cable_length_150: + *min_length = e1000_igp_cable_length_150; + *max_length = e1000_igp_cable_length_180; + break; + default: + return -E1000_ERR_PHY; + } + } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ + uint16_t cur_agc_value; + uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; + uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + {IGP01E1000_PHY_AGC_A, + IGP01E1000_PHY_AGC_B, + IGP01E1000_PHY_AGC_C, + IGP01E1000_PHY_AGC_D}; + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + + ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); + if (ret_val) + return ret_val; + + cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; + + /* Value bound check. */ + if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || + (cur_agc_value == 0)) + return -E1000_ERR_PHY; + + agc_value += cur_agc_value; + + /* Update minimal AGC value. */ + if (min_agc_value > cur_agc_value) + min_agc_value = cur_agc_value; + } + + /* Remove the minimal AGC result for length < 50m */ + if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { + agc_value -= min_agc_value; + + /* Get the average length of the remaining 3 channels */ + agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); + } else { + /* Get the average length of all the 4 channels. */ + agc_value /= IGP01E1000_PHY_CHANNEL_NUM; + } + + /* Set the range of the calculated length. */ + *min_length = ((e1000_igp_cable_length_table[agc_value] - + IGP01E1000_AGC_RANGE) > 0) ? + (e1000_igp_cable_length_table[agc_value] - + IGP01E1000_AGC_RANGE) : 0; + *max_length = e1000_igp_cable_length_table[agc_value] + + IGP01E1000_AGC_RANGE; + } else if (hw->phy_type == e1000_phy_igp_2 || + hw->phy_type == e1000_phy_igp_3) { + uint16_t cur_agc_index, max_agc_index = 0; + uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; + uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = + {IGP02E1000_PHY_AGC_A, + IGP02E1000_PHY_AGC_B, + IGP02E1000_PHY_AGC_C, + IGP02E1000_PHY_AGC_D}; + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); + if (ret_val) + return ret_val; + + /* Getting bits 15:9, which represent the combination of course and + * fine gain values. The result is a number that can be put into + * the lookup table to obtain the approximate cable length. */ + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & + IGP02E1000_AGC_LENGTH_MASK; + + /* Array index bound check. */ + if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || + (cur_agc_index == 0)) + return -E1000_ERR_PHY; + + /* Remove min & max AGC values from calculation. */ + if (e1000_igp_2_cable_length_table[min_agc_index] > + e1000_igp_2_cable_length_table[cur_agc_index]) + min_agc_index = cur_agc_index; + if (e1000_igp_2_cable_length_table[max_agc_index] < + e1000_igp_2_cable_length_table[cur_agc_index]) + max_agc_index = cur_agc_index; + + agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; + } + + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + + e1000_igp_2_cable_length_table[max_agc_index]); + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); + + /* Calculate cable length with the error range of +/- 10 meters. */ + *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? + (agc_value - IGP02E1000_AGC_RANGE) : 0; + *max_length = agc_value + IGP02E1000_AGC_RANGE; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Check the cable polarity + * + * hw - Struct containing variables accessed by shared code + * polarity - output parameter : 0 - Polarity is not reversed + * 1 - Polarity is reversed. + * + * returns: - E1000_ERR_XXX + * E1000_SUCCESS + * + * For phy's older then IGP, this function simply reads the polarity bit in the + * Phy Status register. For IGP phy's, this bit is valid only if link speed is + * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will + * return 0. If the link speed is 1000 Mbps the polarity status is in the + * IGP01E1000_PHY_PCS_INIT_REG. + *****************************************************************************/ +STATIC int32_t +e1000_check_polarity(struct e1000_hw *hw, + e1000_rev_polarity *polarity) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_check_polarity"); + + if ((hw->phy_type == e1000_phy_m88) || + (hw->phy_type == e1000_phy_gg82563)) { + /* return the Polarity bit in the Status register. */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, + &phy_data); + if (ret_val) + return ret_val; + *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> + M88E1000_PSSR_REV_POLARITY_SHIFT) ? + e1000_rev_polarity_reversed : e1000_rev_polarity_normal; + + } else if (hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) { + /* Read the Status register to check the speed */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, + &phy_data); + if (ret_val) + return ret_val; + + /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to + * find the polarity status */ + if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == + IGP01E1000_PSSR_SPEED_1000MBPS) { + + /* Read the GIG initialization PCS register (0x00B4) */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, + &phy_data); + if (ret_val) + return ret_val; + + /* Check the polarity bits */ + *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? + e1000_rev_polarity_reversed : e1000_rev_polarity_normal; + } else { + /* For 10 Mbps, read the polarity bit in the status register. (for + * 100 Mbps this bit is always 0) */ + *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? + e1000_rev_polarity_reversed : e1000_rev_polarity_normal; + } + } else if (hw->phy_type == e1000_phy_ife) { + ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, + &phy_data); + if (ret_val) + return ret_val; + *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> + IFE_PESC_POLARITY_REVERSED_SHIFT) ? + e1000_rev_polarity_reversed : e1000_rev_polarity_normal; + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Check if Downshift occured + * + * hw - Struct containing variables accessed by shared code + * downshift - output parameter : 0 - No Downshift ocured. + * 1 - Downshift ocured. + * + * returns: - E1000_ERR_XXX + * E1000_SUCCESS + * + * For phy's older then IGP, this function reads the Downshift bit in the Phy + * Specific Status register. For IGP phy's, it reads the Downgrade bit in the + * Link Health register. In IGP this bit is latched high, so the driver must + * read it immediately after link is established. + *****************************************************************************/ +STATIC int32_t +e1000_check_downshift(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC("e1000_check_downshift"); + + if (hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, + &phy_data); + if (ret_val) + return ret_val; + + hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; + } else if ((hw->phy_type == e1000_phy_m88) || + (hw->phy_type == e1000_phy_gg82563)) { + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, + &phy_data); + if (ret_val) + return ret_val; + + hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> + M88E1000_PSSR_DOWNSHIFT_SHIFT; + } else if (hw->phy_type == e1000_phy_ife) { + /* e1000_phy_ife supports 10/100 speed only */ + hw->speed_downgraded = FALSE; + } + + return E1000_SUCCESS; +} + +#ifndef FIFO_WORKAROUND +/***************************************************************************** + * + * Workaround for the Tanacross TX fifo failure. + * + * hw - Struct containing variables accessed by shared code + * length - Length of next outgoing frame + * + * + * returns: - E1000_ERR_FIFO_WRAP if the next packet cannot be transmitted yet + * E1000_SUCCESS if the next packet can be transmitted + * + *****************************************************************************/ +int32_t +e1000_82547_fifo_workaround(struct e1000_hw *hw, + uint16_t length) +{ + uint32_t tctl; + uint16_t fifo_space, fifo_pkt_len; + + /* get the length as seen by the FIFO of the next real packet to + * be transmitted + */ + fifo_pkt_len = E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, + E1000_FIFO_GRANULARITY); + + if (fifo_pkt_len > E1000_82547_FIFO_PAD + E1000_FIFO_HDR_SIZE) { + fifo_space = hw->tx_fifo_size - hw->tx_fifo_head; + + if ((hw->tx_fifo_head + fifo_pkt_len) >= + (hw->tx_fifo_size + E1000_82547_FIFO_PAD)) { + if (E1000_READ_REG(hw, TDT) != E1000_READ_REG(hw, TDH)) + return -E1000_ERR_FIFO_WRAP; + + if (E1000_READ_REG(hw, TDFT) != E1000_READ_REG(hw, TDFH)) + return -E1000_ERR_FIFO_WRAP; + + if (E1000_READ_REG(hw, TDFTS) != E1000_READ_REG(hw, TDFHS)) + return -E1000_ERR_FIFO_WRAP; + + /* Disable the tx unit to avoid further pointer movement */ + tctl = E1000_READ_REG(hw, TCTL); + E1000_WRITE_REG(hw, TCTL, tctl & ~E1000_TCTL_EN); + + /* Reset the fifo pointers. */ + E1000_WRITE_REG(hw, TDFT, hw->tx_fifo_start); + E1000_WRITE_REG(hw, TDFH, hw->tx_fifo_start); + E1000_WRITE_REG(hw, TDFTS, hw->tx_fifo_start); + E1000_WRITE_REG(hw, TDFHS, hw->tx_fifo_start); + + /* Re-enabling tx unit */ + E1000_WRITE_REG(hw, TCTL, tctl); + E1000_WRITE_FLUSH(hw); + + hw->tx_fifo_head = 0; + + } + } + return E1000_SUCCESS; +} + +/***************************************************************************** + * + * Updates the SW calculated TX FIFO head pointer. + * + * hw - Struct containing variables accessed by shared code + * length - Length of next outgoing frame + ****************************************************************************/ +void +e1000_update_tx_fifo_head(struct e1000_hw *hw, + uint32_t length) +{ + hw->tx_fifo_head += E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, + E1000_FIFO_GRANULARITY); + + if (hw->tx_fifo_head > hw->tx_fifo_size) + hw->tx_fifo_head -= hw->tx_fifo_size; + + return; +} + +#endif /* FIFO_WORKAROUND */ +/***************************************************************************** + * + * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a + * gigabit link is achieved to improve link quality. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS at any other case. + * + ****************************************************************************/ + +STATIC int32_t +e1000_config_dsp_after_link_change(struct e1000_hw *hw, + boolean_t link_up) +{ + int32_t ret_val; + uint16_t phy_data, phy_saved_data, speed, duplex, i; + uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + {IGP01E1000_PHY_AGC_PARAM_A, + IGP01E1000_PHY_AGC_PARAM_B, + IGP01E1000_PHY_AGC_PARAM_C, + IGP01E1000_PHY_AGC_PARAM_D}; + uint16_t min_length, max_length; + + DEBUGFUNC("e1000_config_dsp_after_link_change"); + + if (hw->phy_type != e1000_phy_igp) + return E1000_SUCCESS; + + if (link_up) { + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + return ret_val; + } + + if (speed == SPEED_1000) { + + ret_val = e1000_get_cable_length(hw, &min_length, &max_length); + if (ret_val) + return ret_val; + + if ((hw->dsp_config_state == e1000_dsp_config_enabled) && + min_length >= e1000_igp_cable_length_50) { + + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], + &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; + + ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], + phy_data); + if (ret_val) + return ret_val; + } + hw->dsp_config_state = e1000_dsp_config_activated; + } + + if ((hw->ffe_config_state == e1000_ffe_config_enabled) && + (min_length < e1000_igp_cable_length_50)) { + + uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; + uint32_t idle_errs = 0; + + /* clear previous idle error counts */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, + &phy_data); + if (ret_val) + return ret_val; + + for (i = 0; i < ffe_idle_err_timeout; i++) { + usec_delay(1000); + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, + &phy_data); + if (ret_val) + return ret_val; + + idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); + if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { + hw->ffe_config_state = e1000_ffe_config_active; + + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_DSP_FFE, + IGP01E1000_PHY_DSP_FFE_CM_CP); + if (ret_val) + return ret_val; + break; + } + + if (idle_errs) + ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; + } + } + } + } else { + if (hw->dsp_config_state == e1000_dsp_config_activated) { + /* Save off the current value of register 0x2F5B to be restored at + * the end of the routines. */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + + if (ret_val) + return ret_val; + + /* Disable the PHY transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + + if (ret_val) + return ret_val; + + msec_delay_irq(20); + + ret_val = e1000_write_phy_reg(hw, 0x0000, + IGP01E1000_IEEE_FORCE_GIGA); + if (ret_val) + return ret_val; + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; + phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; + + ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); + if (ret_val) + return ret_val; + } + + ret_val = e1000_write_phy_reg(hw, 0x0000, + IGP01E1000_IEEE_RESTART_AUTONEG); + if (ret_val) + return ret_val; + + msec_delay_irq(20); + + /* Now enable the transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (ret_val) + return ret_val; + + hw->dsp_config_state = e1000_dsp_config_enabled; + } + + if (hw->ffe_config_state == e1000_ffe_config_active) { + /* Save off the current value of register 0x2F5B to be restored at + * the end of the routines. */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + + if (ret_val) + return ret_val; + + /* Disable the PHY transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + + if (ret_val) + return ret_val; + + msec_delay_irq(20); + + ret_val = e1000_write_phy_reg(hw, 0x0000, + IGP01E1000_IEEE_FORCE_GIGA); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, + IGP01E1000_PHY_DSP_FFE_DEFAULT); + if (ret_val) + return ret_val; + + ret_val = e1000_write_phy_reg(hw, 0x0000, + IGP01E1000_IEEE_RESTART_AUTONEG); + if (ret_val) + return ret_val; + + msec_delay_irq(20); + + /* Now enable the transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (ret_val) + return ret_val; + + hw->ffe_config_state = e1000_ffe_config_enabled; + } + } + return E1000_SUCCESS; +} + +#ifndef FIFO_WORKAROUND +/*************************************************************************** + * + * Workaround for the 82547 long TTL on noisy 100HD hubs. + * + * This function, specific to 82547 hardware only, needs to be called every + * second. It checks if a parallel detect fault has occurred. If a fault + * occurred, disable/enable the DSP reset mechanism up to 5 times (once per + * second). If link is established, stop the workaround and ensure the DSP + * reset is enabled. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS in any other case + * + ****************************************************************************/ +int32_t +e1000_igp_ttl_workaround(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data = 0; + uint16_t dsp_value = DSP_RESET_ENABLE; + + /* The workaround needed only for B-0 silicon HW */ + if (((hw->mac_type != e1000_82541) && (hw->mac_type != e1000_82547)) || + (!hw->ttl_wa_activation)) { + return E1000_SUCCESS; + } + + /* Check for link first */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if (phy_data & MII_SR_LINK_STATUS) { + /* If link is established during the workaround, the DSP mechanism must + * be enabled. */ + if (hw->dsp_reset_counter) { + hw->dsp_reset_counter = 0; + dsp_value = DSP_RESET_ENABLE; + } else + return E1000_SUCCESS; + } else { + if (hw->dsp_reset_counter == 0) { + /* Workaround not activated, check if it needs activation */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); + if (ret_val) + return ret_val; + /* Activate the workaround if there was a parallel detect fault */ + if (phy_data & NWAY_ER_PAR_DETECT_FAULT) + hw->dsp_reset_counter++; + else + return E1000_SUCCESS; + } + + if (hw->dsp_reset_counter) { + /* After 5 times, stop the workaround */ + if (hw->dsp_reset_counter > E1000_MAX_DSP_RESETS) { + hw->dsp_reset_counter = 0; + dsp_value = DSP_RESET_ENABLE; + } else { + dsp_value = (hw->dsp_reset_counter & 1) ? DSP_RESET_DISABLE : + DSP_RESET_ENABLE; + hw->dsp_reset_counter++; + } + } + } + + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value); + if (ret_val) + return ret_val; + + return E1000_SUCCESS; +} + +#endif /* FIFO_WORKAROUND */ +/***************************************************************************** + * Set PHY to class A mode + * Assumes the following operations will follow to enable the new class mode. + * 1. Do a PHY soft reset + * 2. Restart auto-negotiation or force link. + * + * hw - Struct containing variables accessed by shared code + ****************************************************************************/ +static int32_t +e1000_set_phy_mode(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC("e1000_set_phy_mode"); + + if ((hw->mac_type == e1000_82545_rev_3) && + (hw->media_type == e1000_media_type_copper)) { + ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); + if (ret_val) { + return ret_val; + } + + if ((eeprom_data != EEPROM_RESERVED_WORD) && + (eeprom_data & EEPROM_PHY_CLASS_A)) { + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); + if (ret_val) + return ret_val; + + hw->phy_reset_disable = FALSE; + } + } + + return E1000_SUCCESS; +} + +/***************************************************************************** + * + * This function sets the lplu state according to the active flag. When + * activating lplu this function also disables smart speed and vise versa. + * lplu will not be activated unless the device autonegotiation advertisment + * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. + * hw: Struct containing variables accessed by shared code + * active - true to enable lplu false to disable lplu. + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS at any other case. + * + ****************************************************************************/ + +STATIC int32_t +e1000_set_d3_lplu_state(struct e1000_hw *hw, + boolean_t active) +{ + uint32_t phy_ctrl = 0; + int32_t ret_val; + uint16_t phy_data; + DEBUGFUNC("e1000_set_d3_lplu_state"); + + if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 + && hw->phy_type != e1000_phy_igp_3) + return E1000_SUCCESS; + + /* During driver activity LPLU should not be used or it will attain link + * from the lowest speeds starting from 10Mbps. The capability is used for + * Dx transitions and states */ + if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); + if (ret_val) + return ret_val; + } else if (hw->mac_type == e1000_ich8lan) { + /* MAC writes into PHY register based on the state transition + * and start auto-negotiation. SW driver can overwrite the settings + * in CSR PHY power control E1000_PHY_CTRL register. */ + phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else { + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); + if (ret_val) + return ret_val; + } + + if (!active) { + if (hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547_rev_2) { + phy_data &= ~IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); + if (ret_val) + return ret_val; + } else { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data &= ~IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, + phy_data); + if (ret_val) + return ret_val; + } + } + + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during + * Dx states where the power conservation is most important. During + * driver activity we should enable SmartSpeed, so performance is + * maintained. */ + if (hw->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + + phy_data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + } else if (hw->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + } + + } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || + (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || + (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { + + if (hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547_rev_2) { + phy_data |= IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); + if (ret_val) + return ret_val; + } else { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data |= IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, + phy_data); + if (ret_val) + return ret_val; + } + } + + /* When LPLU is enabled we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + + } + return E1000_SUCCESS; +} + +/***************************************************************************** + * + * This function sets the lplu d0 state according to the active flag. When + * activating lplu this function also disables smart speed and vise versa. + * lplu will not be activated unless the device autonegotiation advertisment + * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. + * hw: Struct containing variables accessed by shared code + * active - true to enable lplu false to disable lplu. + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS at any other case. + * + ****************************************************************************/ + +STATIC int32_t +e1000_set_d0_lplu_state(struct e1000_hw *hw, + boolean_t active) +{ + uint32_t phy_ctrl = 0; + int32_t ret_val; + uint16_t phy_data; + DEBUGFUNC("e1000_set_d0_lplu_state"); + + if (hw->mac_type <= e1000_82547_rev_2) + return E1000_SUCCESS; + + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else { + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); + if (ret_val) + return ret_val; + } + + if (!active) { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data &= ~IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during + * Dx states where the power conservation is most important. During + * driver activity we should enable SmartSpeed, so performance is + * maintained. */ + if (hw->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + + phy_data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + } else if (hw->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + } + + + } else { + + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data |= IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + + /* When LPLU is enabled we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Change VCO speed register to improve Bit Error Rate performance of SERDES. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int32_t +e1000_set_vco_speed(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t default_page = 0; + uint16_t phy_data; + + DEBUGFUNC("e1000_set_vco_speed"); + + switch (hw->mac_type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + break; + default: + return E1000_SUCCESS; + } + + /* Set PHY register 30, page 5, bit 8 to 0 */ + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); + if (ret_val) + return ret_val; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); + if (ret_val) + return ret_val; + + /* Set PHY register 30, page 4, bit 11 to 1 */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_PHY_VCO_REG_BIT11; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); + if (ret_val) + return ret_val; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); + if (ret_val) + return ret_val; + + return E1000_SUCCESS; +} + + +/***************************************************************************** + * This function reads the cookie from ARC ram. + * + * returns: - E1000_SUCCESS . + ****************************************************************************/ +STATIC int32_t +e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) +{ + uint8_t i; + uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; + uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; + + length = (length >> 2); + offset = (offset >> 2); + + for (i = 0; i < length; i++) { + *((uint32_t *) buffer + i) = + E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); + } + return E1000_SUCCESS; +} + + +/***************************************************************************** + * This function checks whether the HOST IF is enabled for command operaton + * and also checks whether the previous command is completed. + * It busy waits in case of previous command is not completed. + * + * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or + * timeout + * - E1000_SUCCESS for success. + ****************************************************************************/ +STATIC int32_t +e1000_mng_enable_host_if(struct e1000_hw * hw) +{ + uint32_t hicr; + uint8_t i; + + /* Check that the host interface is enabled. */ + hicr = E1000_READ_REG(hw, HICR); + if ((hicr & E1000_HICR_EN) == 0) { + DEBUGOUT("E1000_HOST_EN bit disabled.\n"); + return -E1000_ERR_HOST_INTERFACE_COMMAND; + } + /* check the previous command is completed */ + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { + hicr = E1000_READ_REG(hw, HICR); + if (!(hicr & E1000_HICR_C)) + break; + msec_delay_irq(1); + } + + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { + DEBUGOUT("Previous command timeout failed .\n"); + return -E1000_ERR_HOST_INTERFACE_COMMAND; + } + return E1000_SUCCESS; +} + +/***************************************************************************** + * This function writes the buffer content at the offset given on the host if. + * It also does alignment considerations to do the writes in most efficient way. + * Also fills up the sum of the buffer in *buffer parameter. + * + * returns - E1000_SUCCESS for success. + ****************************************************************************/ +STATIC int32_t +e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, + uint16_t length, uint16_t offset, uint8_t *sum) +{ + uint8_t *tmp; + uint8_t *bufptr = buffer; + uint32_t data = 0; + uint16_t remaining, i, j, prev_bytes; + + /* sum = only sum of the data and it is not checksum */ + + if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { + return -E1000_ERR_PARAM; + } + + tmp = (uint8_t *)&data; + prev_bytes = offset & 0x3; + offset &= 0xFFFC; + offset >>= 2; + + if (prev_bytes) { + data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); + for (j = prev_bytes; j < sizeof(uint32_t); j++) { + *(tmp + j) = *bufptr++; + *sum += *(tmp + j); + } + E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); + length -= j - prev_bytes; + offset++; + } + + remaining = length & 0x3; + length -= remaining; + + /* Calculate length in DWORDs */ + length >>= 2; + + /* The device driver writes the relevant command block into the + * ram area. */ + for (i = 0; i < length; i++) { + for (j = 0; j < sizeof(uint32_t); j++) { + *(tmp + j) = *bufptr++; + *sum += *(tmp + j); + } + + E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); + } + if (remaining) { + for (j = 0; j < sizeof(uint32_t); j++) { + if (j < remaining) + *(tmp + j) = *bufptr++; + else + *(tmp + j) = 0; + + *sum += *(tmp + j); + } + E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); + } + + return E1000_SUCCESS; +} + + +/***************************************************************************** + * This function writes the command header after does the checksum calculation. + * + * returns - E1000_SUCCESS for success. + ****************************************************************************/ +STATIC int32_t +e1000_mng_write_cmd_header(struct e1000_hw * hw, + struct e1000_host_mng_command_header * hdr) +{ + uint16_t i; + uint8_t sum; + uint8_t *buffer; + + /* Write the whole command header structure which includes sum of + * the buffer */ + + uint16_t length = sizeof(struct e1000_host_mng_command_header); + + sum = hdr->checksum; + hdr->checksum = 0; + + buffer = (uint8_t *) hdr; + i = length; + while (i--) + sum += buffer[i]; + + hdr->checksum = 0 - sum; + + length >>= 2; + /* The device driver writes the relevant command block into the ram area. */ + for (i = 0; i < length; i++) { + E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); + E1000_WRITE_FLUSH(hw); + } + + return E1000_SUCCESS; +} + + +/***************************************************************************** + * This function indicates to ARC that a new command is pending which completes + * one write operation by the driver. + * + * returns - E1000_SUCCESS for success. + ****************************************************************************/ +STATIC int32_t +e1000_mng_write_commit(struct e1000_hw * hw) +{ + uint32_t hicr; + + hicr = E1000_READ_REG(hw, HICR); + /* Setting this bit tells the ARC that a new command is pending. */ + E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); + + return E1000_SUCCESS; +} + + +/***************************************************************************** + * This function checks the mode of the firmware. + * + * returns - TRUE when the mode is IAMT or FALSE. + ****************************************************************************/ +boolean_t +e1000_check_mng_mode(struct e1000_hw *hw) +{ + uint32_t fwsm; + + fwsm = E1000_READ_REG(hw, FWSM); + + if (hw->mac_type == e1000_ich8lan) { + if ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) + return TRUE; + } else if ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) + return TRUE; + + return FALSE; +} + + +/***************************************************************************** + * This function writes the dhcp info . + ****************************************************************************/ +int32_t +e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, + uint16_t length) +{ + int32_t ret_val; + struct e1000_host_mng_command_header hdr; + + hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; + hdr.command_length = length; + hdr.reserved1 = 0; + hdr.reserved2 = 0; + hdr.checksum = 0; + + ret_val = e1000_mng_enable_host_if(hw); + if (ret_val == E1000_SUCCESS) { + ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), + &(hdr.checksum)); + if (ret_val == E1000_SUCCESS) { + ret_val = e1000_mng_write_cmd_header(hw, &hdr); + if (ret_val == E1000_SUCCESS) + ret_val = e1000_mng_write_commit(hw); + } + } + return ret_val; +} + + +/***************************************************************************** + * This function calculates the checksum. + * + * returns - checksum of buffer contents. + ****************************************************************************/ +STATIC uint8_t +e1000_calculate_mng_checksum(char *buffer, uint32_t length) +{ + uint8_t sum = 0; + uint32_t i; + + if (!buffer) + return 0; + + for (i=0; i < length; i++) + sum += buffer[i]; + + return (uint8_t) (0 - sum); +} + +/***************************************************************************** + * This function checks whether tx pkt filtering needs to be enabled or not. + * + * returns - TRUE for packet filtering or FALSE. + ****************************************************************************/ +boolean_t +e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) +{ + /* called in init as well as watchdog timer functions */ + + int32_t ret_val, checksum; + boolean_t tx_filter = FALSE; + struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); + uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); + + if (e1000_check_mng_mode(hw)) { + ret_val = e1000_mng_enable_host_if(hw); + if (ret_val == E1000_SUCCESS) { + ret_val = e1000_host_if_read_cookie(hw, buffer); + if (ret_val == E1000_SUCCESS) { + checksum = hdr->checksum; + hdr->checksum = 0; + if ((hdr->signature == E1000_IAMT_SIGNATURE) && + checksum == e1000_calculate_mng_checksum((char *)buffer, + E1000_MNG_DHCP_COOKIE_LENGTH)) { + if (hdr->status & + E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) + tx_filter = TRUE; + } else + tx_filter = TRUE; + } else + tx_filter = TRUE; + } + } + + hw->tx_pkt_filtering = tx_filter; + return tx_filter; +} + +/****************************************************************************** + * Verifies the hardware needs to allow ARPs to be processed by the host + * + * hw - Struct containing variables accessed by shared code + * + * returns: - TRUE/FALSE + * + *****************************************************************************/ +uint32_t +e1000_enable_mng_pass_thru(struct e1000_hw *hw) +{ + uint32_t manc; + uint32_t fwsm, factps; + + if (hw->asf_firmware_present) { + manc = E1000_READ_REG(hw, MANC); + + if (!(manc & E1000_MANC_RCV_TCO_EN) || + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) + return FALSE; + if (e1000_arc_subsystem_valid(hw) == TRUE) { + fwsm = E1000_READ_REG(hw, FWSM); + factps = E1000_READ_REG(hw, FACTPS); + + if (((fwsm & E1000_FWSM_MODE_MASK) == + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && + (factps & E1000_FACTPS_MNGCG)) + return TRUE; + } else + if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) + return TRUE; + } + return FALSE; +} + +static int32_t +e1000_polarity_reversal_workaround(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_status_reg; + uint16_t i; + + /* Polarity reversal workaround for forced 10F/10H links. */ + + /* Disable the transmitter on the PHY */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); + if (ret_val) + return ret_val; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); + if (ret_val) + return ret_val; + + /* This loop will early-out if the NO link condition has been met. */ + for (i = PHY_FORCE_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Link Status bit + * to be clear. + */ + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; + msec_delay_irq(100); + } + + /* Recommended delay time after link has been lost */ + msec_delay_irq(1000); + + /* Now we will re-enable th transmitter on the PHY */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); + if (ret_val) + return ret_val; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); + if (ret_val) + return ret_val; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); + if (ret_val) + return ret_val; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); + if (ret_val) + return ret_val; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); + if (ret_val) + return ret_val; + + /* This loop will early-out if the link condition has been met. */ + for (i = PHY_FORCE_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Link Status bit + * to be set. + */ + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + return ret_val; + + if (mii_status_reg & MII_SR_LINK_STATUS) break; + msec_delay_irq(100); + } + return E1000_SUCCESS; +} + +/*************************************************************************** + * + * Disables PCI-Express master access. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - none. + * + ***************************************************************************/ +STATIC void +e1000_set_pci_express_master_disable(struct e1000_hw *hw) +{ + uint32_t ctrl; + + DEBUGFUNC("e1000_set_pci_express_master_disable"); + + if (hw->bus_type != e1000_bus_type_pci_express) + return; + + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; + E1000_WRITE_REG(hw, CTRL, ctrl); +} + +/******************************************************************************* + * + * Disables PCI-Express master access and verifies there are no pending requests + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't + * caused the master requests to be disabled. + * E1000_SUCCESS master requests disabled. + * + ******************************************************************************/ +int32_t +e1000_disable_pciex_master(struct e1000_hw *hw) +{ + int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ + + DEBUGFUNC("e1000_disable_pciex_master"); + + if (hw->bus_type != e1000_bus_type_pci_express) + return E1000_SUCCESS; + + e1000_set_pci_express_master_disable(hw); + + while (timeout) { + if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) + break; + else + usec_delay(100); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Master requests are pending.\n"); + return -E1000_ERR_MASTER_REQUESTS_PENDING; + } + + return E1000_SUCCESS; +} + +/******************************************************************************* + * + * Check for EEPROM Auto Read bit done. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_RESET if fail to reset MAC + * E1000_SUCCESS at any other case. + * + ******************************************************************************/ +STATIC int32_t +e1000_get_auto_rd_done(struct e1000_hw *hw) +{ + int32_t timeout = AUTO_READ_DONE_TIMEOUT; + + DEBUGFUNC("e1000_get_auto_rd_done"); + + switch (hw->mac_type) { + default: + msec_delay(5); + break; + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_80003es2lan: + case e1000_ich8lan: + while (timeout) { + if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) + break; + else msec_delay(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); + return -E1000_ERR_RESET; + } + break; + } + + /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. + * Need to wait for PHY configuration completion before accessing NVM + * and PHY. */ + if (hw->mac_type == e1000_82573) + msec_delay(25); + + return E1000_SUCCESS; +} + +/*************************************************************************** + * Checks if the PHY configuration is done + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_RESET if fail to reset MAC + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +STATIC int32_t +e1000_get_phy_cfg_done(struct e1000_hw *hw) +{ + int32_t timeout = PHY_CFG_TIMEOUT; + uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; + + DEBUGFUNC("e1000_get_phy_cfg_done"); + + switch (hw->mac_type) { + default: + msec_delay_irq(10); + break; + case e1000_80003es2lan: + /* Separate *_CFG_DONE_* bit for each port */ + if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; + /* Fall Through */ + case e1000_82571: + case e1000_82572: + while (timeout) { + if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) + break; + else + msec_delay(1); + timeout--; + } + if (!timeout) { + DEBUGOUT("MNG configuration cycle has not completed.\n"); + } + break; + } + + return E1000_SUCCESS; +} + +/*************************************************************************** + * + * Using the combination of SMBI and SWESMBI semaphore bits when resetting + * adapter or Eeprom access. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_EEPROM if fail to access EEPROM. + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +STATIC int32_t +e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) +{ + int32_t timeout; + uint32_t swsm; + + DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); + + if (!hw->eeprom_semaphore_present) + return E1000_SUCCESS; + + if (hw->mac_type == e1000_80003es2lan) { + /* Get the SW semaphore. */ + if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) + return -E1000_ERR_EEPROM; + } + + /* Get the FW semaphore. */ + timeout = hw->eeprom.word_size + 1; + while (timeout) { + swsm = E1000_READ_REG(hw, SWSM); + swsm |= E1000_SWSM_SWESMBI; + E1000_WRITE_REG(hw, SWSM, swsm); + /* if we managed to set the bit we got the semaphore. */ + swsm = E1000_READ_REG(hw, SWSM); + if (swsm & E1000_SWSM_SWESMBI) + break; + + usec_delay(50); + timeout--; + } + + if (!timeout) { + /* Release semaphores */ + e1000_put_hw_eeprom_semaphore(hw); + DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); + return -E1000_ERR_EEPROM; + } + + return E1000_SUCCESS; +} + +/*************************************************************************** + * This function clears HW semaphore bits. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - None. + * + ***************************************************************************/ +STATIC void +e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) +{ + uint32_t swsm; + + DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); + + if (!hw->eeprom_semaphore_present) + return; + + swsm = E1000_READ_REG(hw, SWSM); + if (hw->mac_type == e1000_80003es2lan) { + /* Release both semaphores. */ + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + } else + swsm &= ~(E1000_SWSM_SWESMBI); + E1000_WRITE_REG(hw, SWSM, swsm); +} + +/*************************************************************************** + * + * Obtaining software semaphore bit (SMBI) before resetting PHY. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_RESET if fail to obtain semaphore. + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +STATIC int32_t +e1000_get_software_semaphore(struct e1000_hw *hw) +{ + int32_t timeout = hw->eeprom.word_size + 1; + uint32_t swsm; + + DEBUGFUNC("e1000_get_software_semaphore"); + + if (hw->mac_type != e1000_80003es2lan) { + return E1000_SUCCESS; + } + + while (timeout) { + swsm = E1000_READ_REG(hw, SWSM); + /* If SMBI bit cleared, it is now set and we hold the semaphore */ + if (!(swsm & E1000_SWSM_SMBI)) + break; + msec_delay_irq(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + return -E1000_ERR_RESET; + } + + return E1000_SUCCESS; +} + +/*************************************************************************** + * + * Release semaphore bit (SMBI). + * + * hw: Struct containing variables accessed by shared code + * + ***************************************************************************/ +STATIC void +e1000_release_software_semaphore(struct e1000_hw *hw) +{ + uint32_t swsm; + + DEBUGFUNC("e1000_release_software_semaphore"); + + if (hw->mac_type != e1000_80003es2lan) { + return; + } + + swsm = E1000_READ_REG(hw, SWSM); + /* Release the SW semaphores.*/ + swsm &= ~E1000_SWSM_SMBI; + E1000_WRITE_REG(hw, SWSM, swsm); +} + +/****************************************************************************** + * Checks if PHY reset is blocked due to SOL/IDER session, for example. + * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to + * the caller to figure out how to deal with it. + * + * hw - Struct containing variables accessed by shared code + * + * returns: - E1000_BLK_PHY_RESET + * E1000_SUCCESS + * + *****************************************************************************/ +int32_t +e1000_check_phy_reset_block(struct e1000_hw *hw) +{ + uint32_t manc = 0; + uint32_t fwsm = 0; + + if (hw->mac_type == e1000_ich8lan) { + fwsm = E1000_READ_REG(hw, FWSM); + return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS + : E1000_BLK_PHY_RESET; + } + + if (hw->mac_type > e1000_82547_rev_2) + manc = E1000_READ_REG(hw, MANC); + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? + E1000_BLK_PHY_RESET : E1000_SUCCESS; +} + +STATIC uint8_t +e1000_arc_subsystem_valid(struct e1000_hw *hw) +{ + uint32_t fwsm; + + /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC + * may not be provided a DMA clock when no manageability features are + * enabled. We do not want to perform any reads/writes to these registers + * if this is the case. We read FWSM to determine the manageability mode. + */ + switch (hw->mac_type) { + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_80003es2lan: + fwsm = E1000_READ_REG(hw, FWSM); + if ((fwsm & E1000_FWSM_MODE_MASK) != 0) + return TRUE; + break; + case e1000_ich8lan: + return TRUE; + default: + break; + } + return FALSE; +} + + +/****************************************************************************** + * Configure PCI-Ex no-snoop + * + * hw - Struct containing variables accessed by shared code. + * no_snoop - Bitmap of no-snoop events. + * + * returns: E1000_SUCCESS + * + *****************************************************************************/ +STATIC int32_t +e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) +{ + uint32_t gcr_reg = 0; + + DEBUGFUNC("e1000_set_pci_ex_no_snoop"); + + if (hw->bus_type == e1000_bus_type_unknown) + e1000_get_bus_info(hw); + + if (hw->bus_type != e1000_bus_type_pci_express) + return E1000_SUCCESS; + + if (no_snoop) { + gcr_reg = E1000_READ_REG(hw, GCR); + gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); + gcr_reg |= no_snoop; + E1000_WRITE_REG(hw, GCR, gcr_reg); + } + if (hw->mac_type == e1000_ich8lan) { + uint32_t ctrl_ext; + + E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); + + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + return E1000_SUCCESS; +} + +/*************************************************************************** + * + * Get software semaphore FLAG bit (SWFLAG). + * SWFLAG is used to synchronize the access to all shared resource between + * SW, FW and HW. + * + * hw: Struct containing variables accessed by shared code + * + ***************************************************************************/ +STATIC int32_t +e1000_get_software_flag(struct e1000_hw *hw) +{ + int32_t timeout = PHY_CFG_TIMEOUT; + uint32_t extcnf_ctrl; + + DEBUGFUNC("e1000_get_software_flag"); + + if (hw->mac_type == e1000_ich8lan) { + while (timeout) { + extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); + extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; + E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); + + extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) + break; + msec_delay_irq(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("FW or HW locks the resource too long.\n"); + return -E1000_ERR_CONFIG; + } + } + + return E1000_SUCCESS; +} + +/*************************************************************************** + * + * Release software semaphore FLAG bit (SWFLAG). + * SWFLAG is used to synchronize the access to all shared resource between + * SW, FW and HW. + * + * hw: Struct containing variables accessed by shared code + * + ***************************************************************************/ +STATIC void +e1000_release_software_flag(struct e1000_hw *hw) +{ + uint32_t extcnf_ctrl; + + DEBUGFUNC("e1000_release_software_flag"); + + if (hw->mac_type == e1000_ich8lan) { + extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; + E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); + } + + return; +} + + +/****************************************************************************** + * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access + * register. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +STATIC int32_t +e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, + uint16_t *data) +{ + int32_t error = E1000_SUCCESS; + uint32_t flash_bank = 0; + uint32_t act_offset = 0; + uint32_t bank_offset = 0; + uint16_t word = 0; + uint16_t i = 0; + + /* We need to know which is the valid flash bank. In the event + * that we didn't allocate eeprom_shadow_ram, we may not be + * managing flash_bank. So it cannot be trusted and needs + * to be updated with each read. + */ + /* Value of bit 22 corresponds to the flash bank we're on. */ + flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; + + /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ + bank_offset = flash_bank * (hw->flash_bank_size * 2); + + error = e1000_get_software_flag(hw); + if (error != E1000_SUCCESS) + return error; + + for (i = 0; i < words; i++) { + if (hw->eeprom_shadow_ram != NULL && + hw->eeprom_shadow_ram[offset+i].modified == TRUE) { + data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; + } else { + /* The NVM part needs a byte offset, hence * 2 */ + act_offset = bank_offset + ((offset + i) * 2); + error = e1000_read_ich8_word(hw, act_offset, &word); + if (error != E1000_SUCCESS) + break; + data[i] = word; + } + } + + e1000_release_software_flag(hw); + + return error; +} + +/****************************************************************************** + * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access + * register. Actually, writes are written to the shadow ram cache in the hw + * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to + * the NVM, which occurs when the NVM checksum is updated. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to write + * words - number of words to write + * data - words to write to the EEPROM + *****************************************************************************/ +STATIC int32_t +e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, + uint16_t *data) +{ + uint32_t i = 0; + int32_t error = E1000_SUCCESS; + + error = e1000_get_software_flag(hw); + if (error != E1000_SUCCESS) + return error; + + /* A driver can write to the NVM only if it has eeprom_shadow_ram + * allocated. Subsequent reads to the modified words are read from + * this cached structure as well. Writes will only go into this + * cached structure unless it's followed by a call to + * e1000_update_eeprom_checksum() where it will commit the changes + * and clear the "modified" field. + */ + if (hw->eeprom_shadow_ram != NULL) { + for (i = 0; i < words; i++) { + if ((offset + i) < E1000_SHADOW_RAM_WORDS) { + hw->eeprom_shadow_ram[offset+i].modified = TRUE; + hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; + } else { + error = -E1000_ERR_EEPROM; + break; + } + } + } else { + /* Drivers have the option to not allocate eeprom_shadow_ram as long + * as they don't perform any NVM writes. An attempt in doing so + * will result in this error. + */ + error = -E1000_ERR_EEPROM; + } + + e1000_release_software_flag(hw); + + return error; +} + +/****************************************************************************** + * This function does initial flash setup so that a new read/write/erase cycle + * can be started. + * + * hw - The pointer to the hw structure + ****************************************************************************/ +STATIC int32_t +e1000_ich8_cycle_init(struct e1000_hw *hw) +{ + union ich8_hws_flash_status hsfsts; + int32_t error = E1000_ERR_EEPROM; + int32_t i = 0; + + DEBUGFUNC("e1000_ich8_cycle_init"); + + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + + /* May be check the Flash Des Valid bit in Hw status */ + if (hsfsts.hsf_status.fldesvalid == 0) { + DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); + return error; + } + + /* Clear FCERR in Hw status by writing 1 */ + /* Clear DAEL in Hw status by writing a 1 */ + hsfsts.hsf_status.flcerr = 1; + hsfsts.hsf_status.dael = 1; + + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); + + /* Either we should have a hardware SPI cycle in progress bit to check + * against, in order to start a new cycle or FDONE bit should be changed + * in the hardware so that it is 1 after harware reset, which can then be + * used as an indication whether a cycle is in progress or has been + * completed .. we should also have some software semaphore mechanism to + * guard FDONE or the cycle in progress bit so that two threads access to + * those bits can be sequentiallized or a way so that 2 threads dont + * start the cycle at the same time */ + + if (hsfsts.hsf_status.flcinprog == 0) { + /* There is no cycle running at present, so we can start a cycle */ + /* Begin by setting Flash Cycle Done. */ + hsfsts.hsf_status.flcdone = 1; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); + error = E1000_SUCCESS; + } else { + /* otherwise poll for sometime so the current cycle has a chance + * to end before giving up. */ + for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcinprog == 0) { + error = E1000_SUCCESS; + break; + } + usec_delay(1); + } + if (error == E1000_SUCCESS) { + /* Successful in waiting for previous cycle to timeout, + * now set the Flash Cycle Done. */ + hsfsts.hsf_status.flcdone = 1; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); + } else { + DEBUGOUT("Flash controller busy, cannot get access"); + } + } + return error; +} + +/****************************************************************************** + * This function starts a flash cycle and waits for its completion + * + * hw - The pointer to the hw structure + ****************************************************************************/ +STATIC int32_t +e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) +{ + union ich8_hws_flash_ctrl hsflctl; + union ich8_hws_flash_status hsfsts; + int32_t error = E1000_ERR_EEPROM; + uint32_t i = 0; + + /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ + hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + hsflctl.hsf_ctrl.flcgo = 1; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + /* wait till FDONE bit is set to 1 */ + do { + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcdone == 1) + break; + usec_delay(1); + i++; + } while (i < timeout); + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { + error = E1000_SUCCESS; + } + return error; +} + +/****************************************************************************** + * Reads a byte or word from the NVM using the ICH8 flash access registers. + * + * hw - The pointer to the hw structure + * index - The index of the byte or word to read. + * size - Size of data to read, 1=byte 2=word + * data - Pointer to the word to store the value read. + *****************************************************************************/ +STATIC int32_t +e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, + uint32_t size, uint16_t* data) +{ + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + uint32_t flash_linear_address; + uint32_t flash_data = 0; + int32_t error = -E1000_ERR_EEPROM; + int32_t count = 0; + + DEBUGFUNC("e1000_read_ich8_data"); + + if (size < 1 || size > 2 || data == 0x0 || + index > ICH_FLASH_LINEAR_ADDR_MASK) + return error; + + flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + + hw->flash_base_addr; + + do { + usec_delay(1); + /* Steps */ + error = e1000_ich8_cycle_init(hw); + if (error != E1000_SUCCESS) + break; + + hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ + hsflctl.hsf_ctrl.fldbcount = size - 1; + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + /* Write the last 24 bits of index into Flash Linear address field in + * Flash Address */ + /* TODO: TBD maybe check the index against the size of flash */ + + E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); + + error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); + + /* Check if FCERR is set to 1, if set to 1, clear it and try the whole + * sequence a few more times, else read in (shift in) the Flash Data0, + * the order is least significant byte first msb to lsb */ + if (error == E1000_SUCCESS) { + flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); + if (size == 1) { + *data = (uint8_t)(flash_data & 0x000000FF); + } else if (size == 2) { + *data = (uint16_t)(flash_data & 0x0000FFFF); + } + break; + } else { + /* If we've gotten here, then things are probably completely hosed, + * but if the error condition is detected, it won't hurt to give + * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. + */ + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* Repeat for some time before giving up. */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) { + DEBUGOUT("Timeout error - flash cycle did not complete."); + break; + } + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + + return error; +} + +/****************************************************************************** + * Writes One /two bytes to the NVM using the ICH8 flash access registers. + * + * hw - The pointer to the hw structure + * index - The index of the byte/word to read. + * size - Size of data to read, 1=byte 2=word + * data - The byte(s) to write to the NVM. + *****************************************************************************/ +STATIC int32_t +e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, + uint16_t data) +{ + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + uint32_t flash_linear_address; + uint32_t flash_data = 0; + int32_t error = -E1000_ERR_EEPROM; + int32_t count = 0; + + DEBUGFUNC("e1000_write_ich8_data"); + + if (size < 1 || size > 2 || data > size * 0xff || + index > ICH_FLASH_LINEAR_ADDR_MASK) + return error; + + flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + + hw->flash_base_addr; + + do { + usec_delay(1); + /* Steps */ + error = e1000_ich8_cycle_init(hw); + if (error != E1000_SUCCESS) + break; + + hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ + hsflctl.hsf_ctrl.fldbcount = size -1; + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + /* Write the last 24 bits of index into Flash Linear address field in + * Flash Address */ + E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); + + if (size == 1) + flash_data = (uint32_t)data & 0x00FF; + else + flash_data = (uint32_t)data; + + E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); + + /* check if FCERR is set to 1 , if set to 1, clear it and try the whole + * sequence a few more times else done */ + error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); + if (error == E1000_SUCCESS) { + break; + } else { + /* If we're here, then things are most likely completely hosed, + * but if the error condition is detected, it won't hurt to give + * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. + */ + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* Repeat for some time before giving up. */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) { + DEBUGOUT("Timeout error - flash cycle did not complete."); + break; + } + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + + return error; +} + +/****************************************************************************** + * Reads a single byte from the NVM using the ICH8 flash access registers. + * + * hw - pointer to e1000_hw structure + * index - The index of the byte to read. + * data - Pointer to a byte to store the value read. + *****************************************************************************/ +STATIC int32_t +e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) +{ + int32_t status = E1000_SUCCESS; + uint16_t word = 0; + + status = e1000_read_ich8_data(hw, index, 1, &word); + if (status == E1000_SUCCESS) { + *data = (uint8_t)word; + } + + return status; +} + +/****************************************************************************** + * Writes a single byte to the NVM using the ICH8 flash access registers. + * Performs verification by reading back the value and then going through + * a retry algorithm before giving up. + * + * hw - pointer to e1000_hw structure + * index - The index of the byte to write. + * byte - The byte to write to the NVM. + *****************************************************************************/ +STATIC int32_t +e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) +{ + int32_t error = E1000_SUCCESS; + int32_t program_retries = 0; + + DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); + + error = e1000_write_ich8_byte(hw, index, byte); + + if (error != E1000_SUCCESS) { + for (program_retries = 0; program_retries < 100; program_retries++) { + DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); + error = e1000_write_ich8_byte(hw, index, byte); + usec_delay(100); + if (error == E1000_SUCCESS) + break; + } + } + + if (program_retries == 100) + error = E1000_ERR_EEPROM; + + return error; +} + +/****************************************************************************** + * Writes a single byte to the NVM using the ICH8 flash access registers. + * + * hw - pointer to e1000_hw structure + * index - The index of the byte to read. + * data - The byte to write to the NVM. + *****************************************************************************/ +STATIC int32_t +e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) +{ + int32_t status = E1000_SUCCESS; + uint16_t word = (uint16_t)data; + + status = e1000_write_ich8_data(hw, index, 1, word); + + return status; +} + +/****************************************************************************** + * Reads a word from the NVM using the ICH8 flash access registers. + * + * hw - pointer to e1000_hw structure + * index - The starting byte index of the word to read. + * data - Pointer to a word to store the value read. + *****************************************************************************/ +STATIC int32_t +e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) +{ + int32_t status = E1000_SUCCESS; + status = e1000_read_ich8_data(hw, index, 2, data); + return status; +} + + +/****************************************************************************** + * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 + * based. + * + * hw - pointer to e1000_hw structure + * bank - 0 for first bank, 1 for second bank + * + * Note that this function may actually erase as much as 8 or 64 KBytes. The + * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the + * bank size may be 4, 8 or 64 KBytes + *****************************************************************************/ +int32_t +e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) +{ + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + uint32_t flash_linear_address; + int32_t count = 0; + int32_t error = E1000_ERR_EEPROM; + int32_t iteration; + int32_t sub_sector_size = 0; + int32_t bank_size; + int32_t j = 0; + int32_t error_flag = 0; + + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + + /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ + /* 00: The Hw sector is 256 bytes, hence we need to erase 16 + * consecutive sectors. The start index for the nth Hw sector can be + * calculated as bank * 4096 + n * 256 + * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. + * The start index for the nth Hw sector can be calculated + * as bank * 4096 + * 10: The HW sector is 8K bytes + * 11: The Hw sector size is 64K bytes */ + if (hsfsts.hsf_status.berasesz == 0x0) { + /* Hw sector size 256 */ + sub_sector_size = ICH_FLASH_SEG_SIZE_256; + bank_size = ICH_FLASH_SECTOR_SIZE; + iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; + } else if (hsfsts.hsf_status.berasesz == 0x1) { + bank_size = ICH_FLASH_SEG_SIZE_4K; + iteration = 1; + } else if (hsfsts.hsf_status.berasesz == 0x3) { + bank_size = ICH_FLASH_SEG_SIZE_64K; + iteration = 1; + } else { + return error; + } + + for (j = 0; j < iteration ; j++) { + do { + count++; + /* Steps */ + error = e1000_ich8_cycle_init(hw); + if (error != E1000_SUCCESS) { + error_flag = 1; + break; + } + + /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash + * Control */ + hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; + E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + /* Write the last 24 bits of an index within the block into Flash + * Linear address field in Flash Address. This probably needs to + * be calculated here based off the on-chip erase sector size and + * the software bank size (4, 8 or 64 KBytes) */ + flash_linear_address = bank * bank_size + j * sub_sector_size; + flash_linear_address += hw->flash_base_addr; + flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; + + E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); + + error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); + /* Check if FCERR is set to 1. If 1, clear it and try the whole + * sequence a few more times else Done */ + if (error == E1000_SUCCESS) { + break; + } else { + hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* repeat for some time before giving up */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) { + error_flag = 1; + break; + } + } + } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); + if (error_flag == 1) + break; + } + if (error_flag != 1) + error = E1000_SUCCESS; + return error; +} + + +STATIC int32_t +e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, + uint32_t cnf_base_addr, uint32_t cnf_size) +{ + uint32_t ret_val = E1000_SUCCESS; + uint16_t word_addr, reg_data, reg_addr; + uint16_t i; + + /* cnf_base_addr is in DWORD */ + word_addr = (uint16_t)(cnf_base_addr << 1); + + /* cnf_size is returned in size of dwords */ + for (i = 0; i < cnf_size; i++) { + ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); + if (ret_val) + return ret_val; + + ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); + if (ret_val) + return ret_val; + + ret_val = e1000_get_software_flag(hw); + if (ret_val != E1000_SUCCESS) + return ret_val; + + ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); + + e1000_release_software_flag(hw); + } + + return ret_val; +} + + +/****************************************************************************** + * This function initializes the PHY from the NVM on ICH8 platforms. This + * is needed due to an issue where the NVM configuration is not properly + * autoloaded after power transitions. Therefore, after each PHY reset, we + * will load the configuration data out of the NVM manually. + * + * hw: Struct containing variables accessed by shared code + *****************************************************************************/ +STATIC int32_t +e1000_init_lcd_from_nvm(struct e1000_hw *hw) +{ + uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; + + if (hw->phy_type != e1000_phy_igp_3) + return E1000_SUCCESS; + + /* Check if SW needs configure the PHY */ + reg_data = E1000_READ_REG(hw, FEXTNVM); + if (!(reg_data & FEXTNVM_SW_CONFIG)) + return E1000_SUCCESS; + + /* Wait for basic configuration completes before proceeding*/ + loop = 0; + do { + reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; + usec_delay(100); + loop++; + } while ((!reg_data) && (loop < 50)); + + /* Clear the Init Done bit for the next init event */ + reg_data = E1000_READ_REG(hw, STATUS); + reg_data &= ~E1000_STATUS_LAN_INIT_DONE; + E1000_WRITE_REG(hw, STATUS, reg_data); + + /* Make sure HW does not configure LCD from PHY extended configuration + before SW configuration */ + reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); + if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { + reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); + cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; + cnf_size >>= 16; + if (cnf_size) { + reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); + cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; + /* cnf_base_addr is in DWORD */ + cnf_base_addr >>= 16; + + /* Configure LCD from extended configuration region. */ + ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, + cnf_size); + if (ret_val) + return ret_val; + } + } + + return E1000_SUCCESS; +} +
--- a/usr/src/pkgdefs/SUNWintgige/postinstall Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/pkgdefs/SUNWintgige/postinstall Tue Aug 21 00:30:10 2007 -0700 @@ -188,9 +188,16 @@ "pci8086,10ba" "pci8086,10bb" "pci8086,10bc" + "pci8086,10bd" + "pci8086,10be" + "pci8086,10bf" + "pci8086,10c0" + "pci8086,10c2" + "pci8086,10c3" "pci8086,10c4" "pci8086,10c5" "pci8086,10d5" + "pci8086,294c" "pciex8086,1049" "pciex8086,104a" "pciex8086,104b" @@ -212,7 +219,14 @@ "pciex8086,10ba" "pciex8086,10bb" "pciex8086,10bc" + "pciex8086,10bd" + "pciex8086,10be" + "pciex8086,10bf" + "pciex8086,10c0" + "pciex8086,10c2" + "pciex8086,10c3" "pciex8086,10c4" "pciex8086,10c5" - "pciex8086,10d5"' \ + "pciex8086,10d5" + "pciex8086,294c"' \ -m '* 0666 root root' e1000g
--- a/usr/src/uts/common/Makefile.files Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/Makefile.files Tue Aug 21 00:30:10 2007 -0700 @@ -1396,7 +1396,10 @@ # # e1000g module # -E1000G_OBJS += e1000g_debug.o e1000_hw.o e1000g_main.o e1000g_alloc.o \ +E1000G_OBJS += e1000_80003es2lan.o e1000_82540.o e1000_82541.o e1000_82542.o \ + e1000_82543.o e1000_82571.o e1000_api.o e1000_ich8lan.o \ + e1000_mac.o e1000_manage.o e1000_nvm.o e1000_osdep.o \ + e1000_phy.o e1000g_debug.o e1000g_main.o e1000g_alloc.o \ e1000g_tx.o e1000g_rx.o e1000g_stat.o e1000g_ndd.o # # NIU 10G/1G driver module
--- a/usr/src/uts/common/io/e1000g/README Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/README Tue Aug 21 00:30:10 2007 -0700 @@ -520,3 +520,11 @@ ====== This version has the following fix: 6552853 system panics in e1000g_alloc_dvma_buffer during hotplug testing + +5.2.0 +====== + This version has the following fix: + 6535620 e1000g needs to support ICH9 devices + 6572330 e1000g: integrate the latest Intel refactored shared code + 6573381 e1000g receiving VLAN tagged frames does not do hardware checksumming +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_80003es2lan.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1351 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_80003es2lan + */ + +#include "e1000_api.h" +#include "e1000_80003es2lan.h" + +void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); +static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + u32 offset, u16 *data); +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + u32 offset, u16 data); +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, + u16 *duplex); +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); + +/* + * A table for the GG82563 cable length where the range is defined with a + * lower bound at "index" and the upper bound at "index + 5". + */ +static const u16 e1000_gg82563_cable_length_table[] = + {0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF}; + +#define GG82563_CABLE_LENGTH_TABLE_SIZE \ + (sizeof (e1000_gg82563_cable_length_table) / \ + sizeof (e1000_gg82563_cable_length_table[0])) + +/* + * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_phy_params_80003es2lan"); + + if (hw->media_type != e1000_media_type_copper) { + phy->type = e1000_phy_none; + goto out; + } + + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 100; + phy->type = e1000_phy_gg82563; + + func->acquire_phy = e1000_acquire_phy_80003es2lan; + func->check_polarity = e1000_check_polarity_m88; + func->check_reset_block = e1000_check_reset_block_generic; + func->commit_phy = e1000_phy_sw_reset_generic; + func->get_cfg_done = e1000_get_cfg_done_80003es2lan; + func->get_phy_info = e1000_get_phy_info_m88; + func->release_phy = e1000_release_phy_80003es2lan; + func->reset_phy = e1000_phy_hw_reset_generic; + func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; + + func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; + func->get_cable_length = e1000_get_cable_length_80003es2lan; + func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; + func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; + + /* This can only be done after all function pointers are setup. */ + ret_val = e1000_get_phy_id(hw); + + /* Verify phy id */ + if (phy->id != GG82563_E_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u16 size; + + DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); + + nvm->opcode_bits = 8; + nvm->delay_usec = 1; + switch (nvm->override) { + case e1000_nvm_override_spi_large: + nvm->page_size = 32; + nvm->address_bits = 16; + break; + case e1000_nvm_override_spi_small: + nvm->page_size = 8; + nvm->address_bits = 8; + break; + default: + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; + break; + } + + nvm->type = e1000_nvm_eeprom_spi; + + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + + /* + * Added to a constant, "size" becomes the left-shift value + * for setting word_size. + */ + size += NVM_WORD_SIZE_BASE_SHIFT; + nvm->word_size = 1 << size; + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_nvm_80003es2lan; + func->read_nvm = e1000_read_nvm_eerd; + func->release_nvm = e1000_release_nvm_80003es2lan; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->valid_led_default = e1000_valid_led_default_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + func->write_nvm = e1000_write_nvm_80003es2lan; + + return (E1000_SUCCESS); +} + +/* + * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_mac_params_80003es2lan"); + + /* Set media type */ + switch (hw->device_id) { + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + hw->media_type = e1000_media_type_internal_serdes; + break; + default: + hw->media_type = e1000_media_type_copper; + break; + } + + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + /* Set if part includes ASF firmware */ + mac->asf_firmware_present = TRUE; + /* Set if manageability features are enabled. */ + mac->arc_subsystem_valid = + (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) + ? TRUE : FALSE; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_pcie_generic; + /* reset */ + func->reset_hw = e1000_reset_hw_80003es2lan; + /* hw initialization */ + func->init_hw = e1000_init_hw_80003es2lan; + /* link setup */ + func->setup_link = e1000_setup_link_generic; + /* physical interface link setup */ + func->setup_physical_interface = + (hw->media_type == e1000_media_type_copper) + ? e1000_setup_copper_link_80003es2lan + : e1000_setup_fiber_serdes_link_generic; + /* check for link */ + switch (hw->media_type) { + case e1000_media_type_copper: + func->check_for_link = e1000_check_for_copper_link_generic; + break; + case e1000_media_type_fiber: + func->check_for_link = e1000_check_for_fiber_link_generic; + break; + case e1000_media_type_internal_serdes: + func->check_for_link = e1000_check_for_serdes_link_generic; + break; + default: + ret_val = -E1000_ERR_CONFIG; + goto out; + } + /* check management mode */ + func->check_mng_mode = e1000_check_mng_mode_generic; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_generic; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* blink LED */ + func->blink_led = e1000_blink_led_generic; + /* setup LED */ + func->setup_led = e1000_setup_led_generic; + /* cleanup LED */ + func->cleanup_led = e1000_cleanup_led_generic; + /* turn on/off LED */ + func->led_on = e1000_led_on_generic; + func->led_off = e1000_led_off_generic; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; + /* link info */ + func->get_link_up_info = e1000_get_link_up_info_80003es2lan; + +out: + return (ret_val); +} + +/* + * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); + + hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; + hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; + hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; +} + +/* + * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY + * @hw: pointer to the HW structure + * + * A wrapper to acquire access rights to the correct PHY. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) +{ + u16 mask; + + DEBUGFUNC("e1000_acquire_phy_80003es2lan"); + + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; + + return (e1000_acquire_swfw_sync_80003es2lan(hw, mask)); +} + +/* + * e1000_release_phy_80003es2lan - Release rights to access PHY + * @hw: pointer to the HW structure + * + * A wrapper to release access rights to the correct PHY. This is a + * function pointer entry point called by the api module. + */ +static void +e1000_release_phy_80003es2lan(struct e1000_hw *hw) +{ + u16 mask; + + DEBUGFUNC("e1000_release_phy_80003es2lan"); + + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; + e1000_release_swfw_sync_80003es2lan(hw, mask); +} + +/* + * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM + * @hw: pointer to the HW structure + * + * Acquire the semaphore to access the EEPROM. This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) +{ + s32 ret_val; + + DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); + + ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); + if (ret_val) + goto out; + + ret_val = e1000_acquire_nvm_generic(hw); + + if (ret_val) + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); + +out: + return (ret_val); +} + +/* + * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM + * @hw: pointer to the HW structure + * + * Release the semaphore used to access the EEPROM. This is a + * function pointer entry point called by the api module. + */ +static void +e1000_release_nvm_80003es2lan(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_release_nvm_80003es2lan"); + + e1000_release_nvm_generic(hw); + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); +} + +/* + * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore + * @hw: pointer to the HW structure + * @mask: specifies which semaphore to acquire + * + * Acquire the SW/FW semaphore to access the PHY or NVM. The mask + * will also specify which port we're acquiring the lock for. + */ +static s32 +e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) +{ + u32 swfw_sync; + u32 swmask = mask; + u32 fwmask = mask << 16; + s32 ret_val = E1000_SUCCESS; + s32 i = 0, timeout = 200; + + DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); + + while (i < timeout) { + if (e1000_get_hw_semaphore_generic(hw)) { + ret_val = -E1000_ERR_SWFW_SYNC; + goto out; + } + + swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); + if (!(swfw_sync & (fwmask | swmask))) + break; + + /* + * Firmware currently using resource (fwmask) + * or other software thread using resource (swmask) + */ + e1000_put_hw_semaphore_generic(hw); + msec_delay_irq(5); + i++; + } + + if (i == timeout) { + DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); + ret_val = -E1000_ERR_SWFW_SYNC; + goto out; + } + + swfw_sync |= swmask; + E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); + + e1000_put_hw_semaphore_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore + * @hw: pointer to the HW structure + * @mask: specifies which semaphore to acquire + * + * Release the SW/FW semaphore used to access the PHY or NVM. The mask + * will also specify which port we're releasing the lock for. + */ +static void +e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) +{ + u32 swfw_sync; + + DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); + + while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) { + /* Empty */ + } + + swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); + swfw_sync &= ~mask; + E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); + + e1000_put_hw_semaphore_generic(hw); +} + +/* + * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register + * @hw: pointer to the HW structure + * @offset: offset of the register to read + * @data: pointer to the data returned from the operation + * + * Read the GG82563 PHY register. This is a function pointer entry + * point called by the api module. + */ +static s32 +e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + u32 offset, u16 *data) +{ + s32 ret_val; + u32 page_select; + u16 temp; + + DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); + + /* Select Configuration Page */ + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { + page_select = GG82563_PHY_PAGE_SELECT; + } else { + /* + * Use Alternative Page Select register to access + * registers 30 and 31 + */ + page_select = GG82563_PHY_PAGE_SELECT_ALT; + } + + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); + ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) + goto out; + + /* + * The "ready" bit in the MDIC register may be incorrectly set + * before the device has completed the "Page Select" MDI + * transaction. So we wait 200us after each MDI command... + */ + usec_delay(200); + + /* ...and verify the command was successful. */ + ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); + + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + usec_delay(200); + + ret_val = e1000_read_phy_reg_m88(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + usec_delay(200); + +out: + return (ret_val); +} + +/* + * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register + * @hw: pointer to the HW structure + * @offset: offset of the register to read + * @data: value to write to the register + * + * Write to the GG82563 PHY register. This is a function pointer entry + * point called by the api module. + */ +static s32 +e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + u32 offset, u16 data) +{ + s32 ret_val; + u32 page_select; + u16 temp; + + DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); + + /* Select Configuration Page */ + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { + page_select = GG82563_PHY_PAGE_SELECT; + } else { + /* + * Use Alternative Page Select register to access + * registers 30 and 31 + */ + page_select = GG82563_PHY_PAGE_SELECT_ALT; + } + + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); + ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) + goto out; + + + /* + * The "ready" bit in the MDIC register may be incorrectly set + * before the device has completed the "Page Select" MDI + * transaction. So we wait 200us after each MDI command... + */ + usec_delay(200); + + /* ...and verify the command was successful. */ + ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); + + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + usec_delay(200); + + ret_val = e1000_write_phy_reg_m88(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + usec_delay(200); + +out: + return (ret_val); +} + +/* + * e1000_write_nvm_80003es2lan - Write to ESB2 NVM + * @hw: pointer to the HW structure + * @offset: offset of the register to read + * @words: number of words to write + * @data: buffer of data to write to the NVM + * + * Write "words" of data to the ESB2 NVM. This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data) +{ + DEBUGFUNC("e1000_write_nvm_80003es2lan"); + + return (e1000_write_nvm_spi(hw, offset, words, data)); +} + +/* + * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete + * @hw: pointer to the HW structure + * + * Wait a specific amount of time for manageability processes to complete. + * This is a function pointer entry point called by the phy module. + */ +static s32 +e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) +{ + s32 timeout = PHY_CFG_TIMEOUT; + s32 ret_val = E1000_SUCCESS; + u32 mask = E1000_NVM_CFG_DONE_PORT_0; + + DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); + + if (hw->bus.func == 1) + mask = E1000_NVM_CFG_DONE_PORT_1; + + while (timeout) { + if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) + break; + msec_delay(1); + timeout--; + } + if (!timeout) { + DEBUGOUT("MNG configuration cycle has not completed.\n"); + ret_val = -E1000_ERR_RESET; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex + * @hw: pointer to the HW structure + * + * Force the speed and duplex settings onto the PHY. This is a + * function pointer entry point called by the phy module. + */ +static s32 +e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) +{ + s32 ret_val; + u16 phy_data; + boolean_t link; + + DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); + + /* + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI + * forced whenever speed and duplex are forced. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + + DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); + + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); + if (ret_val) + goto out; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + + /* Reset the phy to commit changes. */ + phy_data |= MII_CR_RESET; + + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); + if (ret_val) + goto out; + + usec_delay(1); + + if (hw->phy.wait_for_link) { + DEBUGOUT("Waiting for forced speed/duplex link " + "on GG82563 phy.\n"); + + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + goto out; + + if (!link) { + /* + * We didn't get link. + * Reset the DSP and cross our fingers. + */ + ret_val = e1000_phy_reset_dsp_generic(hw); + if (ret_val) + goto out; + } + + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + goto out; + } + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + /* + * Resetting the phy means we need to verify the TX_CLK corresponds + * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. + */ + phy_data &= ~GG82563_MSCR_TX_CLK_MASK; + if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) + phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; + else + phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; + + /* + * In addition, we must re-enable CRS on Tx for both half and full + * duplex. + */ + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); + +out: + return (ret_val); +} + +/* + * e1000_get_cable_length_80003es2lan - Set approximate cable length + * @hw: pointer to the HW structure + * + * Find the approximate cable length as measured by the GG82563 PHY. + * This is a function pointer entry point called by the phy module. + */ +static s32 +e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, index; + + DEBUGFUNC("e1000_get_cable_length_80003es2lan"); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); + if (ret_val) + goto out; + + index = phy_data & GG82563_DSPD_CABLE_LENGTH; + phy->min_cable_length = e1000_gg82563_cable_length_table[index]; + phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +out: + return (ret_val); +} + +/* + * e1000_get_link_up_info_80003es2lan - Report speed and duplex + * @hw: pointer to the HW structure + * @speed: pointer to speed buffer + * @duplex: pointer to duplex buffer + * + * Retrieve the current speed and duplex configuration. + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) +{ + s32 ret_val; + + DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); + + if (hw->media_type == e1000_media_type_copper) { + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, + speed, + duplex); + if (ret_val) + goto out; + if (*speed == SPEED_1000) + ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); + else + ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, + *duplex); + } else { + ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, + speed, + duplex); + } + +out: + return (ret_val); +} + +/* + * e1000_reset_hw_80003es2lan - Reset the ESB2 controller + * @hw: pointer to the HW structure + * + * Perform a global reset to the ESB2 controller. + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_80003es2lan(struct e1000_hw *hw) +{ + u32 ctrl, icr; + s32 ret_val; + + DEBUGFUNC("e1000_reset_hw_80003es2lan"); + + /* + * Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ + ret_val = e1000_disable_pcie_master_generic(hw); + if (ret_val) { + DEBUGOUT("PCI-E Master disable polling has failed.\n"); + } + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + msec_delay(10); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGOUT("Issuing a global reset to MAC\n"); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + + ret_val = e1000_get_auto_rd_done_generic(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ + goto out; + + /* Clear any pending interrupt events. */ + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + +out: + return (ret_val); +} + +/* + * e1000_init_hw_80003es2lan - Initialize the ESB2 controller + * @hw: pointer to the HW structure + * + * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_hw_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 reg_data; + s32 ret_val; + u16 i; + + DEBUGFUNC("e1000_init_hw_80003es2lan"); + + e1000_initialize_hw_bits_80003es2lan(hw); + + /* Initialize identification LED */ + ret_val = e1000_id_led_init_generic(hw); + if (ret_val) { + DEBUGOUT("Error initializing identification LED\n"); + goto out; + } + + /* Disabling VLAN filtering */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + e1000_clear_vfta(hw); + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + /* Set the transmit descriptor write-back policy */ + reg_data = E1000_READ_REG(hw, E1000_TXDCTL); + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); + + /* ...for both queues. */ + reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); + + /* Enable retransmit on late collisions */ + reg_data = E1000_READ_REG(hw, E1000_TCTL); + reg_data |= E1000_TCTL_RTLC; + E1000_WRITE_REG(hw, E1000_TCTL, reg_data); + + /* Configure Gigabit Carry Extend Padding */ + reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; + reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; + E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); + + /* Configure Transmit Inter-Packet Gap */ + reg_data = E1000_READ_REG(hw, E1000_TIPG); + reg_data &= ~E1000_TIPG_IPGT_MASK; + reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; + E1000_WRITE_REG(hw, E1000_TIPG, reg_data); + + reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); + reg_data &= ~0x00100000; + E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_80003es2lan(hw); + +out: + return (ret_val); +} + +/* + * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 + * @hw: pointer to the HW structure + * + * Initializes required hardware-dependent bits needed for normal operation. + */ +static void +e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) +{ + u32 reg; + + DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); + + if (hw->mac.disable_hw_init_bits) + return; + + /* Transmit Descriptor Control 0 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL, reg); + + /* Transmit Descriptor Control 1 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL1); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); + + /* Transmit Arbitration Control 0 */ + reg = E1000_READ_REG(hw, E1000_TARC0); + reg &= ~(0xF << 27); /* 30:27 */ + if (hw->media_type != e1000_media_type_copper) + reg &= ~(1 << 20); + E1000_WRITE_REG(hw, E1000_TARC0, reg); + + /* Transmit Arbitration Control 1 */ + reg = E1000_READ_REG(hw, E1000_TARC1); + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) + reg &= ~(1 << 28); + else + reg |= (1 << 28); + E1000_WRITE_REG(hw, E1000_TARC1, reg); +} + +/* + * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link + * @hw: pointer to the HW structure + * + * Setup some GG82563 PHY registers for obtaining link + */ +static s32 +e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u32 ctrl_ext; + u16 data; + + DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); + + if (!phy->reset_disable) { + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + &data); + if (ret_val) + goto out; + + data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ + data |= GG82563_MSCR_TX_CLK_1000MBPS_25; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + data); + if (ret_val) + goto out; + + /* + * Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); + if (ret_val) + goto out; + + data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; + + switch (phy->mdix) { + case 1: + data |= GG82563_PSCR_CROSSOVER_MODE_MDI; + break; + case 2: + data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; + break; + case 0: + default: + data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; + break; + } + + /* + * Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; + if (phy->disable_polarity_correction) + data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); + if (ret_val) + goto out; + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_commit(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + goto out; + } + + } + + /* Bypass RX and TX FIFO's */ + ret_val = e1000_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); + if (ret_val) + goto out; + + data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); + if (ret_val) + goto out; + + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); + if (ret_val) + goto out; + + /* + * Do not init these registers when the HW is in IAMT mode, since the + * firmware will have already initialized them. We only initialize + * them if the HW is not in IAMT mode. + */ + if (!(e1000_check_mng_mode(hw))) { + /* Enable Electrical Idle on the PHY */ + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_PWR_MGMT_CTRL, + data); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_KMRN_MODE_CTRL, + &data); + if (ret_val) + goto out; + + data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_KMRN_MODE_CTRL, + data); + + if (ret_val) + goto out; + } + + /* + * Workaround: Disable padding in Kumeran interface in the MAC + * and in the PHY to avoid CRC errors. + */ + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); + if (ret_val) + goto out; + + data |= GG82563_ICR_DIS_PADDING; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); + if (ret_val) + goto out; + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 + * @hw: pointer to the HW structure + * + * Essentially a wrapper for setting up all things "copper" related. + * This is a function pointer entry point called by the mac module. + */ +static s32 +e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + u16 reg_data; + + DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* + * Set the mac to wait the maximum time between each + * iteration and increase the max iterations when + * polling the phy; this fixes erroneous timeouts at 10Mbps. + */ + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + goto out; + ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) + goto out; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) + goto out; + ret_val = e1000_read_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + ®_data); + if (ret_val) + goto out; + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + reg_data); + if (ret_val) + goto out; + + ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); + if (ret_val) + goto out; + + ret_val = e1000_setup_copper_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation + * @hw: pointer to the HW structure + * @duplex: current duplex setting + * + * Configure the KMRN interface by applying last minute quirks for + * 10/100 operation. + */ +static s32 +e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) +{ + s32 ret_val = E1000_SUCCESS; + u32 tipg; + u32 i = 0; + u16 reg_data, reg_data2; + + DEBUGFUNC("e1000_configure_kmrn_for_10_100"); + + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) + goto out; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, E1000_TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; + E1000_WRITE_REG(hw, E1000_TIPG, tipg); + + + do { + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + ®_data); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + ®_data2); + if (ret_val) + goto out; + i++; + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); + + if (duplex == HALF_DUPLEX) + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; + else + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + +out: + return (ret_val); +} + +/* + * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation + * @hw: pointer to the HW structure + * + * Configure the KMRN interface by applying last minute quirks for + * gigabit operation. + */ +static s32 +e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 reg_data, reg_data2; + u32 tipg; + u32 i = 0; + + DEBUGFUNC("e1000_configure_kmrn_for_1000"); + + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) + goto out; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, E1000_TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; + E1000_WRITE_REG(hw, E1000_TIPG, tipg); + + + do { + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + ®_data); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + ®_data2); + if (ret_val) + goto out; + i++; + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); + + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + +out: + return (ret_val); +} + +/* + * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); + + temp = E1000_READ_REG(hw, E1000_MGTPRC); + temp = E1000_READ_REG(hw, E1000_MGTPDC); + temp = E1000_READ_REG(hw, E1000_MGTPTC); + + temp = E1000_READ_REG(hw, E1000_IAC); + temp = E1000_READ_REG(hw, E1000_ICRXOC); + + temp = E1000_READ_REG(hw, E1000_ICRXPTC); + temp = E1000_READ_REG(hw, E1000_ICRXATC); + temp = E1000_READ_REG(hw, E1000_ICTXPTC); + temp = E1000_READ_REG(hw, E1000_ICTXATC); + temp = E1000_READ_REG(hw, E1000_ICTXQEC); + temp = E1000_READ_REG(hw, E1000_ICTXQMTC); + temp = E1000_READ_REG(hw, E1000_ICRXDMTC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_80003es2lan.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,105 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_80003ES2LAN_H_ +#define _E1000_80003ES2LAN_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 + +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 + +#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 + +/* Gigabit Carry Extend Padding */ +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 + +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 + +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 + +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */ +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ + +/* PHY Specific Control Register 2 (Page 0, Register 26) */ +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 + /* 1=Reverse Auto-Negotiation */ + +/* MAC Specific Control Register (Page 2, Register 21) */ +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ +#define GG82563_MSCR_TX_CLK_MASK 0x0007 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 +#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 +#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006 +#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 + +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ + +/* DSP Distance Register (Page 5, Register 26) */ +/* + * 0 = <50M + * 1 = 50-80M + * 2 = 80-100M + * 3 = 110-140M + * 4 = >140M + */ +#define GG82563_DSPD_CABLE_LENGTH 0x0007 + +/* Kumeran Mode Control Register (Page 193, Register 16) */ +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 + +/* Max number of times Kumeran read/write should be validated */ +#define GG82563_MAX_KMRN_RETRY 0x5 + +/* Power Management Control Register (Page 193, Register 20) */ +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 + /* 1=Enable SERDES Electrical Idle */ + +/* In-Band Control Register (Page 194, Register 18) */ +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_80003ES2LAN_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82540.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,676 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_82540 + * e1000_82545 + * e1000_82546 + * e1000_82545_rev_3 + * e1000_82546_rev_3 + */ + +#include "e1000_api.h" + +void e1000_init_function_pointers_82540(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_82540(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw); +static s32 e1000_init_mac_params_82540(struct e1000_hw *hw); +static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw); +static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw); +static s32 e1000_init_hw_82540(struct e1000_hw *hw); +static s32 e1000_reset_hw_82540(struct e1000_hw *hw); +static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw); +static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw); +static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw); + +/* + * e1000_init_phy_params_82540 - Init PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_82540(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 10000; + phy->type = e1000_phy_m88; + + /* Function Pointers */ + func->check_polarity = e1000_check_polarity_m88; + func->commit_phy = e1000_phy_sw_reset_generic; + func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; + func->get_cable_length = e1000_get_cable_length_m88; + func->get_cfg_done = e1000_get_cfg_done_generic; + func->read_phy_reg = e1000_read_phy_reg_m88; + func->reset_phy = e1000_phy_hw_reset_generic; + func->write_phy_reg = e1000_write_phy_reg_m88; + func->get_phy_info = e1000_get_phy_info_m88; + + ret_val = e1000_get_phy_id(hw); + if (ret_val) + goto out; + + /* Verify phy id */ + switch (hw->mac.type) { + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + if (phy->id == M88E1011_I_PHY_ID) + break; + /* Fall Through */ + default: + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_82540 - Init NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_82540(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + + DEBUGFUNC("e1000_init_nvm_params_82540"); + + nvm->type = e1000_nvm_eeprom_microwire; + nvm->delay_usec = 50; + nvm->opcode_bits = 3; + switch (nvm->override) { + case e1000_nvm_override_microwire_large: + nvm->address_bits = 8; + nvm->word_size = 256; + break; + case e1000_nvm_override_microwire_small: + nvm->address_bits = 6; + nvm->word_size = 64; + break; + default: + nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; + nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; + break; + } + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_nvm_generic; + func->read_nvm = e1000_read_nvm_microwire; + func->release_nvm = e1000_release_nvm_generic; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->valid_led_default = e1000_valid_led_default_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + func->write_nvm = e1000_write_nvm_microwire; + + return (E1000_SUCCESS); +} + +/* + * e1000_init_mac_params_82540 - Init MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_82540(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_mac_params_82540"); + + /* Set media type */ + switch (hw->device_id) { + case E1000_DEV_ID_82545EM_FIBER: + case E1000_DEV_ID_82545GM_FIBER: + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546GB_FIBER: + hw->media_type = e1000_media_type_fiber; + break; + case E1000_DEV_ID_82545GM_SERDES: + case E1000_DEV_ID_82546GB_SERDES: + hw->media_type = e1000_media_type_internal_serdes; + break; + default: + hw->media_type = e1000_media_type_copper; + break; + } + + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_pci_generic; + /* reset */ + func->reset_hw = e1000_reset_hw_82540; + /* hw initialization */ + func->init_hw = e1000_init_hw_82540; + /* link setup */ + func->setup_link = e1000_setup_link_generic; + /* physical interface setup */ + func->setup_physical_interface = + (hw->media_type == e1000_media_type_copper) + ? e1000_setup_copper_link_82540 + : e1000_setup_fiber_serdes_link_82540; + /* check for link */ + switch (hw->media_type) { + case e1000_media_type_copper: + func->check_for_link = e1000_check_for_copper_link_generic; + break; + case e1000_media_type_fiber: + func->check_for_link = e1000_check_for_fiber_link_generic; + break; + case e1000_media_type_internal_serdes: + func->check_for_link = e1000_check_for_serdes_link_generic; + break; + default: + ret_val = -E1000_ERR_CONFIG; + goto out; + } + /* link info */ + func->get_link_up_info = + (hw->media_type == e1000_media_type_copper) + ? e1000_get_speed_and_duplex_copper_generic + : e1000_get_speed_and_duplex_fiber_serdes_generic; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_generic; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* setup LED */ + func->setup_led = e1000_setup_led_generic; + /* cleanup LED */ + func->cleanup_led = e1000_cleanup_led_generic; + /* turn on/off LED */ + func->led_on = e1000_led_on_generic; + func->led_off = e1000_led_off_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_82540; + +out: + return (ret_val); +} + +/* + * e1000_init_function_pointers_82540 - Init func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_82540(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_82540"); + + hw->func.init_mac_params = e1000_init_mac_params_82540; + hw->func.init_nvm_params = e1000_init_nvm_params_82540; + hw->func.init_phy_params = e1000_init_phy_params_82540; +} + +/* + * e1000_reset_hw_82540 - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_82540(struct e1000_hw *hw) +{ + u32 ctrl, icr, manc; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_reset_hw_82540"); + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + /* + * Delay to allow any outstanding PCI transactions to complete + * before resetting the device. + */ + msec_delay(10); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n"); + switch (hw->mac.type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST); + break; + default: + /* + * These controllers can't ack the 64-bit write when + * issuing the reset, so we use IO-mapping as a + * workaround to issue the reset. + */ + E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + break; + } + + /* Wait for EEPROM reload */ + msec_delay(5); + + /* Disable HW ARPs on ASF enabled adapters */ + manc = E1000_READ_REG(hw, E1000_MANC); + manc &= ~E1000_MANC_ARP_EN; + E1000_WRITE_REG(hw, E1000_MANC, manc); + + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + + return (ret_val); +} + +/* + * e1000_init_hw_82540 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_init_hw_82540(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 txdctl, ctrl_ext; + s32 ret_val = E1000_SUCCESS; + u16 i; + + DEBUGFUNC("e1000_init_hw_82540"); + + /* Initialize identification LED */ + ret_val = e1000_id_led_init_generic(hw); + if (ret_val) { + DEBUGOUT("Error initializing identification LED\n"); + goto out; + } + + /* Disabling VLAN filtering */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + if (mac->type < e1000_82545_rev_3) + E1000_WRITE_REG(hw, E1000_VET, 0); + + e1000_clear_vfta(hw); + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) { + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + /* + * Avoid back to back register writes by adding the register + * read (flush). This is to protect against some strange + * bridge configurations that may issue Memory Write Block + * (MWB) to our register space. The *_rev_3 hardware at + * least doesn't respond correctly to every other dword in an + * MWB to our register space. + */ + E1000_WRITE_FLUSH(hw); + } + + if (mac->type < e1000_82545_rev_3) + e1000_pcix_mmrbc_workaround_generic(hw); + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + txdctl = E1000_READ_REG(hw, E1000_TXDCTL); + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_82540(hw); + + if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) || + (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) { + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + /* + * Relaxed ordering must be disabled to avoid a parity + * error crash in a PCI slot. + */ + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + } + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_82540 - Configure copper link settings + * @hw: pointer to the HW structure + * + * Calls the appropriate function to configure the link for auto-neg or forced + * speed and duplex. Then we check for link, once link is established calls + * to configure collision distance and flow control are called. If link is + * not established, we return -E1000_ERR_PHY (-2). This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_setup_copper_link_82540(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_setup_copper_link_82540"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + ret_val = e1000_set_phy_mode_82540(hw); + if (ret_val) + goto out; + + if (hw->mac.type == e1000_82545_rev_3 || + hw->mac.type == e1000_82546_rev_3) { + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &data); + if (ret_val) + goto out; + data |= 0x00000008; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, data); + if (ret_val) + goto out; + } + + ret_val = e1000_copper_link_setup_m88(hw); + if (ret_val) + goto out; + + ret_val = e1000_setup_copper_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes + * @hw: pointer to the HW structure + * + * Set the output amplitude to the value in the EEPROM and adjust the VCO + * speed to improve Bit Error Rate (BER) performance. Configures collision + * distance and flow control for fiber and serdes links. Upon successful + * setup, poll for link. This is a function pointer entry point called by + * the api module. + */ +static s32 +e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_fiber_serdes_link_82540"); + + switch (mac->type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + if (hw->media_type == e1000_media_type_internal_serdes) { + /* + * If we're on serdes media, adjust the output + * amplitude to value set in the EEPROM. + */ + ret_val = e1000_adjust_serdes_amplitude_82540(hw); + if (ret_val) + goto out; + } + /* Adjust VCO speed to improve BER performance */ + ret_val = e1000_set_vco_speed_82540(hw); + if (ret_val) + goto out; + default: + break; + } + + ret_val = e1000_setup_fiber_serdes_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM + * @hw: pointer to the HW structure + * + * Adjust the SERDES ouput amplitude based on the EEPROM settings. + */ +static s32 +e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 nvm_data; + + DEBUGFUNC("e1000_adjust_serdes_amplitude_82540"); + + ret_val = e1000_read_nvm(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); + if (ret_val) + goto out; + + if (nvm_data != NVM_RESERVED_WORD) { + /* Adjust serdes output amplitude only. */ + nvm_data &= NVM_SERDES_AMPLITUDE_MASK; + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_EXT_CTRL, + nvm_data); + if (ret_val) + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_set_vco_speed_82540 - Set VCO speed for better performance + * @hw: pointer to the HW structure + * + * Set the VCO speed to improve Bit Error Rate (BER) performance. + */ +static s32 +e1000_set_vco_speed_82540(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 default_page = 0; + u16 phy_data; + + DEBUGFUNC("e1000_set_vco_speed_82540"); + + /* Set PHY register 30, page 5, bit 8 to 0 */ + + ret_val = e1000_read_phy_reg(hw, + M88E1000_PHY_PAGE_SELECT, + &default_page); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); + if (ret_val) + goto out; + + /* Set PHY register 30, page 4, bit 11 to 1 */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); + if (ret_val) + goto out; + + phy_data |= M88E1000_PHY_VCO_REG_BIT11; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, + default_page); + +out: + return (ret_val); +} + +/* + * e1000_set_phy_mode_82540 - Set PHY to class A mode + * @hw: pointer to the HW structure + * + * Sets the PHY to class A mode and assumes the following operations will + * follow to enable the new class mode: + * 1. Do a PHY soft reset. + * 2. Restart auto-negotiation or force link. + */ +static s32 +e1000_set_phy_mode_82540(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + u16 nvm_data; + + DEBUGFUNC("e1000_set_phy_mode_82540"); + + if (hw->mac.type != e1000_82545_rev_3) + goto out; + + ret_val = e1000_read_nvm(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); + if (ret_val) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, + 0x000B); + if (ret_val) { + ret_val = -E1000_ERR_PHY; + goto out; + } + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_GEN_CONTROL, + 0x8104); + if (ret_val) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + phy->reset_disable = FALSE; + } + +out: + return (ret_val); +} + +/* + * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_82540(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_82540"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); + + temp = E1000_READ_REG(hw, E1000_MGTPRC); + temp = E1000_READ_REG(hw, E1000_MGTPDC); + temp = E1000_READ_REG(hw, E1000_MGTPTC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82541.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1601 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_82541 + * e1000_82547 + * e1000_82541_rev_2 + * e1000_82547_rev_2 + */ + +#include "e1000_api.h" +#include "e1000_82541.h" + +void e1000_init_function_pointers_82541(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); +static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); +static s32 e1000_reset_hw_82541(struct e1000_hw *hw); +static s32 e1000_init_hw_82541(struct e1000_hw *hw); +static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, + u16 *duplex); +static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); +static s32 e1000_check_for_link_82541(struct e1000_hw *hw); +static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); +static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, + boolean_t active); +static s32 e1000_setup_led_82541(struct e1000_hw *hw); +static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); +static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); +static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, + boolean_t link_up); +static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); + +static const u16 e1000_igp_cable_length_table[] = +{5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, +5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, +25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, +40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, +60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, +90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, +100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, +110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; + +#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ + (sizeof (e1000_igp_cable_length_table) / \ + sizeof (e1000_igp_cable_length_table[0])) + +struct e1000_dev_spec_82541 { + e1000_dsp_config dsp_config; + e1000_ffe_config ffe_config; +#ifndef FIFO_WORKAROUND + u32 tx_fifo_head; + u32 tx_fifo_start; + u32 tx_fifo_size; + u16 dsp_reset_counter; +#endif + u16 spd_default; + boolean_t phy_init_script; +#ifndef FIFO_WORKAROUND + boolean_t ttl_workaround; +#endif +}; + +/* + * e1000_init_phy_params_82541 - Init PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_82541(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_phy_params_82541"); + + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 10000; + phy->type = e1000_phy_igp; + + /* Function Pointers */ + func->check_polarity = e1000_check_polarity_igp; + func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; + func->get_cable_length = e1000_get_cable_length_igp_82541; + func->get_cfg_done = e1000_get_cfg_done_generic; + func->get_phy_info = e1000_get_phy_info_igp; + func->read_phy_reg = e1000_read_phy_reg_igp; + func->reset_phy = e1000_phy_hw_reset_82541; + func->set_d3_lplu_state = e1000_set_d3_lplu_state_82541; + func->write_phy_reg = e1000_write_phy_reg_igp; + + ret_val = e1000_get_phy_id(hw); + if (ret_val) + goto out; + + /* Verify phy id */ + if (phy->id != IGP01E1000_I_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_82541 - Init NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_82541(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u16 size; + + DEBUGFUNC("e1000_init_nvm_params_82541"); + + switch (nvm->override) { + case e1000_nvm_override_spi_large: + nvm->type = e1000_nvm_eeprom_spi; + eecd |= E1000_EECD_ADDR_BITS; + break; + case e1000_nvm_override_spi_small: + nvm->type = e1000_nvm_eeprom_spi; + eecd &= ~E1000_EECD_ADDR_BITS; + break; + case e1000_nvm_override_microwire_large: + nvm->type = e1000_nvm_eeprom_microwire; + eecd |= E1000_EECD_SIZE; + break; + case e1000_nvm_override_microwire_small: + nvm->type = e1000_nvm_eeprom_microwire; + eecd &= ~E1000_EECD_SIZE; + break; + default: + nvm->type = eecd & E1000_EECD_TYPE + ? e1000_nvm_eeprom_spi + : e1000_nvm_eeprom_microwire; + break; + } + + if (nvm->type == e1000_nvm_eeprom_spi) { + nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) + ? 16 : 8; + nvm->delay_usec = 1; + nvm->opcode_bits = 8; + nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) + ? 32 : 8; + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_nvm_generic; + func->read_nvm = e1000_read_nvm_spi; + func->release_nvm = e1000_release_nvm_generic; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->valid_led_default = e1000_valid_led_default_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + func->write_nvm = e1000_write_nvm_spi; + + /* + * nvm->word_size must be discovered after the pointers + * are set so we can verify the size from the nvm image + * itself. Temporarily set it to a dummy value so the + * read will work. + */ + nvm->word_size = 64; + ret_val = e1000_read_nvm(hw, NVM_CFG, 1, &size); + if (ret_val) + goto out; + size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; + /* + * if size != 0, it can be added to a constant and become + * the left-shift value to set the word_size. Otherwise, + * word_size stays at 64. + */ + if (size) { + size += NVM_WORD_SIZE_BASE_SHIFT_82541; + nvm->word_size = 1 << size; + } + } else { + nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) + ? 8 : 6; + nvm->delay_usec = 50; + nvm->opcode_bits = 3; + nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) + ? 256 : 64; + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_nvm_generic; + func->read_nvm = e1000_read_nvm_microwire; + func->release_nvm = e1000_release_nvm_generic; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->valid_led_default = e1000_valid_led_default_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + func->write_nvm = e1000_write_nvm_microwire; + } + +out: + return (ret_val); +} + +/* + * e1000_init_mac_params_82541 - Init MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_82541(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val; + + DEBUGFUNC("e1000_init_mac_params_82541"); + + /* Set media type */ + hw->media_type = e1000_media_type_copper; + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + /* Set if part includes ASF firmware */ + mac->asf_firmware_present = TRUE; + + /* Function Pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_pci_generic; + /* reset */ + func->reset_hw = e1000_reset_hw_82541; + /* hw initialization */ + func->init_hw = e1000_init_hw_82541; + /* link setup */ + func->setup_link = e1000_setup_link_generic; + /* physical interface link setup */ + func->setup_physical_interface = e1000_setup_copper_link_82541; + /* check for link */ + func->check_for_link = e1000_check_for_link_82541; + /* link info */ + func->get_link_up_info = e1000_get_link_up_info_82541; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_generic; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* setup LED */ + func->setup_led = e1000_setup_led_82541; + /* cleanup LED */ + func->cleanup_led = e1000_cleanup_led_82541; + /* turn on/off LED */ + func->led_on = e1000_led_on_generic; + func->led_off = e1000_led_off_generic; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_82541; + + hw->dev_spec_size = sizeof (struct e1000_dev_spec_82541); + + /* Device-specific structure allocation */ + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); + + return (ret_val); +} + +/* + * e1000_init_function_pointers_82541 - Init func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_82541(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_82541"); + + hw->func.init_mac_params = e1000_init_mac_params_82541; + hw->func.init_nvm_params = e1000_init_nvm_params_82541; + hw->func.init_phy_params = e1000_init_phy_params_82541; +} + +/* + * e1000_reset_hw_82541 - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_82541(struct e1000_hw *hw) +{ +#ifndef FIFO_WORKAROUND + struct e1000_dev_spec_82541 *dev_spec; +#endif + u32 ledctl, ctrl, icr, manc; + + DEBUGFUNC("e1000_reset_hw_82541"); + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + +#ifndef FIFO_WORKAROUND + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + dev_spec->tx_fifo_head = 0; + +#endif + /* + * Delay to allow any outstanding PCI transactions to complete + * before resetting the device. + */ + msec_delay(10); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* Must reset the Phy before resetting the MAC */ + if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); + msec_delay(5); + } + + DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); + switch (hw->mac.type) { + case e1000_82541: + case e1000_82541_rev_2: + /* + * These controllers can't ack the 64-bit write when + * issuing the reset, so we use IO-mapping as a + * workaround to issue the reset. + */ + E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + break; + default: + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + break; + } + + /* Wait for NVM reload */ + msec_delay(20); + + /* Disable HW ARPs on ASF enabled adapters */ + manc = E1000_READ_REG(hw, E1000_MANC); + manc &= ~E1000_MANC_ARP_EN; + E1000_WRITE_REG(hw, E1000_MANC, manc); + + if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { + e1000_phy_init_script_82541(hw); + + /* Configure activity LED after Phy reset */ + ledctl = E1000_READ_REG(hw, E1000_LEDCTL); + ledctl &= IGP_ACTIVITY_LED_MASK; + ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); + } + + /* Once again, mask the interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); + + /* Clear any pending interrupt events. */ + icr = E1000_READ_REG(hw, E1000_ICR); + + return (E1000_SUCCESS); +} + +/* + * e1000_init_hw_82541 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_init_hw_82541(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; +#ifndef FIFO_WORKAROUND + struct e1000_dev_spec_82541 *dev_spec; + u32 pba; +#endif + u32 i, txdctl; + s32 ret_val; + + DEBUGFUNC("e1000_init_hw_82541"); + + /* Initialize identification LED */ + ret_val = e1000_id_led_init_generic(hw); + if (ret_val) { + DEBUGOUT("Error initializing identification LED\n"); + goto out; + } + +#ifndef FIFO_WORKAROUND + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + pba = E1000_READ_REG(hw, E1000_PBA); + dev_spec->tx_fifo_start = (pba & 0x0000FFFF) * E1000_FIFO_MULTIPLIER; + dev_spec->tx_fifo_size = (pba & 0xFFFF0000) >> 6; + +#endif + /* Disabling VLAN filtering */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + e1000_clear_vfta(hw); + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) { + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + /* + * Avoid back to back register writes by adding the register + * read (flush). This is to protect against some strange + * bridge configurations that may issue Memory Write Block + * (MWB) to our register space. + */ + E1000_WRITE_FLUSH(hw); + } + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + txdctl = E1000_READ_REG(hw, E1000_TXDCTL); + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_82541(hw); + +out: + return (ret_val); +} + +/* + * e1000_get_link_up_info_82541 - Report speed and duplex + * @hw: pointer to the HW structure + * @speed: pointer to speed buffer + * @duplex: pointer to duplex buffer + * + * Retrieve the current speed and duplex configuration. + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, u16 *duplex) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_get_link_up_info_82541"); + + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); + if (ret_val) + goto out; + + if (!phy->speed_downgraded) + goto out; + + /* + * IGP01 PHY may advertise full duplex operation after speed + * downgrade even if it is operating at half duplex. + * Here we set the duplex settings to match the duplex in the + * link partner's capabilities. + */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &data); + if (ret_val) + goto out; + + if (!(data & NWAY_ER_LP_NWAY_CAPS)) { + *duplex = HALF_DUPLEX; + } else { + ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &data); + if (ret_val) + goto out; + + if (*speed == SPEED_100) { + if (!(data & NWAY_LPAR_100TX_FD_CAPS)) + *duplex = HALF_DUPLEX; + } else if (*speed == SPEED_10) { + if (!(data & NWAY_LPAR_10T_FD_CAPS)) + *duplex = HALF_DUPLEX; + } + } + +out: + return (ret_val); +} + +/* + * e1000_phy_hw_reset_82541 - PHY hardware reset + * @hw: pointer to the HW structure + * + * Verify the reset block is not blocking us from resetting. Acquire + * semaphore (if necessary) and read/set/write the device control reset + * bit in the PHY. Wait the appropriate delay time for the device to + * reset and relase the semaphore (if necessary). + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_phy_hw_reset_82541(struct e1000_hw *hw) +{ + s32 ret_val; + u32 ledctl; + + DEBUGFUNC("e1000_phy_hw_reset_82541"); + + ret_val = e1000_phy_hw_reset_generic(hw); + if (ret_val) + goto out; + + e1000_phy_init_script_82541(hw); + + if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { + /* Configure activity LED after PHY reset */ + ledctl = E1000_READ_REG(hw, E1000_LEDCTL); + ledctl &= IGP_ACTIVITY_LED_MASK; + ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); + } + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_82541 - Configure copper link settings + * @hw: pointer to the HW structure + * + * Calls the appropriate function to configure the link for auto-neg or forced + * speed and duplex. Then we check for link, once link is established calls + * to configure collision distance and flow control are called. If link is + * not established, we return -E1000_ERR_PHY (-2). This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_setup_copper_link_82541(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_dev_spec_82541 *dev_spec; + s32 ret_val; + u32 ctrl, ledctl; + + DEBUGFUNC("e1000_setup_copper_link_82541"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + hw->phy.reset_disable = FALSE; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + /* Earlier revs of the IGP phy require us to force MDI. */ + if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { + dev_spec->dsp_config = e1000_dsp_config_disabled; + phy->mdix = 1; + } else { + dev_spec->dsp_config = e1000_dsp_config_enabled; + } + + ret_val = e1000_copper_link_setup_igp(hw); + if (ret_val) + goto out; + + if (hw->mac.autoneg) { + if (dev_spec->ffe_config == e1000_ffe_config_active) + dev_spec->ffe_config = e1000_ffe_config_enabled; + } + + /* Configure activity LED after Phy reset */ + ledctl = E1000_READ_REG(hw, E1000_LEDCTL); + ledctl &= IGP_ACTIVITY_LED_MASK; + ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); + + ret_val = e1000_setup_copper_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_check_for_link_82541 - Check/Store link connection + * @hw: pointer to the HW structure + * + * This checks the link condition of the adapter and stores the + * results in the hw->mac structure. This is a function pointer entry + * point called by the api module. + */ +static s32 +e1000_check_for_link_82541(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + boolean_t link; + + DEBUGFUNC("e1000_check_for_link_82541"); + + /* + * We only want to go out to the PHY registers to see if Auto-Neg + * has completed and/or if our link status has changed. The + * get_link_status flag is set upon receiving a Link Status + * Change or Rx Sequence Error interrupt. + */ + if (!mac->get_link_status) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* + * First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex + * of the PHY. + */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { + ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); + goto out; /* No link detected */ + } + + mac->get_link_status = FALSE; + + /* + * Check if there was DownShift, must be checked + * immediately after link-up + */ + e1000_check_downshift_generic(hw); + + /* + * If we are forcing speed/duplex, then we simply return since + * we have already determined whether we have link or not. + */ + if (!mac->autoneg) { + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); + + /* + * Auto-Neg is enabled. Auto Speed Detection takes care + * of MAC speed/duplex configuration. So we only need to + * configure Collision Distance in the MAC. + */ + e1000_config_collision_dist_generic(hw); + + /* + * Configure Flow Control now that Auto-Neg has completed. + * First, we need to restore the desired flow control + * settings because we may have had to re-autoneg with a + * different link partner. + */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_config_dsp_after_link_change_82541 - Config DSP after link + * @hw: pointer to the HW structure + * @link_up: boolean flag for link up status + * + * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS + * at any other case. + * + * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a + * gigabit link is achieved to improve link quality. + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, + boolean_t link_up) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_dev_spec_82541 *dev_spec; + s32 ret_val; + u32 idle_errs = 0; + u16 phy_data, phy_saved_data, speed, duplex, i; + u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; + u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + {IGP01E1000_PHY_AGC_PARAM_A, + IGP01E1000_PHY_AGC_PARAM_B, + IGP01E1000_PHY_AGC_PARAM_C, + IGP01E1000_PHY_AGC_PARAM_D}; + + DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + if (link_up) { + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + goto out; + } + + if (speed != SPEED_1000) { + ret_val = E1000_SUCCESS; + goto out; + } + + ret_val = e1000_get_cable_length(hw); + if (ret_val) + goto out; + + if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && + phy->min_cable_length >= 50) { + + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, + dsp_reg_array[i], + &phy_data); + if (ret_val) + goto out; + + phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; + + ret_val = e1000_write_phy_reg(hw, + dsp_reg_array[i], + phy_data); + if (ret_val) + goto out; + } + dev_spec->dsp_config = e1000_dsp_config_activated; + } + + if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || + (phy->min_cable_length >= 50)) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* clear previous idle error counts */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) + goto out; + + for (i = 0; i < ffe_idle_err_timeout; i++) { + usec_delay(1000); + ret_val = e1000_read_phy_reg(hw, + PHY_1000T_STATUS, + &phy_data); + if (ret_val) + goto out; + + idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); + if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { + dev_spec->ffe_config = e1000_ffe_config_active; + + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_DSP_FFE, + IGP01E1000_PHY_DSP_FFE_CM_CP); + if (ret_val) + goto out; + break; + } + + if (idle_errs) + ffe_idle_err_timeout = + FFE_IDLE_ERR_COUNT_TIMEOUT_100; + } + } else { + if (dev_spec->dsp_config == e1000_dsp_config_activated) { + /* + * Save off the current value of register 0x2F5B + * to be restored at the end of the routines. + */ + ret_val = e1000_read_phy_reg(hw, + 0x2F5B, + &phy_saved_data); + if (ret_val) + goto out; + + /* Disable the PHY transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + if (ret_val) + goto out; + + msec_delay_irq(20); + + ret_val = e1000_write_phy_reg(hw, + 0x0000, + IGP01E1000_IEEE_FORCE_GIG); + if (ret_val) + goto out; + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, + dsp_reg_array[i], + &phy_data); + if (ret_val) + goto out; + + phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; + phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; + + ret_val = e1000_write_phy_reg(hw, + dsp_reg_array[i], + phy_data); + if (ret_val) + goto out; + } + + ret_val = e1000_write_phy_reg(hw, + 0x0000, + IGP01E1000_IEEE_RESTART_AUTONEG); + if (ret_val) + goto out; + + msec_delay_irq(20); + + /* Now enable the transmitter */ + ret_val = e1000_write_phy_reg(hw, + 0x2F5B, + phy_saved_data); + if (ret_val) + goto out; + + dev_spec->dsp_config = e1000_dsp_config_enabled; + } + + if (dev_spec->ffe_config != e1000_ffe_config_active) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* + * Save off the current value of register 0x2F5B + * to be restored at the end of the routines. + */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + if (ret_val) + goto out; + + /* Disable the PHY transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + if (ret_val) + goto out; + + msec_delay_irq(20); + + ret_val = e1000_write_phy_reg(hw, + 0x0000, + IGP01E1000_IEEE_FORCE_GIG); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_DSP_FFE, + IGP01E1000_PHY_DSP_FFE_DEFAULT); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, + 0x0000, + IGP01E1000_IEEE_RESTART_AUTONEG); + if (ret_val) + goto out; + + msec_delay_irq(20); + + /* Now enable the transmitter */ + ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (ret_val) + goto out; + + dev_spec->ffe_config = e1000_ffe_config_enabled; + } + +out: + return (ret_val); +} + +/* + * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY + * @hw: pointer to the HW structure + * + * The automatic gain control (agc) normalizes the amplitude of the + * received signal, adjusting for the attenuation produced by the + * cable. By reading the AGC registers, which reperesent the + * cobination of course and fine gain value, the value can be put + * into a lookup table to obtain the approximate cable length + * for each channel. This is a function pointer entry point called by the + * api module. + */ +static s32 +e1000_get_cable_length_igp_82541(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + u16 i, data; + u16 cur_agc_value, agc_value = 0; + u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; + u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + {IGP01E1000_PHY_AGC_A, + IGP01E1000_PHY_AGC_B, + IGP01E1000_PHY_AGC_C, + IGP01E1000_PHY_AGC_D}; + + DEBUGFUNC("e1000_get_cable_length_igp_82541"); + + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &data); + if (ret_val) + goto out; + + cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; + + /* Bounds checking */ + if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || + (cur_agc_value == 0)) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + agc_value += cur_agc_value; + + if (min_agc_value > cur_agc_value) + min_agc_value = cur_agc_value; + } + + /* Remove the minimal AGC result for length < 50m */ + if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { + agc_value -= min_agc_value; + /* Average the three remaining channels for the length. */ + agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); + } else { + /* Average the channels for the length. */ + agc_value /= IGP01E1000_PHY_CHANNEL_NUM; + } + + phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > + IGP01E1000_AGC_RANGE) + ? (e1000_igp_cable_length_table[agc_value] - + IGP01E1000_AGC_RANGE) + : 0; + phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + + IGP01E1000_AGC_RANGE; + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +out: + return (ret_val); +} + +/* + * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * Success returns 0, Failure returns 1 + * + * The low power link up (lplu) state is set to the power management level D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. This is a function pointer entry point called by the + * api module. + */ +static s32 +e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, boolean_t active) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_set_d3_lplu_state_82541"); + + switch (hw->mac.type) { + case e1000_82541_rev_2: + case e1000_82547_rev_2: + break; + default: + ret_val = e1000_set_d3_lplu_state_generic(hw, active); + goto out; + } + + ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &data); + if (ret_val) + goto out; + + if (!active) { + data &= ~IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); + if (ret_val) + goto out; + + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); + if (ret_val) + goto out; + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + } + +out: + return (ret_val); +} + +/* + * e1000_setup_led_82541 - Configures SW controllable LED + * @hw: pointer to the HW structure + * + * This prepares the SW controllable LED for use and saves the current state + * of the LED so it can be later restored. This is a function pointer entry + * point called by the api module. + */ +static s32 +e1000_setup_led_82541(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82541 *dev_spec; + s32 ret_val; + + DEBUGFUNC("e1000_setup_led_82541"); + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_GMII_FIFO, + &dev_spec->spd_default); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_GMII_FIFO, + (u16)(dev_spec->spd_default & + ~IGP01E1000_GMII_SPD)); + if (ret_val) + goto out; + + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); + +out: + return (ret_val); +} + +/* + * e1000_cleanup_led_82541 - Set LED config to default operation + * @hw: pointer to the HW structure + * + * Remove the current LED configuration and set the LED configuration + * to the default value, saved from the EEPROM. This is a function pointer + * entry point called by the api module. + */ +static s32 +e1000_cleanup_led_82541(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82541 *dev_spec; + s32 ret_val; + + DEBUGFUNC("e1000_cleanup_led_82541"); + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_GMII_FIFO, + dev_spec->spd_default); + if (ret_val) + goto out; + + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); + +out: + return (ret_val); +} + +/* + * e1000_phy_init_script_82541 - Initialize GbE PHY + * @hw: pointer to the HW structure + * + * Initializes the IGP PHY. + */ +static s32 +e1000_phy_init_script_82541(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82541 *dev_spec; + u32 ret_val; + u16 phy_saved_data; + + DEBUGFUNC("e1000_phy_init_script_82541"); + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + if (!dev_spec->phy_init_script) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* Delay after phy reset to enable NVM configuration to load */ + msec_delay(20); + + /* + * Save off the current value of register 0x2F5B to be restored at + * the end of this routine. + */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + + /* Disabled the PHY transmitter */ + e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + + msec_delay(20); + + e1000_write_phy_reg(hw, 0x0000, 0x0140); + + msec_delay(5); + + switch (hw->mac.type) { + case e1000_82541: + case e1000_82547: + e1000_write_phy_reg(hw, 0x1F95, 0x0001); + + e1000_write_phy_reg(hw, 0x1F71, 0xBD21); + + e1000_write_phy_reg(hw, 0x1F79, 0x0018); + + e1000_write_phy_reg(hw, 0x1F30, 0x1600); + + e1000_write_phy_reg(hw, 0x1F31, 0x0014); + + e1000_write_phy_reg(hw, 0x1F32, 0x161C); + + e1000_write_phy_reg(hw, 0x1F94, 0x0003); + + e1000_write_phy_reg(hw, 0x1F96, 0x003F); + + e1000_write_phy_reg(hw, 0x2010, 0x0008); + break; + case e1000_82541_rev_2: + case e1000_82547_rev_2: + e1000_write_phy_reg(hw, 0x1F73, 0x0099); + break; + default: + break; + } + + e1000_write_phy_reg(hw, 0x0000, 0x3300); + + msec_delay(20); + + /* Now enable the transmitter */ + e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (hw->mac.type == e1000_82547) { + u16 fused, fine, coarse; + + /* Move to analog registers page */ + e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_SPARE_FUSE_STATUS, + &fused); + + if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { + e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_STATUS, + &fused); + + fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; + coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; + + if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { + coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; + fine -= IGP01E1000_ANALOG_FUSE_FINE_1; + } else if (coarse == + IGP01E1000_ANALOG_FUSE_COARSE_THRESH) + fine -= IGP01E1000_ANALOG_FUSE_FINE_10; + + fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | + (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | + (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); + + e1000_write_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_CONTROL, + fused); + e1000_write_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_BYPASS, + IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); + } + } + +out: + return (ret_val); +} + +/* + * e1000_init_script_state_82541 - Enable/Disable PHY init script + * @hw: pointer to the HW structure + * @state: boolean value used to enable/disable PHY init script + * + * Allows the driver to enable/disable the PHY init script, if the PHY is an + * IGP PHY. This is a function pointer entry point called by the api module. + */ +void +e1000_init_script_state_82541(struct e1000_hw *hw, boolean_t state) +{ + struct e1000_dev_spec_82541 *dev_spec; + + DEBUGFUNC("e1000_init_script_state_82541"); + + if (hw->phy.type != e1000_phy_igp) { + DEBUGOUT("Initialization script not necessary.\n"); + return; + } + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + return; + } + + dev_spec->phy_init_script = state; +} + +#ifndef FIFO_WORKAROUND +/* + * e1000_fifo_workaround_82547 - Workaround for TX fifo failure + * @hw: pointer to the HW structure + * @length: length of next outgoing frame + * + * Returns: E1000_ERR_FIFO_WRAP if the next packet cannot be transmitted yet + * E1000_SUCCESS if the next packet can be transmitted + * + * Workaround for the 82547 TX fifo failure. + */ +s32 +e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length) +{ + struct e1000_dev_spec_82541 *dev_spec; + u32 tctl; + s32 ret_val = E1000_SUCCESS; + u16 fifo_pkt_len; + + DEBUGFUNC("e1000_fifo_workaround_82547"); + + if (hw->mac.type != e1000_82547) + goto out; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + /* + * Get the length as seen by the FIFO of the next real + * packet to be transmitted. + */ + fifo_pkt_len = E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, + E1000_FIFO_GRANULARITY); + + if (fifo_pkt_len <= (E1000_FIFO_PAD_82547 + E1000_FIFO_HDR_SIZE)) + goto out; + + if ((dev_spec->tx_fifo_head + fifo_pkt_len) < + (dev_spec->tx_fifo_size + E1000_FIFO_PAD_82547)) + goto out; + + if (E1000_READ_REG(hw, E1000_TDT) != E1000_READ_REG(hw, E1000_TDH)) { + ret_val = -E1000_ERR_FIFO_WRAP; + goto out; + } + + if (E1000_READ_REG(hw, E1000_TDFT) != E1000_READ_REG(hw, E1000_TDFH)) { + ret_val = -E1000_ERR_FIFO_WRAP; + goto out; + } + + if (E1000_READ_REG(hw, E1000_TDFTS) != + E1000_READ_REG(hw, E1000_TDFHS)) { + ret_val = -E1000_ERR_FIFO_WRAP; + goto out; + } + + /* Disable the tx unit to avoid further pointer movement */ + tctl = E1000_READ_REG(hw, E1000_TCTL); + E1000_WRITE_REG(hw, E1000_TCTL, tctl & ~E1000_TCTL_EN); + + /* Reset the fifo pointers. */ + E1000_WRITE_REG(hw, E1000_TDFT, dev_spec->tx_fifo_start); + E1000_WRITE_REG(hw, E1000_TDFH, dev_spec->tx_fifo_start); + E1000_WRITE_REG(hw, E1000_TDFTS, dev_spec->tx_fifo_start); + E1000_WRITE_REG(hw, E1000_TDFHS, dev_spec->tx_fifo_start); + + /* Re-enabling tx unit */ + E1000_WRITE_REG(hw, E1000_TCTL, tctl); + E1000_WRITE_FLUSH(hw); + + dev_spec->tx_fifo_head = 0; + +out: + return (ret_val); +} + +/* + * e1000_update_tx_fifo_head - Update TX fifo head pointer + * @hw: pointer to the HW structure + * @length: length of next outgoing frame + * + * Updates the SW calculated TX FIFO head pointer. + */ +void +e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length) +{ + struct e1000_dev_spec_82541 *dev_spec; + + DEBUGFUNC("e1000_update_tx_fifo_head_82547"); + + if (hw->mac.type != e1000_82547) + return; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + dev_spec->tx_fifo_head += E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, + E1000_FIFO_GRANULARITY); + + if (dev_spec->tx_fifo_head > dev_spec->tx_fifo_size) + dev_spec->tx_fifo_head -= dev_spec->tx_fifo_size; +} + +/* + * e1000_set_ttl_workaround_state_82541 - Enable/Disables TTL workaround + * @hw: pointer to the HW structure + * @state: boolean to enable/disable TTL workaround + * + * For 82541 or 82547 only silicon, allows the driver to enable/disable the + * TTL workaround. + */ +void +e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, boolean_t state) +{ + struct e1000_dev_spec_82541 *dev_spec; + + DEBUGFUNC("e1000_set_ttl_workaround_state_82541"); + + if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) + return; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + dev_spec->ttl_workaround = state; +} + +/* + * e1000_ttl_workaround_enabled_82541 - Returns current TTL workaround status + * @hw: pointer to the HW structure + * + * Returns the current status of the TTL workaround, as to whether the + * workaround is enabled or disabled. + */ +boolean_t +e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82541 *dev_spec; + boolean_t state = FALSE; + + DEBUGFUNC("e1000_ttl_workaround_enabled_82541"); + + if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) + goto out; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + state = dev_spec->ttl_workaround; + +out: + return (state); +} + +/* + * e1000_igp_ttl_workaround_82547 - Workaround for long TTL on 100HD hubs + * @hw: pointer to the HW structure + * + * Returns: E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS in any other case + * + * This function, specific to 82547 hardware only, needs to be called every + * second. It checks if a parallel detect fault has occurred. If a fault + * occurred, disable/enable the DSP reset mechanism up to 5 times (once per + * second). If link is established, stop the workaround and ensure the DSP + * reset is enabled. + */ +s32 +e1000_igp_ttl_workaround_82547(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82541 *dev_spec; + s32 ret_val = E1000_SUCCESS; + u16 phy_data = 0; + u16 dsp_value = DSP_RESET_ENABLE; + boolean_t link; + + DEBUGFUNC("e1000_igp_ttl_workaround_82547"); + + /* The workaround needed only for B-0 silicon HW */ + if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) + goto out; + + if (!(e1000_ttl_workaround_enabled_82541(hw))) + goto out; + + dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; + + /* Check for link first */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (link) { + /* + * If link is established during the workaround, + * the DSP mechanism must be enabled. + */ + if (dev_spec->dsp_reset_counter) { + dev_spec->dsp_reset_counter = 0; + dsp_value = DSP_RESET_ENABLE; + } else { + ret_val = E1000_SUCCESS; + goto out; + } + } else { + if (dev_spec->dsp_reset_counter == 0) { + /* + * Workaround not activated, + * check if it needs activation + */ + ret_val = e1000_read_phy_reg(hw, + PHY_AUTONEG_EXP, + &phy_data); + if (ret_val) + goto out; + /* + * Activate the workaround if there was a + * parallel detect fault + */ + if (phy_data & NWAY_ER_PAR_DETECT_FAULT) { + dev_spec->dsp_reset_counter++; + } else { + ret_val = E1000_SUCCESS; + goto out; + } + } + + /* After 5 times, stop the workaround */ + if (dev_spec->dsp_reset_counter > E1000_MAX_DSP_RESETS) { + dev_spec->dsp_reset_counter = 0; + dsp_value = DSP_RESET_ENABLE; + } else { + if (dev_spec->dsp_reset_counter) { + dsp_value = (dev_spec->dsp_reset_counter & 1) + ? DSP_RESET_DISABLE + : DSP_RESET_ENABLE; + dev_spec->dsp_reset_counter++; + } + } + } + + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value); + +out: + return (ret_val); +} + +#endif +/* + * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_82541"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); + + temp = E1000_READ_REG(hw, E1000_MGTPRC); + temp = E1000_READ_REG(hw, E1000_MGTPDC); + temp = E1000_READ_REG(hw, E1000_MGTPTC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82541.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,109 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_82541_H_ +#define _E1000_82541_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) + +#define IGP01E1000_PHY_CHANNEL_NUM 4 + +#define IGP01E1000_PHY_AGC_A 0x1172 +#define IGP01E1000_PHY_AGC_B 0x1272 +#define IGP01E1000_PHY_AGC_C 0x1472 +#define IGP01E1000_PHY_AGC_D 0x1872 + +#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 +#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 +#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 +#define IGP01E1000_PHY_AGC_PARAM_D 0x1871 + +#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 +#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 + +#define IGP01E1000_PHY_DSP_RESET 0x1F33 + +#define IGP01E1000_PHY_DSP_FFE 0x1F35 +#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 +#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A + +#define IGP01E1000_IEEE_FORCE_GIG 0x0140 +#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 + +#define IGP01E1000_AGC_LENGTH_SHIFT 7 +#define IGP01E1000_AGC_RANGE 10 + +#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 +#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 + +#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 +#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 +#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC +#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE + +#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 +#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 +#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 +#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 +#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 +#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 +#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 +#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 +#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 + +#define IGP01E1000_MSE_CHANNEL_D 0x000F +#define IGP01E1000_MSE_CHANNEL_C 0x00F0 +#define IGP01E1000_MSE_CHANNEL_B 0x0F00 +#define IGP01E1000_MSE_CHANNEL_A 0xF000 + +#ifndef FIFO_WORKAROUND +#define E1000_FIFO_MULTIPLIER 0x80 +#define E1000_FIFO_HDR_SIZE 0x10 +#define E1000_FIFO_GRANULARITY 0x10 +#define E1000_FIFO_PAD_82547 0x3E0 +#define E1000_ERR_FIFO_WRAP 8 + +#define DSP_RESET_ENABLE 0x0 +#define DSP_RESET_DISABLE 0x2 +#define E1000_MAX_DSP_RESETS 10 + +#define E1000_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_82541_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82542.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,560 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_82542 (rev 1 & 2) + */ + +#include "e1000_api.h" + +void e1000_init_function_pointers_82542(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); +static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); +static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); +static s32 e1000_reset_hw_82542(struct e1000_hw *hw); +static s32 e1000_init_hw_82542(struct e1000_hw *hw); +static s32 e1000_setup_link_82542(struct e1000_hw *hw); +static s32 e1000_led_on_82542(struct e1000_hw *hw); +static s32 e1000_led_off_82542(struct e1000_hw *hw); +static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); + +struct e1000_dev_spec_82542 { + boolean_t dma_fairness; +}; + +/* + * e1000_init_phy_params_82542 - Init PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_82542(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_phy_params_82542"); + + phy->type = e1000_phy_none; + + return (ret_val); +} + +/* + * e1000_init_nvm_params_82542 - Init NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_82542(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + + DEBUGFUNC("e1000_init_nvm_params_82542"); + + nvm->address_bits = 6; + nvm->delay_usec = 50; + nvm->opcode_bits = 3; + nvm->type = e1000_nvm_eeprom_microwire; + nvm->word_size = 64; + + /* Function Pointers */ + func->read_nvm = e1000_read_nvm_microwire; + func->release_nvm = e1000_stop_nvm; + func->write_nvm = e1000_write_nvm_microwire; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + + return (E1000_SUCCESS); +} + +/* + * e1000_init_mac_params_82542 - Init MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_82542(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_mac_params_82542"); + + /* Set media type */ + hw->media_type = e1000_media_type_fiber; + + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_82542; + /* reset */ + func->reset_hw = e1000_reset_hw_82542; + /* hw initialization */ + func->init_hw = e1000_init_hw_82542; + /* link setup */ + func->setup_link = e1000_setup_link_82542; + /* phy/fiber/serdes setup */ + func->setup_physical_interface = e1000_setup_fiber_serdes_link_generic; + /* check for link */ + func->check_for_link = e1000_check_for_fiber_link_generic; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_generic; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* turn on/off LED */ + func->led_on = e1000_led_on_82542; + func->led_off = e1000_led_off_82542; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_82542; + /* link info */ + func->get_link_up_info = + e1000_get_speed_and_duplex_fiber_serdes_generic; + + hw->dev_spec_size = sizeof (struct e1000_dev_spec_82542); + + /* Device-specific structure allocation */ + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); + + return (ret_val); +} + +/* + * e1000_init_function_pointers_82542 - Init func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_82542(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_82542"); + + hw->func.init_mac_params = e1000_init_mac_params_82542; + hw->func.init_nvm_params = e1000_init_nvm_params_82542; + hw->func.init_phy_params = e1000_init_phy_params_82542; +} + +/* + * e1000_get_bus_info_82542 - Obtain bus information for adapter + * @hw: pointer to the HW structure + * + * This will obtain information about the HW bus for which the + * adaper is attached and stores it in the hw structure. This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_get_bus_info_82542(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_get_bus_info_82542"); + + hw->bus.type = e1000_bus_type_pci; + hw->bus.speed = e1000_bus_speed_unknown; + hw->bus.width = e1000_bus_width_unknown; + + return (E1000_SUCCESS); +} + +/* + * e1000_reset_hw_82542 - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_82542(struct e1000_hw *hw) +{ + struct e1000_bus_info *bus = &hw->bus; + s32 ret_val = E1000_SUCCESS; + u32 ctrl, icr; + + DEBUGFUNC("e1000_reset_hw_82542"); + + if (hw->revision_id == E1000_REVISION_2) { + DEBUGOUT("Disabling MWI on 82542 rev 2\n"); + e1000_pci_clear_mwi(hw); + } + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + /* + * Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + msec_delay(10); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + + e1000_reload_nvm(hw); + msec_delay(2); + + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + + if (hw->revision_id == E1000_REVISION_2) { + if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + e1000_pci_set_mwi(hw); + } + return (ret_val); +} + +/* + * e1000_init_hw_82542 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_init_hw_82542(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_dev_spec_82542 *dev_spec; + s32 ret_val = E1000_SUCCESS; + u32 ctrl; + u16 i; + + DEBUGFUNC("e1000_init_hw_82542"); + + dev_spec = (struct e1000_dev_spec_82542 *)hw->dev_spec; + + /* Disabling VLAN filtering */ + E1000_WRITE_REG(hw, E1000_VET, 0); + e1000_clear_vfta(hw); + + /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ + if (hw->revision_id == E1000_REVISION_2) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + e1000_pci_clear_mwi(hw); + E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); + E1000_WRITE_FLUSH(hw); + msec_delay(5); + } + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ + if (hw->revision_id == E1000_REVISION_2) { + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_FLUSH(hw); + msec_delay(1); + if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + e1000_pci_set_mwi(hw); + } + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* + * Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. + */ + if (dev_spec->dma_fairness) { + ctrl = E1000_READ_REG(hw, E1000_CTRL); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); + } + + /* Setup link and flow control */ + ret_val = e1000_setup_link_82542(hw); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_82542(hw); + + return (ret_val); +} + +/* + * e1000_setup_link_82542 - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow + * control. Calls the appropriate media-specific link configuration + * function. Assuming the adapter has a valid link partner, a valid link + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. This is a function + * pointer entry point called by the api module. + */ +static s32 +e1000_setup_link_82542(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_link_82542"); + + ret_val = e1000_set_default_fc_generic(hw); + if (ret_val) + goto out; + + mac->fc &= ~e1000_fc_tx_pause; + + if (mac->report_tx_early == 1) + mac->fc &= ~e1000_fc_rx_pause; + + /* + * We want to save off the original Flow Control configuration just in + * case we get disconnected and then reconnected into a different hub + * or switch with different Flow Control capabilities. + */ + mac->original_fc = mac->fc; + + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); + + /* Call the necessary subroutine to configure the link. */ + ret_val = func->setup_physical_interface(hw); + if (ret_val) + goto out; + + /* + * Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); + + E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); + E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); + + E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); + + ret_val = e1000_set_fc_watermarks_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_led_on_82542 - Turn on SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED on. This is a function pointer entry point + * called by the api module. + */ +static s32 +e1000_led_on_82542(struct e1000_hw *hw) +{ + u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGFUNC("e1000_led_on_82542"); + + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + return (E1000_SUCCESS); +} + +/* + * e1000_led_off_82542 - Turn off SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED off. This is a function pointer entry point + * called by the api module. + */ +static s32 +e1000_led_off_82542(struct e1000_hw *hw) +{ + u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGFUNC("e1000_led_off_82542"); + + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + return (E1000_SUCCESS); +} + +/* + * e1000_translate_register_82542 - Translate the proper regiser offset + * @reg: e1000 register to be read + * + * Registers in 82542 are located in different offsets than other adapters + * even though they function in the same manner. This function takes in + * the name of the register to read and returns the correct offset for + * 82542 silicon. + */ +u32 +e1000_translate_register_82542(u32 reg) +{ + /* + * Some of the 82542 registers are located at different + * offsets than they are in newer adapters. + * Despite the difference in location, the registers + * function in the same manner. + */ + switch (reg) { + case E1000_RA: + reg = 0x00040; + break; + case E1000_RDTR: + reg = 0x00108; + break; + case E1000_RDBAL: + reg = 0x00110; + break; + case E1000_RDBAH: + reg = 0x00114; + break; + case E1000_RDLEN: + reg = 0x00118; + break; + case E1000_RDH: + reg = 0x00120; + break; + case E1000_RDT: + reg = 0x00128; + break; + case E1000_RDBAL1: + reg = 0x00138; + break; + case E1000_RDBAH1: + reg = 0x0013C; + break; + case E1000_RDLEN1: + reg = 0x00140; + break; + case E1000_RDH1: + reg = 0x00148; + break; + case E1000_RDT1: + reg = 0x00150; + break; + case E1000_FCRTH: + reg = 0x00160; + break; + case E1000_FCRTL: + reg = 0x00168; + break; + case E1000_MTA: + reg = 0x00200; + break; + case E1000_TDBAL: + reg = 0x00420; + break; + case E1000_TDBAH: + reg = 0x00424; + break; + case E1000_TDLEN: + reg = 0x00428; + break; + case E1000_TDH: + reg = 0x00430; + break; + case E1000_TDT: + reg = 0x00438; + break; + case E1000_TIDV: + reg = 0x00440; + break; + case E1000_VFTA: + reg = 0x00600; + break; + case E1000_TDFH: + reg = 0x08010; + break; + case E1000_TDFT: + reg = 0x08018; + break; + default: + break; + } + + return (reg); +} + +/* + * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_82542"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82543.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1691 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_82543 + * e1000_82544 + */ + +#include "e1000_api.h" +#include "e1000_82543.h" + +void e1000_init_function_pointers_82543(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); +static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); +static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, + u16 *data); +static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, + u16 data); +static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); +static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); +static s32 e1000_reset_hw_82543(struct e1000_hw *hw); +static s32 e1000_init_hw_82543(struct e1000_hw *hw); +static s32 e1000_setup_link_82543(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); +static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); +static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); +static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); +static s32 e1000_led_on_82543(struct e1000_hw *hw); +static s32 e1000_led_off_82543(struct e1000_hw *hw); +static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, + u32 value); +static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); +static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); +static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); +static boolean_t e1000_init_phy_disabled_82543(struct e1000_hw *hw); +static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); +static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); +static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); +static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); +static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, + u16 count); +static boolean_t e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); +static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state); + +struct e1000_dev_spec_82543 { + u32 tbi_compatibility; + boolean_t dma_fairness; + boolean_t init_phy_disabled; +}; + +/* + * e1000_init_phy_params_82543 - Init PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_82543(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_phy_params_82543"); + + if (hw->media_type != e1000_media_type_copper) { + phy->type = e1000_phy_none; + goto out; + } + + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 10000; + phy->type = e1000_phy_m88; + + /* Function Pointers */ + func->check_polarity = e1000_check_polarity_m88; + func->commit_phy = e1000_phy_sw_reset_generic; + func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; + func->get_cable_length = e1000_get_cable_length_m88; + func->get_cfg_done = e1000_get_cfg_done_generic; + func->read_phy_reg = (hw->mac.type == e1000_82543) + ? e1000_read_phy_reg_82543 + : e1000_read_phy_reg_m88; + func->reset_phy = (hw->mac.type == e1000_82543) + ? e1000_phy_hw_reset_82543 + : e1000_phy_hw_reset_generic; + func->write_phy_reg = (hw->mac.type == e1000_82543) + ? e1000_write_phy_reg_82543 + : e1000_write_phy_reg_m88; + func->get_phy_info = e1000_get_phy_info_m88; + + /* + * The external PHY of the 82543 can be in a funky state. + * Resetting helps us read the PHY registers for acquiring + * the PHY ID. + */ + if (!e1000_init_phy_disabled_82543(hw)) { + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) { + DEBUGOUT("Resetting PHY during init failed.\n"); + goto out; + } + msec_delay(20); + } + + ret_val = e1000_get_phy_id(hw); + if (ret_val) + goto out; + + /* Verify phy id */ + switch (hw->mac.type) { + case e1000_82543: + if (phy->id != M88E1000_E_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } + break; + case e1000_82544: + if (phy->id != M88E1000_I_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_82543 - Init NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_82543(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + + DEBUGFUNC("e1000_init_nvm_params_82543"); + + nvm->type = e1000_nvm_eeprom_microwire; + nvm->word_size = 64; + nvm->delay_usec = 50; + nvm->address_bits = 6; + nvm->opcode_bits = 3; + + /* Function Pointers */ + func->read_nvm = e1000_read_nvm_microwire; + func->update_nvm = e1000_update_nvm_checksum_generic; + func->valid_led_default = e1000_valid_led_default_generic; + func->validate_nvm = e1000_validate_nvm_checksum_generic; + func->write_nvm = e1000_write_nvm_microwire; + + return (E1000_SUCCESS); +} + +/* + * e1000_init_mac_params_82543 - Init MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_82543(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val; + + DEBUGFUNC("e1000_init_mac_params_82543"); + + /* Set media type */ + switch (hw->device_id) { + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82544EI_FIBER: + hw->media_type = e1000_media_type_fiber; + break; + default: + hw->media_type = e1000_media_type_copper; + break; + } + + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_pci_generic; + /* reset */ + func->reset_hw = e1000_reset_hw_82543; + /* hw initialization */ + func->init_hw = e1000_init_hw_82543; + /* link setup */ + func->setup_link = e1000_setup_link_82543; + /* physical interface setup */ + func->setup_physical_interface = + (hw->media_type == e1000_media_type_copper) + ? e1000_setup_copper_link_82543 + : e1000_setup_fiber_link_82543; + /* check for link */ + func->check_for_link = + (hw->media_type == e1000_media_type_copper) + ? e1000_check_for_copper_link_82543 + : e1000_check_for_fiber_link_82543; + /* link info */ + func->get_link_up_info = + (hw->media_type == e1000_media_type_copper) + ? e1000_get_speed_and_duplex_copper_generic + : e1000_get_speed_and_duplex_fiber_serdes_generic; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_82543; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_82543; + /* turn on/off LED */ + func->led_on = e1000_led_on_82543; + func->led_off = e1000_led_off_82543; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; + + hw->dev_spec_size = sizeof (struct e1000_dev_spec_82543); + + /* Device-specific structure allocation */ + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); + if (ret_val) + goto out; + + /* Set tbi compatibility */ + if ((hw->mac.type != e1000_82543) || + (hw->media_type == e1000_media_type_fiber)) + e1000_set_tbi_compatibility_82543(hw, FALSE); + +out: + return (ret_val); +} + +/* + * e1000_init_function_pointers_82543 - Init func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_82543(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_82543"); + + hw->func.init_mac_params = e1000_init_mac_params_82543; + hw->func.init_nvm_params = e1000_init_nvm_params_82543; + hw->func.init_phy_params = e1000_init_phy_params_82543; +} + +/* + * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status + * @hw: pointer to the HW structure + * + * Returns the curent status of 10-bit Interface (TBI) compatibility + * (enabled/disabled). + */ +static boolean_t +e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82543 *dev_spec; + boolean_t state = FALSE; + + DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); + + if (hw->mac.type != e1000_82543) { + DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); + goto out; + } + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + goto out; + } + + state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) + ? TRUE : FALSE; + +out: + return (state); +} + +/* + * e1000_set_tbi_compatibility_82543 - Set TBI compatibility + * @hw: pointer to the HW structure + * @state: enable/disable TBI compatibility + * + * Enables or disabled 10-bit Interface (TBI) compatibility. + */ +void +e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, boolean_t state) +{ + struct e1000_dev_spec_82543 *dev_spec; + + DEBUGFUNC("e1000_set_tbi_compatibility_82543"); + + if (hw->mac.type != e1000_82543) { + DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); + return; + } + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + return; + } + + if (state) + dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; + else + dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; +} + +/* + * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status + * @hw: pointer to the HW structure + * + * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) + * (enabled/disabled). + */ +boolean_t +e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82543 *dev_spec; + boolean_t state = FALSE; + + DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); + + if (hw->mac.type != e1000_82543) { + DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); + goto out; + } + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + goto out; + } + + state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) + ? TRUE : FALSE; + +out: + return (state); +} + +/* + * e1000_set_tbi_sbp_82543 - Set TBI SBP + * @hw: pointer to the HW structure + * @state: enable/disable TBI store bad packet + * + * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). + */ +static void +e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state) +{ + struct e1000_dev_spec_82543 *dev_spec; + + DEBUGFUNC("e1000_set_tbi_sbp_82543"); + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (state && e1000_tbi_compatibility_enabled_82543(hw)) + dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; + else + dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; +} + +/* + * e1000_init_phy_disabled_82543 - Returns init PHY status + * @hw: pointer to the HW structure + * + * Returns the current status of whether PHY initialization is disabled. + * True if PHY initialization is disabled else false. + */ +static boolean_t +e1000_init_phy_disabled_82543(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82543 *dev_spec; + boolean_t ret_val; + + DEBUGFUNC("e1000_init_phy_disabled_82543"); + + if (hw->mac.type != e1000_82543) { + ret_val = FALSE; + goto out; + } + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = FALSE; + goto out; + } + + ret_val = dev_spec->init_phy_disabled; + +out: + return (ret_val); +} + +/* + * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled + * @hw: pointer to the HW structure + * @stats: Struct containing statistic register values + * @frame_len: The length of the frame in question + * @mac_addr: The Ethernet destination address of the frame in question + * + * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT + */ +void +e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, + struct e1000_hw_stats *stats, u32 frame_len, u8 *mac_addr) +{ + u64 carry_bit; + + if (!(e1000_tbi_sbp_enabled_82543(hw))) + return; + + /* First adjust the frame length. */ + frame_len--; + /* + * We need to adjust the statistics counters, since the hardware + * counters overcount this packet as a CRC error and undercount + * the packet as a good packet + */ + /* This packet should not be counted as a CRC error. */ + stats->crcerrs--; + /* This packet does count as a Good Packet Received. */ + stats->gprc++; + + /* Adjust the Good Octets received counters */ + carry_bit = 0x80000000 & stats->gorcl; + stats->gorcl += frame_len; + /* + * If the high bit of Gorcl (the low 32 bits of the Good Octets + * Received Count) was one before the addition, + * AND it is zero after, then we lost the carry out, + * need to add one to Gorch (Good Octets Received Count High). + * This could be simplified if all environments supported + * 64-bit integers. + */ + if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) + stats->gorch++; + /* + * Is this a broadcast or multicast? Check broadcast first, + * since the test for a multicast frame will test positive on + * a broadcast frame. + */ + if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) + /* Broadcast packet */ + stats->bprc++; + else if (*mac_addr & 0x01) + /* Multicast packet */ + stats->mprc++; + + /* + * In this case, the hardware has overcounted the number of + * oversize frames. + */ + if ((frame_len == hw->mac.max_frame_size) && (stats->roc > 0)) + stats->roc--; + + /* + * Adjust the bin counters when the extra byte put the frame in the + * wrong bin. Remember that the frame_len was adjusted above. + */ + if (frame_len == 64) { + stats->prc64++; + stats->prc127--; + } else if (frame_len == 127) { + stats->prc127++; + stats->prc255--; + } else if (frame_len == 255) { + stats->prc255++; + stats->prc511--; + } else if (frame_len == 511) { + stats->prc511++; + stats->prc1023--; + } else if (frame_len == 1023) { + stats->prc1023++; + stats->prc1522--; + } else if (frame_len == 1522) { + stats->prc1522++; + } +} + +/* + * e1000_read_phy_reg_82543 - Read PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Reads the PHY at offset and stores the information read to data. + */ +static s32 +e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 * data) +{ + u32 mdic; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_read_phy_reg_82543"); + + if (offset > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", offset); + ret_val = -E1000_ERR_PARAM; + goto out; + } + + /* + * We must first send a preamble through the MDIO pin to signal the + * beginning of an MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* + * Now combine the next few fields that are required for a read + * operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine five different times. The format + * of an MII read instruction consists of a shift out of 14 bits and + * is defined as follows: + * <Preamble><SOF><Op Code><Phy Addr><Offset> + * followed by a shift in of 18 bits. This first two bits shifted in + * are TurnAround bits used to avoid contention on the MDIO pin when a + * READ operation is performed. These two bits are thrown away + * followed by a shift in of 16 bits which contains the desired data. + */ + mdic = (offset | (hw->phy.addr << 5) | + (PHY_OP_READ << 10) | (PHY_SOF << 12)); + + e1000_shift_out_mdi_bits_82543(hw, mdic, 14); + + /* + * Now that we've shifted out the read command to the MII, we need to + * "shift in" the 16-bit value (18 total bits) of the requested PHY + * register address. + */ + *data = e1000_shift_in_mdi_bits_82543(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_phy_reg_82543 - Write PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be written + * @data: pointer to the data to be written at offset + * + * Writes data to the PHY at offset. + */ +static s32 +e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) +{ + u32 mdic; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_write_phy_reg_82543"); + + if (offset > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", offset); + ret_val = -E1000_ERR_PARAM; + goto out; + } + + /* + * We'll need to use the SW defined pins to shift the write command + * out to the PHY. We first send a preamble to the PHY to signal the + * beginning of the MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* + * Now combine the remaining required fields that will indicate a + * write operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine for each field in the command. The + * format of a MII write instruction is as follows: + * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. + */ + mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | + (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); + mdic <<= 16; + mdic |= (u32) data; + + e1000_shift_out_mdi_bits_82543(hw, mdic, 32); + +out: + return (ret_val); +} + +/* + * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock + * @hw: pointer to the HW structure + * @ctrl: pointer to the control register + * + * Raise the management data input clock by setting the MDC bit in the control + * register. + */ +static void +e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 * ctrl) +{ + /* + * Raise the clock input to the Management Data Clock (by setting the + * MDC bit), and then delay a sufficient amount of time. + */ + E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + usec_delay(10); +} + +/* + * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock + * @hw: pointer to the HW structure + * @ctrl: pointer to the control register + * + * Lower the management data input clock by clearing the MDC bit in the control + * register. + */ +static void +e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 * ctrl) +{ + /* + * Lower the clock input to the Management Data Clock (by clearing the + * MDC bit), and then delay a sufficient amount of time. + */ + E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + usec_delay(10); +} + +/* + * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY + * @hw: pointer to the HW structure + * @data: data to send to the PHY + * @count: number of bits to shift out + * + * We need to shift 'count' bits out to the PHY. So, the value in the + * "data" parameter will be shifted out to the PHY one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ +static void +e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, + u16 count) +{ + u32 ctrl, mask; + + /* + * We need to shift "count" number of bits out to the PHY. So, the + * value in the "data" parameter will be shifted out to the PHY one + * bit at a time. In order to do this, "data" must be broken down + * into bits. + */ + mask = 0x01; + mask <<= (count - 1); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ + ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); + + while (mask) { + /* + * A "1" is shifted out to the PHY by setting the MDIO bit to + * "1" and then raising and lowering the Management Data Clock. + * A "0" is shifted out to the PHY by setting the MDIO bit to + * "0" and then raising and lowering the clock. + */ + if (data & mask) + ctrl |= E1000_CTRL_MDIO; + else + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + usec_delay(10); + + e1000_raise_mdi_clk_82543(hw, &ctrl); + e1000_lower_mdi_clk_82543(hw, &ctrl); + + mask >>= 1; + } +} + +/* + * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY + * @hw: pointer to the HW structure + * + * In order to read a register from the PHY, we need to shift 18 bits + * in from the PHY. Bits are "shifted in" by raising the clock input to + * the PHY (setting the MDC bit), and then reading the value of the data out + * MDIO bit. + */ +static u16 +e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) +{ + u32 ctrl; + u16 data = 0; + u8 i; + + /* + * In order to read a register from the PHY, we need to shift in a + * total of 18 bits from the PHY. The first two bit (turnaround) + * times are used to avoid contention on the MDIO pin when a read + * operation is performed. These two bits are ignored by us and + * thrown away. Bits are "shifted in" by raising the input to the + * Management Data Clock (setting the MDC bit) and then reading the + * value of the MDIO bit. + */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* + * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as + * input. + */ + ctrl &= ~E1000_CTRL_MDIO_DIR; + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + /* + * Raise and lower the clock before reading in the data. This accounts + * for the turnaround bits. The first clock occurred when we clocked + * out the last bit of the Register Address. + */ + e1000_raise_mdi_clk_82543(hw, &ctrl); + e1000_lower_mdi_clk_82543(hw, &ctrl); + + for (data = 0, i = 0; i < 16; i++) { + data <<= 1; + e1000_raise_mdi_clk_82543(hw, &ctrl); + ctrl = E1000_READ_REG(hw, E1000_CTRL); + /* Check to see if we shifted in a "1". */ + if (ctrl & E1000_CTRL_MDIO) + data |= 1; + e1000_lower_mdi_clk_82543(hw, &ctrl); + } + + e1000_raise_mdi_clk_82543(hw, &ctrl); + e1000_lower_mdi_clk_82543(hw, &ctrl); + + return (data); +} + +/* + * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY + * @hw: pointer to the HW structure + * + * Calls the function to force speed and duplex for the m88 PHY, and + * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, + * then call the function for polarity reversal workaround. + */ +static s32 +e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) +{ + s32 ret_val; + + DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); + + ret_val = e1000_phy_force_speed_duplex_m88(hw); + if (ret_val) + goto out; + + if (!hw->mac.autoneg && + (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) + ret_val = e1000_polarity_reversal_workaround_82543(hw); + +out: + return (ret_val); +} + +/* + * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal + * @hw: pointer to the HW structure + * + * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity + * inadvertantly. To workaround the issue, we disable the transmitter on + * the PHY until we have established the link partner's link parameters. + */ +static s32 +e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) +{ + s32 ret_val; + u16 mii_status_reg; + u16 i; + boolean_t link; + + /* Polarity reversal workaround for forced 10F/10H links. */ + + /* Disable the transmitter on the PHY */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); + if (ret_val) + goto out; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); + if (ret_val) + goto out; + + /* + * This loop will early-out if the NO link condition has been met. + * In other words, DO NOT use e1000_phy_has_link_generic() here. + */ + for (i = PHY_FORCE_TIME; i > 0; i--) { + /* + * Read the MII Status Register and wait for Link Status bit + * to be clear. + */ + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; + + if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) + break; + msec_delay_irq(100); + } + + /* Recommended delay time after link has been lost */ + msec_delay_irq(1000); + + /* Now we will re-enable the transmitter on the PHY */ + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); + if (ret_val) + goto out; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); + if (ret_val) + goto out; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); + if (ret_val) + goto out; + msec_delay_irq(50); + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); + if (ret_val) + goto out; + + /* + * Read the MII Status Register and wait for Link Status bit + * to be set. + */ + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); + if (ret_val) + goto out; + +out: + return (ret_val); +} + +/* + * e1000_phy_hw_reset_82543 - PHY hardware reset + * @hw: pointer to the HW structure + * + * Sets the PHY_RESET_DIR bit in the extended device control register + * to put the PHY into a reset and waits for completion. Once the reset + * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out + * of reset. This is a function pointer entry point called by the api module. + */ +static s32 +e1000_phy_hw_reset_82543(struct e1000_hw *hw) +{ + struct e1000_functions *func = &hw->func; + u32 ctrl_ext; + s32 ret_val; + + DEBUGFUNC("e1000_phy_hw_reset_82543"); + + /* + * Read the Extended Device Control Register, assert the PHY_RESET_DIR + * bit to put the PHY into reset... + */ + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; + ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + + msec_delay(10); + + /* ...then take it out of reset. */ + ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + + usec_delay(150); + + ret_val = func->get_cfg_done(hw); + + return (ret_val); +} + +/* + * e1000_reset_hw_82543 - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_82543(struct e1000_hw *hw) +{ + u32 ctrl, icr; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_reset_hw_82543"); + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + e1000_set_tbi_sbp_82543(hw, FALSE); + + /* + * Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + msec_delay(10); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); + if (hw->mac.type == e1000_82543) { + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + } else { + /* + * The 82544 can't ACK the 64-bit write when issuing the + * reset, so use IO-mapping as a workaround. + */ + E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + } + + /* + * After MAC reset, force reload of NVM to restore power-on + * settings to device. + */ + e1000_reload_nvm(hw); + msec_delay(2); + + /* Masking off and clearing any pending interrupts */ + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + + return (ret_val); +} + +/* + * e1000_init_hw_82543 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. + */ +static s32 +e1000_init_hw_82543(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_dev_spec_82543 *dev_spec; + u32 ctrl; + s32 ret_val; + u16 i; + + DEBUGFUNC("e1000_init_hw_82543"); + + dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + /* Disabling VLAN filtering */ + E1000_WRITE_REG(hw, E1000_VET, 0); + e1000_clear_vfta(hw); + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) { + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + E1000_WRITE_FLUSH(hw); + } + + /* + * Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. + */ + if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { + ctrl = E1000_READ_REG(hw, E1000_CTRL); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); + } + + e1000_pcix_mmrbc_workaround_generic(hw); + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_82543(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_link_82543 - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Read the EEPROM to determine the initial polarity value and write the + * extended device control register with the information before calling + * the generic setup link function, which does the following: + * Determines which flow control settings to use, then configures flow + * control. Calls the appropriate media-specific link configuration + * function. Assuming the adapter has a valid link partner, a valid link + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + */ +static s32 +e1000_setup_link_82543(struct e1000_hw *hw) +{ + u32 ctrl_ext; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_setup_link_82543"); + + /* + * Take the 4 bits from NVM word 0xF that determine the initial + * polarity value for the SW controlled pins, and setup the + * Extended Device Control reg with that info. + * This is needed because one of the SW controlled pins is used for + * signal detection. So this should be done before phy setup. + */ + if (hw->mac.type == e1000_82543) { + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << + NVM_SWDPIO_EXT_SHIFT); + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + } + + ret_val = e1000_setup_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_82543 - Configure copper link settings + * @hw: pointer to the HW structure + * + * Configures the link for auto-neg or forced speed and duplex. Then we check + * for link, once link is established calls to configure collision distance + * and flow control are called. + */ +static s32 +e1000_setup_copper_link_82543(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + boolean_t link; + + DEBUGFUNC("e1000_setup_copper_link_82543"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; + /* + * With 82543, we need to force speed and duplex on the MAC + * equal to what the PHY speed and duplex configuration is. + * In addition, we need to perform a hardware reset on the + * PHY to take it out of reset. + */ + if (hw->mac.type == e1000_82543) { + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) + goto out; + hw->phy.reset_disable = FALSE; + } else { + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + } + + /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ + ret_val = e1000_copper_link_setup_m88(hw); + if (ret_val) + goto out; + + if (hw->mac.autoneg) { + /* + * Setup autoneg and flow control advertisement and perform + * autonegotiation. + */ + ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) + goto out; + } else { + /* + * PHY will be set to 10H, 10F, 100H or 100F + * depending on user settings. + */ + DEBUGOUT("Forcing Speed and Duplex\n"); + ret_val = e1000_phy_force_speed_duplex_82543(hw); + if (ret_val) { + DEBUGOUT("Error Forcing Speed and Duplex\n"); + goto out; + } + } + + /* + * Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + ret_val = e1000_phy_has_link_generic(hw, + COPPER_LINK_UP_LIMIT, + 10, + &link); + if (ret_val) + goto out; + + + if (link) { + DEBUGOUT("Valid link established!!!\n"); + /* Config the MAC and PHY after link is up */ + if (hw->mac.type == e1000_82544) { + e1000_config_collision_dist_generic(hw); + } else { + ret_val = e1000_config_mac_to_phy_82543(hw); + if (ret_val) + goto out; + } + ret_val = e1000_config_fc_after_link_up_generic(hw); + } else { + DEBUGOUT("Unable to establish link!!!\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_setup_fiber_link_82543 - Setup link for fiber + * @hw: pointer to the HW structure + * + * Configures collision distance and flow control for fiber links. Upon + * successful setup, poll for link. + */ +static s32 +e1000_setup_fiber_link_82543(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + + DEBUGFUNC("e1000_setup_fiber_link_82543"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* Take the link out of reset */ + ctrl &= ~E1000_CTRL_LRST; + + e1000_config_collision_dist_generic(hw); + + ret_val = e1000_commit_fc_settings_generic(hw); + if (ret_val) + goto out; + + DEBUGOUT("Auto-negotiation enabled\n"); + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + msec_delay(1); + + /* + * For these adapters, the SW defineable pin 1 is cleared when the + * optics detect a signal. If we have a signal, then poll for a + * "Link-Up" indication. + */ + if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { + ret_val = e1000_poll_fiber_serdes_link_generic(hw); + } else { + DEBUGOUT("No signal detected\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_check_for_copper_link_82543 - Check for link (Copper) + * @hw: pointer to the HW structure + * + * Checks the phy for link, if link exists, do the following: + * - check for downshift + * - do polarity workaround (if necessary) + * - configure collision distance + * - configure flow control after link up + * - configure tbi compatibility + */ +static s32 +e1000_check_for_copper_link_82543(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 icr, rctl; + s32 ret_val; + u16 speed, duplex; + boolean_t link; + + DEBUGFUNC("e1000_check_for_copper_link_82543"); + + if (!mac->get_link_status) { + ret_val = E1000_SUCCESS; + goto out; + } + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) + goto out; /* No link detected */ + + mac->get_link_status = FALSE; + + e1000_check_downshift_generic(hw); + + /* + * If we are forcing speed/duplex, then we can return since + * we have already determined whether we have link or not. + */ + if (!mac->autoneg) { + /* + * If speed and duplex are forced to 10H or 10F, then we will + * implement the polarity reversal workaround. We disable + * interrupts first, and upon returning, place the devices + * interrupt state to its previous value except for the link + * status change interrupt which will happened due to the + * execution of this workaround. + */ + if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { + E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); + ret_val = e1000_polarity_reversal_workaround_82543(hw); + icr = E1000_READ_REG(hw, E1000_ICR); + E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); + E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); + } + + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + /* + * We have a M88E1000 PHY and Auto-Neg is enabled. If we + * have Si on board that is 82544 or newer, Auto + * Speed Detection takes care of MAC speed/duplex + * configuration. So we only need to configure Collision + * Distance in the MAC. Otherwise, we need to force + * speed/duplex on the MAC to the current PHY speed/duplex + * settings. + */ + if (mac->type == e1000_82544) + e1000_config_collision_dist_generic(hw); + else { + ret_val = e1000_config_mac_to_phy_82543(hw); + if (ret_val) { + DEBUGOUT("Error configuring MAC to PHY settings\n"); + goto out; + } + } + + /* + * Configure Flow Control now that Auto-Neg has completed. + * First, we need to restore the desired flow control + * settings because we may have had to re-autoneg with a + * different link partner. + */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + } + + /* + * At this point we know that we are on copper and we have + * auto-negotiated link. These are conditions for checking the link + * partner capability register. We use the link speed to determine if + * TBI compatibility needs to be turned on or off. If the link is not + * at gigabit speed, then TBI compatibility is not needed. If we are + * at gigabit speed, we turn on TBI compatibility. + */ + if (e1000_tbi_compatibility_enabled_82543(hw)) { + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + return (ret_val); + } + if (speed != SPEED_1000) { + /* + * If link speed is not set to gigabit speed, + * we do not need to enable TBI compatibility. + */ + if (e1000_tbi_sbp_enabled_82543(hw)) { + /* + * If we previously were in the mode, + * turn it off. + */ + e1000_set_tbi_sbp_82543(hw, FALSE); + rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl &= ~E1000_RCTL_SBP; + E1000_WRITE_REG(hw, E1000_RCTL, rctl); + } + } else { + /* + * If TBI compatibility is was previously off, + * turn it on. For compatibility with a TBI link + * partner, we will store bad packets. Some + * frames have an additional byte on the end and + * will look like CRC errors to to the hardware. + */ + if (!e1000_tbi_sbp_enabled_82543(hw)) { + e1000_set_tbi_sbp_82543(hw, TRUE); + rctl = E1000_READ_REG(hw, E1000_RCTL); + rctl |= E1000_RCTL_SBP; + E1000_WRITE_REG(hw, E1000_RCTL, rctl); + } + } + } +out: + return (ret_val); +} + +/* + * e1000_check_for_fiber_link_82543 - Check for link (Fiber) + * @hw: pointer to the HW structure + * + * Checks for link up on the hardware. If link is not up and we have + * a signal, then we need to force link up. + */ +static s32 +e1000_check_for_fiber_link_82543(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 rxcw, ctrl, status; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_check_for_fiber_link_82543"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + status = E1000_READ_REG(hw, E1000_STATUS); + rxcw = E1000_READ_REG(hw, E1000_RXCW); + + /* + * If we don't have link (auto-negotiation failed or link partner + * cannot auto-negotiate), the cable is plugged in (we have signal), + * and our link partner is not trying to auto-negotiate with us (we + * are receiving idles or data), we need to force link up. We also + * need to give auto-negotiation time to complete, in case the cable + * was just plugged in. The autoneg_failed flag does this. + */ + /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ + if ((!(ctrl & E1000_CTRL_SWDPIN1)) && + (!(status & E1000_STATUS_LU)) && + (!(rxcw & E1000_RXCW_C))) { + if (mac->autoneg_failed == 0) { + mac->autoneg_failed = 1; + ret_val = 0; + goto out; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + goto out; + } + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + /* + * If we are forcing link and we are receiving /C/ ordered + * sets, re-enable auto-negotiation in the TXCW register + * and disable forced link in the Device Control register + * in an attempt to auto-negotiate with our link partner. + */ + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); + E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); + + mac->serdes_has_link = TRUE; + } + +out: + return (ret_val); +} + +/* + * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings + * @hw: pointer to the HW structure + * + * For the 82543 silicon, we need to set the MAC to match the settings + * of the PHY, even if the PHY is auto-negotiating. + */ +static s32 +e1000_config_mac_to_phy_82543(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + u16 phy_data; + + DEBUGFUNC("e1000_config_mac_to_phy_82543"); + + /* Set the bits to force speed and duplex */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + + /* + * Set up duplex in the Device Control and Transmit Control + * registers depending on negotiated values. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + goto out; + + ctrl &= ~E1000_CTRL_FD; + if (phy_data & M88E1000_PSSR_DPLX) + ctrl |= E1000_CTRL_FD; + + e1000_config_collision_dist_generic(hw); + + /* + * Set up speed in the Device Control register depending on + * negotiated values. + */ + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) + ctrl |= E1000_CTRL_SPD_1000; + else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) + ctrl |= E1000_CTRL_SPD_100; + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + +out: + return (ret_val); +} + +/* + * e1000_write_vfta_82543 - Write value to VLAN filter table + * @hw: pointer to the HW structure + * @offset: the 32-bit offset in which to write the value to. + * @value: the 32-bit value to write at location offset. + * + * This writes a 32-bit value to a 32-bit offset in the VLAN filter + * table. + */ +static void +e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) +{ + u32 temp; + + DEBUGFUNC("e1000_write_vfta_82543"); + + if ((hw->mac.type == e1000_82544) && (offset & 1)) { + temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); + E1000_WRITE_FLUSH(hw); + } else { + e1000_write_vfta_generic(hw, offset, value); + } +} + +/* + * e1000_mta_set_82543 - Set multicast filter table address + * @hw: pointer to the HW structure + * @hash_value: determines the MTA register and bit to set + * + * The multicast table address is a register array of 32-bit registers. + * The hash_value is used to determine what register the bit is in, the + * current value is read, the new bit is OR'd in and the new value is + * written back into the register. + */ +static void +e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) +{ + u32 hash_bit, hash_reg, mta, temp; + + DEBUGFUNC("e1000_mta_set_82543"); + + hash_reg = (hash_value >> 5); + + /* + * If we are on an 82544 and we are trying to write an odd offset + * in the MTA, save off the previous entry before writing and + * restore the old value after writing. + */ + if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { + hash_reg &= (hw->mac.mta_reg_count - 1); + hash_bit = hash_value & 0x1F; + mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); + mta |= (1 << hash_bit); + temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); + + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); + E1000_WRITE_FLUSH(hw); + } else { + e1000_mta_set_generic(hw, hash_value); + } +} + +/* + * e1000_led_on_82543 - Turn on SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED on. This is a function pointer entry point + * called by the api module. + */ +static s32 +e1000_led_on_82543(struct e1000_hw *hw) +{ + u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGFUNC("e1000_led_on_82543"); + + if (hw->mac.type == e1000_82544 && + hw->media_type == e1000_media_type_copper) { + /* Clear SW-defineable Pin 0 to turn on the LED */ + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else { + /* Fiber 82544 and all 82543 use this method */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + return (E1000_SUCCESS); +} + +/* + * e1000_led_off_82543 - Turn off SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED off. This is a function pointer entry point + * called by the api module. + */ +static s32 +e1000_led_off_82543(struct e1000_hw *hw) +{ + u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGFUNC("e1000_led_off_82543"); + + if (hw->mac.type == e1000_82544 && + hw->media_type == e1000_media_type_copper) { + /* Set SW-defineable Pin 0 to turn off the LED */ + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } else { + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + } + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + return (E1000_SUCCESS); +} + +/* + * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_82543"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82543.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,53 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_82543_H_ +#define _E1000_82543_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PHY_PREAMBLE 0xFFFFFFFF +#define PHY_PREAMBLE_SIZE 32 +#define PHY_SOF 0x1 +#define PHY_OP_READ 0x2 +#define PHY_OP_WRITE 0x1 +#define PHY_TURNAROUND 0x2 + +#define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */ +/* If TBI_COMPAT_ENABLED, then this is the current state (on/off) */ +#define TBI_SBP_ENABLED 0x2 + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_82543_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82571.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1417 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_82571 + * e1000_82572 + * e1000_82573 + */ + +#include "e1000_api.h" +#include "e1000_82571.h" + +void e1000_init_function_pointers_82571(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); +static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); +static void e1000_release_nvm_82571(struct e1000_hw *hw); +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, + boolean_t active); +static s32 e1000_reset_hw_82571(struct e1000_hw *hw); +static s32 e1000_init_hw_82571(struct e1000_hw *hw); +static void e1000_clear_vfta_82571(struct e1000_hw *hw); +static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count); +static s32 e1000_setup_link_82571(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); + +struct e1000_dev_spec_82571 { + boolean_t laa_is_present; +}; + +/* + * e1000_init_phy_params_82571 - Init PHY func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_phy_params_82571(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_phy_params_82571"); + + if (hw->media_type != e1000_media_type_copper) { + phy->type = e1000_phy_none; + goto out; + } + + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 100; + + func->acquire_phy = e1000_get_hw_semaphore_82571; + func->check_polarity = e1000_check_polarity_igp; + func->check_reset_block = e1000_check_reset_block_generic; + func->release_phy = e1000_put_hw_semaphore_82571; + func->reset_phy = e1000_phy_hw_reset_generic; + func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; + func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; + + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + phy->type = e1000_phy_igp_2; + func->get_cfg_done = e1000_get_cfg_done_82571; + func->get_phy_info = e1000_get_phy_info_igp; + func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; + func->get_cable_length = e1000_get_cable_length_igp_2; + func->read_phy_reg = e1000_read_phy_reg_igp; + func->write_phy_reg = e1000_write_phy_reg_igp; + break; + case e1000_82573: + phy->type = e1000_phy_m88; + func->get_cfg_done = e1000_get_cfg_done_generic; + func->get_phy_info = e1000_get_phy_info_m88; + func->commit_phy = e1000_phy_sw_reset_generic; + func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; + func->get_cable_length = e1000_get_cable_length_m88; + func->read_phy_reg = e1000_read_phy_reg_m88; + func->write_phy_reg = e1000_write_phy_reg_m88; + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + } + + /* This can only be done after all function pointers are setup. */ + ret_val = e1000_get_phy_id_82571(hw); + + /* Verify phy id */ + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + if (phy->id != IGP01E1000_I_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } + break; + case e1000_82573: + if (phy->id != M88E1111_I_PHY_ID) { + ret_val = -E1000_ERR_PHY; + goto out; + } + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_82571 - Init NVM func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_nvm_params_82571(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u16 size; + + DEBUGFUNC("e1000_init_nvm_params_82571"); + + nvm->opcode_bits = 8; + nvm->delay_usec = 1; + switch (nvm->override) { + case e1000_nvm_override_spi_large: + nvm->page_size = 32; + nvm->address_bits = 16; + break; + case e1000_nvm_override_spi_small: + nvm->page_size = 8; + nvm->address_bits = 8; + break; + default: + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; + break; + } + + switch (hw->mac.type) { + case e1000_82573: + if (((eecd >> 15) & 0x3) == 0x3) { + nvm->type = e1000_nvm_flash_hw; + nvm->word_size = 2048; + /* + * Autonomous Flash update bit must be cleared due + * to Flash update issue. + */ + eecd &= ~E1000_EECD_AUPDEN; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + break; + } + /* Fall Through */ + default: + nvm->type = e1000_nvm_eeprom_spi; + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + /* + * Added to a constant, "size" becomes the left-shift value + * for setting word_size. + */ + size += NVM_WORD_SIZE_BASE_SHIFT; + nvm->word_size = 1 << size; + break; + } + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_nvm_82571; + func->read_nvm = (hw->mac.type == e1000_82573) + ? e1000_read_nvm_eerd + : e1000_read_nvm_spi; + func->release_nvm = e1000_release_nvm_82571; + func->update_nvm = e1000_update_nvm_checksum_82571; + func->validate_nvm = e1000_validate_nvm_checksum_82571; + func->valid_led_default = e1000_valid_led_default_82571; + func->write_nvm = e1000_write_nvm_82571; + + return (E1000_SUCCESS); +} + +/* + * e1000_init_mac_params_82571 - Init MAC func ptrs. + * @hw: pointer to the HW structure + * + * This is a function pointer entry point called by the api module. + */ +static s32 +e1000_init_mac_params_82571(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_mac_params_82571"); + + /* Set media type */ + switch (hw->device_id) { + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82571EB_QUAD_FIBER: + hw->media_type = e1000_media_type_fiber; + break; + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_SERDES_DUAL: + case E1000_DEV_ID_82571EB_SERDES_QUAD: + case E1000_DEV_ID_82572EI_SERDES: + hw->media_type = e1000_media_type_internal_serdes; + break; + default: + hw->media_type = e1000_media_type_copper; + break; + } + + /* Set mta register count */ + mac->mta_reg_count = 128; + /* Set rar entry count */ + mac->rar_entry_count = E1000_RAR_ENTRIES; + /* Set if part includes ASF firmware */ + mac->asf_firmware_present = TRUE; + /* Set if manageability features are enabled. */ + mac->arc_subsystem_valid = + (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) + ? TRUE : FALSE; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_pcie_generic; + /* reset */ + func->reset_hw = e1000_reset_hw_82571; + /* hw initialization */ + func->init_hw = e1000_init_hw_82571; + /* link setup */ + func->setup_link = e1000_setup_link_82571; + /* physical interface link setup */ + func->setup_physical_interface = + (hw->media_type == e1000_media_type_copper) + ? e1000_setup_copper_link_82571 + : e1000_setup_fiber_serdes_link_82571; + /* check for link */ + switch (hw->media_type) { + case e1000_media_type_copper: + func->check_for_link = e1000_check_for_copper_link_generic; + break; + case e1000_media_type_fiber: + func->check_for_link = e1000_check_for_fiber_link_generic; + break; + case e1000_media_type_internal_serdes: + func->check_for_link = e1000_check_for_serdes_link_generic; + break; + default: + ret_val = -E1000_ERR_CONFIG; + goto out; + } + /* check management mode */ + func->check_mng_mode = e1000_check_mng_mode_generic; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_82571; + /* writing VFTA */ + func->write_vfta = e1000_write_vfta_generic; + /* clearing VFTA */ + func->clear_vfta = e1000_clear_vfta_82571; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* blink LED */ + func->blink_led = e1000_blink_led_generic; + /* setup LED */ + func->setup_led = e1000_setup_led_generic; + /* cleanup LED */ + func->cleanup_led = e1000_cleanup_led_generic; + /* turn on/off LED */ + func->led_on = e1000_led_on_generic; + func->led_off = e1000_led_off_generic; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; + /* link info */ + func->get_link_up_info = + (hw->media_type == e1000_media_type_copper) + ? e1000_get_speed_and_duplex_copper_generic + : e1000_get_speed_and_duplex_fiber_serdes_generic; + + hw->dev_spec_size = sizeof (struct e1000_dev_spec_82571); + + /* Device-specific structure allocation */ + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); + +out: + return (ret_val); +} + +/* + * e1000_init_function_pointers_82571 - Init func ptrs. + * @hw: pointer to the HW structure + * + * The only function explicitly called by the api module to initialize + * all function pointers and parameters. + */ +void +e1000_init_function_pointers_82571(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_82571"); + + hw->func.init_mac_params = e1000_init_mac_params_82571; + hw->func.init_nvm_params = e1000_init_nvm_params_82571; + hw->func.init_phy_params = e1000_init_phy_params_82571; +} + +/* + * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision + * @hw: pointer to the HW structure + * + * Reads the PHY registers and stores the PHY ID and possibly the PHY + * revision in the hardware structure. + */ +static s32 +e1000_get_phy_id_82571(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_get_phy_id_82571"); + + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + /* + * The 82571 firmware may still be configuring the PHY. + * In this case, we cannot access the PHY until the + * configuration is done. So we explicitly set the + * PHY ID. + */ + phy->id = IGP01E1000_I_PHY_ID; + break; + case e1000_82573: + ret_val = e1000_get_phy_id(hw); + break; + default: + ret_val = -E1000_ERR_PHY; + break; + } + + return (ret_val); +} + +/* + * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore + * @hw: pointer to the HW structure + * + * Acquire the HW semaphore to access the PHY or NVM + */ +s32 +e1000_get_hw_semaphore_82571(struct e1000_hw *hw) +{ + u32 swsm; + s32 ret_val = E1000_SUCCESS; + s32 timeout = hw->nvm.word_size + 1; + s32 i = 0; + + DEBUGFUNC("e1000_get_hw_semaphore_82571"); + + /* Get the FW semaphore. */ + for (i = 0; i < timeout; i++) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); + + /* Semaphore acquired if bit latched */ + if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) + break; + + usec_delay(50); + } + + if (i == timeout) { + /* Release semaphores */ + e1000_put_hw_semaphore_generic(hw); + DEBUGOUT("Driver can't access the NVM\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_put_hw_semaphore_82571 - Release hardware semaphore + * @hw: pointer to the HW structure + * + * Release hardware semaphore used to access the PHY or NVM + */ +void +e1000_put_hw_semaphore_82571(struct e1000_hw *hw) +{ + u32 swsm; + + DEBUGFUNC("e1000_put_hw_semaphore_82571"); + + swsm = E1000_READ_REG(hw, E1000_SWSM); + + swsm &= ~E1000_SWSM_SWESMBI; + + E1000_WRITE_REG(hw, E1000_SWSM, swsm); +} + +/* + * e1000_acquire_nvm_82571 - Request for access to the EEPROM + * @hw: pointer to the HW structure + * + * To gain access to the EEPROM, first we must obtain a hardware semaphore. + * Then for non-82573 hardware, set the EEPROM access request bit and wait + * for EEPROM access grant bit. If the access grant bit is not set, release + * hardware semaphore. + */ +static s32 +e1000_acquire_nvm_82571(struct e1000_hw *hw) +{ + s32 ret_val; + + DEBUGFUNC("e1000_acquire_nvm_82571"); + + ret_val = e1000_get_hw_semaphore_82571(hw); + if (ret_val) + goto out; + + if (hw->mac.type != e1000_82573) + ret_val = e1000_acquire_nvm_generic(hw); + + if (ret_val) + e1000_put_hw_semaphore_82571(hw); + +out: + return (ret_val); +} + +/* + * e1000_release_nvm_82571 - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * Stop any current commands to the EEPROM and clear the EEPROM request bit. + */ +static void +e1000_release_nvm_82571(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_release_nvm_82571"); + + e1000_release_nvm_generic(hw); + e1000_put_hw_semaphore_82571(hw); +} + +/* + * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write + * @data: 16 bit word(s) to be written to the EEPROM + * + * For non-82573 silicon, write data to EEPROM at offset using SPI interface. + * + * If e1000_update_nvm_checksum is not called after this function, the + * EEPROM will most likley contain an invalid checksum. + */ +static s32 +e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_write_nvm_82571"); + + switch (hw->mac.type) { + case e1000_82573: + ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); + break; + case e1000_82571: + case e1000_82572: + ret_val = e1000_write_nvm_spi(hw, offset, words, data); + break; + default: + ret_val = -E1000_ERR_NVM; + break; + } + + return (ret_val); +} + +/* + * e1000_update_nvm_checksum_82571 - Update EEPROM checksum + * @hw: pointer to the HW structure + * + * Updates the EEPROM checksum by reading/adding each word of the EEPROM + * up to the checksum. Then calculates the EEPROM checksum and writes the + * value to the EEPROM. + */ +static s32 +e1000_update_nvm_checksum_82571(struct e1000_hw *hw) +{ + u32 eecd; + s32 ret_val; + u16 i; + + DEBUGFUNC("e1000_update_nvm_checksum_82571"); + + ret_val = e1000_update_nvm_checksum_generic(hw); + if (ret_val) + goto out; + + /* + * If our nvm is an EEPROM, then we're done + * otherwise, commit the checksum to the flash NVM. + */ + if (hw->nvm.type != e1000_nvm_flash_hw) + goto out; + + /* Check for pending operations. */ + for (i = 0; i < E1000_FLASH_UPDATES; i++) { + msec_delay(1); + if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + break; + } + + if (i == E1000_FLASH_UPDATES) { + ret_val = -E1000_ERR_NVM; + goto out; + } + + /* Reset the firmware if using STM opcode. */ + if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { + /* + * The enabling of and the actual reset must be done + * in two write cycles. + */ + E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); + } + + /* Commit the write to flash */ + eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + + for (i = 0; i < E1000_FLASH_UPDATES; i++) { + msec_delay(1); + if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + break; + } + + if (i == E1000_FLASH_UPDATES) { + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM + * and then verifies that the sum of the EEPROM is equal to 0xBABA. + */ +static s32 +e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_validate_nvm_checksum_82571"); + + if (hw->nvm.type == e1000_nvm_flash_hw) + e1000_fix_nvm_checksum_82571(hw); + + return (e1000_validate_nvm_checksum_generic(hw)); +} + +/* + * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write + * @data: 16 bit word(s) to be written to the EEPROM + * + * After checking for invalid values, poll the EEPROM to ensure the previous + * command has completed before trying to write the next word. After write + * poll for completion. + * + * If e1000_update_nvm_checksum is not called after this function, the + * EEPROM will most likley contain an invalid checksum. + */ +static s32 +e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eewr = 0; + s32 ret_val = 0; + + DEBUGFUNC("e1000_write_nvm_eewr_82571"); + + /* + * A check for invalid values: offset too large, too many words, + * and not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + for (i = 0; i < words; i++) { + eewr = (data[i] << E1000_NVM_RW_REG_DATA) | + ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | + E1000_NVM_RW_REG_START; + + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); + if (ret_val) + break; + + E1000_WRITE_REG(hw, E1000_EEWR, eewr); + + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); + if (ret_val) + break; + } + +out: + return (ret_val); +} + +/* + * e1000_get_cfg_done_82571 - Poll for configuration done + * @hw: pointer to the HW structure + * + * Reads the management control register for the config done bit to be set. + */ +static s32 +e1000_get_cfg_done_82571(struct e1000_hw *hw) +{ + s32 timeout = PHY_CFG_TIMEOUT; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_get_cfg_done_82571"); + + while (timeout) { + if (E1000_READ_REG(hw, E1000_EEMNGCTL) & + E1000_NVM_CFG_DONE_PORT_0) + break; + msec_delay(1); + timeout--; + } + if (!timeout) { + DEBUGOUT("MNG configuration cycle has not completed.\n"); + ret_val = -E1000_ERR_RESET; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D0 state according to the active flag. When activating LPLU + * this function also disables smart speed and vice versa. LPLU will not be + * activated unless the device autonegotiation advertisement meets standards + * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function + * pointer entry point only called by PHY setup routines. + */ +static s32 +e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, boolean_t active) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_set_d0_lplu_state_82571"); + + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) + goto out; + + if (active) { + data |= IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, + data); + if (ret_val) + goto out; + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else { + data &= ~IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, + data); + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } + } + +out: + return (ret_val); +} + +/* + * e1000_reset_hw_82571 - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a + * function pointer entry point called by the api module. + */ +static s32 +e1000_reset_hw_82571(struct e1000_hw *hw) +{ + u32 ctrl, extcnf_ctrl, ctrl_ext, icr; + s32 ret_val; + u16 i = 0; + + DEBUGFUNC("e1000_reset_hw_82571"); + + /* + * Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ + ret_val = e1000_disable_pcie_master_generic(hw); + if (ret_val) { + DEBUGOUT("PCI-E Master disable polling has failed.\n"); + } + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + msec_delay(10); + + /* + * Must acquire the MDIO ownership before MAC reset. + * Ownership defaults to firmware after a reset. + */ + if (hw->mac.type == e1000_82573) { + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; + + do { + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + + if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) + break; + + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; + + msec_delay(2); + i++; + } while (i < MDIO_OWNERSHIP_TIMEOUT); + } + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + DEBUGOUT("Issuing a global reset to MAC\n"); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); + + if (hw->nvm.type == e1000_nvm_flash_hw) { + usec_delay(10); + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + + ret_val = e1000_get_auto_rd_done_generic(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ + goto out; + + /* + * Phy configuration from NVM just starts after EECD_AUTO_RD is set. + * Need to wait for Phy configuration completion before accessing + * NVM and Phy. + */ + if (hw->mac.type == e1000_82573) + msec_delay(25); + + /* Clear any pending interrupt events. */ + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + +out: + return (ret_val); +} + +/* + * e1000_init_hw_82571 - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. + */ +static s32 +e1000_init_hw_82571(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 reg_data; + s32 ret_val; + u16 i, rar_count = mac->rar_entry_count; + + DEBUGFUNC("e1000_init_hw_82571"); + + e1000_initialize_hw_bits_82571(hw); + + /* Initialize identification LED */ + ret_val = e1000_id_led_init_generic(hw); + if (ret_val) { + DEBUGOUT("Error initializing identification LED\n"); + goto out; + } + + /* Disabling VLAN filtering */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + e1000_clear_vfta(hw); + + /* Setup the receive address. */ + /* + * If, however, a locally administered address was assigned to the + * 82571, we must reserve a RAR for it to work around an issue where + * resetting one port will reload the MAC on the other port. + */ + if (e1000_get_laa_state_82571(hw)) + rar_count--; + e1000_init_rx_addrs_generic(hw, rar_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + /* Set the transmit descriptor write-back policy */ + reg_data = E1000_READ_REG(hw, E1000_TXDCTL); + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | + E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); + + /* ...for both queues. */ + if (mac->type != e1000_82573) { + reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | + E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); + } else { + e1000_enable_tx_pkt_filtering(hw); + reg_data = E1000_READ_REG(hw, E1000_GCR); + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + E1000_WRITE_REG(hw, E1000_GCR, reg_data); + } + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_82571(hw); + +out: + return (ret_val); +} + +/* + * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits + * @hw: pointer to the HW structure + * + * Initializes required hardware-dependent bits needed for normal operation. + */ +static void +e1000_initialize_hw_bits_82571(struct e1000_hw *hw) +{ + u32 reg; + + DEBUGFUNC("e1000_initialize_hw_bits_82571"); + + if (hw->mac.disable_hw_init_bits) + return; + + /* Transmit Descriptor Control 0 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL, reg); + + /* Transmit Descriptor Control 1 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL1); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); + + /* Transmit Arbitration Control 0 */ + reg = E1000_READ_REG(hw, E1000_TARC0); + reg &= ~(0xF << 27); /* 30:27 */ + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); + break; + default: + break; + } + E1000_WRITE_REG(hw, E1000_TARC0, reg); + + /* Transmit Arbitration Control 1 */ + reg = E1000_READ_REG(hw, E1000_TARC1); + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + reg &= ~((1 << 29) | (1 << 30)); + reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) + reg &= ~(1 << 28); + else + reg |= (1 << 28); + E1000_WRITE_REG(hw, E1000_TARC1, reg); + break; + default: + break; + } + + /* Device Control */ + if (hw->mac.type == e1000_82573) { + reg = E1000_READ_REG(hw, E1000_CTRL); + reg &= ~(1 << 29); + E1000_WRITE_REG(hw, E1000_CTRL, reg); + } + + /* Extended Device Control */ + if (hw->mac.type == e1000_82573) { + reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + reg &= ~(1 << 23); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); + } +} + +/* + * e1000_clear_vfta_82571 - Clear VLAN filter table + * @hw: pointer to the HW structure + * + * Clears the register array which contains the VLAN filter table by + * setting all the values to 0. + */ +static void +e1000_clear_vfta_82571(struct e1000_hw *hw) +{ + u32 offset; + u32 vfta_value = 0; + u32 vfta_offset = 0; + u32 vfta_bit_in_reg = 0; + + DEBUGFUNC("e1000_clear_vfta_82571"); + + if (hw->mac.type == e1000_82573) { + if (hw->mng_cookie.vlan_id != 0) { + /* + * The VFTA is a 4096b bit-field, each identifying + * a single VLAN ID. The following operations + * determine which 32b entry (i.e. offset) into the + * array we want to set the VLAN ID (i.e. bit) of + * the manageability unit. + */ + vfta_offset = (hw->mng_cookie.vlan_id >> + E1000_VFTA_ENTRY_SHIFT) & + E1000_VFTA_ENTRY_MASK; + vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & + E1000_VFTA_ENTRY_BIT_SHIFT_MASK); + } + } + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { + /* + * If the offset we want to clear is the same offset of the + * manageability VLAN ID, then clear all bits except that of + * the manageability unit. + */ + vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); + E1000_WRITE_FLUSH(hw); + } +} + +/* + * e1000_mc_addr_list_update_82571 - Update Multicast addresses + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program + * @rar_used_count: the first RAR register free to program + * @rar_count: total number of supported Receive Address Registers + * + * Updates the Receive Address Registers and Multicast Table Array. + * The caller must have a packed mc_addr_list of multicast addresses. + * The parameter rar_count will usually be hw->mac.rar_entry_count + * unless there are workarounds that change this. + */ +static void +e1000_mc_addr_list_update_82571(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count) +{ + DEBUGFUNC("e1000_mc_addr_list_update_82571"); + + if (e1000_get_laa_state_82571(hw)) + rar_count--; + + e1000_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, + rar_used_count, rar_count); +} + +/* + * e1000_setup_link_82571 - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow + * control. Calls the appropriate media-specific link configuration + * function. Assuming the adapter has a valid link partner, a valid link + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + */ +static s32 +e1000_setup_link_82571(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_setup_link_82571"); + + /* + * 82573 does not have a word in the NVM to determine + * the default flow control setting, so we explicitly + * set it to full. + */ + if (hw->mac.type == e1000_82573) + hw->mac.fc = e1000_fc_full; + + return (e1000_setup_link_generic(hw)); +} + +/* + * e1000_setup_copper_link_82571 - Configure copper link settings + * @hw: pointer to the HW structure + * + * Configures the link for auto-neg or forced speed and duplex. Then we check + * for link, once link is established calls to configure collision distance + * and flow control are called. + */ +static s32 +e1000_setup_copper_link_82571(struct e1000_hw *hw) +{ + u32 ctrl, led_ctrl; + s32 ret_val; + + DEBUGFUNC("e1000_setup_copper_link_82571"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + switch (hw->phy.type) { + case e1000_phy_m88: + ret_val = e1000_copper_link_setup_m88(hw); + break; + case e1000_phy_igp_2: + ret_val = e1000_copper_link_setup_igp(hw); + /* Setup activity LED */ + led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); + break; + default: + ret_val = -E1000_ERR_PHY; + break; + } + + if (ret_val) + goto out; + + ret_val = e1000_setup_copper_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes + * @hw: pointer to the HW structure + * + * Configures collision distance and flow control for fiber and serdes links. + * Upon successful setup, poll for link. + */ +static s32 +e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); + + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + /* + * If SerDes loopback mode is entered, there is no form + * of reset to take the adapter out of that mode. So we + * have to explicitly take the adapter out of loopback + * mode. This prevents drivers from twidling their thumbs + * if another tool failed to take it out of loopback mode. + */ + E1000_WRITE_REG(hw, E1000_SCTL, + E1000_SCTL_DISABLE_SERDES_LOOPBACK); + break; + default: + break; + } + + return (e1000_setup_fiber_serdes_link_generic(hw)); +} + +/* + * e1000_valid_led_default_82571 - Verify a valid default LED config + * @hw: pointer to the HW structure + * @data: pointer to the NVM (EEPROM) + * + * Read the EEPROM for the current default LED configuration. If the + * LED configuration is not valid, set to a valid LED configuration. + */ +static s32 +e1000_valid_led_default_82571(struct e1000_hw *hw, u16 * data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_valid_led_default_82571"); + + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if (hw->mac.type == e1000_82573 && + *data == ID_LED_RESERVED_F746) + *data = ID_LED_DEFAULT_82573; + else if (*data == ID_LED_RESERVED_0000 || + *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT; + +out: + return (ret_val); +} + +/* + * e1000_get_laa_state_82571 - Get locally administered address state + * @hw: pointer to the HW structure + * + * Retrieve and return the current locally administed address state. + */ +boolean_t +e1000_get_laa_state_82571(struct e1000_hw *hw) +{ + struct e1000_dev_spec_82571 *dev_spec; + boolean_t state = FALSE; + + DEBUGFUNC("e1000_get_laa_state_82571"); + + if (hw->mac.type != e1000_82571) + goto out; + + dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; + + state = dev_spec->laa_is_present; + +out: + return (state); +} + +/* + * e1000_set_laa_state_82571 - Set locally administered address state + * @hw: pointer to the HW structure + * @state: enable/disable locally administered address + * + * Enable/Disable the current locally administed address state. + */ +void +e1000_set_laa_state_82571(struct e1000_hw *hw, boolean_t state) +{ + struct e1000_dev_spec_82571 *dev_spec; + + DEBUGFUNC("e1000_set_laa_state_82571"); + + if (hw->mac.type != e1000_82571) + return; + + dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; + + dev_spec->laa_is_present = state; + + /* If workaround is activated... */ + if (state) { + /* + * Hold a copy of the LAA in RAR[14] This is done so that + * between the time RAR[0] gets clobbered and the time it + * gets fixed, the actual LAA is in one of the RARs and no + * incoming packets directed to this port are dropped. + * Eventually the LAA will be in RAR[0] and RAR[14]. + */ + e1000_rar_set_generic(hw, hw->mac.addr, + hw->mac.rar_entry_count - 1); + } +} + +/* + * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum + * @hw: pointer to the HW structure + * + * Verifies that the EEPROM has completed the update. After updating the + * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If + * the checksum fix is not implemented, we need to set the bit and update + * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, + * we need to return bad checksum. + */ +static s32 +e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_fix_nvm_checksum_82571"); + + if (nvm->type != e1000_nvm_flash_hw) + goto out; + + /* + * Check bit 4 of word 10h. If it is 0, firmware is done updating + * 10h-12h. Checksum may need to be fixed. + */ + ret_val = e1000_read_nvm(hw, 0x10, 1, &data); + if (ret_val) + goto out; + + if (!(data & 0x10)) { + /* + * Read 0x23 and check bit 15. This bit is a 1 + * when the checksum has already been fixed. If + * the checksum is still wrong and this bit is a + * 1, we need to return bad checksum. Otherwise, + * we need to set this bit to a 1 and update the + * checksum. + */ + ret_val = e1000_read_nvm(hw, 0x23, 1, &data); + if (ret_val) + goto out; + + if (!(data & 0x8000)) { + data |= 0x8000; + ret_val = e1000_write_nvm(hw, 0x23, 1, &data); + if (ret_val) + goto out; + ret_val = e1000_update_nvm_checksum(hw); + } + } + +out: + return (ret_val); +} + +/* + * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters + * @hw: pointer to the HW structure + * + * Clears the hardware counters by reading the counter registers. + */ +static void +e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_82571"); + + e1000_clear_hw_cntrs_base_generic(hw); + temp = E1000_READ_REG(hw, E1000_PRC64); + temp = E1000_READ_REG(hw, E1000_PRC127); + temp = E1000_READ_REG(hw, E1000_PRC255); + temp = E1000_READ_REG(hw, E1000_PRC511); + temp = E1000_READ_REG(hw, E1000_PRC1023); + temp = E1000_READ_REG(hw, E1000_PRC1522); + temp = E1000_READ_REG(hw, E1000_PTC64); + temp = E1000_READ_REG(hw, E1000_PTC127); + temp = E1000_READ_REG(hw, E1000_PTC255); + temp = E1000_READ_REG(hw, E1000_PTC511); + temp = E1000_READ_REG(hw, E1000_PTC1023); + temp = E1000_READ_REG(hw, E1000_PTC1522); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); + + temp = E1000_READ_REG(hw, E1000_MGTPRC); + temp = E1000_READ_REG(hw, E1000_MGTPDC); + temp = E1000_READ_REG(hw, E1000_MGTPTC); + + temp = E1000_READ_REG(hw, E1000_IAC); + temp = E1000_READ_REG(hw, E1000_ICRXOC); + + temp = E1000_READ_REG(hw, E1000_ICRXPTC); + temp = E1000_READ_REG(hw, E1000_ICRXATC); + temp = E1000_READ_REG(hw, E1000_ICTXPTC); + temp = E1000_READ_REG(hw, E1000_ICTXATC); + temp = E1000_READ_REG(hw, E1000_ICTXQEC); + temp = E1000_READ_REG(hw, E1000_ICTXQMTC); + temp = E1000_READ_REG(hw, E1000_ICRXDMTC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_82571.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,50 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_82571_H_ +#define _E1000_82571_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ID_LED_RESERVED_F746 0xF746 +#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ + (ID_LED_OFF1_ON2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) + +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_82571_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_api.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1194 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#include "e1000_api.h" +#include "e1000_mac.h" +#include "e1000_nvm.h" +#include "e1000_phy.h" + +extern void e1000_init_function_pointers_82542(struct e1000_hw *hw); +extern void e1000_init_function_pointers_82543(struct e1000_hw *hw); +extern void e1000_init_function_pointers_82540(struct e1000_hw *hw); +extern void e1000_init_function_pointers_82571(struct e1000_hw *hw); +extern void e1000_init_function_pointers_82541(struct e1000_hw *hw); +extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); +extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw); +extern void e1000_init_function_pointers_vf(struct e1000_hw *hw); + +/* + * e1000_init_mac_params - Initialize MAC function pointers + * @hw: pointer to the HW structure + * + * This function initializes the function pointers for the MAC + * set of functions. Called by drivers or by e1000_setup_init_funcs. + */ +s32 +e1000_init_mac_params(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + if (hw->func.init_mac_params) { + ret_val = hw->func.init_mac_params(hw); + if (ret_val) { + DEBUGOUT("MAC Initialization Error\n"); + goto out; + } + } else { + DEBUGOUT("mac.init_mac_params was NULL\n"); + ret_val = -E1000_ERR_CONFIG; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params - Initialize NVM function pointers + * @hw: pointer to the HW structure + * + * This function initializes the function pointers for the NVM + * set of functions. Called by drivers or by e1000_setup_init_funcs. + */ +s32 +e1000_init_nvm_params(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + if (hw->func.init_nvm_params) { + ret_val = hw->func.init_nvm_params(hw); + if (ret_val) { + DEBUGOUT("NVM Initialization Error\n"); + goto out; + } + } else { + DEBUGOUT("nvm.init_nvm_params was NULL\n"); + ret_val = -E1000_ERR_CONFIG; + } + +out: + return (ret_val); +} + +/* + * e1000_init_phy_params - Initialize PHY function pointers + * @hw: pointer to the HW structure + * + * This function initializes the function pointers for the PHY + * set of functions. Called by drivers or by e1000_setup_init_funcs. + */ +s32 +e1000_init_phy_params(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + if (hw->func.init_phy_params) { + ret_val = hw->func.init_phy_params(hw); + if (ret_val) { + DEBUGOUT("PHY Initialization Error\n"); + goto out; + } + } else { + DEBUGOUT("phy.init_phy_params was NULL\n"); + ret_val = -E1000_ERR_CONFIG; + } + +out: + return (ret_val); +} + +/* + * e1000_set_mac_type - Sets MAC type + * @hw: pointer to the HW structure + * + * This function sets the mac type of the adapter based on the + * device ID stored in the hw structure. + * MUST BE FIRST FUNCTION CALLED (explicitly or through + * e1000_setup_init_funcs()). + */ +s32 +e1000_set_mac_type(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_set_mac_type"); + + switch (hw->device_id) { + case E1000_DEV_ID_82542: + mac->type = e1000_82542; + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + mac->type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + mac->type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + case E1000_DEV_ID_82540EP: + case E1000_DEV_ID_82540EP_LOM: + case E1000_DEV_ID_82540EP_LP: + mac->type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + mac->type = e1000_82545; + break; + case E1000_DEV_ID_82545GM_COPPER: + case E1000_DEV_ID_82545GM_FIBER: + case E1000_DEV_ID_82545GM_SERDES: + mac->type = e1000_82545_rev_3; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546EB_QUAD_COPPER: + mac->type = e1000_82546; + break; + case E1000_DEV_ID_82546GB_COPPER: + case E1000_DEV_ID_82546GB_FIBER: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82546GB_PCIE: + case E1000_DEV_ID_82546GB_QUAD_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: + mac->type = e1000_82546_rev_3; + break; + case E1000_DEV_ID_82541EI: + case E1000_DEV_ID_82541EI_MOBILE: + case E1000_DEV_ID_82541ER_LOM: + mac->type = e1000_82541; + break; + case E1000_DEV_ID_82541ER: + case E1000_DEV_ID_82541GI: + case E1000_DEV_ID_82541GI_LF: + case E1000_DEV_ID_82541GI_MOBILE: + mac->type = e1000_82541_rev_2; + break; + case E1000_DEV_ID_82547EI: + case E1000_DEV_ID_82547EI_MOBILE: + mac->type = e1000_82547; + break; + case E1000_DEV_ID_82547GI: + mac->type = e1000_82547_rev_2; + break; + case E1000_DEV_ID_82571EB_COPPER: + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_SERDES_DUAL: + case E1000_DEV_ID_82571EB_SERDES_QUAD: + case E1000_DEV_ID_82571EB_QUAD_COPPER: + case E1000_DEV_ID_82571PT_QUAD_COPPER: + case E1000_DEV_ID_82571EB_QUAD_FIBER: + case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: + mac->type = e1000_82571; + break; + case E1000_DEV_ID_82572EI: + case E1000_DEV_ID_82572EI_COPPER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82572EI_SERDES: + mac->type = e1000_82572; + break; + case E1000_DEV_ID_82573E: + case E1000_DEV_ID_82573E_IAMT: + case E1000_DEV_ID_82573L: + mac->type = e1000_82573; + break; + case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: + mac->type = e1000_80003es2lan; + break; + case E1000_DEV_ID_ICH8_IFE: + case E1000_DEV_ID_ICH8_IFE_GT: + case E1000_DEV_ID_ICH8_IFE_G: + case E1000_DEV_ID_ICH8_IGP_M: + case E1000_DEV_ID_ICH8_IGP_M_AMT: + case E1000_DEV_ID_ICH8_IGP_AMT: + case E1000_DEV_ID_ICH8_IGP_C: + mac->type = e1000_ich8lan; + break; + case E1000_DEV_ID_ICH9_IFE: + case E1000_DEV_ID_ICH9_IFE_GT: + case E1000_DEV_ID_ICH9_IFE_G: + case E1000_DEV_ID_ICH9_IGP_AMT: + case E1000_DEV_ID_ICH9_IGP_C: + mac->type = e1000_ich9lan; + break; + default: + /* Should never have loaded on this device */ + ret_val = -E1000_ERR_MAC_INIT; + break; + } + + return (ret_val); +} + +/* + * e1000_setup_init_funcs - Initializes function pointers + * @hw: pointer to the HW structure + * @init_device: TRUE will initialize the rest of the function pointers + * getting the device ready for use. FALSE will only set + * MAC type and the function pointers for the other init + * functions. Passing FALSE will not generate any hardware + * reads or writes. + * + * This function must be called by a driver in order to use the rest + * of the 'shared' code files. Called by drivers only. + */ +s32 +e1000_setup_init_funcs(struct e1000_hw *hw, boolean_t init_device) +{ + s32 ret_val; + + /* Can't do much good without knowing the MAC type. */ + ret_val = e1000_set_mac_type(hw); + if (ret_val) { + DEBUGOUT("ERROR: MAC type could not be set properly.\n"); + goto out; + } + if (!hw->hw_addr) { + DEBUGOUT("ERROR: Registers not mapped\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + /* + * Init some generic function pointers that are currently all pointing + * to generic implementations. We do this first allowing a driver + * module to override it afterwards. + */ + hw->func.config_collision_dist = e1000_config_collision_dist_generic; + hw->func.rar_set = e1000_rar_set_generic; + hw->func.validate_mdi_setting = e1000_validate_mdi_setting_generic; + hw->func.mng_host_if_write = e1000_mng_host_if_write_generic; + hw->func.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; + hw->func.mng_enable_host_if = e1000_mng_enable_host_if_generic; + hw->func.wait_autoneg = e1000_wait_autoneg_generic; + hw->func.reload_nvm = e1000_reload_nvm_generic; + + /* + * Set up the init function pointers. These are functions within the + * adapter family file that sets up function pointers for the rest of + * the functions in that family. + */ + switch (hw->mac.type) { + case e1000_82542: + e1000_init_function_pointers_82542(hw); + break; + case e1000_82543: + case e1000_82544: + e1000_init_function_pointers_82543(hw); + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + e1000_init_function_pointers_82540(hw); + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + e1000_init_function_pointers_82541(hw); + break; + case e1000_82571: + case e1000_82572: + case e1000_82573: + e1000_init_function_pointers_82571(hw); + break; + case e1000_80003es2lan: + e1000_init_function_pointers_80003es2lan(hw); + break; + case e1000_ich8lan: + case e1000_ich9lan: + e1000_init_function_pointers_ich8lan(hw); + break; + default: + DEBUGOUT("Hardware not supported\n"); + ret_val = -E1000_ERR_CONFIG; + break; + } + + /* + * Initialize the rest of the function pointers. These require some + * register reads/writes in some cases. + */ + if (!(ret_val) && init_device) { + ret_val = e1000_init_mac_params(hw); + if (ret_val) + goto out; + + ret_val = e1000_init_nvm_params(hw); + if (ret_val) + goto out; + + ret_val = e1000_init_phy_params(hw); + if (ret_val) + goto out; + + } + +out: + return (ret_val); +} + +/* + * e1000_remove_device - Free device specific structure + * @hw: pointer to the HW structure + * + * If a device specific structure was allocated, this function will + * free it. This is a function pointer entry point called by drivers. + */ +void +e1000_remove_device(struct e1000_hw *hw) +{ + if (hw->func.remove_device) + hw->func.remove_device(hw); +} + +/* + * e1000_get_bus_info - Obtain bus information for adapter + * @hw: pointer to the HW structure + * + * This will obtain information about the HW bus for which the + * adaper is attached and stores it in the hw structure. This is a + * function pointer entry point called by drivers. + */ +s32 +e1000_get_bus_info(struct e1000_hw *hw) +{ + if (hw->func.get_bus_info) + return (hw->func.get_bus_info(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_clear_vfta - Clear VLAN filter table + * @hw: pointer to the HW structure + * + * This clears the VLAN filter table on the adapter. This is a function + * pointer entry point called by drivers. + */ +void +e1000_clear_vfta(struct e1000_hw *hw) +{ + if (hw->func.clear_vfta) + hw->func.clear_vfta(hw); +} + +/* + * e1000_write_vfta - Write value to VLAN filter table + * @hw: pointer to the HW structure + * @offset: the 32-bit offset in which to write the value to. + * @value: the 32-bit value to write at location offset. + * + * This writes a 32-bit value to a 32-bit offset in the VLAN filter + * table. This is a function pointer entry point called by drivers. + */ +void +e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) +{ + if (hw->func.write_vfta) + hw->func.write_vfta(hw, offset, value); +} + +/* + * e1000_mc_addr_list_update - Update Multicast addresses + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program + * @rar_used_count: the first RAR register free to program + * @rar_count: total number of supported Receive Address Registers + * + * Updates the Receive Address Registers and Multicast Table Array. + * The caller must have a packed mc_addr_list of multicast addresses. + * The parameter rar_count will usually be hw->mac.rar_entry_count + * unless there are workarounds that change this. Currently no func pointer + * exists and all implementations are handled in the generic version of this + * function. + */ +void +e1000_mc_addr_list_update(struct e1000_hw *hw, u8 *mc_addr_list, + u32 mc_addr_count, u32 rar_used_count, u32 rar_count) +{ + if (hw->func.mc_addr_list_update) + hw->func.mc_addr_list_update(hw, + mc_addr_list, + mc_addr_count, + rar_used_count, + rar_count); +} + +/* + * e1000_force_mac_fc - Force MAC flow control + * @hw: pointer to the HW structure + * + * Force the MAC's flow control settings. Currently no func pointer exists + * and all implementations are handled in the generic version of this + * function. + */ +s32 +e1000_force_mac_fc(struct e1000_hw *hw) +{ + return (e1000_force_mac_fc_generic(hw)); +} + +/* + * e1000_check_for_link - Check/Store link connection + * @hw: pointer to the HW structure + * + * This checks the link condition of the adapter and stores the + * results in the hw->mac structure. This is a function pointer entry + * point called by drivers. + */ +s32 +e1000_check_for_link(struct e1000_hw *hw) +{ + if (hw->func.check_for_link) + return (hw->func.check_for_link(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_check_mng_mode - Check management mode + * @hw: pointer to the HW structure + * + * This checks if the adapter has manageability enabled. + * This is a function pointer entry point called by drivers. + */ +boolean_t +e1000_check_mng_mode(struct e1000_hw *hw) +{ + if (hw->func.check_mng_mode) + return (hw->func.check_mng_mode(hw)); + + return (FALSE); +} + +/* + * e1000_mng_write_dhcp_info - Writes DHCP info to host interface + * @hw: pointer to the HW structure + * @buffer: pointer to the host interface + * @length: size of the buffer + * + * Writes the DHCP information to the host interface. + */ +s32 +e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 * buffer, u16 length) +{ + return (e1000_mng_write_dhcp_info_generic(hw, buffer, length)); +} + +/* + * e1000_reset_hw - Reset hardware + * @hw: pointer to the HW structure + * + * This resets the hardware into a known state. This is a function pointer + * entry point called by drivers. + */ +s32 +e1000_reset_hw(struct e1000_hw *hw) +{ + if (hw->func.reset_hw) + return (hw->func.reset_hw(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_init_hw - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. This is a function + * pointer entry point called by drivers. + */ +s32 +e1000_init_hw(struct e1000_hw *hw) +{ + if (hw->func.init_hw) + return (hw->func.init_hw(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_setup_link - Configures link and flow control + * @hw: pointer to the HW structure + * + * This configures link and flow control settings for the adapter. This + * is a function pointer entry point called by drivers. While modules can + * also call this, they probably call their own version of this function. + */ +s32 +e1000_setup_link(struct e1000_hw *hw) +{ + if (hw->func.setup_link) + return (hw->func.setup_link(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_get_speed_and_duplex - Returns current speed and duplex + * @hw: pointer to the HW structure + * @speed: pointer to a 16-bit value to store the speed + * @duplex: pointer to a 16-bit value to store the duplex. + * + * This returns the speed and duplex of the adapter in the two 'out' + * variables passed in. This is a function pointer entry point called + * by drivers. + */ +s32 +e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex) +{ + if (hw->func.get_link_up_info) + return (hw->func.get_link_up_info(hw, speed, duplex)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_setup_led - Configures SW controllable LED + * @hw: pointer to the HW structure + * + * This prepares the SW controllable LED for use and saves the current state + * of the LED so it can be later restored. This is a function pointer entry + * point called by drivers. + */ +s32 +e1000_setup_led(struct e1000_hw *hw) +{ + if (hw->func.setup_led) + return (hw->func.setup_led(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_cleanup_led - Restores SW controllable LED + * @hw: pointer to the HW structure + * + * This restores the SW controllable LED to the value saved off by + * e1000_setup_led. This is a function pointer entry point called by drivers. + */ +s32 +e1000_cleanup_led(struct e1000_hw *hw) +{ + if (hw->func.cleanup_led) + return (hw->func.cleanup_led(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_blink_led - Blink SW controllable LED + * @hw: pointer to the HW structure + * + * This starts the adapter LED blinking. Request the LED to be setup first + * and cleaned up after. This is a function pointer entry point called by + * drivers. + */ +s32 +e1000_blink_led(struct e1000_hw *hw) +{ + if (hw->func.blink_led) + return (hw->func.blink_led(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_led_on - Turn on SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED on. This is a function pointer entry point + * called by drivers. + */ +s32 +e1000_led_on(struct e1000_hw *hw) +{ + if (hw->func.led_on) + return (hw->func.led_on(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_led_off - Turn off SW controllable LED + * @hw: pointer to the HW structure + * + * Turns the SW defined LED off. This is a function pointer entry point + * called by drivers. + */ +s32 +e1000_led_off(struct e1000_hw *hw) +{ + if (hw->func.led_off) + return (hw->func.led_off(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_reset_adaptive - Reset adaptive IFS + * @hw: pointer to the HW structure + * + * Resets the adaptive IFS. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + */ +void +e1000_reset_adaptive(struct e1000_hw *hw) +{ + e1000_reset_adaptive_generic(hw); +} + +/* + * e1000_update_adaptive - Update adaptive IFS + * @hw: pointer to the HW structure + * + * Updates adapter IFS. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + */ +void +e1000_update_adaptive(struct e1000_hw *hw) +{ + e1000_update_adaptive_generic(hw); +} + +/* + * e1000_disable_pcie_master - Disable PCI-Express master access + * @hw: pointer to the HW structure + * + * Disables PCI-Express master access and verifies there are no pending + * requests. Currently no func pointer exists and all implementations are + * handled in the generic version of this function. + */ +s32 +e1000_disable_pcie_master(struct e1000_hw *hw) +{ + return (e1000_disable_pcie_master_generic(hw)); +} + +/* + * e1000_config_collision_dist - Configure collision distance + * @hw: pointer to the HW structure + * + * Configures the collision distance to the default value and is used + * during link setup. + */ +void +e1000_config_collision_dist(struct e1000_hw *hw) +{ + if (hw->func.config_collision_dist) + hw->func.config_collision_dist(hw); +} + +/* + * e1000_rar_set - Sets a receive address register + * @hw: pointer to the HW structure + * @addr: address to set the RAR to + * @index: the RAR to set + * + * Sets a Receive Address Register (RAR) to the specified address. + */ +void +e1000_rar_set(struct e1000_hw *hw, u8 * addr, u32 index) +{ + if (hw->func.rar_set) + hw->func.rar_set(hw, addr, index); +} + +/* + * e1000_validate_mdi_setting - Ensures valid MDI/MDIX SW state + * @hw: pointer to the HW structure + * + * Ensures that the MDI/MDIX SW state is valid. + */ +s32 +e1000_validate_mdi_setting(struct e1000_hw *hw) +{ + if (hw->func.validate_mdi_setting) + return (hw->func.validate_mdi_setting(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_mta_set - Sets multicast table bit + * @hw: pointer to the HW structure + * @hash_value: Multicast hash value. + * + * This sets the bit in the multicast table corresponding to the + * hash value. This is a function pointer entry point called by drivers. + */ +void +e1000_mta_set(struct e1000_hw *hw, u32 hash_value) +{ + if (hw->func.mta_set) + hw->func.mta_set(hw, hash_value); +} + +/* + * e1000_hash_mc_addr - Determines address location in multicast table + * @hw: pointer to the HW structure + * @mc_addr: Multicast address to hash. + * + * This hashes an address to determine its location in the multicast + * table. Currently no func pointer exists and all implementations + * are handled in the generic version of this function. + */ +u32 +e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) +{ + return (e1000_hash_mc_addr_generic(hw, mc_addr)); +} + +/* + * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX + * @hw: pointer to the HW structure + * + * Enables packet filtering on transmit packets if manageability is enabled + * and host interface is enabled. + * Currently no func pointer exists and all implementations are handled in the + * generic version of this function. + */ +boolean_t +e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) +{ + return (e1000_enable_tx_pkt_filtering_generic(hw)); +} + +/* + * e1000_mng_host_if_write - Writes to the manageability host interface + * @hw: pointer to the HW structure + * @buffer: pointer to the host interface buffer + * @length: size of the buffer + * @offset: location in the buffer to write to + * @sum: sum of the data (not checksum) + * + * This function writes the buffer content at the offset given on the host if. + * It also does alignment considerations to do the writes in most efficient + * way. Also fills up the sum of the buffer in *buffer parameter. + */ +s32 +e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, + u16 offset, u8 *sum) +{ + if (hw->func.mng_host_if_write) + return (hw->func.mng_host_if_write(hw, buffer, length, offset, + sum)); + + return (E1000_NOT_IMPLEMENTED); +} + +/* + * e1000_mng_write_cmd_header - Writes manageability command header + * @hw: pointer to the HW structure + * @hdr: pointer to the host interface command header + * + * Writes the command header after does the checksum calculation. + */ +s32 +e1000_mng_write_cmd_header(struct e1000_hw *hw, + struct e1000_host_mng_command_header *hdr) +{ + if (hw->func.mng_write_cmd_header) + return (hw->func.mng_write_cmd_header(hw, hdr)); + + return (E1000_NOT_IMPLEMENTED); +} + +/* + * e1000_mng_enable_host_if - Checks host interface is enabled + * @hw: pointer to the HW structure + * + * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND + * + * This function checks whether the HOST IF is enabled for command operaton + * and also checks whether the previous command is completed. It busy waits + * in case of previous command is not completed. + */ +s32 +e1000_mng_enable_host_if(struct e1000_hw *hw) +{ + if (hw->func.mng_enable_host_if) + return (hw->func.mng_enable_host_if(hw)); + + return (E1000_NOT_IMPLEMENTED); +} + +/* + * e1000_wait_autoneg - Waits for autonegotiation completion + * @hw: pointer to the HW structure + * + * Waits for autoneg to complete. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + */ +s32 +e1000_wait_autoneg(struct e1000_hw *hw) +{ + if (hw->func.wait_autoneg) + return (hw->func.wait_autoneg(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_check_reset_block - Verifies PHY can be reset + * @hw: pointer to the HW structure + * + * Checks if the PHY is in a state that can be reset or if manageability + * has it tied up. This is a function pointer entry point called by drivers. + */ +s32 +e1000_check_reset_block(struct e1000_hw *hw) +{ + if (hw->func.check_reset_block) + return (hw->func.check_reset_block(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_read_phy_reg - Reads PHY register + * @hw: pointer to the HW structure + * @offset: the register to read + * @data: the buffer to store the 16-bit read. + * + * Reads the PHY register and returns the value in data. + * This is a function pointer entry point called by drivers. + */ +s32 +e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) +{ + if (hw->func.read_phy_reg) + return (hw->func.read_phy_reg(hw, offset, data)); + + return (E1000_SUCCESS); +} + +/* + * e1000_write_phy_reg - Writes PHY register + * @hw: pointer to the HW structure + * @offset: the register to write + * @data: the value to write. + * + * Writes the PHY register at offset with the value in data. + * This is a function pointer entry point called by drivers. + */ +s32 +e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) +{ + if (hw->func.write_phy_reg) + return (hw->func.write_phy_reg(hw, offset, data)); + + return (E1000_SUCCESS); +} + +/* + * e1000_read_kmrn_reg - Reads register using Kumeran interface + * @hw: pointer to the HW structure + * @offset: the register to read + * @data: the location to store the 16-bit value read. + * + * Reads a register out of the Kumeran interface. Currently no func pointer + * exists and all implementations are handled in the generic version of + * this function. + */ +s32 +e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) +{ + return (e1000_read_kmrn_reg_generic(hw, offset, data)); +} + +/* + * e1000_write_kmrn_reg - Writes register using Kumeran interface + * @hw: pointer to the HW structure + * @offset: the register to write + * @data: the value to write. + * + * Writes a register to the Kumeran interface. Currently no func pointer + * exists and all implementations are handled in the generic version of + * this function. + */ +s32 +e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) +{ + return (e1000_write_kmrn_reg_generic(hw, offset, data)); +} + +/* + * e1000_get_cable_length - Retrieves cable length estimation + * @hw: pointer to the HW structure + * + * This function estimates the cable length and stores them in + * hw->phy.min_length and hw->phy.max_length. This is a function pointer + * entry point called by drivers. + */ +s32 +e1000_get_cable_length(struct e1000_hw *hw) +{ + if (hw->func.get_cable_length) + return (hw->func.get_cable_length(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_get_phy_info - Retrieves PHY information from registers + * @hw: pointer to the HW structure + * + * This function gets some information from various PHY registers and + * populates hw->phy values with it. This is a function pointer entry + * point called by drivers. + */ +s32 +e1000_get_phy_info(struct e1000_hw *hw) +{ + if (hw->func.get_phy_info) + return (hw->func.get_phy_info(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_phy_hw_reset - Hard PHY reset + * @hw: pointer to the HW structure + * + * Performs a hard PHY reset. This is a function pointer entry point called + * by drivers. + */ +s32 +e1000_phy_hw_reset(struct e1000_hw *hw) +{ + if (hw->func.reset_phy) + return (hw->func.reset_phy(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_phy_commit - Soft PHY reset + * @hw: pointer to the HW structure + * + * Performs a soft PHY reset on those that apply. This is a function pointer + * entry point called by drivers. + */ +s32 +e1000_phy_commit(struct e1000_hw *hw) +{ + if (hw->func.commit_phy) + return (hw->func.commit_phy(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_set_d3_lplu_state - Sets low power link up state for D0 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * Success returns 0, Failure returns 1 + * + * The low power link up (lplu) state is set to the power management level D0 + * and SmartSpeed is disabled when active is true, else clear lplu for D0 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. This is a function pointer entry point called by drivers. + */ +s32 +e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) +{ + if (hw->func.set_d0_lplu_state) + return (hw->func.set_d0_lplu_state(hw, active)); + + return (E1000_SUCCESS); +} + +/* + * e1000_set_d3_lplu_state - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * Success returns 0, Failure returns 1 + * + * The low power link up (lplu) state is set to the power management level D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. This is a function pointer entry point called by drivers. + */ +s32 +e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) +{ + if (hw->func.set_d3_lplu_state) + return (hw->func.set_d3_lplu_state(hw, active)); + + return (E1000_SUCCESS); +} + +/* + * e1000_read_mac_addr - Reads MAC address + * @hw: pointer to the HW structure + * + * Reads the MAC address out of the adapter and stores it in the HW structure. + * Currently no func pointer exists and all implementations are handled in the + * generic version of this function. + */ +s32 +e1000_read_mac_addr(struct e1000_hw *hw) +{ + return (e1000_read_mac_addr_generic(hw)); +} + +/* + * e1000_read_part_num - Read device part number + * @hw: pointer to the HW structure + * @part_num: pointer to device part number + * + * Reads the product board assembly (PBA) number from the EEPROM and stores + * the value in part_num. + * Currently no func pointer exists and all implementations are handled in the + * generic version of this function. + */ +s32 +e1000_read_part_num(struct e1000_hw *hw, u32 * part_num) +{ + return (e1000_read_part_num_generic(hw, part_num)); +} + +/* + * e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum + * @hw: pointer to the HW structure + * + * Validates the NVM checksum is correct. This is a function pointer entry + * point called by drivers. + */ +s32 +e1000_validate_nvm_checksum(struct e1000_hw *hw) +{ + if (hw->func.validate_nvm) + return (hw->func.validate_nvm(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_update_nvm_checksum - Updates NVM (EEPROM) checksum + * @hw: pointer to the HW structure + * + * Updates the NVM checksum. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + */ +s32 +e1000_update_nvm_checksum(struct e1000_hw *hw) +{ + if (hw->func.update_nvm) + return (hw->func.update_nvm(hw)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_reload_nvm - Reloads EEPROM + * @hw: pointer to the HW structure + * + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the + * extended control register. + */ +void +e1000_reload_nvm(struct e1000_hw *hw) +{ + if (hw->func.reload_nvm) + hw->func.reload_nvm(hw); +} + +/* + * e1000_read_nvm - Reads NVM (EEPROM) + * @hw: pointer to the HW structure + * @offset: the word offset to read + * @words: number of 16-bit words to read + * @data: pointer to the properly sized buffer for the data. + * + * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function + * pointer entry point called by drivers. + */ +s32 +e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + if (hw->func.read_nvm) + return (hw->func.read_nvm(hw, offset, words, data)); + + return (-E1000_ERR_CONFIG); +} + +/* + * e1000_write_nvm - Writes to NVM (EEPROM) + * @hw: pointer to the HW structure + * @offset: the word offset to read + * @words: number of 16-bit words to write + * @data: pointer to the properly sized buffer for the data. + * + * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function + * pointer entry point called by drivers. + */ +s32 +e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + if (hw->func.write_nvm) + return (hw->func.write_nvm(hw, offset, words, data)); + + return (E1000_SUCCESS); +} + +/* + * e1000_write_8bit_ctrl_reg - Writes 8bit Control register + * @hw: pointer to the HW structure + * @reg: 32bit register offset + * @offset: the register to write + * @data: the value to write. + * + * Writes the PHY register at offset with the value in data. + * This is a function pointer entry point called by drivers. + */ +s32 +e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset, u8 data) +{ + return (e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_api.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,187 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_API_H_ +#define _E1000_API_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "e1000_hw.h" + +s32 e1000_set_mac_type(struct e1000_hw *hw); +s32 e1000_setup_init_funcs(struct e1000_hw *hw, boolean_t init_device); +s32 e1000_init_mac_params(struct e1000_hw *hw); +s32 e1000_init_nvm_params(struct e1000_hw *hw); +s32 e1000_init_phy_params(struct e1000_hw *hw); +void e1000_remove_device(struct e1000_hw *hw); +s32 e1000_get_bus_info(struct e1000_hw *hw); +void e1000_clear_vfta(struct e1000_hw *hw); +void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); +s32 e1000_force_mac_fc(struct e1000_hw *hw); +s32 e1000_check_for_link(struct e1000_hw *hw); +s32 e1000_reset_hw(struct e1000_hw *hw); +s32 e1000_init_hw(struct e1000_hw *hw); +s32 e1000_setup_link(struct e1000_hw *hw); +s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); +s32 e1000_disable_pcie_master(struct e1000_hw *hw); +void e1000_config_collision_dist(struct e1000_hw *hw); +void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); +void e1000_mta_set(struct e1000_hw *hw, u32 hash_value); +u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); +void e1000_mc_addr_list_update(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count); +s32 e1000_setup_led(struct e1000_hw *hw); +s32 e1000_cleanup_led(struct e1000_hw *hw); +s32 e1000_check_reset_block(struct e1000_hw *hw); +s32 e1000_blink_led(struct e1000_hw *hw); +s32 e1000_led_on(struct e1000_hw *hw); +s32 e1000_led_off(struct e1000_hw *hw); +void e1000_reset_adaptive(struct e1000_hw *hw); +void e1000_update_adaptive(struct e1000_hw *hw); +s32 e1000_get_cable_length(struct e1000_hw *hw); +s32 e1000_validate_mdi_setting(struct e1000_hw *hw); +s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, + u32 offset, u8 data); +s32 e1000_get_phy_info(struct e1000_hw *hw); +s32 e1000_phy_hw_reset(struct e1000_hw *hw); +s32 e1000_phy_commit(struct e1000_hw *hw); +s32 e1000_read_mac_addr(struct e1000_hw *hw); +s32 e1000_read_part_num(struct e1000_hw *hw, u32 *part_num); +void e1000_reload_nvm(struct e1000_hw *hw); +s32 e1000_update_nvm_checksum(struct e1000_hw *hw); +s32 e1000_validate_nvm_checksum(struct e1000_hw *hw); +s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +s32 e1000_wait_autoneg(struct e1000_hw *hw); +s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); +s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); +boolean_t e1000_check_mng_mode(struct e1000_hw *hw); +boolean_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); +boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); +s32 e1000_mng_enable_host_if(struct e1000_hw *hw); +s32 e1000_mng_host_if_write(struct e1000_hw *hw, + u8 *buffer, u16 length, u16 offset, u8 *sum); +s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, + struct e1000_host_mng_command_header *hdr); +s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, + u8 *buffer, u16 length); +void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, + struct e1000_hw_stats *stats, + u32 frame_len, u8 *mac_addr); +void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, + boolean_t state); +boolean_t e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw); +u32 e1000_translate_register_82542(u32 reg); +void e1000_init_script_state_82541(struct e1000_hw *hw, boolean_t state); +boolean_t e1000_get_laa_state_82571(struct e1000_hw *hw); +void e1000_set_laa_state_82571(struct e1000_hw *hw, boolean_t state); +void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + boolean_t state); +void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); +void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); + +#ifndef FIFO_WORKAROUND +s32 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length); +void e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length); +void e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, + boolean_t state); +boolean_t e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw); +s32 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw); +#endif + +s32 e1000_send_mail_to_pf_vf(struct e1000_hw *hw, u32 *msg, s16 size); +s32 e1000_receive_mail_from_pf_vf(struct e1000_hw *hw, + u32 *msg, s16 size); +s32 e1000_send_mail_to_vf(struct e1000_hw *hw, u32 *msg, + u32 vf_number, s16 size); +s32 e1000_receive_mail_from_vf(struct e1000_hw *hw, u32 *msg, + u32 vf_number, s16 size); +void e1000_vmdq_loopback_enable_vf(struct e1000_hw *hw); +void e1000_vmdq_loopback_disable_vf(struct e1000_hw *hw); +void e1000_vmdq_replication_enable_vf(struct e1000_hw *hw, u32 enables); +void e1000_vmdq_replication_disable_vf(struct e1000_hw *hw); +void e1000_init_vfnumber_index_vf(struct e1000_hw *hw, u32 vf_number); +boolean_t e1000_check_for_pf_ack_vf(struct e1000_hw *hw); +boolean_t e1000_check_for_pf_mail_vf(struct e1000_hw *hw); + + +/* + * TBI_ACCEPT macro definition: + * + * This macro requires: + * adapter = a pointer to struct e1000_hw + * status = the 8 bit status field of the RX descriptor with EOP set + * error = the 8 bit error field of the RX descriptor with EOP set + * length = the sum of all the length fields of the RX descriptors that + * make up the current frame + * last_byte = the last byte of the frame DMAed by the hardware + * max_frame_length = the maximum frame length we want to accept. + * min_frame_length = the minimum frame length we want to accept. + * + * This macro is a conditional that should be used in the interrupt + * handler's Rx processing routine when RxErrors have been detected. + * + * Typical use: + * ... + * if (TBI_ACCEPT) { + * accept_frame = TRUE; + * e1000_tbi_adjust_stats(adapter, MacAddress); + * frame_length--; + * } else { + * accept_frame = FALSE; + * } + * ... + */ + +/* The carrier extension symbol, as received by the NIC. */ +#define CARRIER_EXTENSION 0x0F + +#define TBI_ACCEPT(a, status, errors, length, last_byte) \ + (e1000_tbi_sbp_enabled_82543(a) && \ + (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ + ((last_byte) == CARRIER_EXTENSION) && \ + (((status) & E1000_RXD_STAT_VP) ? \ + (((length) > ((a)->mac.min_frame_size - VLAN_TAG_SIZE)) && \ + ((length) <= ((a)->mac.max_frame_size + 1))) : \ + (((length) > (a)->mac.min_frame_size) && \ + ((length) <= ((a)->mac.max_frame_size + VLAN_TAG_SIZE + 1))))) + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_API_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_defines.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,1445 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_DEFINES_H_ +#define _E1000_DEFINES_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ +#define REQ_TX_DESCRIPTOR_MULTIPLE 8 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8 + +/* Definitions for power management and wakeup registers */ +/* Wake Up Control */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ +#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ + +/* Wake Up Filter Control */ +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ +#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filter bits */ +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Wake Up Status */ +#define E1000_WUS_LNKC E1000_WUFC_LNKC +#define E1000_WUS_MAG E1000_WUFC_MAG +#define E1000_WUS_EX E1000_WUFC_EX +#define E1000_WUS_MC E1000_WUFC_MC +#define E1000_WUS_BC E1000_WUFC_BC +#define E1000_WUS_ARP E1000_WUFC_ARP +#define E1000_WUS_IPV4 E1000_WUFC_IPV4 +#define E1000_WUS_IPV6 E1000_WUFC_IPV6 +#define E1000_WUS_FLX0 E1000_WUFC_FLX0 +#define E1000_WUS_FLX1 E1000_WUFC_FLX1 +#define E1000_WUS_FLX2 E1000_WUFC_FLX2 +#define E1000_WUS_FLX3 E1000_WUFC_FLX3 +#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS + +/* Wake Up Packet Length */ +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ + +/* Four Flexible Filters are supported */ +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 + +/* Each Flexible Filter is at most 128 (0x80) bytes in length */ +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 + +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX + +/* Extended Device Control */ +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +/* Physical Func Reset Done Indication */ +#define E1000_CTRL_EXT_PFRSTD 0x00004000 +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 +#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 +#define E1000_CTRL_EXT_EIAME 0x01000000 +#define E1000_CTRL_EXT_IRCA 0x00000001 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 +#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */ +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ +/* Clear Interrupt timers after IMS clear */ +#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 +/* packet buffer parity error detection enabled */ +#define E1000_CRTL_EXT_PB_PAREN 0x01000000 +/* descriptor FIFO parity error detection enable */ +#define E1000_CTRL_EXT_DF_PAREN 0x02000000 +#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 +#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ +#define E1000_I2CCMD_REG_ADDR_SHIFT 16 +#define E1000_I2CCMD_REG_ADDR 0x00FF0000 +#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 +#define E1000_I2CCMD_PHY_ADDR 0x07000000 +#define E1000_I2CCMD_OPCODE_READ 0x08000000 +#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 +#define E1000_I2CCMD_RESET 0x10000000 +#define E1000_I2CCMD_READY 0x20000000 +#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 +#define E1000_I2CCMD_ERROR 0x80000000 +#define E1000_MAX_SGMII_PHY_REG_ADDR 255 +#define E1000_I2CCMD_PHY_TIMEOUT 200 +#define E1000_IVAR_VALID 0x80 +#define E1000_GPIE_NSICR 0x00000001 +#define E1000_GPIE_MSIX_MODE 0x00000010 +#define E1000_GPIE_EIAME 0x40000000 +#define E1000_GPIE_PBA 0x80000000 + +/* Receive Decriptor bit definitions */ +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ +#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ +#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ +#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ +#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define E1000_RXD_SPC_PRI_SHIFT 13 +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +#define E1000_RXD_SPC_CFI_SHIFT 12 + +#define E1000_RXDEXT_STATERR_CE 0x01000000 +#define E1000_RXDEXT_STATERR_SE 0x02000000 +#define E1000_RXDEXT_STATERR_SEQ 0x04000000 +#define E1000_RXDEXT_STATERR_CXE 0x10000000 +#define E1000_RXDEXT_STATERR_TCPE 0x20000000 +#define E1000_RXDEXT_STATERR_IPE 0x40000000 +#define E1000_RXDEXT_STATERR_RXE 0x80000000 + +/* mask to determine if packets should be dropped due to frame errors */ +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ + E1000_RXD_ERR_CE | \ + E1000_RXD_ERR_SE | \ + E1000_RXD_ERR_SEQ | \ + E1000_RXD_ERR_CXE | \ + E1000_RXD_ERR_RXE) + +/* Same mask, but for extended and packet split descriptors */ +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ + E1000_RXDEXT_STATERR_CE | \ + E1000_RXDEXT_STATERR_SE | \ + E1000_RXDEXT_STATERR_SEQ | \ + E1000_RXDEXT_STATERR_CXE | \ + E1000_RXDEXT_STATERR_RXE) + +#define E1000_MRQC_ENABLE_MASK 0x00000007 +#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 +#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 +#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 +#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 +#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 +#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 +#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 + +#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 +#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF + +/* Management Control */ +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +/* Enable Neighbor Discovery Filtering */ +#define E1000_MANC_NEIGHBOR_EN 0x00004000 +#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ +#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ +/* Enable MAC address filtering */ +#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 +/* Enable MNG packets to host memory */ +#define E1000_MANC_EN_MNG2HOST 0x00200000 +/* Enable IP address filtering */ +#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 +#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable cksum filtering */ +#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ + +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ + +/* Receive Control */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ +#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ +#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ +#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ + +/* + * Use byte values for the following shift parameters + * Usage: + * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & + * E1000_PSRCTL_BSIZE0_MASK) | + * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & + * E1000_PSRCTL_BSIZE1_MASK) | + * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & + * E1000_PSRCTL_BSIZE2_MASK) | + * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; + * E1000_PSRCTL_BSIZE3_MASK)) + * where value0 = [128..16256], default=256 + * value1 = [1024..64512], default=4096 + * value2 = [0..64512], default=4096 + * value3 = [0..64512], default=0 + */ + +#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F +#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 +#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 +#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 + +#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ +#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ +#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ +#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ + +/* SWFW_SYNC Definitions */ +#define E1000_SWFW_EEP_SM 0x1 +#define E1000_SWFW_PHY0_SM 0x2 +#define E1000_SWFW_PHY1_SM 0x4 + +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /* Block new Master requests */ +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ +/* Defined polarity of Dock/Undock indication in SDP[0] */ +#define E1000_CTRL_D_UD_POLARITY 0x00004000 +/* Reset both PHY ports, through PHYRST_N pin */ +#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 +/* enable link status from external LINK_0 and LINK_1 pins */ +#define E1000_CTRL_EXT_LINK_EN 0x00010000 +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ +/* Initiate an interrupt to manageability engine */ +#define E1000_CTRL_SW2FW_INT 0x02000000 +#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ + +/* + * Bit definitions for the Management Data IO (MDIO) and Management Data + * Clock (MDC) pins in the Device Control Register. + */ +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA + +#define E1000_CONNSW_ENRGSRC 0x4 +#define E1000_PCS_LCTL_FLV_LINK_UP 1 +#define E1000_PCS_LCTL_FSV_10 0 +#define E1000_PCS_LCTL_FSV_100 2 +#define E1000_PCS_LCTL_FSV_1000 4 +#define E1000_PCS_LCTL_FDV_FULL 8 +#define E1000_PCS_LCTL_FSD 0x10 +#define E1000_PCS_LCTL_FORCE_LINK 0x20 +#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 +#define E1000_PCS_LCTL_AN_ENABLE 0x10000 +#define E1000_PCS_LCTL_AN_RESTART 0x20000 +#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 +#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 +#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 +#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 +#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 +#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 +#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 + +#define E1000_PCS_LSTS_LINK_OK 1 +#define E1000_PCS_LSTS_SPEED_10 0 +#define E1000_PCS_LSTS_SPEED_100 2 +#define E1000_PCS_LSTS_SPEED_1000 4 +#define E1000_PCS_LSTS_DUPLEX_FULL 8 +#define E1000_PCS_LSTS_SYNK_OK 0x10 +#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 +#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 +#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 +#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 +#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_SHIFT 2 +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +/* Change in Dock/Undock state. Clear on write '0'. */ +#define E1000_STATUS_DOCK_CI 0x00000800 +/* Status of Master requests. */ +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ +#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ +#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ +#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ +#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ +/* BMC external code execution disabled */ +#define E1000_STATUS_BMC_LITE 0x01000000 +#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ +#define E1000_STATUS_FUSE_8 0x04000000 +#define E1000_STATUS_FUSE_9 0x08000000 +#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ +#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ + +/* Constants used to intrepret the masked PCI-X bus speed. */ +/* PCI-X bus speed 50-66 MHz */ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 +/* PCI-X bus speed 66-100 MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 +/* PCI-X bus speed 100-133 MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +#define PHY_FORCE_TIME 20 + +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ +#define ADVERTISE_1000_FULL 0x0020 + +/* 1000/H is not supported, nor spec-compliant. */ +#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ + ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ + ADVERTISE_1000_FULL) +#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ + ADVERTISE_100_HALF | ADVERTISE_100_FULL) +#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) +#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) +#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ + ADVERTISE_1000_FULL) +#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) + +#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX + +/* LED Control */ +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F +#define E1000_LEDCTL_LED0_MODE_SHIFT 0 +#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 +#define E1000_LEDCTL_LED0_IVRT 0x00000040 +#define E1000_LEDCTL_LED0_BLINK 0x00000080 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8 +#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 +#define E1000_LEDCTL_LED1_IVRT 0x00004000 +#define E1000_LEDCTL_LED1_BLINK 0x00008000 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16 +#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 +#define E1000_LEDCTL_LED2_IVRT 0x00400000 +#define E1000_LEDCTL_LED2_BLINK 0x00800000 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24 +#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 +#define E1000_LEDCTL_LED3_IVRT 0x40000000 +#define E1000_LEDCTL_LED3_BLINK 0x80000000 + +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 +#define E1000_LEDCTL_MODE_LINK_UP 0x2 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 +#define E1000_LEDCTL_MODE_LINK_10 0x5 +#define E1000_LEDCTL_MODE_LINK_100 0x6 +#define E1000_LEDCTL_MODE_LINK_1000 0x7 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +#define E1000_LEDCTL_MODE_COLLISION 0xA +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +#define E1000_LEDCTL_MODE_PAUSED 0xD +#define E1000_LEDCTL_MODE_LED_ON 0xE +#define E1000_LEDCTL_MODE_LED_OFF 0xF + +/* Transmit Descriptor bit definitions */ +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ +/* Descriptor extension (0 = legacy) */ +#define E1000_TXD_CMD_DEXT 0x20000000 +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ +/* Extended desc bits for Linksec and timesync */ + +/* Transmit Control */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ + +/* Transmit Arbitration Count */ +#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ + +/* SerDes Control */ +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 + +/* Receive Checksum Control */ +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ +#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ +#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ +#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ + +/* Header split receive */ +#define E1000_RFCTL_ISCSI_DIS 0x00000001 +#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E +#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 +#define E1000_RFCTL_NFSW_DIS 0x00000040 +#define E1000_RFCTL_NFSR_DIS 0x00000080 +#define E1000_RFCTL_NFS_VER_MASK 0x00000300 +#define E1000_RFCTL_NFS_VER_SHIFT 8 +#define E1000_RFCTL_IPV6_DIS 0x00000400 +#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 +#define E1000_RFCTL_ACK_DIS 0x00001000 +#define E1000_RFCTL_ACKD_DIS 0x00002000 +#define E1000_RFCTL_IPFRSP_DIS 0x00004000 +#define E1000_RFCTL_EXTEN 0x00008000 +#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 +#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 + +/* Collision related configuration parameters */ +#define E1000_COLLISION_THRESHOLD 15 +#define E1000_CT_SHIFT 4 +#define E1000_COLLISION_DISTANCE 63 +#define E1000_COLD_SHIFT 12 + +/* Default values for the transmit IPG register */ +#define DEFAULT_82542_TIPG_IPGT 10 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8 + +#define E1000_TIPG_IPGT_MASK 0x000003FF +#define E1000_TIPG_IPGR1_MASK 0x000FFC00 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000 + +#define DEFAULT_82542_TIPG_IPGR1 2 +#define DEFAULT_82543_TIPG_IPGR1 8 +#define E1000_TIPG_IPGR1_SHIFT 10 + +#define DEFAULT_82542_TIPG_IPGR2 10 +#define DEFAULT_82543_TIPG_IPGR2 6 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 +#define E1000_TIPG_IPGR2_SHIFT 20 + +/* Ethertype field values */ +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ + +#define ETHERNET_FCS_SIZE 4 +#define MAX_JUMBO_FRAME_SIZE 0x3F00 + +/* Extended Configuration Control and Size */ +#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 +#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 +#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 + +#define E1000_PHY_CTRL_SPD_EN 0x00000001 +#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 +#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 +#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 + +#define E1000_KABGTXD_BGSQLBIAS 0x00050000 + +/* PBA constants */ +#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ +#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ +#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ +#define E1000_PBA_20K 0x0014 +#define E1000_PBA_22K 0x0016 +#define E1000_PBA_24K 0x0018 +#define E1000_PBA_30K 0x001E +#define E1000_PBA_32K 0x0020 +#define E1000_PBA_34K 0x0022 +#define E1000_PBA_38K 0x0026 +#define E1000_PBA_40K 0x0028 +#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ + +#define E1000_PBS_16K E1000_PBA_16K +#define E1000_PBS_24K E1000_PBA_24K + +#define IFS_MAX 80 +#define IFS_MIN 40 +#define IFS_RATIO 4 +#define IFS_STEP 10 +#define MIN_NUM_XMITS 1000 + +/* SW Semaphore Register */ +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + +/* Interrupt Cause Read */ +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ +#define E1000_ICR_TXD_LOW 0x00008000 +#define E1000_ICR_SRPD 0x00010000 +#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ +#define E1000_ICR_MNG 0x00040000 /* Manageability event */ +#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ +/* If this bit asserted, the driver should claim the interrupt */ +#define E1000_ICR_INT_ASSERTED 0x80000000 +/* queue 0 Rx descriptor FIFO parity error */ +#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 +/* queue 0 Tx descriptor FIFO parity error */ +#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 +/* host arb read buffer parity error */ +#define E1000_ICR_HOST_ARB_PAR 0x00400000 +/* packet buffer parity error */ +#define E1000_ICR_PB_PAR 0x00800000 +/* queue 1 Rx descriptor FIFO parity error */ +#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 +/* queue 1 Tx descriptor FIFO parity error */ +#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 +/* all parity error bits */ +#define E1000_ICR_ALL_PARITY 0x03F00000 +/* FW changed the status of DISSW bit in the FWSM */ +#define E1000_ICR_DSW 0x00000020 +/* LAN connected device generates an interrupt */ +#define E1000_ICR_PHYINT 0x00001000 +/* ME handware reset occurs */ +#define E1000_ICR_EPRST 0x00100000 + +/* Extended Interrupt Cause Read */ +#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ +#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ +#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ +#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ +#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ +#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ +#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ +#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ +#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ +#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ +/* TCP Timer */ +#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ +#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ +#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ +#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ + +/* + * This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + */ +#define POLL_IMS_ENABLE_MASK ( \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ) + +/* + * This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXT0 = Receiver Timer Interrupt (ring 0) + * o TXDW = Transmit Descriptor Written Back + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + * o LSC = Link Status Change + */ +#define IMS_ENABLE_MASK ( \ + E1000_IMS_RXT0 | \ + E1000_IMS_TXDW | \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ | \ + E1000_IMS_LSC) + +/* Interrupt Mask Set */ +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMS_SRPD E1000_ICR_SRPD +#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ +#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ +#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +/* queue 0 Rx descriptor FIFO parity error */ +#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 +/* queue 0 Tx descriptor FIFO parity error */ +#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 +/* host arb read buffer parity error */ +#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR +/* packet buffer parity error */ +#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR +/* queue 1 Rx descriptor FIFO parity error */ +#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 +/* queue 1 Tx descriptor FIFO parity error */ +#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 +#define E1000_IMS_DSW E1000_ICR_DSW +#define E1000_IMS_PHYINT E1000_ICR_PHYINT +#define E1000_IMS_EPRST E1000_ICR_EPRST + +/* Extended Interrupt Mask Set */ +#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ +#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ +#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ +#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ +#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ +#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ +#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ +#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ +#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ +#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ + +/* Interrupt Cause Set */ +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_ICS_SRPD E1000_ICR_SRPD +#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ +#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ +#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +/* queue 0 Rx descriptor FIFO parity error */ +#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 +/* queue 0 Tx descriptor FIFO parity error */ +#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 +/* host arb read buffer parity error */ +#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR +/* packet buffer parity error */ +#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR +/* queue 1 Rx descriptor FIFO parity error */ +#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 +/* queue 1 Tx descriptor FIFO parity error */ +#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 +#define E1000_ICS_DSW E1000_ICR_DSW +#define E1000_ICS_PHYINT E1000_ICR_PHYINT +#define E1000_ICS_EPRST E1000_ICR_EPRST + +/* Extended Interrupt Cause Set */ +#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ +#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ +#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ +#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ +#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ +#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ +#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ +#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ +#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ +#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ + +/* Transmit Descriptor Control */ +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ +#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ +#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ +/* Enable the counting of descriptors still to be processed. */ +#define E1000_TXDCTL_COUNT_DESC 0x00400000 + +/* Flow Control Constants */ +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 +#define FLOW_CONTROL_TYPE 0x8808 + +/* 802.1q VLAN Packet Size */ +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ + +/* Receive Address */ +/* + * Number of high/low register pairs in the RAR. The RAR (Receive Address + * Registers) holds the directed and multicast addresses that we monitor. + * Technically, we have 16 spots. However, we reserve one of these spots + * (RAR[15]) for our directed address used by controllers with + * manageability enabled, allowing us room for 15 multicast addresses. + */ +#define E1000_RAR_ENTRIES 15 +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ + +/* Error Codes */ +#define E1000_SUCCESS 0 +#define E1000_ERR_NVM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_INIT 5 +#define E1000_ERR_PHY_TYPE 6 +#define E1000_ERR_RESET 9 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +#define E1000_BLK_PHY_RESET 12 +#define E1000_ERR_SWFW_SYNC 13 +#define E1000_NOT_IMPLEMENTED 14 + +/* Loop limit on how long we wait for auto-negotiation to complete */ +#define FIBER_LINK_UP_LIMIT 50 +#define COPPER_LINK_UP_LIMIT 10 +#define PHY_AUTO_NEG_LIMIT 45 +#define PHY_FORCE_LIMIT 20 +/* Number of 100 microseconds we wait for PCI Express master disable */ +#define MASTER_DISABLE_TIMEOUT 800 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */ +#define PHY_CFG_TIMEOUT 100 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ +#define MDIO_OWNERSHIP_TIMEOUT 10 +/* Number of milliseconds for NVM auto read done after MAC reset. */ +#define AUTO_READ_DONE_TIMEOUT 10 + +/* Flow Control */ +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +/* Transmit Configuration Word */ +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ + +/* Receive Configuration Word */ +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +#define E1000_RXCW_C 0x20000000 /* Receive config */ +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ + +/* PCI Express Control */ +#define E1000_GCR_RXD_NO_SNOOP 0x00000001 +#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 +#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 +#define E1000_GCR_TXD_NO_SNOOP 0x00000008 +#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 +#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 + +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ + E1000_GCR_RXDSCW_NO_SNOOP | \ + E1000_GCR_RXDSCR_NO_SNOOP | \ + E1000_GCR_TXD_NO_SNOOP | \ + E1000_GCR_TXDSCW_NO_SNOOP | \ + E1000_GCR_TXDSCR_NO_SNOOP) + +/* PHY Control Register */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ +#define MII_CR_SPEED_1000 0x0040 +#define MII_CR_SPEED_100 0x2000 +#define MII_CR_SPEED_10 0x0000 + +/* PHY Status Register */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + +/* Autoneg Advertisement Register */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Link Partner Ability Register (Base Page) */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Autoneg Expansion Register */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ + +/* 1000BASE-T Control Register */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + +/* 1000BASE-T Status Register */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ + +#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 + +/* PHY 1000 MII Register/Bit Definitions */ +/* PHY Registers defined by IEEE */ +#define PHY_CONTROL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ + +/* NVM Control */ +#define E1000_EECD_SK 0x00000001 /* NVM Clock */ +#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ +#define E1000_EECD_DI 0x00000004 /* NVM Data In */ +#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ +#define E1000_EECD_FWE_MASK 0x00000030 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ +#define E1000_EECD_FWE_SHIFT 4 +#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ +#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ +#define E1000_EECD_PRES 0x00000100 /* NVM Present */ +#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ +/* NVM Addressing bits based on type 0=small, 1=large */ +#define E1000_EECD_ADDR_BITS 0x00000400 +#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ +#ifndef E1000_NVM_GRANT_ATTEMPTS +#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ +#endif +#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ +#define E1000_EECD_SIZE_EX_SHIFT 11 +#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ +#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ +#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ +#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ +#define E1000_EECD_SECVAL_SHIFT 22 + +#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ +#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ +/* Offset to data in NVM read/write registers */ +#define E1000_NVM_RW_REG_DATA 16 +#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ +#define E1000_NVM_RW_REG_START 1 /* Start operation */ +#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ +#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ +#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ +#define E1000_FLASH_UPDATES 2000 + +/* NVM Word Offsets */ +#define NVM_COMPAT 0x0003 +#define NVM_ID_LED_SETTINGS 0x0004 +#define NVM_VERSION 0x0005 +/* For SERDES output amplitude adjustment. */ +#define NVM_SERDES_AMPLITUDE 0x0006 +#define NVM_PHY_CLASS_WORD 0x0007 +#define NVM_INIT_CONTROL1_REG 0x000A +#define NVM_INIT_CONTROL2_REG 0x000F +#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 +#define NVM_INIT_CONTROL3_PORT_B 0x0014 +#define NVM_INIT_3GIO_3 0x001A +#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 +#define NVM_INIT_CONTROL3_PORT_A 0x0024 +#define NVM_CFG 0x0012 +#define NVM_FLASH_VERSION 0x0032 +#define NVM_CHECKSUM_REG 0x003F + +#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ +#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ + +/* Mask bits for fields in Word 0x0f of the NVM */ +#define NVM_WORD0F_PAUSE_MASK 0x3000 +#define NVM_WORD0F_PAUSE 0x1000 +#define NVM_WORD0F_ASM_DIR 0x2000 +#define NVM_WORD0F_ANE 0x0800 +#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 +#define NVM_WORD0F_LPLU 0x0001 + +/* Mask bits for fields in Word 0x1a of the NVM */ +#define NVM_WORD1A_ASPM_MASK 0x000C + +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ +#define NVM_SUM 0xBABA + +#define NVM_MAC_ADDR_OFFSET 0 +#define NVM_PBA_OFFSET_0 8 +#define NVM_PBA_OFFSET_1 9 +#define NVM_RESERVED_WORD 0xFFFF +#define NVM_PHY_CLASS_A 0x8000 +#define NVM_SERDES_AMPLITUDE_MASK 0x000F +#define NVM_SIZE_MASK 0x1C00 +#define NVM_SIZE_SHIFT 10 +#define NVM_WORD_SIZE_BASE_SHIFT 6 +#define NVM_SWDPIO_EXT_SHIFT 4 + +/* NVM Commands - Microwire */ +#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ +#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ +#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ +#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ +#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erast/write disable */ + +/* NVM Commands - SPI */ +#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ +#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ +#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ +#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ +#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ +#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ +#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ +#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ + +/* SPI NVM Status Register */ +#define NVM_STATUS_RDY_SPI 0x01 +#define NVM_STATUS_WEN_SPI 0x02 +#define NVM_STATUS_BP0_SPI 0x04 +#define NVM_STATUS_BP1_SPI 0x08 +#define NVM_STATUS_WPEN_SPI 0x80 + +/* Word definitions for ID LED Settings */ +#define ID_LED_RESERVED_0000 0x0000 +#define ID_LED_RESERVED_FFFF 0xFFFF +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ + (ID_LED_OFF1_OFF2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) +#define ID_LED_DEF1_DEF2 0x1 +#define ID_LED_DEF1_ON2 0x2 +#define ID_LED_DEF1_OFF2 0x3 +#define ID_LED_ON1_DEF2 0x4 +#define ID_LED_ON1_ON2 0x5 +#define ID_LED_ON1_OFF2 0x6 +#define ID_LED_OFF1_DEF2 0x7 +#define ID_LED_OFF1_ON2 0x8 +#define ID_LED_OFF1_OFF2 0x9 + +#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF +#define IGP_ACTIVITY_LED_ENABLE 0x0300 +#define IGP_LED3_MODE 0x07000000 + +/* PCI/PCI-X/PCI-EX Config space */ +#define PCIX_COMMAND_REGISTER 0xE6 +#define PCIX_STATUS_REGISTER_LO 0xE8 +#define PCIX_STATUS_REGISTER_HI 0xEA +#define PCI_HEADER_TYPE_REGISTER 0x0E +#define PCIE_LINK_STATUS 0x12 + +#define PCIX_COMMAND_MMRBC_MASK 0x000C +#define PCIX_COMMAND_MMRBC_SHIFT 0x2 +#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 +#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 +#define PCIX_STATUS_HI_MMRBC_4K 0x3 +#define PCIX_STATUS_HI_MMRBC_2K 0x2 +#define PCIX_STATUS_LO_FUNC_MASK 0x7 +#define PCI_HEADER_TYPE_MULTIFUNC 0x80 +#define PCIE_LINK_WIDTH_MASK 0x3F0 +#define PCIE_LINK_WIDTH_SHIFT 4 + +#ifndef ETH_ADDR_LEN +#define ETH_ADDR_LEN 6 +#endif + +#define PHY_REVISION_MASK 0xFFFFFFF0 +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +#define MAX_PHY_MULTI_PAGE_REG 0xF + +/* Bit definitions for valid PHY IDs. */ +/* + * I = Integrated + * E = External + */ +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define IGP01E1000_I_PHY_ID 0x02A80380 +#define M88E1011_I_REV_4 0x04 +#define M88E1111_I_PHY_ID 0x01410CC0 +#define GG82563_E_PHY_ID 0x01410CA0 +#define IGP03E1000_E_PHY_ID 0x02A80390 +#define IFE_E_PHY_ID 0x02A80330 +#define IFE_PLUS_E_PHY_ID 0x02A80320 +#define IFE_C_E_PHY_ID 0x02A80310 +#define BME1000_E_PHY_ID 0x01410CB0 +#define M88_VENDOR 0x0141 + +/* M88E1000 Specific Registers */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + +#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ +#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ +#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ + +/* M88E1000 PHY Specific Control Register */ +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +/* 1=CLK125 low, 0=CLK125 toggling */ +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 +/* Auto crossover enabled all speeds */ +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 +/* + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold + * 0=Normal 10BASE-T RX Threshold + */ +#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 +/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ + +/* M88E1000 PHY Specific Status Register */ +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +/* + * 0 = <50M + * 1 = 50-80M + * 2 = 80-110M + * 3 = 110-140M + * 4 = >140M + */ +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ + +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 + +/* M88E1000 Extended PHY Specific Control Register */ +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +/* + * 1 = Lost lock detect enabled. + * Will assert lost lock and bring + * link down if idle not seen + * within 1ms in 1000BASE-T + */ +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 +/* + * Number of times we will attempt to autonegotiate before downshifting if we + * are the master + */ +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 +/* + * Number of times we will attempt to autonegotiate before downshifting if we + * are the slave + */ +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ + +/* M88EC018 Rev 2 specific DownShift settings */ +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 + +/* + * Bits... + * 15-5: page + * 4-0: register offset + */ +#define GG82563_PAGE_SHIFT 5 +#define GG82563_REG(page, reg) \ + (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) +#define GG82563_MIN_ALT_REG 30 + +/* GG82563 Specific Registers */ +#define GG82563_PHY_SPEC_CTRL \ + GG82563_REG(0, 16) /* PHY Specific Control */ +#define GG82563_PHY_SPEC_STATUS \ + GG82563_REG(0, 17) /* PHY Specific Status */ +#define GG82563_PHY_INT_ENABLE \ + GG82563_REG(0, 18) /* Interrupt Enable */ +#define GG82563_PHY_SPEC_STATUS_2 \ + GG82563_REG(0, 19) /* PHY Specific Status 2 */ +#define GG82563_PHY_RX_ERR_CNTR \ + GG82563_REG(0, 21) /* Receive Error Counter */ +#define GG82563_PHY_PAGE_SELECT \ + GG82563_REG(0, 22) /* Page Select */ +#define GG82563_PHY_SPEC_CTRL_2 \ + GG82563_REG(0, 26) /* PHY Specific Control 2 */ +#define GG82563_PHY_PAGE_SELECT_ALT \ + GG82563_REG(0, 29) /* Alternate Page Select */ +#define GG82563_PHY_TEST_CLK_CTRL \ + GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ + +#define GG82563_PHY_MAC_SPEC_CTRL \ + GG82563_REG(2, 21) /* MAC Specific Control Register */ +#define GG82563_PHY_MAC_SPEC_CTRL_2 \ + GG82563_REG(2, 26) /* MAC Specific Control 2 */ + +#define GG82563_PHY_DSP_DISTANCE \ + GG82563_REG(5, 26) /* DSP Distance */ + +/* Page 193 - Port Control Registers */ +#define GG82563_PHY_KMRN_MODE_CTRL \ + GG82563_REG(193, 16) /* Kumeran Mode Control */ +#define GG82563_PHY_PORT_RESET \ + GG82563_REG(193, 17) /* Port Reset */ +#define GG82563_PHY_REVISION_ID \ + GG82563_REG(193, 18) /* Revision ID */ +#define GG82563_PHY_DEVICE_ID \ + GG82563_REG(193, 19) /* Device ID */ +#define GG82563_PHY_PWR_MGMT_CTRL \ + GG82563_REG(193, 20) /* Power Management Control */ +#define GG82563_PHY_RATE_ADAPT_CTRL \ + GG82563_REG(193, 25) /* Rate Adaptation Control */ + +/* Page 194 - KMRN Registers */ +#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ + GG82563_REG(194, 16) /* FIFO's Control/Status */ +#define GG82563_PHY_KMRN_CTRL \ + GG82563_REG(194, 17) /* Control */ +#define GG82563_PHY_INBAND_CTRL \ + GG82563_REG(194, 18) /* Inband Control */ +#define GG82563_PHY_KMRN_DIAGNOSTIC \ + GG82563_REG(194, 19) /* Diagnostic */ +#define GG82563_PHY_ACK_TIMEOUTS \ + GG82563_REG(194, 20) /* Acknowledge Timeouts */ +#define GG82563_PHY_ADV_ABILITY \ + GG82563_REG(194, 21) /* Advertised Ability */ +#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ + GG82563_REG(194, 23) /* Link Partner Advertised Ability */ +#define GG82563_PHY_ADV_NEXT_PAGE \ + GG82563_REG(194, 24) /* Advertised Next Page */ +#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ + GG82563_REG(194, 25) /* Link Partner Advertised Next page */ +#define GG82563_PHY_KMRN_MISC \ + GG82563_REG(194, 26) /* Misc. */ + +/* MDI Control */ +#define E1000_MDIC_DATA_MASK 0x0000FFFF +#define E1000_MDIC_REG_MASK 0x001F0000 +#define E1000_MDIC_REG_SHIFT 16 +#define E1000_MDIC_PHY_MASK 0x03E00000 +#define E1000_MDIC_PHY_SHIFT 21 +#define E1000_MDIC_OP_WRITE 0x04000000 +#define E1000_MDIC_OP_READ 0x08000000 +#define E1000_MDIC_READY 0x10000000 +#define E1000_MDIC_INT_EN 0x20000000 +#define E1000_MDIC_ERROR 0x40000000 + +/* SerDes Control */ +#define E1000_GEN_CTL_READY 0x80000000 +#define E1000_GEN_CTL_ADDRESS_SHIFT 8 +#define E1000_GEN_POLL_TIMEOUT 640 + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_DEFINES_H_ */
--- a/usr/src/uts/common/io/e1000g/e1000_hw.c Mon Aug 20 23:01:08 2007 -0700 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,9309 +0,0 @@ -/* - * This file is provided under a CDDLv1 license. When using or - * redistributing this file, you may do so under this license. - * In redistributing this file this license must be included - * and no other modification of this header file is permitted. - * - * CDDL LICENSE SUMMARY - * - * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. - * - * The contents of this file are subject to the terms of Version - * 1.0 of the Common Development and Distribution License (the "License"). - * - * You should have received a copy of the License with this software. - * You can obtain a copy of the License at - * http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - */ - -/* - * Copyright 2007 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms of the CDDLv1. - */ - -/* - * e1000_hw.c - * Shared functions for accessing and configuring the MAC - * IntelVersion: 1.428.2.1 - */ - -#pragma ident "%Z%%M% %I% %E% SMI" - -#include "e1000_hw.h" - -#define STATIC static - -static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); -static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); -static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); -static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); -static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); -static void e1000_release_software_semaphore(struct e1000_hw *hw); - -static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); -static int32_t e1000_check_downshift(struct e1000_hw *hw); -static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); -static void e1000_clear_vfta(struct e1000_hw *hw); -static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); -static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); -static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); -static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); -static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); -static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); -static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); -static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); -static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); -static int32_t e1000_get_software_flag(struct e1000_hw *hw); -static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); -static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); -static int32_t e1000_id_led_init(struct e1000_hw *hw); -static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); -static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); -static void e1000_init_rx_addrs(struct e1000_hw *hw); -static void e1000_initialize_hardware_bits(struct e1000_hw *hw); -static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); -static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); -static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); -static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); -static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); -static int32_t e1000_mng_write_commit(struct e1000_hw *hw); -static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); -static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); -static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); -static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); -static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); -static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); -static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); -static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); -static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static void e1000_release_software_flag(struct e1000_hw *hw); -static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); -static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); -static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); -static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); -static int32_t e1000_wait_autoneg(struct e1000_hw *hw); -static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); -static int32_t e1000_set_phy_type(struct e1000_hw *hw); -static void e1000_phy_init_script(struct e1000_hw *hw); -static int32_t e1000_setup_copper_link(struct e1000_hw *hw); -static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); -static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); -static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); -static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); -static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); -static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); -static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, - uint16_t count); -static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); -static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); -static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, - uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, - uint16_t offset, uint16_t words, - uint16_t *data); -static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); -static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); -static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); -static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, - uint16_t count); -static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data); -static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, - uint16_t *phy_data); -static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); -static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); -static void e1000_release_eeprom(struct e1000_hw *hw); -static void e1000_standby_eeprom(struct e1000_hw *hw); -static int32_t e1000_set_vco_speed(struct e1000_hw *hw); -static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); -static int32_t e1000_set_phy_mode(struct e1000_hw *hw); -static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); -static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); -static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, - uint16_t duplex); -static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); - -/* IGP cable length table */ -static const -uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = - { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, - 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, - 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, - 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, - 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, - 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, - 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; - -static const -uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = - { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, - 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, - 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, - 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, - 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, - 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, - 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, - 104, 109, 114, 118, 121, 124}; - -/****************************************************************************** - * Set the phy type member in the hw struct. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -STATIC int32_t -e1000_set_phy_type(struct e1000_hw *hw) -{ - DEBUGFUNC("e1000_set_phy_type"); - - if (hw->mac_type == e1000_undefined) - return -E1000_ERR_PHY_TYPE; - - switch (hw->phy_id) { - case M88E1000_E_PHY_ID: - case M88E1000_I_PHY_ID: - case M88E1011_I_PHY_ID: - case M88E1111_I_PHY_ID: - hw->phy_type = e1000_phy_m88; - break; - case IGP01E1000_I_PHY_ID: - if (hw->mac_type == e1000_82541 || - hw->mac_type == e1000_82541_rev_2 || - hw->mac_type == e1000_82547 || - hw->mac_type == e1000_82547_rev_2) { - hw->phy_type = e1000_phy_igp; - break; - } - case IGP03E1000_E_PHY_ID: - hw->phy_type = e1000_phy_igp_3; - break; - case IFE_E_PHY_ID: - case IFE_PLUS_E_PHY_ID: - case IFE_C_E_PHY_ID: - hw->phy_type = e1000_phy_ife; - break; - case GG82563_E_PHY_ID: - if (hw->mac_type == e1000_80003es2lan) { - hw->phy_type = e1000_phy_gg82563; - break; - } - /* Fall Through */ - default: - /* Should never have loaded on this device */ - hw->phy_type = e1000_phy_undefined; - return -E1000_ERR_PHY_TYPE; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * IGP phy init script - initializes the GbE PHY - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -static void -e1000_phy_init_script(struct e1000_hw *hw) -{ - uint32_t ret_val; - uint16_t phy_saved_data; - - DEBUGFUNC("e1000_phy_init_script"); - - if (hw->phy_init_script) { - msec_delay(20); - - /* Save off the current value of register 0x2F5B to be restored at - * the end of this routine. */ - ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); - - /* Disabled the PHY transmitter */ - e1000_write_phy_reg(hw, 0x2F5B, 0x0003); - - msec_delay(20); - - e1000_write_phy_reg(hw,0x0000,0x0140); - - msec_delay(5); - - switch (hw->mac_type) { - case e1000_82541: - case e1000_82547: - e1000_write_phy_reg(hw, 0x1F95, 0x0001); - - e1000_write_phy_reg(hw, 0x1F71, 0xBD21); - - e1000_write_phy_reg(hw, 0x1F79, 0x0018); - - e1000_write_phy_reg(hw, 0x1F30, 0x1600); - - e1000_write_phy_reg(hw, 0x1F31, 0x0014); - - e1000_write_phy_reg(hw, 0x1F32, 0x161C); - - e1000_write_phy_reg(hw, 0x1F94, 0x0003); - - e1000_write_phy_reg(hw, 0x1F96, 0x003F); - - e1000_write_phy_reg(hw, 0x2010, 0x0008); - break; - - case e1000_82541_rev_2: - case e1000_82547_rev_2: - e1000_write_phy_reg(hw, 0x1F73, 0x0099); - break; - default: - break; - } - - e1000_write_phy_reg(hw, 0x0000, 0x3300); - - msec_delay(20); - - /* Now enable the transmitter */ - e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); - - if (hw->mac_type == e1000_82547) { - uint16_t fused, fine, coarse; - - /* Move to analog registers page */ - e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); - - if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { - e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); - - fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; - coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; - - if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { - coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; - fine -= IGP01E1000_ANALOG_FUSE_FINE_1; - } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) - fine -= IGP01E1000_ANALOG_FUSE_FINE_10; - - fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | - (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | - (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); - - e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); - e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, - IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); - } - } - } -} - -/****************************************************************************** - * Set the mac type member in the hw struct. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_set_mac_type(struct e1000_hw *hw) -{ - DEBUGFUNC("e1000_set_mac_type"); - - switch (hw->device_id) { - case E1000_DEV_ID_82542: - switch (hw->revision_id) { - case E1000_82542_2_0_REV_ID: - hw->mac_type = e1000_82542_rev2_0; - break; - case E1000_82542_2_1_REV_ID: - hw->mac_type = e1000_82542_rev2_1; - break; - default: - /* Invalid 82542 revision ID */ - return -E1000_ERR_MAC_TYPE; - } - break; - case E1000_DEV_ID_82543GC_FIBER: - case E1000_DEV_ID_82543GC_COPPER: - hw->mac_type = e1000_82543; - break; - case E1000_DEV_ID_82544EI_COPPER: - case E1000_DEV_ID_82544EI_FIBER: - case E1000_DEV_ID_82544GC_COPPER: - case E1000_DEV_ID_82544GC_LOM: - hw->mac_type = e1000_82544; - break; - case E1000_DEV_ID_82540EM: - case E1000_DEV_ID_82540EM_LOM: - case E1000_DEV_ID_82540EP: - case E1000_DEV_ID_82540EP_LOM: - case E1000_DEV_ID_82540EP_LP: - hw->mac_type = e1000_82540; - break; - case E1000_DEV_ID_82545EM_COPPER: - case E1000_DEV_ID_82545EM_FIBER: - hw->mac_type = e1000_82545; - break; - case E1000_DEV_ID_82545GM_COPPER: - case E1000_DEV_ID_82545GM_FIBER: - case E1000_DEV_ID_82545GM_SERDES: - hw->mac_type = e1000_82545_rev_3; - break; - case E1000_DEV_ID_82546EB_COPPER: - case E1000_DEV_ID_82546EB_FIBER: - case E1000_DEV_ID_82546EB_QUAD_COPPER: - hw->mac_type = e1000_82546; - break; - case E1000_DEV_ID_82546GB_COPPER: - case E1000_DEV_ID_82546GB_FIBER: - case E1000_DEV_ID_82546GB_SERDES: - case E1000_DEV_ID_82546GB_PCIE: - case E1000_DEV_ID_82546GB_QUAD_COPPER: - case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: - hw->mac_type = e1000_82546_rev_3; - break; - case E1000_DEV_ID_82541EI: - case E1000_DEV_ID_82541EI_MOBILE: - case E1000_DEV_ID_82541ER_LOM: - hw->mac_type = e1000_82541; - break; - case E1000_DEV_ID_82541ER: - case E1000_DEV_ID_82541GI: - case E1000_DEV_ID_82541GI_LF: - case E1000_DEV_ID_82541GI_MOBILE: - hw->mac_type = e1000_82541_rev_2; - break; - case E1000_DEV_ID_82547EI: - case E1000_DEV_ID_82547EI_MOBILE: - hw->mac_type = e1000_82547; - break; - case E1000_DEV_ID_82547GI: - hw->mac_type = e1000_82547_rev_2; - break; - case E1000_DEV_ID_82571EB_COPPER: - case E1000_DEV_ID_82571EB_FIBER: - case E1000_DEV_ID_82571EB_SERDES: - case E1000_DEV_ID_82571EB_QUAD_COPPER: - case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: - case E1000_DEV_ID_82571PT_QUAD_COPPER: - hw->mac_type = e1000_82571; - break; - case E1000_DEV_ID_82572EI_COPPER: - case E1000_DEV_ID_82572EI_FIBER: - case E1000_DEV_ID_82572EI_SERDES: - case E1000_DEV_ID_82572EI: - hw->mac_type = e1000_82572; - break; - case E1000_DEV_ID_82573E: - case E1000_DEV_ID_82573E_IAMT: - case E1000_DEV_ID_82573L: - hw->mac_type = e1000_82573; - break; - case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: - case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: - case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: - case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: - hw->mac_type = e1000_80003es2lan; - break; - case E1000_DEV_ID_ICH8_IGP_M_AMT: - case E1000_DEV_ID_ICH8_IGP_AMT: - case E1000_DEV_ID_ICH8_IGP_C: - case E1000_DEV_ID_ICH8_IFE: - case E1000_DEV_ID_ICH8_IFE_GT: - case E1000_DEV_ID_ICH8_IFE_G: - case E1000_DEV_ID_ICH8_IGP_M: - hw->mac_type = e1000_ich8lan; - break; - default: - /* Should never have loaded on this device */ - return -E1000_ERR_MAC_TYPE; - } - - switch (hw->mac_type) { - case e1000_ich8lan: - hw->swfwhw_semaphore_present = TRUE; - hw->asf_firmware_present = TRUE; - break; - case e1000_80003es2lan: - hw->swfw_sync_present = TRUE; - /* fall through */ - case e1000_82571: - case e1000_82572: - case e1000_82573: - hw->eeprom_semaphore_present = TRUE; - /* fall through */ - case e1000_82541: - case e1000_82547: - case e1000_82541_rev_2: - case e1000_82547_rev_2: - hw->asf_firmware_present = TRUE; - break; - default: - break; - } - - return E1000_SUCCESS; -} - -/***************************************************************************** - * Set media type and TBI compatibility. - * - * hw - Struct containing variables accessed by shared code - * **************************************************************************/ -void -e1000_set_media_type(struct e1000_hw *hw) -{ - uint32_t status; - - DEBUGFUNC("e1000_set_media_type"); - - if (hw->mac_type != e1000_82543) { - /* tbi_compatibility is only valid on 82543 */ - hw->tbi_compatibility_en = FALSE; - } - - switch (hw->device_id) { - case E1000_DEV_ID_82545GM_SERDES: - case E1000_DEV_ID_82546GB_SERDES: - case E1000_DEV_ID_82571EB_SERDES: - case E1000_DEV_ID_82572EI_SERDES: - case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: - hw->media_type = e1000_media_type_internal_serdes; - break; - default: - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - hw->media_type = e1000_media_type_fiber; - break; - case e1000_ich8lan: - case e1000_82573: - /* The STATUS_TBIMODE bit is reserved or reused for the this - * device. - */ - hw->media_type = e1000_media_type_copper; - break; - default: - status = E1000_READ_REG(hw, STATUS); - if (status & E1000_STATUS_TBIMODE) { - hw->media_type = e1000_media_type_fiber; - /* tbi_compatibility not valid on fiber */ - hw->tbi_compatibility_en = FALSE; - } else { - hw->media_type = e1000_media_type_copper; - } - break; - } - } -} - -/****************************************************************************** - * Reset the transmit and receive units; mask and clear all interrupts. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_reset_hw(struct e1000_hw *hw) -{ - uint32_t ctrl; - uint32_t ctrl_ext; - uint32_t icr; - uint32_t manc; - uint32_t led_ctrl; - uint32_t timeout; - uint32_t extcnf_ctrl; - int32_t ret_val; - - DEBUGFUNC("e1000_reset_hw"); - - /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ - if (hw->mac_type == e1000_82542_rev2_0) { - DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); - e1000_pci_clear_mwi(hw); - } - - if (hw->bus_type == e1000_bus_type_pci_express) { - /* Prevent the PCI-E bus from sticking if there is no TLP connection - * on the last TLP read/write transaction when MAC is reset. - */ - if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { - DEBUGOUT("PCI-E Master disable polling has failed.\n"); - } - } - - /* Clear interrupt mask to stop board from generating interrupts */ - DEBUGOUT("Masking off all interrupts\n"); - E1000_WRITE_REG(hw, IMC, 0xffffffff); - - /* Disable the Transmit and Receive units. Then delay to allow - * any pending transactions to complete before we hit the MAC with - * the global reset. - */ - E1000_WRITE_REG(hw, RCTL, 0); - E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); - E1000_WRITE_FLUSH(hw); -#ifndef FIFO_WORKAROUND - hw->tx_fifo_head = 0; -#endif - - /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ - hw->tbi_compatibility_on = FALSE; - - /* Delay to allow any outstanding PCI transactions to complete before - * resetting the device - */ - msec_delay(10); - - ctrl = E1000_READ_REG(hw, CTRL); - - /* Must reset the PHY before resetting the MAC */ - if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { - E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); - msec_delay(5); - } - - /* Must acquire the MDIO ownership before MAC reset. - * Ownership defaults to firmware after a reset. */ - if (hw->mac_type == e1000_82573) { - timeout = 10; - - extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; - - do { - E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); - extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); - - if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) - break; - else - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; - - msec_delay(2); - timeout--; - } while (timeout); - } - - /* Workaround for ICH8 bit corruption issue in FIFO memory */ - if (hw->mac_type == e1000_ich8lan) { - /* Set Tx and Rx buffer allocation to 8k apiece. */ - E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); - /* Set Packet Buffer Size to 16k. */ - E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); - } - - /* Issue a global reset to the MAC. This will reset the chip's - * transmit, receive, DMA, and link units. It will not effect - * the current PCI configuration. The global reset bit is self- - * clearing, and should clear within a microsecond. - */ - DEBUGOUT("Issuing a global reset to MAC\n"); - - switch (hw->mac_type) { - case e1000_82544: - case e1000_82540: - case e1000_82545: - case e1000_82546: - case e1000_82541: - case e1000_82541_rev_2: - /* These controllers can't ack the 64-bit write when issuing the - * reset, so use IO-mapping as a workaround to issue the reset */ - E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); - break; - case e1000_82545_rev_3: - case e1000_82546_rev_3: - /* Reset is performed on a shadow of the control register */ - E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); - break; - case e1000_ich8lan: - if (!hw->phy_reset_disable && - e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { - /* e1000_ich8lan PHY HW reset requires MAC CORE reset - * at the same time to make sure the interface between - * MAC and the external PHY is reset. - */ - ctrl |= E1000_CTRL_PHY_RST; - } - - e1000_get_software_flag(hw); - E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); - msec_delay(5); - break; - default: - E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); - break; - } - - /* After MAC reset, force reload of EEPROM to restore power-on settings to - * device. Later controllers reload the EEPROM automatically, so just wait - * for reload to complete. - */ - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - case e1000_82544: - /* Wait for reset to complete */ - usec_delay(10); - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_EE_RST; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - E1000_WRITE_FLUSH(hw); - /* Wait for EEPROM reload */ - msec_delay(2); - break; - case e1000_82541: - case e1000_82541_rev_2: - case e1000_82547: - case e1000_82547_rev_2: - /* Wait for EEPROM reload */ - msec_delay(20); - break; - case e1000_82573: - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { - usec_delay(10); - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_EE_RST; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - E1000_WRITE_FLUSH(hw); - } - /* fall through */ - default: - /* Auto read done will delay 5ms or poll based on mac type */ - ret_val = e1000_get_auto_rd_done(hw); - if (ret_val) - return ret_val; - break; - } - - /* Disable HW ARPs on ASF enabled adapters */ - if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { - manc = E1000_READ_REG(hw, MANC); - manc &= ~(E1000_MANC_ARP_EN); - E1000_WRITE_REG(hw, MANC, manc); - } - - if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { - e1000_phy_init_script(hw); - - /* Configure activity LED after PHY reset */ - led_ctrl = E1000_READ_REG(hw, LEDCTL); - led_ctrl &= IGP_ACTIVITY_LED_MASK; - led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); - E1000_WRITE_REG(hw, LEDCTL, led_ctrl); - } - - /* Clear interrupt mask to stop board from generating interrupts */ - DEBUGOUT("Masking off all interrupts\n"); - E1000_WRITE_REG(hw, IMC, 0xffffffff); - - /* Clear any pending interrupt events. */ - icr = E1000_READ_REG(hw, ICR); - - /* If MWI was previously enabled, reenable it. */ - if (hw->mac_type == e1000_82542_rev2_0) { - if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) - e1000_pci_set_mwi(hw); - } - - if (hw->mac_type == e1000_ich8lan) { - uint32_t kab = E1000_READ_REG(hw, KABGTXD); - kab |= E1000_KABGTXD_BGSQLBIAS; - E1000_WRITE_REG(hw, KABGTXD, kab); - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * - * Initialize a number of hardware-dependent bits - * - * hw: Struct containing variables accessed by shared code - * - *****************************************************************************/ -STATIC void -e1000_initialize_hardware_bits(struct e1000_hw *hw) -{ - if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { - /* Settings common to all silicon */ - uint32_t reg_ctrl, reg_ctrl_ext; - uint32_t reg_tarc0, reg_tarc1; - uint32_t reg_tctl; - uint32_t reg_txdctl, reg_txdctl1; - - reg_tarc0 = E1000_READ_REG(hw, TARC0); - reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 27 */ - - reg_txdctl = E1000_READ_REG(hw, TXDCTL); - reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ - E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); - - reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); - reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ - E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); - - switch (hw->mac_type) { - case e1000_82571: - case e1000_82572: - reg_tarc1 = E1000_READ_REG(hw, TARC1); - reg_tctl = E1000_READ_REG(hw, TCTL); - - /* Set the phy Tx compatible mode bits */ - reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ - - reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ - reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ - - if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ - else - reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ - - E1000_WRITE_REG(hw, TARC1, reg_tarc1); - break; - case e1000_82573: - reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - reg_ctrl = E1000_READ_REG(hw, CTRL); - - reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ - reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ - reg_ctrl &= ~0x20000000; /* Clear bit 29 */ - - E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); - E1000_WRITE_REG(hw, CTRL, reg_ctrl); - break; - case e1000_80003es2lan: - if ((hw->media_type == e1000_media_type_fiber) || - (hw->media_type == e1000_media_type_internal_serdes)) { - reg_tarc0 &= ~0x00100000; /* Clear bit 20 */ - } - - reg_tctl = E1000_READ_REG(hw, TCTL); - reg_tarc1 = E1000_READ_REG(hw, TARC1); - if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ - else - reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ - - E1000_WRITE_REG(hw, TARC1, reg_tarc1); - break; - case e1000_ich8lan: - if ((hw->revision_id < 3) || - ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && - (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) - reg_tarc0 |= 0x30000000; /* Set TARC0 bits 29 and 28 */ - reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ - E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); - - reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 24, 26, 27 */ - - reg_tarc1 = E1000_READ_REG(hw, TARC1); - reg_tctl = E1000_READ_REG(hw, TCTL); - - if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ - else - reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ - - reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 30 */ - - E1000_WRITE_REG(hw, TARC1, reg_tarc1); - break; - default: - break; - } - - E1000_WRITE_REG(hw, TARC0, reg_tarc0); - } -} - -/****************************************************************************** - * Performs basic configuration of the adapter. - * - * hw - Struct containing variables accessed by shared code - * - * Assumes that the controller has previously been reset and is in a - * post-reset uninitialized state. Initializes the receive address registers, - * multicast table, and VLAN filter table. Calls routines to setup link - * configuration and flow control settings. Clears all on-chip counters. Leaves - * the transmit and receive units disabled and uninitialized. - *****************************************************************************/ -int32_t -e1000_init_hw(struct e1000_hw *hw) -{ - uint32_t ctrl; - uint32_t i; - int32_t ret_val; - uint16_t pcix_cmd_word; - uint16_t pcix_stat_hi_word; - uint16_t cmd_mmrbc; - uint16_t stat_mmrbc; - uint32_t mta_size; -#ifndef FIFO_WORKAROUND - uint32_t pba_reg; -#endif - uint32_t reg_data; - uint32_t ctrl_ext; - - DEBUGFUNC("e1000_init_hw"); - - /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ - if ((hw->mac_type == e1000_ich8lan) && - ((hw->revision_id < 3) || - ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && - (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { - reg_data = E1000_READ_REG(hw, STATUS); - reg_data &= ~0x80000000; - E1000_WRITE_REG(hw, STATUS, reg_data); - } - - /* Initialize Identification LED */ - ret_val = e1000_id_led_init(hw); - if (ret_val) { - DEBUGOUT("Error Initializing Identification LED\n"); - return ret_val; - } - - /* Set the media type and TBI compatibility */ - e1000_set_media_type(hw); - -#ifndef FIFO_WORKAROUND - pba_reg = E1000_READ_REG(hw, PBA); - hw->tx_fifo_start = (pba_reg & 0x0000FFFF) * E1000_FIFO_MULTIPLIER; - hw->tx_fifo_size = (pba_reg & 0xFFFF0000) >> 6; - -#endif - /* Disabling VLAN filtering. */ - DEBUGOUT("Initializing the IEEE VLAN\n"); - /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ - if (hw->mac_type != e1000_ich8lan) { - if (hw->mac_type < e1000_82545_rev_3) - E1000_WRITE_REG(hw, VET, 0); - e1000_clear_vfta(hw); - } - - /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ - if (hw->mac_type == e1000_82542_rev2_0) { - DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); - e1000_pci_clear_mwi(hw); - E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); - E1000_WRITE_FLUSH(hw); - msec_delay(5); - } - - /* Setup the receive address. This involves initializing all of the Receive - * Address Registers (RARs 0 - 15). - */ - e1000_init_rx_addrs(hw); - - /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ - if (hw->mac_type == e1000_82542_rev2_0) { - E1000_WRITE_REG(hw, RCTL, 0); - E1000_WRITE_FLUSH(hw); - msec_delay(1); - if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) - e1000_pci_set_mwi(hw); - } - - /* Zero out the Multicast HASH table */ - DEBUGOUT("Zeroing the MTA\n"); - mta_size = E1000_MC_TBL_SIZE; - if (hw->mac_type == e1000_ich8lan) - mta_size = E1000_MC_TBL_SIZE_ICH8LAN; - for (i = 0; i < mta_size; i++) { - E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); - /* use write flush to prevent Memory Write Block (MWB) from - * occuring when accessing our register space */ - E1000_WRITE_FLUSH(hw); - } - - /* Set the PCI priority bit correctly in the CTRL register. This - * determines if the adapter gives priority to receives, or if it - * gives equal priority to transmits and receives. Valid only on - * 82542 and 82543 silicon. - */ - if (hw->dma_fairness && hw->mac_type <= e1000_82543) { - ctrl = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); - } - - switch (hw->mac_type) { - case e1000_82545_rev_3: - case e1000_82546_rev_3: - break; - default: - /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ - if (hw->bus_type == e1000_bus_type_pcix) { - e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); - e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, - &pcix_stat_hi_word); - cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> - PCIX_COMMAND_MMRBC_SHIFT; - stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> - PCIX_STATUS_HI_MMRBC_SHIFT; - if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) - stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; - if (cmd_mmrbc > stat_mmrbc) { - pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; - pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; - e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, - &pcix_cmd_word); - } - } - break; - } - - /* More time needed for PHY to initialize */ - if (hw->mac_type == e1000_ich8lan) - msec_delay(15); - - /* Call a subroutine to configure the link and setup flow control. */ - ret_val = e1000_setup_link(hw); - - /* Set the transmit descriptor write-back policy */ - if (hw->mac_type > e1000_82544) { - ctrl = E1000_READ_REG(hw, TXDCTL); - ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; - E1000_WRITE_REG(hw, TXDCTL, ctrl); - } - - if (hw->mac_type == e1000_82573) { - e1000_enable_tx_pkt_filtering(hw); - } - - switch (hw->mac_type) { - default: - break; - case e1000_80003es2lan: - /* Enable retransmit on late collisions */ - reg_data = E1000_READ_REG(hw, TCTL); - reg_data |= E1000_TCTL_RTLC; - E1000_WRITE_REG(hw, TCTL, reg_data); - - /* Configure Gigabit Carry Extend Padding */ - reg_data = E1000_READ_REG(hw, TCTL_EXT); - reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; - reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; - E1000_WRITE_REG(hw, TCTL_EXT, reg_data); - - /* Configure Transmit Inter-Packet Gap */ - reg_data = E1000_READ_REG(hw, TIPG); - reg_data &= ~E1000_TIPG_IPGT_MASK; - reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; - E1000_WRITE_REG(hw, TIPG, reg_data); - - reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); - reg_data &= ~0x00100000; - E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); - /* Fall through */ - case e1000_82571: - case e1000_82572: - case e1000_ich8lan: - ctrl = E1000_READ_REG(hw, TXDCTL1); - ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; - E1000_WRITE_REG(hw, TXDCTL1, ctrl); - break; - } - - - if (hw->mac_type == e1000_82573) { - uint32_t gcr = E1000_READ_REG(hw, GCR); - gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; - E1000_WRITE_REG(hw, GCR, gcr); - } - - /* Clear all of the statistics registers (clear on read). It is - * important that we do this after we have tried to establish link - * because the symbol error count will increment wildly if there - * is no link. - */ - e1000_clear_hw_cntrs(hw); - - /* ICH8 No-snoop bits are opposite polarity. - * Set to snoop by default after reset. */ - if (hw->mac_type == e1000_ich8lan) - e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); - - if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || - hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - /* Relaxed ordering must be disabled to avoid a parity - * error crash in a PCI slot. */ - ctrl_ext |= E1000_CTRL_EXT_RO_DIS; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - } - - /* Must be called after e1000_set_media_type because media_type is used */ - e1000_initialize_hardware_bits(hw); - - return ret_val; -} - -/****************************************************************************** - * Adjust SERDES output amplitude based on EEPROM setting. - * - * hw - Struct containing variables accessed by shared code. - *****************************************************************************/ -static int32_t -e1000_adjust_serdes_amplitude(struct e1000_hw *hw) -{ - uint16_t eeprom_data; - int32_t ret_val; - - DEBUGFUNC("e1000_adjust_serdes_amplitude"); - - if (hw->media_type != e1000_media_type_internal_serdes) - return E1000_SUCCESS; - - switch (hw->mac_type) { - case e1000_82545_rev_3: - case e1000_82546_rev_3: - break; - default: - return E1000_SUCCESS; - } - - ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); - if (ret_val) { - return ret_val; - } - - if (eeprom_data != EEPROM_RESERVED_WORD) { - /* Adjust SERDES output amplitude only. */ - eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); - if (ret_val) - return ret_val; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Configures flow control and link settings. - * - * hw - Struct containing variables accessed by shared code - * - * Determines which flow control settings to use. Calls the apropriate media- - * specific link configuration function. Configures the flow control settings. - * Assuming the adapter has a valid link partner, a valid link should be - * established. Assumes the hardware has previously been reset and the - * transmitter and receiver are not enabled. - *****************************************************************************/ -int32_t -e1000_setup_link(struct e1000_hw *hw) -{ - uint32_t ctrl_ext; - int32_t ret_val; - uint16_t eeprom_data; - - DEBUGFUNC("e1000_setup_link"); - - /* In the case of the phy reset being blocked, we already have a link. - * We do not have to set it up again. */ - if (e1000_check_phy_reset_block(hw)) - return E1000_SUCCESS; - - /* Read and store word 0x0F of the EEPROM. This word contains bits - * that determine the hardware's default PAUSE (flow control) mode, - * a bit that determines whether the HW defaults to enabling or - * disabling auto-negotiation, and the direction of the - * SW defined pins. If there is no SW over-ride of the flow - * control setting, then the variable hw->fc will - * be initialized based on a value in the EEPROM. - */ - if (hw->fc == E1000_FC_DEFAULT) { - switch (hw->mac_type) { - case e1000_ich8lan: - case e1000_82573: - hw->fc = E1000_FC_FULL; - break; - default: - ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, - 1, &eeprom_data); - if (ret_val) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) - hw->fc = E1000_FC_NONE; - else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == - EEPROM_WORD0F_ASM_DIR) - hw->fc = E1000_FC_TX_PAUSE; - else - hw->fc = E1000_FC_FULL; - break; - } - } - - /* We want to save off the original Flow Control configuration just - * in case we get disconnected and then reconnected into a different - * hub or switch with different Flow Control capabilities. - */ - if (hw->mac_type == e1000_82542_rev2_0) - hw->fc &= (~E1000_FC_TX_PAUSE); - - if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) - hw->fc &= (~E1000_FC_RX_PAUSE); - - hw->original_fc = hw->fc; - - DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); - - /* Take the 4 bits from EEPROM word 0x0F that determine the initial - * polarity value for the SW controlled pins, and setup the - * Extended Device Control reg with that info. - * This is needed because one of the SW controlled pins is used for - * signal detection. So this should be done before e1000_setup_pcs_link() - * or e1000_phy_setup() is called. - */ - if (hw->mac_type == e1000_82543) { - ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, - 1, &eeprom_data); - if (ret_val) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << - SWDPIO__EXT_SHIFT); - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - } - - /* Call the necessary subroutine to configure the link. */ - ret_val = (hw->media_type == e1000_media_type_copper) ? - e1000_setup_copper_link(hw) : - e1000_setup_fiber_serdes_link(hw); - - /* Initialize the flow control address, type, and PAUSE timer - * registers to their default values. This is done even if flow - * control is disabled, because it does not hurt anything to - * initialize these registers. - */ - DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); - - /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ - if (hw->mac_type != e1000_ich8lan) { - E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); - E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); - E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); - } - - E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); - - /* Set the flow control receive threshold registers. Normally, - * these registers will be set to a default threshold that may be - * adjusted later by the driver's runtime code. However, if the - * ability to transmit pause frames in not enabled, then these - * registers will be set to 0. - */ - if (!(hw->fc & E1000_FC_TX_PAUSE)) { - E1000_WRITE_REG(hw, FCRTL, 0); - E1000_WRITE_REG(hw, FCRTH, 0); - } else { - /* We need to set up the Receive Threshold high and low water marks - * as well as (optionally) enabling the transmission of XON frames. - */ - if (hw->fc_send_xon) { - E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); - E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); - } else { - E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); - E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); - } - } - return ret_val; -} - -/****************************************************************************** - * Sets up link for a fiber based or serdes based adapter - * - * hw - Struct containing variables accessed by shared code - * - * Manipulates Physical Coding Sublayer functions in order to configure - * link. Assumes the hardware has been previously reset and the transmitter - * and receiver are not enabled. - *****************************************************************************/ -static int32_t -e1000_setup_fiber_serdes_link(struct e1000_hw *hw) -{ - uint32_t ctrl; - uint32_t status; - uint32_t txcw = 0; - uint32_t i; - uint32_t signal = 0; - int32_t ret_val; - - DEBUGFUNC("e1000_setup_fiber_serdes_link"); - - /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists - * until explicitly turned off or a power cycle is performed. A read to - * the register does not indicate its status. Therefore, we ensure - * loopback mode is disabled during initialization. - */ - if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) - E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); - - /* On adapters with a MAC newer than 82544, SWDP 1 will be - * set when the optics detect a signal. On older adapters, it will be - * cleared when there is a signal. This applies to fiber media only. - * If we're on serdes media, adjust the output amplitude to value - * set in the EEPROM. - */ - ctrl = E1000_READ_REG(hw, CTRL); - if (hw->media_type == e1000_media_type_fiber) - signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; - - ret_val = e1000_adjust_serdes_amplitude(hw); - if (ret_val) - return ret_val; - - /* Take the link out of reset */ - ctrl &= ~(E1000_CTRL_LRST); - - /* Adjust VCO speed to improve BER performance */ - ret_val = e1000_set_vco_speed(hw); - if (ret_val) - return ret_val; - - e1000_config_collision_dist(hw); - - /* Check for a software override of the flow control settings, and setup - * the device accordingly. If auto-negotiation is enabled, then software - * will have to set the "PAUSE" bits to the correct value in the Tranmsit - * Config Word Register (TXCW) and re-start auto-negotiation. However, if - * auto-negotiation is disabled, then software will have to manually - * configure the two flow control enable bits in the CTRL register. - * - * The possible values of the "fc" parameter are: - * 0: Flow control is completely disabled - * 1: Rx flow control is enabled (we can receive pause frames, but - * not send pause frames). - * 2: Tx flow control is enabled (we can send pause frames but we do - * not support receiving pause frames). - * 3: Both Rx and TX flow control (symmetric) are enabled. - */ - switch (hw->fc) { - case E1000_FC_NONE: - /* Flow control is completely disabled by a software over-ride. */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); - break; - case E1000_FC_RX_PAUSE: - /* RX Flow control is enabled and TX Flow control is disabled by a - * software over-ride. Since there really isn't a way to advertise - * that we are capable of RX Pause ONLY, we will advertise that we - * support both symmetric and asymmetric RX PAUSE. Later, we will - * disable the adapter's ability to send PAUSE frames. - */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); - break; - case E1000_FC_TX_PAUSE: - /* TX Flow control is enabled, and RX Flow control is disabled, by a - * software over-ride. - */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); - break; - case E1000_FC_FULL: - /* Flow control (both RX and TX) is enabled by a software over-ride. */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); - break; - default: - DEBUGOUT("Flow control param set incorrectly\n"); - return -E1000_ERR_CONFIG; - } - - /* Since auto-negotiation is enabled, take the link out of reset (the link - * will be in reset, because we previously reset the chip). This will - * restart auto-negotiation. If auto-neogtiation is successful then the - * link-up status bit will be set and the flow control enable bits (RFCE - * and TFCE) will be set according to their negotiated value. - */ - DEBUGOUT("Auto-negotiation enabled\n"); - - E1000_WRITE_REG(hw, TXCW, txcw); - E1000_WRITE_REG(hw, CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - - hw->txcw = txcw; - msec_delay(1); - - /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" - * indication in the Device Status Register. Time-out if a link isn't - * seen in 500 milliseconds seconds (Auto-negotiation should complete in - * less than 500 milliseconds even if the other end is doing it in SW). - * For internal serdes, we just assume a signal is present, then poll. - */ - if (hw->media_type == e1000_media_type_internal_serdes || - (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { - DEBUGOUT("Looking for Link\n"); - for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { - msec_delay(10); - status = E1000_READ_REG(hw, STATUS); - if (status & E1000_STATUS_LU) break; - } - if (i == (LINK_UP_TIMEOUT / 10)) { - DEBUGOUT("Never got a valid link from auto-neg!!!\n"); - hw->autoneg_failed = 1; - /* AutoNeg failed to achieve a link, so we'll call - * e1000_check_for_link. This routine will force the link up if - * we detect a signal. This will allow us to communicate with - * non-autonegotiating link partners. - */ - ret_val = e1000_check_for_link(hw); - if (ret_val) { - DEBUGOUT("Error while checking for link\n"); - return ret_val; - } - hw->autoneg_failed = 0; - } else { - hw->autoneg_failed = 0; - DEBUGOUT("Valid Link Found\n"); - } - } else { - DEBUGOUT("No Signal Detected\n"); - } - return E1000_SUCCESS; -} - -/****************************************************************************** -* Make sure we have a valid PHY and change PHY mode before link setup. -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_copper_link_preconfig(struct e1000_hw *hw) -{ - uint32_t ctrl; - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_copper_link_preconfig"); - - ctrl = E1000_READ_REG(hw, CTRL); - /* With 82543, we need to force speed and duplex on the MAC equal to what - * the PHY speed and duplex configuration is. In addition, we need to - * perform a hardware reset on the PHY to take it out of reset. - */ - if (hw->mac_type > e1000_82543) { - ctrl |= E1000_CTRL_SLU; - ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); - E1000_WRITE_REG(hw, CTRL, ctrl); - } else { - ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); - E1000_WRITE_REG(hw, CTRL, ctrl); - ret_val = e1000_phy_hw_reset(hw); - if (ret_val) - return ret_val; - } - - /* Make sure we have a valid PHY */ - ret_val = e1000_detect_gig_phy(hw); - if (ret_val) { - DEBUGOUT("Error, did not detect valid phy.\n"); - return ret_val; - } - DEBUGOUT1("Phy ID = %x \n", hw->phy_id); - - /* Set PHY to class A mode (if necessary) */ - ret_val = e1000_set_phy_mode(hw); - if (ret_val) - return ret_val; - - if ((hw->mac_type == e1000_82545_rev_3) || - (hw->mac_type == e1000_82546_rev_3)) { - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - phy_data |= 0x00000008; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - } - - if (hw->mac_type <= e1000_82543 || - hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || - hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) - hw->phy_reset_disable = FALSE; - - return E1000_SUCCESS; -} - - -/******************************************************************** -* Copper link setup for e1000_phy_igp series. -* -* hw - Struct containing variables accessed by shared code -*********************************************************************/ -static int32_t -e1000_copper_link_igp_setup(struct e1000_hw *hw) -{ - uint32_t led_ctrl; - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_copper_link_igp_setup"); - - if (hw->phy_reset_disable) - return E1000_SUCCESS; - - ret_val = e1000_phy_reset(hw); - if (ret_val) { - DEBUGOUT("Error Resetting the PHY\n"); - return ret_val; - } - - /* Wait 15ms for MAC to configure PHY from eeprom settings */ - msec_delay(15); - if (hw->mac_type != e1000_ich8lan) { - /* Configure activity LED after PHY reset */ - led_ctrl = E1000_READ_REG(hw, LEDCTL); - led_ctrl &= IGP_ACTIVITY_LED_MASK; - led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); - E1000_WRITE_REG(hw, LEDCTL, led_ctrl); - } - - /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ - if (hw->phy_type == e1000_phy_igp) { - /* disable lplu d3 during driver init */ - ret_val = e1000_set_d3_lplu_state(hw, FALSE); - if (ret_val) { - DEBUGOUT("Error Disabling LPLU D3\n"); - return ret_val; - } - } - - /* disable lplu d0 during driver init */ - ret_val = e1000_set_d0_lplu_state(hw, FALSE); - if (ret_val) { - DEBUGOUT("Error Disabling LPLU D0\n"); - return ret_val; - } - /* Configure mdi-mdix settings */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); - if (ret_val) - return ret_val; - - if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { - hw->dsp_config_state = e1000_dsp_config_disabled; - /* Force MDI for earlier revs of the IGP PHY */ - phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); - hw->mdix = 1; - - } else { - hw->dsp_config_state = e1000_dsp_config_enabled; - phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; - - switch (hw->mdix) { - case 1: - phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; - break; - case 2: - phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; - break; - case 0: - default: - phy_data |= IGP01E1000_PSCR_AUTO_MDIX; - break; - } - } - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); - if (ret_val) - return ret_val; - - /* set auto-master slave resolution settings */ - if (hw->autoneg) { - e1000_ms_type phy_ms_setting = hw->master_slave; - - if (hw->ffe_config_state == e1000_ffe_config_active) - hw->ffe_config_state = e1000_ffe_config_enabled; - - if (hw->dsp_config_state == e1000_dsp_config_activated) - hw->dsp_config_state = e1000_dsp_config_enabled; - - /* when autonegotiation advertisment is only 1000Mbps then we - * should disable SmartSpeed and enable Auto MasterSlave - * resolution as hardware default. */ - if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { - /* Disable SmartSpeed */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - &phy_data); - if (ret_val) - return ret_val; - phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - phy_data); - if (ret_val) - return ret_val; - /* Set auto Master/Slave resolution process */ - ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); - if (ret_val) - return ret_val; - phy_data &= ~CR_1000T_MS_ENABLE; - ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); - if (ret_val) - return ret_val; - } - - ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); - if (ret_val) - return ret_val; - - /* load defaults for future use */ - hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? - ((phy_data & CR_1000T_MS_VALUE) ? - e1000_ms_force_master : - e1000_ms_force_slave) : - e1000_ms_auto; - - switch (phy_ms_setting) { - case e1000_ms_force_master: - phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); - break; - case e1000_ms_force_slave: - phy_data |= CR_1000T_MS_ENABLE; - phy_data &= ~(CR_1000T_MS_VALUE); - break; - case e1000_ms_auto: - phy_data &= ~CR_1000T_MS_ENABLE; - default: - break; - } - ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); - if (ret_val) - return ret_val; - } - - return E1000_SUCCESS; -} - -/******************************************************************** -* Copper link setup for e1000_phy_gg82563 series. -* -* hw - Struct containing variables accessed by shared code -*********************************************************************/ -static int32_t -e1000_copper_link_ggp_setup(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data; - uint32_t reg_data; - - DEBUGFUNC("e1000_copper_link_ggp_setup"); - - if (!hw->phy_reset_disable) { - - /* Enable CRS on TX for half-duplex operation. */ - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, - &phy_data); - if (ret_val) - return ret_val; - - phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; - /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ - phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; - - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, - phy_data); - if (ret_val) - return ret_val; - - /* Options: - * MDI/MDI-X = 0 (default) - * 0 - Auto for all speeds - * 1 - MDI mode - * 2 - MDI-X mode - * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) - */ - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; - - switch (hw->mdix) { - case 1: - phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; - break; - case 2: - phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; - break; - case 0: - default: - phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; - break; - } - - /* Options: - * disable_polarity_correction = 0 (default) - * Automatic Correction for Reversed Cable Polarity - * 0 - Disabled - * 1 - Enabled - */ - phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; - if (hw->disable_polarity_correction == 1) - phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); - - if (ret_val) - return ret_val; - - /* SW Reset the PHY so all changes take effect */ - ret_val = e1000_phy_reset(hw); - if (ret_val) { - DEBUGOUT("Error Resetting the PHY\n"); - return ret_val; - } - } /* phy_reset_disable */ - - if (hw->mac_type == e1000_80003es2lan) { - /* Bypass RX and TX FIFO's */ - ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, - E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | - E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); - - if (ret_val) - return ret_val; - - reg_data = E1000_READ_REG(hw, CTRL_EXT); - reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); - E1000_WRITE_REG(hw, CTRL_EXT, reg_data); - - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, - &phy_data); - if (ret_val) - return ret_val; - - /* Do not init these registers when the HW is in IAMT mode, since the - * firmware will have already initialized them. We only initialize - * them if the HW is not in IAMT mode. - */ - if (e1000_check_mng_mode(hw) == FALSE) { - /* Enable Electrical Idle on the PHY */ - phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, - phy_data); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - phy_data); - - if (ret_val) - return ret_val; - } - - /* Workaround: Disable padding in Kumeran interface in the MAC - * and in the PHY to avoid CRC errors. - */ - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, - &phy_data); - if (ret_val) - return ret_val; - phy_data |= GG82563_ICR_DIS_PADDING; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, - phy_data); - if (ret_val) - return ret_val; - } - - return E1000_SUCCESS; -} - -/******************************************************************** -* Copper link setup for e1000_phy_m88 series. -* -* hw - Struct containing variables accessed by shared code -*********************************************************************/ -static int32_t -e1000_copper_link_mgp_setup(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_copper_link_mgp_setup"); - - if (hw->phy_reset_disable) - return E1000_SUCCESS; - - /* Enable CRS on TX. This must be set for half-duplex operation. */ - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; - - /* Options: - * MDI/MDI-X = 0 (default) - * 0 - Auto for all speeds - * 1 - MDI mode - * 2 - MDI-X mode - * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) - */ - phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; - - switch (hw->mdix) { - case 1: - phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; - break; - case 2: - phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; - break; - case 3: - phy_data |= M88E1000_PSCR_AUTO_X_1000T; - break; - case 0: - default: - phy_data |= M88E1000_PSCR_AUTO_X_MODE; - break; - } - - /* Options: - * disable_polarity_correction = 0 (default) - * Automatic Correction for Reversed Cable Polarity - * 0 - Disabled - * 1 - Enabled - */ - phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; - if (hw->disable_polarity_correction == 1) - phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - - if (hw->phy_revision < M88E1011_I_REV_4) { - /* Force TX_CLK in the Extended PHY Specific Control Register - * to 25MHz clock. - */ - ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= M88E1000_EPSCR_TX_CLK_25; - - if ((hw->phy_revision == E1000_REVISION_2) && - (hw->phy_id == M88E1111_I_PHY_ID)) { - /* Vidalia Phy, set the downshift counter to 5x */ - phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); - phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; - ret_val = e1000_write_phy_reg(hw, - M88E1000_EXT_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - } else { - /* Configure Master and Slave downshift values */ - phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | - M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); - phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | - M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); - ret_val = e1000_write_phy_reg(hw, - M88E1000_EXT_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - } - } - - /* SW Reset the PHY so all changes take effect */ - ret_val = e1000_phy_reset(hw); - if (ret_val) { - DEBUGOUT("Error Resetting the PHY\n"); - return ret_val; - } - - return E1000_SUCCESS; -} - -/******************************************************************** -* Setup auto-negotiation and flow control advertisements, -* and then perform auto-negotiation. -* -* hw - Struct containing variables accessed by shared code -*********************************************************************/ -static int32_t -e1000_copper_link_autoneg(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_copper_link_autoneg"); - - /* Perform some bounds checking on the hw->autoneg_advertised - * parameter. If this variable is zero, then set it to the default. - */ - hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; - - /* If autoneg_advertised is zero, we assume it was not defaulted - * by the calling code so we set to advertise full capability. - */ - if (hw->autoneg_advertised == 0) - hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; - - /* IFE phy only supports 10/100 */ - if (hw->phy_type == e1000_phy_ife) - hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; - - DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); - ret_val = e1000_phy_setup_autoneg(hw); - if (ret_val) { - DEBUGOUT("Error Setting up Auto-Negotiation\n"); - return ret_val; - } - DEBUGOUT("Restarting Auto-Neg\n"); - - /* Restart auto-negotiation by setting the Auto Neg Enable bit and - * the Auto Neg Restart bit in the PHY control register. - */ - ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); - ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); - if (ret_val) - return ret_val; - - /* Does the user want to wait for Auto-Neg to complete here, or - * check at a later time (for example, callback routine). - */ - if (hw->wait_autoneg_complete) { - ret_val = e1000_wait_autoneg(hw); - if (ret_val) { - DEBUGOUT("Error while waiting for autoneg to complete\n"); - return ret_val; - } - } - - hw->get_link_status = TRUE; - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Config the MAC and the PHY after link is up. -* 1) Set up the MAC to the current PHY speed/duplex -* if we are on 82543. If we -* are on newer silicon, we only need to configure -* collision distance in the Transmit Control Register. -* 2) Set up flow control on the MAC to that established with -* the link partner. -* 3) Config DSP to improve Gigabit link quality for some PHY revisions. -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_copper_link_postconfig(struct e1000_hw *hw) -{ - int32_t ret_val; - DEBUGFUNC("e1000_copper_link_postconfig"); - - if (hw->mac_type >= e1000_82544) { - e1000_config_collision_dist(hw); - } else { - ret_val = e1000_config_mac_to_phy(hw); - if (ret_val) { - DEBUGOUT("Error configuring MAC to PHY settings\n"); - return ret_val; - } - } - ret_val = e1000_config_fc_after_link_up(hw); - if (ret_val) { - DEBUGOUT("Error Configuring Flow Control\n"); - return ret_val; - } - - /* Config DSP to improve Giga link quality */ - if (hw->phy_type == e1000_phy_igp) { - ret_val = e1000_config_dsp_after_link_change(hw, TRUE); - if (ret_val) { - DEBUGOUT("Error Configuring DSP after link up\n"); - return ret_val; - } - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Detects which PHY is present and setup the speed and duplex -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_setup_copper_link(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t i; - uint16_t phy_data; - uint16_t reg_data; - - DEBUGFUNC("e1000_setup_copper_link"); - - switch (hw->mac_type) { - case e1000_80003es2lan: - case e1000_ich8lan: - /* Set the mac to wait the maximum time between each - * iteration and increase the max iterations when - * polling the phy; this fixes erroneous timeouts at 10Mbps. */ - ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); - if (ret_val) - return ret_val; - ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); - if (ret_val) - return ret_val; - reg_data |= 0x3F; - ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); - if (ret_val) - return ret_val; - default: - break; - } - - /* Check if it is a valid PHY and set PHY mode if necessary. */ - ret_val = e1000_copper_link_preconfig(hw); - if (ret_val) - return ret_val; - - switch (hw->mac_type) { - case e1000_80003es2lan: - /* Kumeran registers are written-only */ - reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; - reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; - ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, - reg_data); - if (ret_val) - return ret_val; - break; - default: - break; - } - - if (hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) { - ret_val = e1000_copper_link_igp_setup(hw); - if (ret_val) - return ret_val; - } else if (hw->phy_type == e1000_phy_m88) { - ret_val = e1000_copper_link_mgp_setup(hw); - if (ret_val) - return ret_val; - } else if (hw->phy_type == e1000_phy_gg82563) { - ret_val = e1000_copper_link_ggp_setup(hw); - if (ret_val) - return ret_val; - } - - if (hw->autoneg) { - /* Setup autoneg and flow control advertisement - * and perform autonegotiation */ - ret_val = e1000_copper_link_autoneg(hw); - if (ret_val) - return ret_val; - } else { - /* PHY will be set to 10H, 10F, 100H,or 100F - * depending on value from forced_speed_duplex. */ - DEBUGOUT("Forcing speed and duplex\n"); - ret_val = e1000_phy_force_speed_duplex(hw); - if (ret_val) { - DEBUGOUT("Error Forcing Speed and Duplex\n"); - return ret_val; - } - } - - /* Check link status. Wait up to 100 microseconds for link to become - * valid. - */ - for (i = 0; i < 10; i++) { - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - - if (phy_data & MII_SR_LINK_STATUS) { - /* Config the MAC and PHY after link is up */ - ret_val = e1000_copper_link_postconfig(hw); - if (ret_val) - return ret_val; - - DEBUGOUT("Valid link established!!!\n"); - return E1000_SUCCESS; - } - usec_delay(10); - } - - DEBUGOUT("Unable to establish link!!!\n"); - return E1000_SUCCESS; -} - -/****************************************************************************** -* Configure the MAC-to-PHY interface for 10/100Mbps -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) -{ - int32_t ret_val = E1000_SUCCESS; - uint32_t tipg; - uint16_t reg_data; - - DEBUGFUNC("e1000_configure_kmrn_for_10_100"); - - reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; - ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, - reg_data); - if (ret_val) - return ret_val; - - /* Configure Transmit Inter-Packet Gap */ - tipg = E1000_READ_REG(hw, TIPG); - tipg &= ~E1000_TIPG_IPGT_MASK; - tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; - E1000_WRITE_REG(hw, TIPG, tipg); - - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); - - if (ret_val) - return ret_val; - - if (duplex == HALF_DUPLEX) - reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; - else - reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); - - return ret_val; -} - -static int32_t -e1000_configure_kmrn_for_1000(struct e1000_hw *hw) -{ - int32_t ret_val = E1000_SUCCESS; - uint16_t reg_data; - uint32_t tipg; - - DEBUGFUNC("e1000_configure_kmrn_for_1000"); - - reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; - ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, - reg_data); - if (ret_val) - return ret_val; - - /* Configure Transmit Inter-Packet Gap */ - tipg = E1000_READ_REG(hw, TIPG); - tipg &= ~E1000_TIPG_IPGT_MASK; - tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; - E1000_WRITE_REG(hw, TIPG, tipg); - - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); - - if (ret_val) - return ret_val; - - reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); - - return ret_val; -} - -/****************************************************************************** -* Configures PHY autoneg and flow control advertisement settings -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -int32_t -e1000_phy_setup_autoneg(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t mii_autoneg_adv_reg; - uint16_t mii_1000t_ctrl_reg; - - DEBUGFUNC("e1000_phy_setup_autoneg"); - - /* Read the MII Auto-Neg Advertisement Register (Address 4). */ - ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); - if (ret_val) - return ret_val; - - if (hw->phy_type != e1000_phy_ife) { - /* Read the MII 1000Base-T Control Register (Address 9). */ - ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); - if (ret_val) - return ret_val; - } else - mii_1000t_ctrl_reg=0; - - /* Need to parse both autoneg_advertised and fc and set up - * the appropriate PHY registers. First we will parse for - * autoneg_advertised software override. Since we can advertise - * a plethora of combinations, we need to check each bit - * individually. - */ - - /* First we clear all the 10/100 mb speed bits in the Auto-Neg - * Advertisement Register (Address 4) and the 1000 mb speed bits in - * the 1000Base-T Control Register (Address 9). - */ - mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; - mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; - - DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); - - /* Do we want to advertise 10 Mb Half Duplex? */ - if (hw->autoneg_advertised & ADVERTISE_10_HALF) { - DEBUGOUT("Advertise 10mb Half duplex\n"); - mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; - } - - /* Do we want to advertise 10 Mb Full Duplex? */ - if (hw->autoneg_advertised & ADVERTISE_10_FULL) { - DEBUGOUT("Advertise 10mb Full duplex\n"); - mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; - } - - /* Do we want to advertise 100 Mb Half Duplex? */ - if (hw->autoneg_advertised & ADVERTISE_100_HALF) { - DEBUGOUT("Advertise 100mb Half duplex\n"); - mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; - } - - /* Do we want to advertise 100 Mb Full Duplex? */ - if (hw->autoneg_advertised & ADVERTISE_100_FULL) { - DEBUGOUT("Advertise 100mb Full duplex\n"); - mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; - } - - /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ - if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { - DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); - } - - /* Do we want to advertise 1000 Mb Full Duplex? */ - if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { - DEBUGOUT("Advertise 1000mb Full duplex\n"); - mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; - if (hw->phy_type == e1000_phy_ife) { - DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); - } - } - - /* Check for a software override of the flow control settings, and - * setup the PHY advertisement registers accordingly. If - * auto-negotiation is enabled, then software will have to set the - * "PAUSE" bits to the correct value in the Auto-Negotiation - * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. - * - * The possible values of the "fc" parameter are: - * 0: Flow control is completely disabled - * 1: Rx flow control is enabled (we can receive pause frames - * but not send pause frames). - * 2: Tx flow control is enabled (we can send pause frames - * but we do not support receiving pause frames). - * 3: Both Rx and TX flow control (symmetric) are enabled. - * other: No software override. The flow control configuration - * in the EEPROM is used. - */ - switch (hw->fc) { - case E1000_FC_NONE: /* 0 */ - /* Flow control (RX & TX) is completely disabled by a - * software over-ride. - */ - mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); - break; - case E1000_FC_RX_PAUSE: /* 1 */ - /* RX Flow control is enabled, and TX Flow control is - * disabled, by a software over-ride. - */ - /* Since there really isn't a way to advertise that we are - * capable of RX Pause ONLY, we will advertise that we - * support both symmetric and asymmetric RX PAUSE. Later - * (in e1000_config_fc_after_link_up) we will disable the - *hw's ability to send PAUSE frames. - */ - mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); - break; - case E1000_FC_TX_PAUSE: /* 2 */ - /* TX Flow control is enabled, and RX Flow control is - * disabled, by a software over-ride. - */ - mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; - mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; - break; - case E1000_FC_FULL: /* 3 */ - /* Flow control (both RX and TX) is enabled by a software - * over-ride. - */ - mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); - break; - default: - DEBUGOUT("Flow control param set incorrectly\n"); - return -E1000_ERR_CONFIG; - } - - ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); - if (ret_val) - return ret_val; - - DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); - - if (hw->phy_type != e1000_phy_ife) { - ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); - if (ret_val) - return ret_val; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Force PHY speed and duplex settings to hw->forced_speed_duplex -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_phy_force_speed_duplex(struct e1000_hw *hw) -{ - uint32_t ctrl; - int32_t ret_val; - uint16_t mii_ctrl_reg; - uint16_t mii_status_reg; - uint16_t phy_data; - uint16_t i; - - DEBUGFUNC("e1000_phy_force_speed_duplex"); - - /* Turn off Flow control if we are forcing speed and duplex. */ - hw->fc = E1000_FC_NONE; - - DEBUGOUT1("hw->fc = %d\n", hw->fc); - - /* Read the Device Control Register. */ - ctrl = E1000_READ_REG(hw, CTRL); - - /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ - ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); - ctrl &= ~(DEVICE_SPEED_MASK); - - /* Clear the Auto Speed Detect Enable bit. */ - ctrl &= ~E1000_CTRL_ASDE; - - /* Read the MII Control Register. */ - ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); - if (ret_val) - return ret_val; - - /* We need to disable autoneg in order to force link and duplex. */ - - mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; - - /* Are we forcing Full or Half Duplex? */ - if (hw->forced_speed_duplex == e1000_100_full || - hw->forced_speed_duplex == e1000_10_full) { - /* We want to force full duplex so we SET the full duplex bits in the - * Device and MII Control Registers. - */ - ctrl |= E1000_CTRL_FD; - mii_ctrl_reg |= MII_CR_FULL_DUPLEX; - DEBUGOUT("Full Duplex\n"); - } else { - /* We want to force half duplex so we CLEAR the full duplex bits in - * the Device and MII Control Registers. - */ - ctrl &= ~E1000_CTRL_FD; - mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; - DEBUGOUT("Half Duplex\n"); - } - - /* Are we forcing 100Mbps??? */ - if (hw->forced_speed_duplex == e1000_100_full || - hw->forced_speed_duplex == e1000_100_half) { - /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ - ctrl |= E1000_CTRL_SPD_100; - mii_ctrl_reg |= MII_CR_SPEED_100; - mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); - DEBUGOUT("Forcing 100mb "); - } else { - /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ - ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); - mii_ctrl_reg |= MII_CR_SPEED_10; - mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); - DEBUGOUT("Forcing 10mb "); - } - - e1000_config_collision_dist(hw); - - /* Write the configured values back to the Device Control Reg. */ - E1000_WRITE_REG(hw, CTRL, ctrl); - - if ((hw->phy_type == e1000_phy_m88) || - (hw->phy_type == e1000_phy_gg82563)) { - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI - * forced whenever speed are duplex are forced. - */ - phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - - DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); - - /* Need to reset the PHY or these changes will be ignored */ - mii_ctrl_reg |= MII_CR_RESET; - - /* Disable MDI-X support for 10/100 */ - } else if (hw->phy_type == e1000_phy_ife) { - ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IFE_PMC_AUTO_MDIX; - phy_data &= ~IFE_PMC_FORCE_MDIX; - - ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); - if (ret_val) - return ret_val; - - } else { - /* Clear Auto-Crossover to force MDI manually. IGP requires MDI - * forced whenever speed or duplex are forced. - */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; - phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; - - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); - if (ret_val) - return ret_val; - } - - /* Write back the modified PHY MII control register. */ - ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); - if (ret_val) - return ret_val; - - usec_delay(1); - - /* The wait_autoneg_complete flag may be a little misleading here. - * Since we are forcing speed and duplex, Auto-Neg is not enabled. - * But we do want to delay for a period while forcing only so we - * don't generate false No Link messages. So we will wait here - * only if the user has set wait_autoneg_complete to 1, which is - * the default. - */ - if (hw->wait_autoneg_complete) { - /* We will wait for autoneg to complete. */ - DEBUGOUT("Waiting for forced speed/duplex link.\n"); - mii_status_reg = 0; - - /* We will wait for autoneg to complete or 4.5 seconds to expire. */ - for (i = PHY_FORCE_TIME; i > 0; i--) { - /* Read the MII Status Register and wait for Auto-Neg Complete bit - * to be set. - */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - if (mii_status_reg & MII_SR_LINK_STATUS) break; - msec_delay(100); - } - if ((i == 0) && - ((hw->phy_type == e1000_phy_m88) || - (hw->phy_type == e1000_phy_gg82563))) { - /* We didn't get link. Reset the DSP and wait again for link. */ - ret_val = e1000_phy_reset_dsp(hw); - if (ret_val) { - DEBUGOUT("Error Resetting PHY DSP\n"); - return ret_val; - } - } - /* This loop will early-out if the link condition has been met. */ - for (i = PHY_FORCE_TIME; i > 0; i--) { - if (mii_status_reg & MII_SR_LINK_STATUS) break; - msec_delay(100); - /* Read the MII Status Register and wait for Auto-Neg Complete bit - * to be set. - */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - } - } - - if (hw->phy_type == e1000_phy_m88) { - /* Because we reset the PHY above, we need to re-force TX_CLK in the - * Extended PHY Specific Control Register to 25MHz clock. This value - * defaults back to a 2.5MHz clock when the PHY is reset. - */ - ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= M88E1000_EPSCR_TX_CLK_25; - ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - - /* In addition, because of the s/w reset above, we need to enable CRS on - * TX. This must be set for both full and half duplex operation. - */ - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - - if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && - (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || - hw->forced_speed_duplex == e1000_10_half)) { - ret_val = e1000_polarity_reversal_workaround(hw); - if (ret_val) - return ret_val; - } - } else if (hw->phy_type == e1000_phy_gg82563) { - /* The TX_CLK of the Extended PHY Specific Control Register defaults - * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if - * we're not in a forced 10/duplex configuration. */ - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~GG82563_MSCR_TX_CLK_MASK; - if ((hw->forced_speed_duplex == e1000_10_full) || - (hw->forced_speed_duplex == e1000_10_half)) - phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; - else - phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; - - /* Also due to the reset, we need to enable CRS on Tx. */ - phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; - - ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; - } - return E1000_SUCCESS; -} - -/****************************************************************************** -* Sets the collision distance in the Transmit Control register -* -* hw - Struct containing variables accessed by shared code -* -* Link should have been established previously. Reads the speed and duplex -* information from the Device Status register. -******************************************************************************/ -void -e1000_config_collision_dist(struct e1000_hw *hw) -{ - uint32_t tctl, coll_dist; - - DEBUGFUNC("e1000_config_collision_dist"); - - if (hw->mac_type < e1000_82543) - coll_dist = E1000_COLLISION_DISTANCE_82542; - else - coll_dist = E1000_COLLISION_DISTANCE; - - tctl = E1000_READ_REG(hw, TCTL); - - tctl &= ~E1000_TCTL_COLD; - tctl |= coll_dist << E1000_COLD_SHIFT; - - E1000_WRITE_REG(hw, TCTL, tctl); - E1000_WRITE_FLUSH(hw); -} - -/****************************************************************************** -* Sets MAC speed and duplex settings to reflect the those in the PHY -* -* hw - Struct containing variables accessed by shared code -* mii_reg - data to write to the MII control register -* -* The contents of the PHY register containing the needed information need to -* be passed in. -******************************************************************************/ -static int32_t -e1000_config_mac_to_phy(struct e1000_hw *hw) -{ - uint32_t ctrl; - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_config_mac_to_phy"); - - /* 82544 or newer MAC, Auto Speed Detection takes care of - * MAC speed/duplex configuration.*/ - if (hw->mac_type >= e1000_82544) - return E1000_SUCCESS; - - /* Read the Device Control Register and set the bits to Force Speed - * and Duplex. - */ - ctrl = E1000_READ_REG(hw, CTRL); - ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); - ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); - - /* Set up duplex in the Device Control and Transmit Control - * registers depending on negotiated values. - */ - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); - if (ret_val) - return ret_val; - - if (phy_data & M88E1000_PSSR_DPLX) - ctrl |= E1000_CTRL_FD; - else - ctrl &= ~E1000_CTRL_FD; - - e1000_config_collision_dist(hw); - - /* Set up speed in the Device Control register depending on - * negotiated values. - */ - if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) - ctrl |= E1000_CTRL_SPD_1000; - else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) - ctrl |= E1000_CTRL_SPD_100; - - /* Write the configured values back to the Device Control Reg. */ - E1000_WRITE_REG(hw, CTRL, ctrl); - return E1000_SUCCESS; -} - -/****************************************************************************** - * Forces the MAC's flow control settings. - * - * hw - Struct containing variables accessed by shared code - * - * Sets the TFCE and RFCE bits in the device control register to reflect - * the adapter settings. TFCE and RFCE need to be explicitly set by - * software when a Copper PHY is used because autonegotiation is managed - * by the PHY rather than the MAC. Software must also configure these - * bits when link is forced on a fiber connection. - *****************************************************************************/ -int32_t -e1000_force_mac_fc(struct e1000_hw *hw) -{ - uint32_t ctrl; - - DEBUGFUNC("e1000_force_mac_fc"); - - /* Get the current configuration of the Device Control Register */ - ctrl = E1000_READ_REG(hw, CTRL); - - /* Because we didn't get link via the internal auto-negotiation - * mechanism (we either forced link or we got link via PHY - * auto-neg), we have to manually enable/disable transmit an - * receive flow control. - * - * The "Case" statement below enables/disable flow control - * according to the "hw->fc" parameter. - * - * The possible values of the "fc" parameter are: - * 0: Flow control is completely disabled - * 1: Rx flow control is enabled (we can receive pause - * frames but not send pause frames). - * 2: Tx flow control is enabled (we can send pause frames - * frames but we do not receive pause frames). - * 3: Both Rx and TX flow control (symmetric) is enabled. - * other: No other values should be possible at this point. - */ - - switch (hw->fc) { - case E1000_FC_NONE: - ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); - break; - case E1000_FC_RX_PAUSE: - ctrl &= (~E1000_CTRL_TFCE); - ctrl |= E1000_CTRL_RFCE; - break; - case E1000_FC_TX_PAUSE: - ctrl &= (~E1000_CTRL_RFCE); - ctrl |= E1000_CTRL_TFCE; - break; - case E1000_FC_FULL: - ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); - break; - default: - DEBUGOUT("Flow control param set incorrectly\n"); - return -E1000_ERR_CONFIG; - } - - /* Disable TX Flow Control for 82542 (rev 2.0) */ - if (hw->mac_type == e1000_82542_rev2_0) - ctrl &= (~E1000_CTRL_TFCE); - - E1000_WRITE_REG(hw, CTRL, ctrl); - return E1000_SUCCESS; -} - -/****************************************************************************** - * Configures flow control settings after link is established - * - * hw - Struct containing variables accessed by shared code - * - * Should be called immediately after a valid link has been established. - * Forces MAC flow control settings if link was forced. When in MII/GMII mode - * and autonegotiation is enabled, the MAC flow control settings will be set - * based on the flow control negotiated by the PHY. In TBI mode, the TFCE - * and RFCE bits will be automaticaly set to the negotiated flow control mode. - *****************************************************************************/ -STATIC int32_t -e1000_config_fc_after_link_up(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t mii_status_reg; - uint16_t mii_nway_adv_reg; - uint16_t mii_nway_lp_ability_reg; - uint16_t speed; - uint16_t duplex; - - DEBUGFUNC("e1000_config_fc_after_link_up"); - - /* Check for the case where we have fiber media and auto-neg failed - * so we had to force link. In this case, we need to force the - * configuration of the MAC to match the "fc" parameter. - */ - if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || - ((hw->media_type == e1000_media_type_internal_serdes) && - (hw->autoneg_failed)) || - ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { - ret_val = e1000_force_mac_fc(hw); - if (ret_val) { - DEBUGOUT("Error forcing flow control settings\n"); - return ret_val; - } - } - - /* Check for the case where we have copper media and auto-neg is - * enabled. In this case, we need to check and see if Auto-Neg - * has completed, and if so, how the PHY and link partner has - * flow control configured. - */ - if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { - /* Read the MII Status Register and check to see if AutoNeg - * has completed. We read this twice because this reg has - * some "sticky" (latched) bits. - */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { - /* The AutoNeg process has completed, so we now need to - * read both the Auto Negotiation Advertisement Register - * (Address 4) and the Auto_Negotiation Base Page Ability - * Register (Address 5) to determine how flow control was - * negotiated. - */ - ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, - &mii_nway_adv_reg); - if (ret_val) - return ret_val; - ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, - &mii_nway_lp_ability_reg); - if (ret_val) - return ret_val; - - /* Two bits in the Auto Negotiation Advertisement Register - * (Address 4) and two bits in the Auto Negotiation Base - * Page Ability Register (Address 5) determine flow control - * for both the PHY and the link partner. The following - * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, - * 1999, describes these PAUSE resolution bits and how flow - * control is determined based upon these settings. - * NOTE: DC = Don't Care - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution - *-------|---------|-------|---------|-------------------- - * 0 | 0 | DC | DC | e1000_fc_none - * 0 | 1 | 0 | DC | e1000_fc_none - * 0 | 1 | 1 | 0 | e1000_fc_none - * 0 | 1 | 1 | 1 | e1000_fc_tx_pause - * 1 | 0 | 0 | DC | e1000_fc_none - * 1 | DC | 1 | DC | e1000_fc_full - * 1 | 1 | 0 | 0 | e1000_fc_none - * 1 | 1 | 0 | 1 | e1000_fc_rx_pause - * - */ - /* Are both PAUSE bits set to 1? If so, this implies - * Symmetric Flow Control is enabled at both ends. The - * ASM_DIR bits are irrelevant per the spec. - * - * For Symmetric Flow Control: - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 1 | DC | 1 | DC | e1000_fc_full - * - */ - if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && - (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { - /* Now we need to check if the user selected RX ONLY - * of pause frames. In this case, we had to advertise - * FULL flow control because we could not advertise RX - * ONLY. Hence, we must now check to see if we need to - * turn OFF the TRANSMISSION of PAUSE frames. - */ - if (hw->original_fc == E1000_FC_FULL) { - hw->fc = E1000_FC_FULL; - DEBUGOUT("Flow Control = FULL.\n"); - } else { - hw->fc = E1000_FC_RX_PAUSE; - DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); - } - } - /* For receiving PAUSE frames ONLY. - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 0 | 1 | 1 | 1 | e1000_fc_tx_pause - * - */ - else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && - (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && - (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && - (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { - hw->fc = E1000_FC_TX_PAUSE; - DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); - } - /* For transmitting PAUSE frames ONLY. - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 1 | 1 | 0 | 1 | e1000_fc_rx_pause - * - */ - else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && - (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && - !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && - (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { - hw->fc = E1000_FC_RX_PAUSE; - DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); - } - /* Per the IEEE spec, at this point flow control should be - * disabled. However, we want to consider that we could - * be connected to a legacy switch that doesn't advertise - * desired flow control, but can be forced on the link - * partner. So if we advertised no flow control, that is - * what we will resolve to. If we advertised some kind of - * receive capability (Rx Pause Only or Full Flow Control) - * and the link partner advertised none, we will configure - * ourselves to enable Rx Flow Control only. We can do - * this safely for two reasons: If the link partner really - * didn't want flow control enabled, and we enable Rx, no - * harm done since we won't be receiving any PAUSE frames - * anyway. If the intent on the link partner was to have - * flow control enabled, then by us enabling RX only, we - * can at least receive pause frames and process them. - * This is a good idea because in most cases, since we are - * predominantly a server NIC, more times than not we will - * be asked to delay transmission of packets than asking - * our link partner to pause transmission of frames. - */ - else if ((hw->original_fc == E1000_FC_NONE|| - hw->original_fc == E1000_FC_TX_PAUSE) || - hw->fc_strict_ieee) { - hw->fc = E1000_FC_NONE; - DEBUGOUT("Flow Control = NONE.\n"); - } else { - hw->fc = E1000_FC_RX_PAUSE; - DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); - } - - /* Now we need to do one last check... If we auto- - * negotiated to HALF DUPLEX, flow control should not be - * enabled per IEEE 802.3 spec. - */ - ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); - if (ret_val) { - DEBUGOUT("Error getting link speed and duplex\n"); - return ret_val; - } - - if (duplex == HALF_DUPLEX) - hw->fc = E1000_FC_NONE; - - /* Now we call a subroutine to actually force the MAC - * controller to use the correct flow control settings. - */ - ret_val = e1000_force_mac_fc(hw); - if (ret_val) { - DEBUGOUT("Error forcing flow control settings\n"); - return ret_val; - } - } else { - DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); - } - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Checks to see if the link status of the hardware has changed. - * - * hw - Struct containing variables accessed by shared code - * - * Called by any function that needs to check the link status of the adapter. - *****************************************************************************/ -int32_t -e1000_check_for_link(struct e1000_hw *hw) -{ - uint32_t rxcw = 0; - uint32_t ctrl; - uint32_t status; - uint32_t rctl; - uint32_t icr; - uint32_t signal = 0; - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_check_for_link"); - - ctrl = E1000_READ_REG(hw, CTRL); - status = E1000_READ_REG(hw, STATUS); - - /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be - * set when the optics detect a signal. On older adapters, it will be - * cleared when there is a signal. This applies to fiber media only. - */ - if ((hw->media_type == e1000_media_type_fiber) || - (hw->media_type == e1000_media_type_internal_serdes)) { - rxcw = E1000_READ_REG(hw, RXCW); - - if (hw->media_type == e1000_media_type_fiber) { - signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; - if (status & E1000_STATUS_LU) - hw->get_link_status = FALSE; - } - } - - /* If we have a copper PHY then we only want to go out to the PHY - * registers to see if Auto-Neg has completed and/or if our link - * status has changed. The get_link_status flag will be set if we - * receive a Link Status Change interrupt or we have Rx Sequence - * Errors. - */ - if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { - /* First we want to see if the MII Status Register reports - * link. If so, then we want to get the current speed/duplex - * of the PHY. - * Read the register twice since the link bit is sticky. - */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - - if (phy_data & MII_SR_LINK_STATUS) { - hw->get_link_status = FALSE; - /* Check if there was DownShift, must be checked immediately after - * link-up */ - e1000_check_downshift(hw); - - /* If we are on 82544 or 82543 silicon and speed/duplex - * are forced to 10H or 10F, then we will implement the polarity - * reversal workaround. We disable interrupts first, and upon - * returning, place the devices interrupt state to its previous - * value except for the link status change interrupt which will - * happen due to the execution of this workaround. - */ - - if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && - (!hw->autoneg) && - (hw->forced_speed_duplex == e1000_10_full || - hw->forced_speed_duplex == e1000_10_half)) { - E1000_WRITE_REG(hw, IMC, 0xffffffff); - ret_val = e1000_polarity_reversal_workaround(hw); - icr = E1000_READ_REG(hw, ICR); - E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); - E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); - } - - } else { - /* No link detected */ - e1000_config_dsp_after_link_change(hw, FALSE); - return 0; - } - - /* If we are forcing speed/duplex, then we simply return since - * we have already determined whether we have link or not. - */ - if (!hw->autoneg) return -E1000_ERR_CONFIG; - - /* optimize the dsp settings for the igp phy */ - e1000_config_dsp_after_link_change(hw, TRUE); - - /* We have a M88E1000 PHY and Auto-Neg is enabled. If we - * have Si on board that is 82544 or newer, Auto - * Speed Detection takes care of MAC speed/duplex - * configuration. So we only need to configure Collision - * Distance in the MAC. Otherwise, we need to force - * speed/duplex on the MAC to the current PHY speed/duplex - * settings. - */ - if (hw->mac_type >= e1000_82544) - e1000_config_collision_dist(hw); - else { - ret_val = e1000_config_mac_to_phy(hw); - if (ret_val) { - DEBUGOUT("Error configuring MAC to PHY settings\n"); - return ret_val; - } - } - - /* Configure Flow Control now that Auto-Neg has completed. First, we - * need to restore the desired flow control settings because we may - * have had to re-autoneg with a different link partner. - */ - ret_val = e1000_config_fc_after_link_up(hw); - if (ret_val) { - DEBUGOUT("Error configuring flow control\n"); - return ret_val; - } - - /* At this point we know that we are on copper and we have - * auto-negotiated link. These are conditions for checking the link - * partner capability register. We use the link speed to determine if - * TBI compatibility needs to be turned on or off. If the link is not - * at gigabit speed, then TBI compatibility is not needed. If we are - * at gigabit speed, we turn on TBI compatibility. - */ - if (hw->tbi_compatibility_en) { - uint16_t speed, duplex; - ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); - if (ret_val) { - DEBUGOUT("Error getting link speed and duplex\n"); - return ret_val; - } - if (speed != SPEED_1000) { - /* If link speed is not set to gigabit speed, we do not need - * to enable TBI compatibility. - */ - if (hw->tbi_compatibility_on) { - /* If we previously were in the mode, turn it off. */ - rctl = E1000_READ_REG(hw, RCTL); - rctl &= ~E1000_RCTL_SBP; - E1000_WRITE_REG(hw, RCTL, rctl); - hw->tbi_compatibility_on = FALSE; - } - } else { - /* If TBI compatibility is was previously off, turn it on. For - * compatibility with a TBI link partner, we will store bad - * packets. Some frames have an additional byte on the end and - * will look like CRC errors to to the hardware. - */ - if (!hw->tbi_compatibility_on) { - hw->tbi_compatibility_on = TRUE; - rctl = E1000_READ_REG(hw, RCTL); - rctl |= E1000_RCTL_SBP; - E1000_WRITE_REG(hw, RCTL, rctl); - } - } - } - } - /* If we don't have link (auto-negotiation failed or link partner cannot - * auto-negotiate), the cable is plugged in (we have signal), and our - * link partner is not trying to auto-negotiate with us (we are receiving - * idles or data), we need to force link up. We also need to give - * auto-negotiation time to complete, in case the cable was just plugged - * in. The autoneg_failed flag does this. - */ - else if ((((hw->media_type == e1000_media_type_fiber) && - ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || - (hw->media_type == e1000_media_type_internal_serdes)) && - (!(status & E1000_STATUS_LU)) && - (!(rxcw & E1000_RXCW_C))) { - if (hw->autoneg_failed == 0) { - hw->autoneg_failed = 1; - return 0; - } - DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); - - /* Disable auto-negotiation in the TXCW register */ - E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); - - /* Force link-up and also force full-duplex. */ - ctrl = E1000_READ_REG(hw, CTRL); - ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); - E1000_WRITE_REG(hw, CTRL, ctrl); - - /* Configure Flow Control after forcing link up. */ - ret_val = e1000_config_fc_after_link_up(hw); - if (ret_val) { - DEBUGOUT("Error configuring flow control\n"); - return ret_val; - } - } - /* If we are forcing link and we are receiving /C/ ordered sets, re-enable - * auto-negotiation in the TXCW register and disable forced link in the - * Device Control register in an attempt to auto-negotiate with our link - * partner. - */ - else if (((hw->media_type == e1000_media_type_fiber) || - (hw->media_type == e1000_media_type_internal_serdes)) && - (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { - DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); - E1000_WRITE_REG(hw, TXCW, hw->txcw); - E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); - - hw->serdes_link_down = FALSE; - } - /* If we force link for non-auto-negotiation switch, check link status - * based on MAC synchronization for internal serdes media type. - */ - else if ((hw->media_type == e1000_media_type_internal_serdes) && - !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { - /* SYNCH bit and IV bit are sticky. */ - usec_delay(10); - if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { - if (!(rxcw & E1000_RXCW_IV)) { - hw->serdes_link_down = FALSE; - DEBUGOUT("SERDES: Link is up.\n"); - } - } else { - hw->serdes_link_down = TRUE; - DEBUGOUT("SERDES: Link is down.\n"); - } - } - if ((hw->media_type == e1000_media_type_internal_serdes) && - (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { - hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Detects the current speed and duplex settings of the hardware. - * - * hw - Struct containing variables accessed by shared code - * speed - Speed of the connection - * duplex - Duplex setting of the connection - *****************************************************************************/ -int32_t -e1000_get_speed_and_duplex(struct e1000_hw *hw, - uint16_t *speed, - uint16_t *duplex) -{ - uint32_t status; - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_get_speed_and_duplex"); - - if (hw->mac_type >= e1000_82543) { - status = E1000_READ_REG(hw, STATUS); - if (status & E1000_STATUS_SPEED_1000) { - *speed = SPEED_1000; - DEBUGOUT("1000 Mbs, "); - } else if (status & E1000_STATUS_SPEED_100) { - *speed = SPEED_100; - DEBUGOUT("100 Mbs, "); - } else { - *speed = SPEED_10; - DEBUGOUT("10 Mbs, "); - } - - if (status & E1000_STATUS_FD) { - *duplex = FULL_DUPLEX; - DEBUGOUT("Full Duplex\n"); - } else { - *duplex = HALF_DUPLEX; - DEBUGOUT(" Half Duplex\n"); - } - } else { - DEBUGOUT("1000 Mbs, Full Duplex\n"); - *speed = SPEED_1000; - *duplex = FULL_DUPLEX; - } - - /* IGP01 PHY may advertise full duplex operation after speed downgrade even - * if it is operating at half duplex. Here we set the duplex settings to - * match the duplex in the link partner's capabilities. - */ - if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { - ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); - if (ret_val) - return ret_val; - - if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) - *duplex = HALF_DUPLEX; - else { - ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); - if (ret_val) - return ret_val; - if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || - (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) - *duplex = HALF_DUPLEX; - } - } - - if ((hw->mac_type == e1000_80003es2lan) && - (hw->media_type == e1000_media_type_copper)) { - if (*speed == SPEED_1000) - ret_val = e1000_configure_kmrn_for_1000(hw); - else - ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); - if (ret_val) - return ret_val; - } - - if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { - ret_val = e1000_kumeran_lock_loss_workaround(hw); - if (ret_val) - return ret_val; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Blocks until autoneg completes or times out (~4.5 seconds) -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -STATIC int32_t -e1000_wait_autoneg(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t i; - uint16_t phy_data; - - DEBUGFUNC("e1000_wait_autoneg"); - DEBUGOUT("Waiting for Auto-Neg to complete.\n"); - - /* We will wait for autoneg to complete or 4.5 seconds to expire. */ - for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { - /* Read the MII Status Register and wait for Auto-Neg - * Complete bit to be set. - */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - if (phy_data & MII_SR_AUTONEG_COMPLETE) { - return E1000_SUCCESS; - } - msec_delay(100); - } - return E1000_SUCCESS; -} - -/****************************************************************************** -* Raises the Management Data Clock -* -* hw - Struct containing variables accessed by shared code -* ctrl - Device control register's current value -******************************************************************************/ -static void -e1000_raise_mdi_clk(struct e1000_hw *hw, - uint32_t *ctrl) -{ - /* Raise the clock input to the Management Data Clock (by setting the MDC - * bit), and then delay 10 microseconds. - */ - E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); - E1000_WRITE_FLUSH(hw); - usec_delay(10); -} - -/****************************************************************************** -* Lowers the Management Data Clock -* -* hw - Struct containing variables accessed by shared code -* ctrl - Device control register's current value -******************************************************************************/ -static void -e1000_lower_mdi_clk(struct e1000_hw *hw, - uint32_t *ctrl) -{ - /* Lower the clock input to the Management Data Clock (by clearing the MDC - * bit), and then delay 10 microseconds. - */ - E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); - E1000_WRITE_FLUSH(hw); - usec_delay(10); -} - -/****************************************************************************** -* Shifts data bits out to the PHY -* -* hw - Struct containing variables accessed by shared code -* data - Data to send out to the PHY -* count - Number of bits to shift out -* -* Bits are shifted out in MSB to LSB order. -******************************************************************************/ -static void -e1000_shift_out_mdi_bits(struct e1000_hw *hw, - uint32_t data, - uint16_t count) -{ - uint32_t ctrl; - uint32_t mask; - - /* We need to shift "count" number of bits out to the PHY. So, the value - * in the "data" parameter will be shifted out to the PHY one bit at a - * time. In order to do this, "data" must be broken down into bits. - */ - mask = 0x01; - mask <<= (count - 1); - - ctrl = E1000_READ_REG(hw, CTRL); - - /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ - ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); - - while (mask) { - /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and - * then raising and lowering the Management Data Clock. A "0" is - * shifted out to the PHY by setting the MDIO bit to "0" and then - * raising and lowering the clock. - */ - if (data & mask) - ctrl |= E1000_CTRL_MDIO; - else - ctrl &= ~E1000_CTRL_MDIO; - - E1000_WRITE_REG(hw, CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - - usec_delay(10); - - e1000_raise_mdi_clk(hw, &ctrl); - e1000_lower_mdi_clk(hw, &ctrl); - - mask = mask >> 1; - } -} - -/****************************************************************************** -* Shifts data bits in from the PHY -* -* hw - Struct containing variables accessed by shared code -* -* Bits are shifted in in MSB to LSB order. -******************************************************************************/ -static uint16_t -e1000_shift_in_mdi_bits(struct e1000_hw *hw) -{ - uint32_t ctrl; - uint16_t data = 0; - uint8_t i; - - /* In order to read a register from the PHY, we need to shift in a total - * of 18 bits from the PHY. The first two bit (turnaround) times are used - * to avoid contention on the MDIO pin when a read operation is performed. - * These two bits are ignored by us and thrown away. Bits are "shifted in" - * by raising the input to the Management Data Clock (setting the MDC bit), - * and then reading the value of the MDIO bit. - */ - ctrl = E1000_READ_REG(hw, CTRL); - - /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ - ctrl &= ~E1000_CTRL_MDIO_DIR; - ctrl &= ~E1000_CTRL_MDIO; - - E1000_WRITE_REG(hw, CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - - /* Raise and Lower the clock before reading in the data. This accounts for - * the turnaround bits. The first clock occurred when we clocked out the - * last bit of the Register Address. - */ - e1000_raise_mdi_clk(hw, &ctrl); - e1000_lower_mdi_clk(hw, &ctrl); - - for (data = 0, i = 0; i < 16; i++) { - data = data << 1; - e1000_raise_mdi_clk(hw, &ctrl); - ctrl = E1000_READ_REG(hw, CTRL); - /* Check to see if we shifted in a "1". */ - if (ctrl & E1000_CTRL_MDIO) - data |= 1; - e1000_lower_mdi_clk(hw, &ctrl); - } - - e1000_raise_mdi_clk(hw, &ctrl); - e1000_lower_mdi_clk(hw, &ctrl); - - return data; -} - -STATIC int32_t -e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) -{ - uint32_t swfw_sync = 0; - uint32_t swmask = mask; - uint32_t fwmask = mask << 16; - int32_t timeout = 200; - - DEBUGFUNC("e1000_swfw_sync_acquire"); - - if (hw->swfwhw_semaphore_present) - return e1000_get_software_flag(hw); - - if (!hw->swfw_sync_present) - return e1000_get_hw_eeprom_semaphore(hw); - - while (timeout) { - if (e1000_get_hw_eeprom_semaphore(hw)) - return -E1000_ERR_SWFW_SYNC; - - swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); - if (!(swfw_sync & (fwmask | swmask))) { - break; - } - - /* firmware currently using resource (fwmask) */ - /* or other software thread currently using resource (swmask) */ - e1000_put_hw_eeprom_semaphore(hw); - msec_delay_irq(5); - timeout--; - } - - if (!timeout) { - DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); - return -E1000_ERR_SWFW_SYNC; - } - - swfw_sync |= swmask; - E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); - - e1000_put_hw_eeprom_semaphore(hw); - return E1000_SUCCESS; -} - -STATIC void -e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) -{ - uint32_t swfw_sync; - uint32_t swmask = mask; - - DEBUGFUNC("e1000_swfw_sync_release"); - - if (hw->swfwhw_semaphore_present) { - e1000_release_software_flag(hw); - return; - } - - if (!hw->swfw_sync_present) { - e1000_put_hw_eeprom_semaphore(hw); - return; - } - - /* if (e1000_get_hw_eeprom_semaphore(hw)) - * return -E1000_ERR_SWFW_SYNC; */ - while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); - /* empty */ - - swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); - swfw_sync &= ~swmask; - E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); - - e1000_put_hw_eeprom_semaphore(hw); -} - -/***************************************************************************** -* Reads the value from a PHY register, if the value is on a specific non zero -* page, sets the page first. -* hw - Struct containing variables accessed by shared code -* reg_addr - address of the PHY register to read -******************************************************************************/ -int32_t -e1000_read_phy_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t *phy_data) -{ - uint32_t ret_val; - uint16_t swfw; - - DEBUGFUNC("e1000_read_phy_reg"); - - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } - if (e1000_swfw_sync_acquire(hw, swfw)) - return -E1000_ERR_SWFW_SYNC; - - if ((hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) && - (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { - ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, - (uint16_t)reg_addr); - if (ret_val) { - e1000_swfw_sync_release(hw, swfw); - return ret_val; - } - } else if (hw->phy_type == e1000_phy_gg82563) { - if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || - (hw->mac_type == e1000_80003es2lan)) { - /* Select Configuration Page */ - if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { - ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); - } else { - /* Use Alternative Page Select register to access - * registers 30 and 31 - */ - ret_val = e1000_write_phy_reg_ex(hw, - GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); - } - - if (ret_val) { - e1000_swfw_sync_release(hw, swfw); - return ret_val; - } - } - } - - ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, - phy_data); - - e1000_swfw_sync_release(hw, swfw); - return ret_val; -} - -STATIC int32_t -e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t *phy_data) -{ - uint32_t i; - uint32_t mdic = 0; - const uint32_t phy_addr = 1; - - DEBUGFUNC("e1000_read_phy_reg_ex"); - - if (reg_addr > MAX_PHY_REG_ADDRESS) { - DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); - return -E1000_ERR_PARAM; - } - - if (hw->mac_type > e1000_82543) { - /* Set up Op-code, Phy Address, and register address in the MDI - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ - mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | - (phy_addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_READ)); - - E1000_WRITE_REG(hw, MDIC, mdic); - - /* Poll the ready bit to see if the MDI read completed */ - for (i = 0; i < 64; i++) { - usec_delay(50); - mdic = E1000_READ_REG(hw, MDIC); - if (mdic & E1000_MDIC_READY) break; - } - if (!(mdic & E1000_MDIC_READY)) { - DEBUGOUT("MDI Read did not complete\n"); - return -E1000_ERR_PHY; - } - if (mdic & E1000_MDIC_ERROR) { - DEBUGOUT("MDI Error\n"); - return -E1000_ERR_PHY; - } - *phy_data = (uint16_t) mdic; - } else { - /* We must first send a preamble through the MDIO pin to signal the - * beginning of an MII instruction. This is done by sending 32 - * consecutive "1" bits. - */ - e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); - - /* Now combine the next few fields that are required for a read - * operation. We use this method instead of calling the - * e1000_shift_out_mdi_bits routine five different times. The format of - * a MII read instruction consists of a shift out of 14 bits and is - * defined as follows: - * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> - * followed by a shift in of 18 bits. This first two bits shifted in - * are TurnAround bits used to avoid contention on the MDIO pin when a - * READ operation is performed. These two bits are thrown away - * followed by a shift in of 16 bits which contains the desired data. - */ - mdic = ((reg_addr) | (phy_addr << 5) | - (PHY_OP_READ << 10) | (PHY_SOF << 12)); - - e1000_shift_out_mdi_bits(hw, mdic, 14); - - /* Now that we've shifted out the read command to the MII, we need to - * "shift in" the 16-bit value (18 total bits) of the requested PHY - * register address. - */ - *phy_data = e1000_shift_in_mdi_bits(hw); - } - return E1000_SUCCESS; -} - -/****************************************************************************** -* Writes a value to a PHY register -* -* hw - Struct containing variables accessed by shared code -* reg_addr - address of the PHY register to write -* data - data to write to the PHY -******************************************************************************/ -int32_t -e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data) -{ - uint32_t ret_val; - uint16_t swfw; - - DEBUGFUNC("e1000_write_phy_reg"); - - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } - if (e1000_swfw_sync_acquire(hw, swfw)) - return -E1000_ERR_SWFW_SYNC; - - if ((hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) && - (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { - ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, - (uint16_t)reg_addr); - if (ret_val) { - e1000_swfw_sync_release(hw, swfw); - return ret_val; - } - } else if (hw->phy_type == e1000_phy_gg82563) { - if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || - (hw->mac_type == e1000_80003es2lan)) { - /* Select Configuration Page */ - if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { - ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); - } else { - /* Use Alternative Page Select register to access - * registers 30 and 31 - */ - ret_val = e1000_write_phy_reg_ex(hw, - GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); - } - - if (ret_val) { - e1000_swfw_sync_release(hw, swfw); - return ret_val; - } - } - } - - ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, - phy_data); - - e1000_swfw_sync_release(hw, swfw); - return ret_val; -} - -STATIC int32_t -e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data) -{ - uint32_t i; - uint32_t mdic = 0; - const uint32_t phy_addr = 1; - - DEBUGFUNC("e1000_write_phy_reg_ex"); - - if (reg_addr > MAX_PHY_REG_ADDRESS) { - DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); - return -E1000_ERR_PARAM; - } - - if (hw->mac_type > e1000_82543) { - /* Set up Op-code, Phy Address, register address, and data intended - * for the PHY register in the MDI Control register. The MAC will take - * care of interfacing with the PHY to send the desired data. - */ - mdic = (((uint32_t) phy_data) | - (reg_addr << E1000_MDIC_REG_SHIFT) | - (phy_addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_WRITE)); - - E1000_WRITE_REG(hw, MDIC, mdic); - - /* Poll the ready bit to see if the MDI read completed */ - for (i = 0; i < 641; i++) { - usec_delay(5); - mdic = E1000_READ_REG(hw, MDIC); - if (mdic & E1000_MDIC_READY) break; - } - if (!(mdic & E1000_MDIC_READY)) { - DEBUGOUT("MDI Write did not complete\n"); - return -E1000_ERR_PHY; - } - } else { - /* We'll need to use the SW defined pins to shift the write command - * out to the PHY. We first send a preamble to the PHY to signal the - * beginning of the MII instruction. This is done by sending 32 - * consecutive "1" bits. - */ - e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); - - /* Now combine the remaining required fields that will indicate a - * write operation. We use this method instead of calling the - * e1000_shift_out_mdi_bits routine for each field in the command. The - * format of a MII write instruction is as follows: - * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. - */ - mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | - (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); - mdic <<= 16; - mdic |= (uint32_t) phy_data; - - e1000_shift_out_mdi_bits(hw, mdic, 32); - } - - return E1000_SUCCESS; -} - -STATIC int32_t -e1000_read_kmrn_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t *data) -{ - uint32_t reg_val; - uint16_t swfw; - DEBUGFUNC("e1000_read_kmrn_reg"); - - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } - if (e1000_swfw_sync_acquire(hw, swfw)) - return -E1000_ERR_SWFW_SYNC; - - /* Write register address */ - reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & - E1000_KUMCTRLSTA_OFFSET) | - E1000_KUMCTRLSTA_REN; - E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); - usec_delay(2); - - /* Read the data returned */ - reg_val = E1000_READ_REG(hw, KUMCTRLSTA); - *data = (uint16_t)reg_val; - - e1000_swfw_sync_release(hw, swfw); - return E1000_SUCCESS; -} - -STATIC int32_t -e1000_write_kmrn_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t data) -{ - uint32_t reg_val; - uint16_t swfw; - DEBUGFUNC("e1000_write_kmrn_reg"); - - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } - if (e1000_swfw_sync_acquire(hw, swfw)) - return -E1000_ERR_SWFW_SYNC; - - reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & - E1000_KUMCTRLSTA_OFFSET) | data; - E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); - usec_delay(2); - - e1000_swfw_sync_release(hw, swfw); - return E1000_SUCCESS; -} - -/****************************************************************************** -* Returns the PHY to the power-on reset state -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -int32_t -e1000_phy_hw_reset(struct e1000_hw *hw) -{ - uint32_t ctrl, ctrl_ext; - uint32_t led_ctrl; - int32_t ret_val; - uint16_t swfw; - - DEBUGFUNC("e1000_phy_hw_reset"); - - /* In the case of the phy reset being blocked, it's not an error, we - * simply return success without performing the reset. */ - ret_val = e1000_check_phy_reset_block(hw); - if (ret_val) - return E1000_SUCCESS; - - DEBUGOUT("Resetting Phy...\n"); - - if (hw->mac_type > e1000_82543) { - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } - if (e1000_swfw_sync_acquire(hw, swfw)) { - DEBUGOUT("Unable to acquire swfw sync\n"); - return -E1000_ERR_SWFW_SYNC; - } - /* Read the device control register and assert the E1000_CTRL_PHY_RST - * bit. Then, take it out of reset. - * For pre-e1000_82571 hardware, we delay for 10ms between the assert - * and deassert. For e1000_82571 hardware and later, we instead delay - * for 50us between and 10ms after the deassertion. - */ - ctrl = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); - E1000_WRITE_FLUSH(hw); - - if (hw->mac_type < e1000_82571) - msec_delay(10); - else - usec_delay(100); - - E1000_WRITE_REG(hw, CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - - if (hw->mac_type >= e1000_82571) - msec_delay_irq(10); - - e1000_swfw_sync_release(hw, swfw); - } else { - /* Read the Extended Device Control Register, assert the PHY_RESET_DIR - * bit to put the PHY into reset. Then, take it out of reset. - */ - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; - ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - E1000_WRITE_FLUSH(hw); - msec_delay(10); - ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - E1000_WRITE_FLUSH(hw); - } - usec_delay(150); - - if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { - /* Configure activity LED after PHY reset */ - led_ctrl = E1000_READ_REG(hw, LEDCTL); - led_ctrl &= IGP_ACTIVITY_LED_MASK; - led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); - E1000_WRITE_REG(hw, LEDCTL, led_ctrl); - } - - /* Wait for FW to finish PHY configuration. */ - ret_val = e1000_get_phy_cfg_done(hw); - if (ret_val != E1000_SUCCESS) - return ret_val; - e1000_release_software_semaphore(hw); - - if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) - ret_val = e1000_init_lcd_from_nvm(hw); - - return ret_val; -} - -/****************************************************************************** -* Resets the PHY -* -* hw - Struct containing variables accessed by shared code -* -* Sets bit 15 of the MII Control regiser -******************************************************************************/ -int32_t -e1000_phy_reset(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_phy_reset"); - - /* In the case of the phy reset being blocked, it's not an error, we - * simply return success without performing the reset. */ - ret_val = e1000_check_phy_reset_block(hw); - if (ret_val) - return E1000_SUCCESS; - - switch (hw->phy_type) { - case e1000_phy_igp: - case e1000_phy_igp_2: - case e1000_phy_igp_3: - case e1000_phy_ife: - ret_val = e1000_phy_hw_reset(hw); - if (ret_val) - return ret_val; - break; - default: - ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= MII_CR_RESET; - ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); - if (ret_val) - return ret_val; - - usec_delay(1); - break; - } - - if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) - e1000_phy_init_script(hw); - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Work-around for 82566 power-down: on D3 entry- -* 1) disable gigabit link -* 2) write VR power-down enable -* 3) read it back -* if successful continue, else issue LCD reset and repeat -* -* hw - struct containing variables accessed by shared code -******************************************************************************/ -void -e1000_phy_powerdown_workaround(struct e1000_hw *hw) -{ - int32_t reg; - uint16_t phy_data; - int32_t retry = 0; - - DEBUGFUNC("e1000_phy_powerdown_workaround"); - - if (hw->phy_type != e1000_phy_igp_3) - return; - - do { - /* Disable link */ - reg = E1000_READ_REG(hw, PHY_CTRL); - E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | - E1000_PHY_CTRL_NOND0A_GBE_DISABLE); - - /* Write VR power-down enable - bits 9:8 should be 10b */ - e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); - phy_data |= (1 << 9); - phy_data &= ~(1 << 8); - e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); - - /* Read it back and test */ - e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); - if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) - break; - - /* Issue PHY reset and repeat at most one more time */ - reg = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); - retry++; - } while (retry); - - return; - -} - -/****************************************************************************** -* Work-around for 82566 Kumeran PCS lock loss: -* On link status change (i.e. PCI reset, speed change) and link is up and -* speed is gigabit- -* 0) if workaround is optionally disabled do nothing -* 1) wait 1ms for Kumeran link to come up -* 2) check Kumeran Diagnostic register PCS lock loss bit -* 3) if not set the link is locked (all is good), otherwise... -* 4) reset the PHY -* 5) repeat up to 10 times -* Note: this is only called for IGP3 copper when speed is 1gb. -* -* hw - struct containing variables accessed by shared code -******************************************************************************/ -STATIC int32_t -e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) -{ - int32_t ret_val; - int32_t reg; - int32_t cnt; - uint16_t phy_data; - - if (hw->kmrn_lock_loss_workaround_disabled) - return E1000_SUCCESS; - - /* Make sure link is up before proceeding. If not just return. - * Attempting this while link is negotiating fouled up link - * stability */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - - if (phy_data & MII_SR_LINK_STATUS) { - for (cnt = 0; cnt < 10; cnt++) { - /* read once to clear */ - ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); - if (ret_val) - return ret_val; - /* and again to get new status */ - ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); - if (ret_val) - return ret_val; - - /* check for PCS lock */ - if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) - return E1000_SUCCESS; - - /* Issue PHY reset */ - e1000_phy_hw_reset(hw); - msec_delay_irq(5); - } - /* Disable GigE link negotiation */ - reg = E1000_READ_REG(hw, PHY_CTRL); - E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | - E1000_PHY_CTRL_NOND0A_GBE_DISABLE); - - /* unable to acquire PCS lock */ - return E1000_ERR_PHY; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Probes the expected PHY address for known PHY IDs -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -STATIC int32_t -e1000_detect_gig_phy(struct e1000_hw *hw) -{ - int32_t phy_init_status, ret_val; - uint16_t phy_id_high, phy_id_low; - boolean_t match = FALSE; - - DEBUGFUNC("e1000_detect_gig_phy"); - - if (hw->phy_id != 0) - return E1000_SUCCESS; - - /* The 82571 firmware may still be configuring the PHY. In this - * case, we cannot access the PHY until the configuration is done. So - * we explicitly set the PHY values. */ - if (hw->mac_type == e1000_82571 || - hw->mac_type == e1000_82572) { - hw->phy_id = IGP01E1000_I_PHY_ID; - hw->phy_type = e1000_phy_igp_2; - return E1000_SUCCESS; - } - - /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- - * around that forces PHY page 0 to be set or the reads fail. The rest of - * the code in this routine uses e1000_read_phy_reg to read the PHY ID. - * So for ESB-2 we need to have this set so our reads won't fail. If the - * attached PHY is not a e1000_phy_gg82563, the routines below will figure - * this out as well. */ - if (hw->mac_type == e1000_80003es2lan) - hw->phy_type = e1000_phy_gg82563; - - /* Read the PHY ID Registers to identify which PHY is onboard. */ - ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); - if (ret_val) - return ret_val; - - hw->phy_id = (uint32_t) (phy_id_high << 16); - usec_delay(20); - ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); - if (ret_val) - return ret_val; - - hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); - hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; - - switch (hw->mac_type) { - case e1000_82543: - if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; - break; - case e1000_82544: - if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; - break; - case e1000_82540: - case e1000_82545: - case e1000_82545_rev_3: - case e1000_82546: - case e1000_82546_rev_3: - if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; - break; - case e1000_82541: - case e1000_82541_rev_2: - case e1000_82547: - case e1000_82547_rev_2: - if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; - break; - case e1000_82573: - if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; - break; - case e1000_80003es2lan: - if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; - break; - case e1000_ich8lan: - if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; - break; - default: - DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); - return -E1000_ERR_CONFIG; - } - phy_init_status = e1000_set_phy_type(hw); - - if ((match) && (phy_init_status == E1000_SUCCESS)) { - DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); - return E1000_SUCCESS; - } - DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); - return -E1000_ERR_PHY; -} - -/****************************************************************************** -* Resets the PHY's DSP -* -* hw - Struct containing variables accessed by shared code -******************************************************************************/ -static int32_t -e1000_phy_reset_dsp(struct e1000_hw *hw) -{ - int32_t ret_val; - DEBUGFUNC("e1000_phy_reset_dsp"); - - do { - if (hw->phy_type != e1000_phy_gg82563) { - ret_val = e1000_write_phy_reg(hw, 29, 0x001d); - if (ret_val) break; - } - ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); - if (ret_val) break; - ret_val = e1000_write_phy_reg(hw, 30, 0x0000); - if (ret_val) break; - ret_val = E1000_SUCCESS; - } while (0); - - return ret_val; -} - -/****************************************************************************** -* Get PHY information from various PHY registers for igp PHY only. -* -* hw - Struct containing variables accessed by shared code -* phy_info - PHY information structure -******************************************************************************/ -STATIC int32_t -e1000_phy_igp_get_info(struct e1000_hw *hw, - struct e1000_phy_info *phy_info) -{ - int32_t ret_val; - uint16_t phy_data, min_length, max_length, average; - e1000_rev_polarity polarity; - - DEBUGFUNC("e1000_phy_igp_get_info"); - - /* The downshift status is checked only once, after link is established, - * and it stored in the hw->speed_downgraded parameter. */ - phy_info->downshift = (e1000_downshift)hw->speed_downgraded; - - /* IGP01E1000 does not need to support it. */ - phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; - - /* IGP01E1000 always correct polarity reversal */ - phy_info->polarity_correction = e1000_polarity_reversal_enabled; - - /* Check polarity status */ - ret_val = e1000_check_polarity(hw, &polarity); - if (ret_val) - return ret_val; - - phy_info->cable_polarity = polarity; - - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); - if (ret_val) - return ret_val; - - phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> - IGP01E1000_PSSR_MDIX_SHIFT); - - if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == - IGP01E1000_PSSR_SPEED_1000MBPS) { - /* Local/Remote Receiver Information are only valid at 1000 Mbps */ - ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); - if (ret_val) - return ret_val; - - phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> - SR_1000T_LOCAL_RX_STATUS_SHIFT) ? - e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; - phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> - SR_1000T_REMOTE_RX_STATUS_SHIFT) ? - e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; - - /* Get cable length */ - ret_val = e1000_get_cable_length(hw, &min_length, &max_length); - if (ret_val) - return ret_val; - - /* Translate to old method */ - average = (max_length + min_length) / 2; - - if (average <= e1000_igp_cable_length_50) - phy_info->cable_length = e1000_cable_length_50; - else if (average <= e1000_igp_cable_length_80) - phy_info->cable_length = e1000_cable_length_50_80; - else if (average <= e1000_igp_cable_length_110) - phy_info->cable_length = e1000_cable_length_80_110; - else if (average <= e1000_igp_cable_length_140) - phy_info->cable_length = e1000_cable_length_110_140; - else - phy_info->cable_length = e1000_cable_length_140; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Get PHY information from various PHY registers for ife PHY only. -* -* hw - Struct containing variables accessed by shared code -* phy_info - PHY information structure -******************************************************************************/ -STATIC int32_t -e1000_phy_ife_get_info(struct e1000_hw *hw, - struct e1000_phy_info *phy_info) -{ - int32_t ret_val; - uint16_t phy_data; - e1000_rev_polarity polarity; - - DEBUGFUNC("e1000_phy_ife_get_info"); - - phy_info->downshift = (e1000_downshift)hw->speed_downgraded; - phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; - - ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); - if (ret_val) - return ret_val; - phy_info->polarity_correction = - ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> - IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? - e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; - - if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { - ret_val = e1000_check_polarity(hw, &polarity); - if (ret_val) - return ret_val; - } else { - /* Polarity is forced. */ - polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> - IFE_PSC_FORCE_POLARITY_SHIFT) ? - e1000_rev_polarity_reversed : e1000_rev_polarity_normal; - } - phy_info->cable_polarity = polarity; - - ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); - if (ret_val) - return ret_val; - - phy_info->mdix_mode = (e1000_auto_x_mode) - ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> - IFE_PMC_MDIX_MODE_SHIFT); - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Get PHY information from various PHY registers fot m88 PHY only. -* -* hw - Struct containing variables accessed by shared code -* phy_info - PHY information structure -******************************************************************************/ -STATIC int32_t -e1000_phy_m88_get_info(struct e1000_hw *hw, - struct e1000_phy_info *phy_info) -{ - int32_t ret_val; - uint16_t phy_data; - e1000_rev_polarity polarity; - - DEBUGFUNC("e1000_phy_m88_get_info"); - - /* The downshift status is checked only once, after link is established, - * and it stored in the hw->speed_downgraded parameter. */ - phy_info->downshift = (e1000_downshift)hw->speed_downgraded; - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; - - phy_info->extended_10bt_distance = - ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> - M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? - e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; - - phy_info->polarity_correction = - ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> - M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? - e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; - - /* Check polarity status */ - ret_val = e1000_check_polarity(hw, &polarity); - if (ret_val) - return ret_val; - phy_info->cable_polarity = polarity; - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); - if (ret_val) - return ret_val; - - phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> - M88E1000_PSSR_MDIX_SHIFT); - - if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { - /* Cable Length Estimation and Local/Remote Receiver Information - * are only valid at 1000 Mbps. - */ - if (hw->phy_type != e1000_phy_gg82563) { - phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> - M88E1000_PSSR_CABLE_LENGTH_SHIFT); - } else { - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, - &phy_data); - if (ret_val) - return ret_val; - - phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); - } - - ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); - if (ret_val) - return ret_val; - - phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> - SR_1000T_LOCAL_RX_STATUS_SHIFT) ? - e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; - phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> - SR_1000T_REMOTE_RX_STATUS_SHIFT) ? - e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; - - } - - return E1000_SUCCESS; -} - -/****************************************************************************** -* Get PHY information from various PHY registers -* -* hw - Struct containing variables accessed by shared code -* phy_info - PHY information structure -******************************************************************************/ -int32_t -e1000_phy_get_info(struct e1000_hw *hw, - struct e1000_phy_info *phy_info) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_phy_get_info"); - - phy_info->cable_length = e1000_cable_length_undefined; - phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; - phy_info->cable_polarity = e1000_rev_polarity_undefined; - phy_info->downshift = e1000_downshift_undefined; - phy_info->polarity_correction = e1000_polarity_reversal_undefined; - phy_info->mdix_mode = e1000_auto_x_mode_undefined; - phy_info->local_rx = e1000_1000t_rx_status_undefined; - phy_info->remote_rx = e1000_1000t_rx_status_undefined; - - if (hw->media_type != e1000_media_type_copper) { - DEBUGOUT("PHY info is only valid for copper media\n"); - return -E1000_ERR_CONFIG; - } - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - - if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { - DEBUGOUT("PHY info is only valid if link is up\n"); - return -E1000_ERR_CONFIG; - } - - if (hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) - return e1000_phy_igp_get_info(hw, phy_info); - else if (hw->phy_type == e1000_phy_ife) - return e1000_phy_ife_get_info(hw, phy_info); - else - return e1000_phy_m88_get_info(hw, phy_info); -} - -int32_t -e1000_validate_mdi_setting(struct e1000_hw *hw) -{ - DEBUGFUNC("e1000_validate_mdi_settings"); - - if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { - DEBUGOUT("Invalid MDI setting detected\n"); - hw->mdix = 1; - return -E1000_ERR_CONFIG; - } - return E1000_SUCCESS; -} - - -/****************************************************************************** - * Sets up eeprom variables in the hw struct. Must be called after mac_type - * is configured. Additionally, if this is ICH8, the flash controller GbE - * registers must be mapped, or this will crash. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_init_eeprom_params(struct e1000_hw *hw) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd = E1000_READ_REG(hw, EECD); - int32_t ret_val = E1000_SUCCESS; - uint16_t eeprom_size; - - DEBUGFUNC("e1000_init_eeprom_params"); - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - case e1000_82544: - eeprom->type = e1000_eeprom_microwire; - eeprom->word_size = 64; - eeprom->opcode_bits = 3; - eeprom->address_bits = 6; - eeprom->delay_usec = 50; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; - break; - case e1000_82540: - case e1000_82545: - case e1000_82545_rev_3: - case e1000_82546: - case e1000_82546_rev_3: - eeprom->type = e1000_eeprom_microwire; - eeprom->opcode_bits = 3; - eeprom->delay_usec = 50; - if (eecd & E1000_EECD_SIZE) { - eeprom->word_size = 256; - eeprom->address_bits = 8; - } else { - eeprom->word_size = 64; - eeprom->address_bits = 6; - } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; - break; - case e1000_82541: - case e1000_82541_rev_2: - case e1000_82547: - case e1000_82547_rev_2: - if (eecd & E1000_EECD_TYPE) { - eeprom->type = e1000_eeprom_spi; - eeprom->opcode_bits = 8; - eeprom->delay_usec = 1; - if (eecd & E1000_EECD_ADDR_BITS) { - eeprom->page_size = 32; - eeprom->address_bits = 16; - } else { - eeprom->page_size = 8; - eeprom->address_bits = 8; - } - } else { - eeprom->type = e1000_eeprom_microwire; - eeprom->opcode_bits = 3; - eeprom->delay_usec = 50; - if (eecd & E1000_EECD_ADDR_BITS) { - eeprom->word_size = 256; - eeprom->address_bits = 8; - } else { - eeprom->word_size = 64; - eeprom->address_bits = 6; - } - } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; - break; - case e1000_82571: - case e1000_82572: - eeprom->type = e1000_eeprom_spi; - eeprom->opcode_bits = 8; - eeprom->delay_usec = 1; - if (eecd & E1000_EECD_ADDR_BITS) { - eeprom->page_size = 32; - eeprom->address_bits = 16; - } else { - eeprom->page_size = 8; - eeprom->address_bits = 8; - } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; - break; - case e1000_82573: - eeprom->type = e1000_eeprom_spi; - eeprom->opcode_bits = 8; - eeprom->delay_usec = 1; - if (eecd & E1000_EECD_ADDR_BITS) { - eeprom->page_size = 32; - eeprom->address_bits = 16; - } else { - eeprom->page_size = 8; - eeprom->address_bits = 8; - } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = TRUE; - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { - eeprom->type = e1000_eeprom_flash; - eeprom->word_size = 2048; - - /* Ensure that the Autonomous FLASH update bit is cleared due to - * Flash update issue on parts which use a FLASH for NVM. */ - eecd &= ~E1000_EECD_AUPDEN; - E1000_WRITE_REG(hw, EECD, eecd); - } - break; - case e1000_80003es2lan: - eeprom->type = e1000_eeprom_spi; - eeprom->opcode_bits = 8; - eeprom->delay_usec = 1; - if (eecd & E1000_EECD_ADDR_BITS) { - eeprom->page_size = 32; - eeprom->address_bits = 16; - } else { - eeprom->page_size = 8; - eeprom->address_bits = 8; - } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = FALSE; - break; - case e1000_ich8lan: - { - int32_t i = 0; - uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); - - eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; - eeprom->word_size = E1000_SHADOW_RAM_WORDS; - - /* Zero the shadow RAM structure. But don't load it from NVM - * so as to save time for driver init */ - if (hw->eeprom_shadow_ram != NULL) { - for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; - hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; - } - } - - hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * - ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; - hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); - - hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size /= 2 * sizeof(uint16_t); - - break; - } - default: - break; - } - - if (eeprom->type == e1000_eeprom_spi) { - /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to - * 32KB (incremented by powers of 2). - */ - if (hw->mac_type <= e1000_82547_rev_2) { - /* Set to default value for initial eeprom read. */ - eeprom->word_size = 64; - ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); - if (ret_val) - return ret_val; - eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; - /* 256B eeprom size was not supported in earlier hardware, so we - * bump eeprom_size up one to ensure that "1" (which maps to 256B) - * is never the result used in the shifting logic below. */ - if (eeprom_size) - eeprom_size++; - } else { - eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> - E1000_EECD_SIZE_EX_SHIFT); - } - - eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); - } - return ret_val; -} - -/****************************************************************************** - * Raises the EEPROM's clock input. - * - * hw - Struct containing variables accessed by shared code - * eecd - EECD's current value - *****************************************************************************/ -static void -e1000_raise_ee_clk(struct e1000_hw *hw, - uint32_t *eecd) -{ - /* Raise the clock input to the EEPROM (by setting the SK bit), and then - * wait <delay> microseconds. - */ - *eecd = *eecd | E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, *eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(hw->eeprom.delay_usec); -} - -/****************************************************************************** - * Lowers the EEPROM's clock input. - * - * hw - Struct containing variables accessed by shared code - * eecd - EECD's current value - *****************************************************************************/ -static void -e1000_lower_ee_clk(struct e1000_hw *hw, - uint32_t *eecd) -{ - /* Lower the clock input to the EEPROM (by clearing the SK bit), and then - * wait 50 microseconds. - */ - *eecd = *eecd & ~E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, *eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(hw->eeprom.delay_usec); -} - -/****************************************************************************** - * Shift data bits out to the EEPROM. - * - * hw - Struct containing variables accessed by shared code - * data - data to send to the EEPROM - * count - number of bits to shift out - *****************************************************************************/ -static void -e1000_shift_out_ee_bits(struct e1000_hw *hw, - uint16_t data, - uint16_t count) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; - uint32_t mask; - - /* We need to shift "count" bits out to the EEPROM. So, value in the - * "data" parameter will be shifted out to the EEPROM one bit at a time. - * In order to do this, "data" must be broken down into bits. - */ - mask = 0x01 << (count - 1); - eecd = E1000_READ_REG(hw, EECD); - if (eeprom->type == e1000_eeprom_microwire) { - eecd &= ~E1000_EECD_DO; - } else if (eeprom->type == e1000_eeprom_spi) { - eecd |= E1000_EECD_DO; - } - do { - /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", - * and then raising and then lowering the clock (the SK bit controls - * the clock input to the EEPROM). A "0" is shifted out to the EEPROM - * by setting "DI" to "0" and then raising and then lowering the clock. - */ - eecd &= ~E1000_EECD_DI; - - if (data & mask) - eecd |= E1000_EECD_DI; - - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - - usec_delay(eeprom->delay_usec); - - e1000_raise_ee_clk(hw, &eecd); - e1000_lower_ee_clk(hw, &eecd); - - mask = mask >> 1; - - } while (mask); - - /* We leave the "DI" bit set to "0" when we leave this routine. */ - eecd &= ~E1000_EECD_DI; - E1000_WRITE_REG(hw, EECD, eecd); -} - -/****************************************************************************** - * Shift data bits in from the EEPROM - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -static uint16_t -e1000_shift_in_ee_bits(struct e1000_hw *hw, - uint16_t count) -{ - uint32_t eecd; - uint32_t i; - uint16_t data; - - /* In order to read a register from the EEPROM, we need to shift 'count' - * bits in from the EEPROM. Bits are "shifted in" by raising the clock - * input to the EEPROM (setting the SK bit), and then reading the value of - * the "DO" bit. During this "shifting in" process the "DI" bit should - * always be clear. - */ - - eecd = E1000_READ_REG(hw, EECD); - - eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); - data = 0; - - for (i = 0; i < count; i++) { - data = data << 1; - e1000_raise_ee_clk(hw, &eecd); - - eecd = E1000_READ_REG(hw, EECD); - - eecd &= ~(E1000_EECD_DI); - if (eecd & E1000_EECD_DO) - data |= 1; - - e1000_lower_ee_clk(hw, &eecd); - } - - return data; -} - -/****************************************************************************** - * Prepares EEPROM for access - * - * hw - Struct containing variables accessed by shared code - * - * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This - * function should be called before issuing a command to the EEPROM. - *****************************************************************************/ -static int32_t -e1000_acquire_eeprom(struct e1000_hw *hw) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd, i=0; - - DEBUGFUNC("e1000_acquire_eeprom"); - - if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) - return -E1000_ERR_SWFW_SYNC; - eecd = E1000_READ_REG(hw, EECD); - - if (hw->mac_type != e1000_82573) { - /* Request EEPROM Access */ - if (hw->mac_type > e1000_82544) { - eecd |= E1000_EECD_REQ; - E1000_WRITE_REG(hw, EECD, eecd); - eecd = E1000_READ_REG(hw, EECD); - while ((!(eecd & E1000_EECD_GNT)) && - (i < E1000_EEPROM_GRANT_ATTEMPTS)) { - i++; - usec_delay(5); - eecd = E1000_READ_REG(hw, EECD); - } - if (!(eecd & E1000_EECD_GNT)) { - eecd &= ~E1000_EECD_REQ; - E1000_WRITE_REG(hw, EECD, eecd); - DEBUGOUT("Could not acquire EEPROM grant\n"); - e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); - return -E1000_ERR_EEPROM; - } - } - } - - /* Setup EEPROM for Read/Write */ - - if (eeprom->type == e1000_eeprom_microwire) { - /* Clear SK and DI */ - eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); - E1000_WRITE_REG(hw, EECD, eecd); - - /* Set CS */ - eecd |= E1000_EECD_CS; - E1000_WRITE_REG(hw, EECD, eecd); - } else if (eeprom->type == e1000_eeprom_spi) { - /* Clear SK and CS */ - eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); - E1000_WRITE_REG(hw, EECD, eecd); - usec_delay(1); - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Returns EEPROM to a "standby" state - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -static void -e1000_standby_eeprom(struct e1000_hw *hw) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; - - eecd = E1000_READ_REG(hw, EECD); - - if (eeprom->type == e1000_eeprom_microwire) { - eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - - /* Clock high */ - eecd |= E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - - /* Select EEPROM */ - eecd |= E1000_EECD_CS; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - - /* Clock low */ - eecd &= ~E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - } else if (eeprom->type == e1000_eeprom_spi) { - /* Toggle CS to flush commands */ - eecd |= E1000_EECD_CS; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - eecd &= ~E1000_EECD_CS; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(eeprom->delay_usec); - } -} - -/****************************************************************************** - * Terminates a command by inverting the EEPROM's chip select pin - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -static void -e1000_release_eeprom(struct e1000_hw *hw) -{ - uint32_t eecd; - - DEBUGFUNC("e1000_release_eeprom"); - - eecd = E1000_READ_REG(hw, EECD); - - if (hw->eeprom.type == e1000_eeprom_spi) { - eecd |= E1000_EECD_CS; /* Pull CS high */ - eecd &= ~E1000_EECD_SK; /* Lower SCK */ - - E1000_WRITE_REG(hw, EECD, eecd); - - usec_delay(hw->eeprom.delay_usec); - } else if (hw->eeprom.type == e1000_eeprom_microwire) { - /* cleanup eeprom */ - - /* CS on Microwire is active-high */ - eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); - - E1000_WRITE_REG(hw, EECD, eecd); - - /* Rising edge of clock */ - eecd |= E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(hw->eeprom.delay_usec); - - /* Falling edge of clock */ - eecd &= ~E1000_EECD_SK; - E1000_WRITE_REG(hw, EECD, eecd); - E1000_WRITE_FLUSH(hw); - usec_delay(hw->eeprom.delay_usec); - } - - /* Stop requesting EEPROM access */ - if (hw->mac_type > e1000_82544) { - eecd &= ~E1000_EECD_REQ; - E1000_WRITE_REG(hw, EECD, eecd); - } - - e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); -} - -/****************************************************************************** - * Reads a 16 bit word from the EEPROM. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -STATIC int32_t -e1000_spi_eeprom_ready(struct e1000_hw *hw) -{ - uint16_t retry_count = 0; - uint8_t spi_stat_reg; - - DEBUGFUNC("e1000_spi_eeprom_ready"); - - /* Read "Status Register" repeatedly until the LSB is cleared. The - * EEPROM will signal that the command has been completed by clearing - * bit 0 of the internal status register. If it's not cleared within - * 5 milliseconds, then error out. - */ - retry_count = 0; - do { - e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, - hw->eeprom.opcode_bits); - spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); - if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) - break; - - usec_delay(5); - retry_count += 5; - - e1000_standby_eeprom(hw); - } while (retry_count < EEPROM_MAX_RETRY_SPI); - - /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and - * only 0-5mSec on 5V devices) - */ - if (retry_count >= EEPROM_MAX_RETRY_SPI) { - DEBUGOUT("SPI EEPROM Status error\n"); - return -E1000_ERR_EEPROM; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Reads a 16 bit word from the EEPROM. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM - * words - number of words to read - *****************************************************************************/ -int32_t -e1000_read_eeprom(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t i = 0; - - DEBUGFUNC("e1000_read_eeprom"); - - /* If eeprom is not yet detected, do so now */ - if (eeprom->word_size == 0) - e1000_init_eeprom_params(hw); - - /* A check for invalid values: offset too large, too many words, and not - * enough words. - */ - if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || - (words == 0)) { - DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); - return -E1000_ERR_EEPROM; - } - - /* EEPROM's that don't use EERD to read require us to bit-bang the SPI - * directly. In this case, we need to acquire the EEPROM so that - * FW or other port software does not interrupt. - */ - if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && - hw->eeprom.use_eerd == FALSE) { - /* Prepare the EEPROM for bit-bang reading */ - if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) - return -E1000_ERR_EEPROM; - } - - /* Eerd register EEPROM access requires no eeprom aquire/release */ - if (eeprom->use_eerd == TRUE) - return e1000_read_eeprom_eerd(hw, offset, words, data); - - /* ICH EEPROM access is done via the ICH flash controller */ - if (eeprom->type == e1000_eeprom_ich8) - return e1000_read_eeprom_ich8(hw, offset, words, data); - - /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have - * acquired the EEPROM at this point, so any returns should relase it */ - if (eeprom->type == e1000_eeprom_spi) { - uint16_t word_in; - uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; - - if (e1000_spi_eeprom_ready(hw)) { - e1000_release_eeprom(hw); - return -E1000_ERR_EEPROM; - } - - e1000_standby_eeprom(hw); - - /* Some SPI eeproms use the 8th address bit embedded in the opcode */ - if ((eeprom->address_bits == 8) && (offset >= 128)) - read_opcode |= EEPROM_A8_OPCODE_SPI; - - /* Send the READ command (opcode + addr) */ - e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); - - /* Read the data. The address of the eeprom internally increments with - * each byte (spi) being read, saving on the overhead of eeprom setup - * and tear-down. The address counter will roll over if reading beyond - * the size of the eeprom, thus allowing the entire memory to be read - * starting from any offset. */ - for (i = 0; i < words; i++) { - word_in = e1000_shift_in_ee_bits(hw, 16); - data[i] = (word_in >> 8) | (word_in << 8); - } - } else if (eeprom->type == e1000_eeprom_microwire) { - for (i = 0; i < words; i++) { - /* Send the READ command (opcode + addr) */ - e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, - eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), - eeprom->address_bits); - - /* Read the data. For microwire, each word requires the overhead - * of eeprom setup and tear-down. */ - data[i] = e1000_shift_in_ee_bits(hw, 16); - e1000_standby_eeprom(hw); - } - } - - /* End this read operation */ - e1000_release_eeprom(hw); - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Reads a 16 bit word from the EEPROM using the EERD register. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM - * words - number of words to read - *****************************************************************************/ -STATIC int32_t -e1000_read_eeprom_eerd(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - uint32_t i, eerd = 0; - int32_t error = 0; - - for (i = 0; i < words; i++) { - eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + - E1000_EEPROM_RW_REG_START; - - E1000_WRITE_REG(hw, EERD, eerd); - error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); - - if (error) { - break; - } - data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); - - } - - return error; -} - -/****************************************************************************** - * Writes a 16 bit word from the EEPROM using the EEWR register. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM - * words - number of words to read - *****************************************************************************/ -STATIC int32_t -e1000_write_eeprom_eewr(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - uint32_t register_value = 0; - uint32_t i = 0; - int32_t error = 0; - - if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) - return -E1000_ERR_SWFW_SYNC; - - for (i = 0; i < words; i++) { - register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | - ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | - E1000_EEPROM_RW_REG_START; - - error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); - if (error) { - break; - } - - E1000_WRITE_REG(hw, EEWR, register_value); - - error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); - - if (error) { - break; - } - } - - e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); - return error; -} - -/****************************************************************************** - * Polls the status bit (bit 1) of the EERD to determine when the read is done. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -STATIC int32_t -e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) -{ - uint32_t attempts = 100000; - uint32_t i, reg = 0; - int32_t done = E1000_ERR_EEPROM; - - for (i = 0; i < attempts; i++) { - if (eerd == E1000_EEPROM_POLL_READ) - reg = E1000_READ_REG(hw, EERD); - else - reg = E1000_READ_REG(hw, EEWR); - - if (reg & E1000_EEPROM_RW_REG_DONE) { - done = E1000_SUCCESS; - break; - } - usec_delay(5); - } - - return done; -} - -/*************************************************************************** -* Description: Determines if the onboard NVM is FLASH or EEPROM. -* -* hw - Struct containing variables accessed by shared code -****************************************************************************/ -STATIC boolean_t -e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) -{ - uint32_t eecd = 0; - - DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); - - if (hw->mac_type == e1000_ich8lan) - return FALSE; - - if (hw->mac_type == e1000_82573) { - eecd = E1000_READ_REG(hw, EECD); - - /* Isolate bits 15 & 16 */ - eecd = ((eecd >> 15) & 0x03); - - /* If both bits are set, device is Flash type */ - if (eecd == 0x03) { - return FALSE; - } - } - return TRUE; -} - -/****************************************************************************** - * Verifies that the EEPROM has a valid checksum - * - * hw - Struct containing variables accessed by shared code - * - * Reads the first 64 16 bit words of the EEPROM and sums the values read. - * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is - * valid. - *****************************************************************************/ -int32_t -e1000_validate_eeprom_checksum(struct e1000_hw *hw) -{ - uint16_t checksum = 0; - uint16_t i, eeprom_data; - - DEBUGFUNC("e1000_validate_eeprom_checksum"); - - if ((hw->mac_type == e1000_82573) && - (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { - /* Check bit 4 of word 10h. If it is 0, firmware is done updating - * 10h-12h. Checksum may need to be fixed. */ - e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); - if ((eeprom_data & 0x10) == 0) { - /* Read 0x23 and check bit 15. This bit is a 1 when the checksum - * has already been fixed. If the checksum is still wrong and this - * bit is a 1, we need to return bad checksum. Otherwise, we need - * to set this bit to a 1 and update the checksum. */ - e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); - if ((eeprom_data & 0x8000) == 0) { - eeprom_data |= 0x8000; - e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); - e1000_update_eeprom_checksum(hw); - } - } - } - - if (hw->mac_type == e1000_ich8lan) { - /* Drivers must allocate the shadow ram structure for the - * EEPROM checksum to be updated. Otherwise, this bit as well - * as the checksum must both be set correctly for this - * validation to pass. - */ - e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); - if ((eeprom_data & 0x40) == 0) { - eeprom_data |= 0x40; - e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); - e1000_update_eeprom_checksum(hw); - } - } - - for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { - if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - checksum += eeprom_data; - } - - if (checksum == (uint16_t) EEPROM_SUM) - return E1000_SUCCESS; - else { - DEBUGOUT("EEPROM Checksum Invalid\n"); - return -E1000_ERR_EEPROM; - } -} - -/****************************************************************************** - * Calculates the EEPROM checksum and writes it to the EEPROM - * - * hw - Struct containing variables accessed by shared code - * - * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. - * Writes the difference to word offset 63 of the EEPROM. - *****************************************************************************/ -int32_t -e1000_update_eeprom_checksum(struct e1000_hw *hw) -{ - uint32_t ctrl_ext; - uint16_t checksum = 0; - uint16_t i, eeprom_data; - - DEBUGFUNC("e1000_update_eeprom_checksum"); - - for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { - if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - checksum += eeprom_data; - } - checksum = (uint16_t) EEPROM_SUM - checksum; - if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { - DEBUGOUT("EEPROM Write Error\n"); - return -E1000_ERR_EEPROM; - } else if (hw->eeprom.type == e1000_eeprom_flash) { - e1000_commit_shadow_ram(hw); - } else if (hw->eeprom.type == e1000_eeprom_ich8) { - e1000_commit_shadow_ram(hw); - /* Reload the EEPROM, or else modifications will not appear - * until after next adapter reset. */ - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_EE_RST; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - msec_delay(10); - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Parent function for writing words to the different EEPROM types. - * - * hw - Struct containing variables accessed by shared code - * offset - offset within the EEPROM to be written to - * words - number of words to write - * data - 16 bit word to be written to the EEPROM - * - * If e1000_update_eeprom_checksum is not called after this function, the - * EEPROM will most likely contain an invalid checksum. - *****************************************************************************/ -int32_t -e1000_write_eeprom(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - int32_t status = 0; - - DEBUGFUNC("e1000_write_eeprom"); - - /* If eeprom is not yet detected, do so now */ - if (eeprom->word_size == 0) - e1000_init_eeprom_params(hw); - - /* A check for invalid values: offset too large, too many words, and not - * enough words. - */ - if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || - (words == 0)) { - DEBUGOUT("\"words\" parameter out of bounds\n"); - return -E1000_ERR_EEPROM; - } - - /* 82573 writes only through eewr */ - if (eeprom->use_eewr == TRUE) - return e1000_write_eeprom_eewr(hw, offset, words, data); - - if (eeprom->type == e1000_eeprom_ich8) - return e1000_write_eeprom_ich8(hw, offset, words, data); - - /* Prepare the EEPROM for writing */ - if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) - return -E1000_ERR_EEPROM; - - if (eeprom->type == e1000_eeprom_microwire) { - status = e1000_write_eeprom_microwire(hw, offset, words, data); - } else { - status = e1000_write_eeprom_spi(hw, offset, words, data); - msec_delay(10); - } - - /* Done with writing */ - e1000_release_eeprom(hw); - - return status; -} - -/****************************************************************************** - * Writes a 16 bit word to a given offset in an SPI EEPROM. - * - * hw - Struct containing variables accessed by shared code - * offset - offset within the EEPROM to be written to - * words - number of words to write - * data - pointer to array of 8 bit words to be written to the EEPROM - * - *****************************************************************************/ -STATIC int32_t -e1000_write_eeprom_spi(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint16_t widx = 0; - - DEBUGFUNC("e1000_write_eeprom_spi"); - - while (widx < words) { - uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; - - if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; - - e1000_standby_eeprom(hw); - - /* Send the WRITE ENABLE command (8 bit opcode ) */ - e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, - eeprom->opcode_bits); - - e1000_standby_eeprom(hw); - - /* Some SPI eeproms use the 8th address bit embedded in the opcode */ - if ((eeprom->address_bits == 8) && (offset >= 128)) - write_opcode |= EEPROM_A8_OPCODE_SPI; - - /* Send the Write command (8-bit opcode + addr) */ - e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); - - e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), - eeprom->address_bits); - - /* Send the data */ - - /* Loop to allow for up to whole page write (32 bytes) of eeprom */ - while (widx < words) { - uint16_t word_out = data[widx]; - word_out = (word_out >> 8) | (word_out << 8); - e1000_shift_out_ee_bits(hw, word_out, 16); - widx++; - - /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE - * operation, while the smaller eeproms are capable of an 8-byte - * PAGE WRITE operation. Break the inner loop to pass new address - */ - if ((((offset + widx)*2) % eeprom->page_size) == 0) { - e1000_standby_eeprom(hw); - break; - } - } - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Writes a 16 bit word to a given offset in a Microwire EEPROM. - * - * hw - Struct containing variables accessed by shared code - * offset - offset within the EEPROM to be written to - * words - number of words to write - * data - pointer to array of 16 bit words to be written to the EEPROM - * - *****************************************************************************/ -STATIC int32_t -e1000_write_eeprom_microwire(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) -{ - struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; - uint16_t words_written = 0; - uint16_t i = 0; - - DEBUGFUNC("e1000_write_eeprom_microwire"); - - /* Send the write enable command to the EEPROM (3-bit opcode plus - * 6/8-bit dummy address beginning with 11). It's less work to include - * the 11 of the dummy address as part of the opcode than it is to shift - * it over the correct number of bits for the address. This puts the - * EEPROM into write/erase mode. - */ - e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, - (uint16_t)(eeprom->opcode_bits + 2)); - - e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); - - /* Prepare the EEPROM */ - e1000_standby_eeprom(hw); - - while (words_written < words) { - /* Send the Write command (3-bit opcode + addr) */ - e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, - eeprom->opcode_bits); - - e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), - eeprom->address_bits); - - /* Send the data */ - e1000_shift_out_ee_bits(hw, data[words_written], 16); - - /* Toggle the CS line. This in effect tells the EEPROM to execute - * the previous command. - */ - e1000_standby_eeprom(hw); - - /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will - * signal that the command has been completed by raising the DO signal. - * If DO does not go high in 10 milliseconds, then error out. - */ - for (i = 0; i < 200; i++) { - eecd = E1000_READ_REG(hw, EECD); - if (eecd & E1000_EECD_DO) break; - usec_delay(50); - } - if (i == 200) { - DEBUGOUT("EEPROM Write did not complete\n"); - return -E1000_ERR_EEPROM; - } - - /* Recover from write */ - e1000_standby_eeprom(hw); - - words_written++; - } - - /* Send the write disable command to the EEPROM (3-bit opcode plus - * 6/8-bit dummy address beginning with 10). It's less work to include - * the 10 of the dummy address as part of the opcode than it is to shift - * it over the correct number of bits for the address. This takes the - * EEPROM out of write/erase mode. - */ - e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, - (uint16_t)(eeprom->opcode_bits + 2)); - - e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Flushes the cached eeprom to NVM. This is done by saving the modified values - * in the eeprom cache and the non modified values in the currently active bank - * to the new bank. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM - * words - number of words to read - *****************************************************************************/ -STATIC int32_t -e1000_commit_shadow_ram(struct e1000_hw *hw) -{ - uint32_t attempts = 100000; - uint32_t eecd = 0; - uint32_t flop = 0; - uint32_t i = 0; - int32_t error = E1000_SUCCESS; - uint32_t old_bank_offset = 0; - uint32_t new_bank_offset = 0; - uint8_t low_byte = 0; - uint8_t high_byte = 0; - boolean_t sector_write_failed = FALSE; - - if (hw->mac_type == e1000_82573) { - /* The flop register will be used to determine if flash type is STM */ - flop = E1000_READ_REG(hw, FLOP); - for (i=0; i < attempts; i++) { - eecd = E1000_READ_REG(hw, EECD); - if ((eecd & E1000_EECD_FLUPD) == 0) { - break; - } - usec_delay(5); - } - - if (i == attempts) { - return -E1000_ERR_EEPROM; - } - - /* If STM opcode located in bits 15:8 of flop, reset firmware */ - if ((flop & 0xFF00) == E1000_STM_OPCODE) { - E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); - } - - /* Perform the flash update */ - E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); - - for (i=0; i < attempts; i++) { - eecd = E1000_READ_REG(hw, EECD); - if ((eecd & E1000_EECD_FLUPD) == 0) { - break; - } - usec_delay(5); - } - - if (i == attempts) { - return -E1000_ERR_EEPROM; - } - } - - if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { - /* We're writing to the opposite bank so if we're on bank 1, - * write to bank 0 etc. We also need to erase the segment that - * is going to be written */ - if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { - new_bank_offset = hw->flash_bank_size * 2; - old_bank_offset = 0; - e1000_erase_ich8_4k_segment(hw, 1); - } else { - old_bank_offset = hw->flash_bank_size * 2; - new_bank_offset = 0; - e1000_erase_ich8_4k_segment(hw, 0); - } - - sector_write_failed = FALSE; - /* Loop for every byte in the shadow RAM, - * which is in units of words. */ - for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - /* Determine whether to write the value stored - * in the other NVM bank or a modified value stored - * in the shadow RAM */ - if (hw->eeprom_shadow_ram[i].modified == TRUE) { - low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; - usec_delay(100); - error = e1000_verify_write_ich8_byte(hw, - (i << 1) + new_bank_offset, low_byte); - - if (error != E1000_SUCCESS) - sector_write_failed = TRUE; - else { - high_byte = - (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); - usec_delay(100); - } - } else { - e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, - &low_byte); - usec_delay(100); - error = e1000_verify_write_ich8_byte(hw, - (i << 1) + new_bank_offset, low_byte); - - if (error != E1000_SUCCESS) - sector_write_failed = TRUE; - else { - e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, - &high_byte); - usec_delay(100); - } - } - - /* If the write of the low byte was successful, go ahread and - * write the high byte while checking to make sure that if it - * is the signature byte, then it is handled properly */ - if (sector_write_failed == FALSE) { - /* If the word is 0x13, then make sure the signature bits - * (15:14) are 11b until the commit has completed. - * This will allow us to write 10b which indicates the - * signature is valid. We want to do this after the write - * has completed so that we don't mark the segment valid - * while the write is still in progress */ - if (i == E1000_ICH_NVM_SIG_WORD) - high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; - - error = e1000_verify_write_ich8_byte(hw, - (i << 1) + new_bank_offset + 1, high_byte); - if (error != E1000_SUCCESS) - sector_write_failed = TRUE; - - } else { - /* If the write failed then break from the loop and - * return an error */ - break; - } - } - - /* Don't bother writing the segment valid bits if sector - * programming failed. */ - if (sector_write_failed == FALSE) { - /* Finally validate the new segment by setting bit 15:14 - * to 10b in word 0x13 , this can be done without an - * erase as well since these bits are 11 to start with - * and we need to change bit 14 to 0b */ - e1000_read_ich8_byte(hw, - E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, - &high_byte); - high_byte &= 0xBF; - error = e1000_verify_write_ich8_byte(hw, - E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); - /* And invalidate the previously valid segment by setting - * its signature word (0x13) high_byte to 0b. This can be - * done without an erase because flash erase sets all bits - * to 1's. We can write 1's to 0's without an erase */ - if (error == E1000_SUCCESS) { - error = e1000_verify_write_ich8_byte(hw, - E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); - } - - /* Clear the now not used entry in the cache */ - for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; - hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; - } - } - } - - return error; -} - -/****************************************************************************** - * Reads the adapter's part number from the EEPROM - * - * hw - Struct containing variables accessed by shared code - * part_num - Adapter's part number - *****************************************************************************/ -int32_t -e1000_read_part_num(struct e1000_hw *hw, - uint32_t *part_num) -{ - uint16_t offset = EEPROM_PBA_BYTE_1; - uint16_t eeprom_data; - - DEBUGFUNC("e1000_read_part_num"); - - /* Get word 0 from EEPROM */ - if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - /* Save word 0 in upper half of part_num */ - *part_num = (uint32_t) (eeprom_data << 16); - - /* Get word 1 from EEPROM */ - if (e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - /* Save word 1 in lower half of part_num */ - *part_num |= eeprom_data; - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the - * second function of dual function devices - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_read_mac_addr(struct e1000_hw * hw) -{ - uint16_t offset; - uint16_t eeprom_data, i; - - DEBUGFUNC("e1000_read_mac_addr"); - - for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { - offset = i >> 1; - if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); - hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); - } - - switch (hw->mac_type) { - default: - break; - case e1000_82546: - case e1000_82546_rev_3: - case e1000_82571: - case e1000_80003es2lan: - if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) - hw->perm_mac_addr[5] ^= 0x01; - break; - } - - for (i = 0; i < NODE_ADDRESS_SIZE; i++) - hw->mac_addr[i] = hw->perm_mac_addr[i]; - return E1000_SUCCESS; -} - -/****************************************************************************** - * Initializes receive address filters. - * - * hw - Struct containing variables accessed by shared code - * - * Places the MAC address in receive address register 0 and clears the rest - * of the receive addresss registers. Clears the multicast table. Assumes - * the receiver is in reset when the routine is called. - *****************************************************************************/ -STATIC void -e1000_init_rx_addrs(struct e1000_hw *hw) -{ - uint32_t i; - uint32_t rar_num; - - DEBUGFUNC("e1000_init_rx_addrs"); - - /* Setup the receive address. */ - DEBUGOUT("Programming MAC Address into RAR[0]\n"); - - e1000_rar_set(hw, hw->mac_addr, 0); - - rar_num = E1000_RAR_ENTRIES; - - /* Reserve a spot for the Locally Administered Address to work around - * an 82571 issue in which a reset on one port will reload the MAC on - * the other port. */ - if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) - rar_num -= 1; - if (hw->mac_type == e1000_ich8lan) - rar_num = E1000_RAR_ENTRIES_ICH8LAN; - - /* Zero out the other 15 receive addresses. */ - DEBUGOUT("Clearing RAR[1-15]\n"); - for (i = 1; i < rar_num; i++) { - E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); - E1000_WRITE_FLUSH(hw); - E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); - E1000_WRITE_FLUSH(hw); - } -} - -/****************************************************************************** - * Updates the MAC's list of multicast addresses. - * - * hw - Struct containing variables accessed by shared code - * mc_addr_list - the list of new multicast addresses - * mc_addr_count - number of addresses - * pad - number of bytes between addresses in the list - * rar_used_count - offset where to start adding mc addresses into the RAR's - * - * The given list replaces any existing list. Clears the last 15 receive - * address registers and the multicast table. Uses receive address registers - * for the first 15 multicast addresses, and hashes the rest into the - * multicast table. - *****************************************************************************/ -void -e1000_mc_addr_list_update(struct e1000_hw *hw, - uint8_t *mc_addr_list, - uint32_t mc_addr_count, - uint32_t pad, - uint32_t rar_used_count) -{ - uint32_t hash_value; - uint32_t i; - uint32_t num_rar_entry; - uint32_t num_mta_entry; - - DEBUGFUNC("e1000_mc_addr_list_update"); - - /* Set the new number of MC addresses that we are being requested to use. */ - hw->num_mc_addrs = mc_addr_count; - - /* Clear RAR[1-15] */ - DEBUGOUT(" Clearing RAR[1-15]\n"); - num_rar_entry = E1000_RAR_ENTRIES; - if (hw->mac_type == e1000_ich8lan) - num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; - - /* Reserve a spot for the Locally Administered Address to work around - * an 82571 issue in which a reset on one port will reload the MAC on - * the other port. */ - if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) - num_rar_entry -= 1; - - for (i = rar_used_count; i < num_rar_entry; i++) { - E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); - E1000_WRITE_FLUSH(hw); - E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); - E1000_WRITE_FLUSH(hw); - } - - /* Clear the MTA */ - DEBUGOUT(" Clearing MTA\n"); - num_mta_entry = E1000_NUM_MTA_REGISTERS; - if (hw->mac_type == e1000_ich8lan) - num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; - - for (i = 0; i < num_mta_entry; i++) { - E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); - E1000_WRITE_FLUSH(hw); - } - - /* Add the new addresses */ - for (i = 0; i < mc_addr_count; i++) { - DEBUGOUT(" Adding the multicast addresses:\n"); - DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], - mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); - - hash_value = e1000_hash_mc_addr(hw, - mc_addr_list + - (i * (ETH_LENGTH_OF_ADDRESS + pad))); - - DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); - - /* Place this multicast address in the RAR if there is room, * - * else put it in the MTA - */ - if (rar_used_count < num_rar_entry) { - e1000_rar_set(hw, - mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), - rar_used_count); - rar_used_count++; - } else { - e1000_mta_set(hw, hash_value); - } - } - DEBUGOUT("MC Update Complete\n"); -} - -/****************************************************************************** - * Hashes an address to determine its location in the multicast table - * - * hw - Struct containing variables accessed by shared code - * mc_addr - the multicast address to hash - *****************************************************************************/ -uint32_t -e1000_hash_mc_addr(struct e1000_hw *hw, - uint8_t *mc_addr) -{ - uint32_t hash_value = 0; - - /* The portion of the address that is used for the hash table is - * determined by the mc_filter_type setting. - */ - switch (hw->mc_filter_type) { - /* [0] [1] [2] [3] [4] [5] - * 01 AA 00 12 34 56 - * LSB MSB - */ - case 0: - if (hw->mac_type == e1000_ich8lan) { - /* [47:38] i.e. 0x158 for above example address */ - hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); - } else { - /* [47:36] i.e. 0x563 for above example address */ - hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); - } - break; - case 1: - if (hw->mac_type == e1000_ich8lan) { - /* [46:37] i.e. 0x2B1 for above example address */ - hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); - } else { - /* [46:35] i.e. 0xAC6 for above example address */ - hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); - } - break; - case 2: - if (hw->mac_type == e1000_ich8lan) { - /*[45:36] i.e. 0x163 for above example address */ - hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); - } else { - /* [45:34] i.e. 0x5D8 for above example address */ - hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); - } - break; - case 3: - if (hw->mac_type == e1000_ich8lan) { - /* [43:34] i.e. 0x18D for above example address */ - hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); - } else { - /* [43:32] i.e. 0x634 for above example address */ - hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); - } - break; - } - - hash_value &= 0xFFF; - if (hw->mac_type == e1000_ich8lan) - hash_value &= 0x3FF; - - return hash_value; -} - -/****************************************************************************** - * Sets the bit in the multicast table corresponding to the hash value. - * - * hw - Struct containing variables accessed by shared code - * hash_value - Multicast address hash value - *****************************************************************************/ -void -e1000_mta_set(struct e1000_hw *hw, - uint32_t hash_value) -{ - uint32_t hash_bit, hash_reg; - uint32_t mta; - uint32_t temp; - - /* The MTA is a register array of 128 32-bit registers. - * It is treated like an array of 4096 bits. We want to set - * bit BitArray[hash_value]. So we figure out what register - * the bit is in, read it, OR in the new bit, then write - * back the new value. The register is determined by the - * upper 7 bits of the hash value and the bit within that - * register are determined by the lower 5 bits of the value. - */ - hash_reg = (hash_value >> 5) & 0x7F; - if (hw->mac_type == e1000_ich8lan) - hash_reg &= 0x1F; - - hash_bit = hash_value & 0x1F; - - mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); - - mta |= (1 << hash_bit); - - /* If we are on an 82544 and we are trying to write an odd offset - * in the MTA, save off the previous entry before writing and - * restore the old value after writing. - */ - if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { - temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); - E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); - E1000_WRITE_FLUSH(hw); - E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); - E1000_WRITE_FLUSH(hw); - } else { - E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); - E1000_WRITE_FLUSH(hw); - } -} - -/****************************************************************************** - * Puts an ethernet address into a receive address register. - * - * hw - Struct containing variables accessed by shared code - * addr - Address to put into receive address register - * index - Receive address register to write - *****************************************************************************/ -void -e1000_rar_set(struct e1000_hw *hw, - uint8_t *addr, - uint32_t index) -{ - uint32_t rar_low, rar_high; - - /* HW expects these in little endian so we reverse the byte order - * from network order (big endian) to little endian - */ - rar_low = ((uint32_t) addr[0] | - ((uint32_t) addr[1] << 8) | - ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); - rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); - - /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx - * unit hang. - * - * Description: - * If there are any Rx frames queued up or otherwise present in the HW - * before RSS is enabled, and then we enable RSS, the HW Rx unit will - * hang. To work around this issue, we have to disable receives and - * flush out all Rx frames before we enable RSS. To do so, we modify we - * redirect all Rx traffic to manageability and then reset the HW. - * This flushes away Rx frames, and (since the redirections to - * manageability persists across resets) keeps new ones from coming in - * while we work. Then, we clear the Address Valid AV bit for all MAC - * addresses and undo the re-direction to manageability. - * Now, frames are coming in again, but the MAC won't accept them, so - * far so good. We now proceed to initialize RSS (if necessary) and - * configure the Rx unit. Last, we re-enable the AV bits and continue - * on our merry way. - */ - switch (hw->mac_type) { - case e1000_82571: - case e1000_82572: - case e1000_80003es2lan: - if (hw->leave_av_bit_off == TRUE) - break; - default: - /* Indicate to hardware the Address is Valid. */ - rar_high |= E1000_RAH_AV; - break; - } - - E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); - E1000_WRITE_FLUSH(hw); - E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); - E1000_WRITE_FLUSH(hw); -} - -/****************************************************************************** - * Writes a value to the specified offset in the VLAN filter table. - * - * hw - Struct containing variables accessed by shared code - * offset - Offset in VLAN filer table to write - * value - Value to write into VLAN filter table - *****************************************************************************/ -void -e1000_write_vfta(struct e1000_hw *hw, - uint32_t offset, - uint32_t value) -{ - uint32_t temp; - - if (hw->mac_type == e1000_ich8lan) - return; - - if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { - temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); - E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); - E1000_WRITE_FLUSH(hw); - E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); - E1000_WRITE_FLUSH(hw); - } else { - E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); - E1000_WRITE_FLUSH(hw); - } -} - -/****************************************************************************** - * Clears the VLAN filer table - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -STATIC void -e1000_clear_vfta(struct e1000_hw *hw) -{ - uint32_t offset; - uint32_t vfta_value = 0; - uint32_t vfta_offset = 0; - uint32_t vfta_bit_in_reg = 0; - - if (hw->mac_type == e1000_ich8lan) - return; - - if (hw->mac_type == e1000_82573) { - if (hw->mng_cookie.vlan_id != 0) { - /* The VFTA is a 4096b bit-field, each identifying a single VLAN - * ID. The following operations determine which 32b entry - * (i.e. offset) into the array we want to set the VLAN ID - * (i.e. bit) of the manageability unit. */ - vfta_offset = (hw->mng_cookie.vlan_id >> - E1000_VFTA_ENTRY_SHIFT) & - E1000_VFTA_ENTRY_MASK; - vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & - E1000_VFTA_ENTRY_BIT_SHIFT_MASK); - } - } - for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { - /* If the offset we want to clear is the same offset of the - * manageability VLAN ID, then clear all bits except that of the - * manageability unit */ - vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; - E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); - E1000_WRITE_FLUSH(hw); - } -} - -STATIC int32_t -e1000_id_led_init(struct e1000_hw * hw) -{ - uint32_t ledctl; - const uint32_t ledctl_mask = 0x000000FF; - const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; - const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; - uint16_t eeprom_data, i, temp; - const uint16_t led_mask = 0x0F; - - DEBUGFUNC("e1000_id_led_init"); - - if (hw->mac_type < e1000_82540) { - /* Nothing to do */ - return E1000_SUCCESS; - } - - ledctl = E1000_READ_REG(hw, LEDCTL); - hw->ledctl_default = ledctl; - hw->ledctl_mode1 = hw->ledctl_default; - hw->ledctl_mode2 = hw->ledctl_default; - - if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - - if ((hw->mac_type == e1000_82573) && - (eeprom_data == ID_LED_RESERVED_82573)) - eeprom_data = ID_LED_DEFAULT_82573; - else if ((eeprom_data == ID_LED_RESERVED_0000) || - (eeprom_data == ID_LED_RESERVED_FFFF)) { - if (hw->mac_type == e1000_ich8lan) - eeprom_data = ID_LED_DEFAULT_ICH8LAN; - else - eeprom_data = ID_LED_DEFAULT; - } - - for (i = 0; i < 4; i++) { - temp = (eeprom_data >> (i << 2)) & led_mask; - switch (temp) { - case ID_LED_ON1_DEF2: - case ID_LED_ON1_ON2: - case ID_LED_ON1_OFF2: - hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); - hw->ledctl_mode1 |= ledctl_on << (i << 3); - break; - case ID_LED_OFF1_DEF2: - case ID_LED_OFF1_ON2: - case ID_LED_OFF1_OFF2: - hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); - hw->ledctl_mode1 |= ledctl_off << (i << 3); - break; - default: - /* Do nothing */ - break; - } - switch (temp) { - case ID_LED_DEF1_ON2: - case ID_LED_ON1_ON2: - case ID_LED_OFF1_ON2: - hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); - hw->ledctl_mode2 |= ledctl_on << (i << 3); - break; - case ID_LED_DEF1_OFF2: - case ID_LED_ON1_OFF2: - case ID_LED_OFF1_OFF2: - hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); - hw->ledctl_mode2 |= ledctl_off << (i << 3); - break; - default: - /* Do nothing */ - break; - } - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Prepares SW controlable LED for use and saves the current state of the LED. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_setup_led(struct e1000_hw *hw) -{ - uint32_t ledctl; - int32_t ret_val = E1000_SUCCESS; - - DEBUGFUNC("e1000_setup_led"); - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - case e1000_82544: - /* No setup necessary */ - break; - case e1000_82541: - case e1000_82547: - case e1000_82541_rev_2: - case e1000_82547_rev_2: - /* Turn off PHY Smart Power Down (if enabled) */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, - &hw->phy_spd_default); - if (ret_val) - return ret_val; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, - (uint16_t)(hw->phy_spd_default & - ~IGP01E1000_GMII_SPD)); - if (ret_val) - return ret_val; - /* Fall Through */ - default: - if (hw->media_type == e1000_media_type_fiber) { - ledctl = E1000_READ_REG(hw, LEDCTL); - /* Save current LEDCTL settings */ - hw->ledctl_default = ledctl; - /* Turn off LED0 */ - ledctl &= ~(E1000_LEDCTL_LED0_IVRT | - E1000_LEDCTL_LED0_BLINK | - E1000_LEDCTL_LED0_MODE_MASK); - ledctl |= (E1000_LEDCTL_MODE_LED_OFF << - E1000_LEDCTL_LED0_MODE_SHIFT); - E1000_WRITE_REG(hw, LEDCTL, ledctl); - } else if (hw->media_type == e1000_media_type_copper) - E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); - break; - } - - return E1000_SUCCESS; -} - - -/****************************************************************************** - * Used on 82571 and later Si that has LED blink bits. - * Callers must use their own timer and should have already called - * e1000_id_led_init() - * Call e1000_cleanup led() to stop blinking - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_blink_led_start(struct e1000_hw *hw) -{ - int16_t i; - uint32_t ledctl_blink = 0; - - DEBUGFUNC("e1000_id_led_blink_on"); - - if (hw->mac_type < e1000_82571) { - /* Nothing to do */ - return E1000_SUCCESS; - } - if (hw->media_type == e1000_media_type_fiber) { - /* always blink LED0 for PCI-E fiber */ - ledctl_blink = E1000_LEDCTL_LED0_BLINK | - (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); - } else { - /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ - ledctl_blink = hw->ledctl_mode2; - for (i=0; i < 4; i++) - if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == - E1000_LEDCTL_MODE_LED_ON) - ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); - } - - E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Restores the saved state of the SW controlable LED. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_cleanup_led(struct e1000_hw *hw) -{ - int32_t ret_val = E1000_SUCCESS; - - DEBUGFUNC("e1000_cleanup_led"); - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - case e1000_82544: - /* No cleanup necessary */ - break; - case e1000_82541: - case e1000_82547: - case e1000_82541_rev_2: - case e1000_82547_rev_2: - /* Turn on PHY Smart Power Down (if previously enabled) */ - ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, - hw->phy_spd_default); - if (ret_val) - return ret_val; - /* Fall Through */ - default: - if (hw->phy_type == e1000_phy_ife) { - e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); - break; - } - /* Restore LEDCTL settings */ - E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); - break; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Turns on the software controllable LED - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_led_on(struct e1000_hw *hw) -{ - uint32_t ctrl = E1000_READ_REG(hw, CTRL); - - DEBUGFUNC("e1000_led_on"); - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - /* Set SW Defineable Pin 0 to turn on the LED */ - ctrl |= E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - break; - case e1000_82544: - if (hw->media_type == e1000_media_type_fiber) { - /* Set SW Defineable Pin 0 to turn on the LED */ - ctrl |= E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } else { - /* Clear SW Defineable Pin 0 to turn on the LED */ - ctrl &= ~E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } - break; - default: - if (hw->media_type == e1000_media_type_fiber) { - /* Clear SW Defineable Pin 0 to turn on the LED */ - ctrl &= ~E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } else if (hw->phy_type == e1000_phy_ife) { - e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, - (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); - } else if (hw->media_type == e1000_media_type_copper) { - E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); - return E1000_SUCCESS; - } - break; - } - - E1000_WRITE_REG(hw, CTRL, ctrl); - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Turns off the software controllable LED - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -int32_t -e1000_led_off(struct e1000_hw *hw) -{ - uint32_t ctrl = E1000_READ_REG(hw, CTRL); - - DEBUGFUNC("e1000_led_off"); - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - case e1000_82543: - /* Clear SW Defineable Pin 0 to turn off the LED */ - ctrl &= ~E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - break; - case e1000_82544: - if (hw->media_type == e1000_media_type_fiber) { - /* Clear SW Defineable Pin 0 to turn off the LED */ - ctrl &= ~E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } else { - /* Set SW Defineable Pin 0 to turn off the LED */ - ctrl |= E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } - break; - default: - if (hw->media_type == e1000_media_type_fiber) { - /* Set SW Defineable Pin 0 to turn off the LED */ - ctrl |= E1000_CTRL_SWDPIN0; - ctrl |= E1000_CTRL_SWDPIO0; - } else if (hw->phy_type == e1000_phy_ife) { - e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, - (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); - } else if (hw->media_type == e1000_media_type_copper) { - E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); - return E1000_SUCCESS; - } - break; - } - - E1000_WRITE_REG(hw, CTRL, ctrl); - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Clears all hardware statistics counters. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -void -e1000_clear_hw_cntrs(struct e1000_hw *hw) -{ - volatile uint32_t temp; - - temp = E1000_READ_REG(hw, CRCERRS); - temp = E1000_READ_REG(hw, SYMERRS); - temp = E1000_READ_REG(hw, MPC); - temp = E1000_READ_REG(hw, SCC); - temp = E1000_READ_REG(hw, ECOL); - temp = E1000_READ_REG(hw, MCC); - temp = E1000_READ_REG(hw, LATECOL); - temp = E1000_READ_REG(hw, COLC); - temp = E1000_READ_REG(hw, DC); - temp = E1000_READ_REG(hw, SEC); - temp = E1000_READ_REG(hw, RLEC); - temp = E1000_READ_REG(hw, XONRXC); - temp = E1000_READ_REG(hw, XONTXC); - temp = E1000_READ_REG(hw, XOFFRXC); - temp = E1000_READ_REG(hw, XOFFTXC); - temp = E1000_READ_REG(hw, FCRUC); - - if (hw->mac_type != e1000_ich8lan) { - temp = E1000_READ_REG(hw, PRC64); - temp = E1000_READ_REG(hw, PRC127); - temp = E1000_READ_REG(hw, PRC255); - temp = E1000_READ_REG(hw, PRC511); - temp = E1000_READ_REG(hw, PRC1023); - temp = E1000_READ_REG(hw, PRC1522); - } - - temp = E1000_READ_REG(hw, GPRC); - temp = E1000_READ_REG(hw, BPRC); - temp = E1000_READ_REG(hw, MPRC); - temp = E1000_READ_REG(hw, GPTC); - temp = E1000_READ_REG(hw, GORCL); - temp = E1000_READ_REG(hw, GORCH); - temp = E1000_READ_REG(hw, GOTCL); - temp = E1000_READ_REG(hw, GOTCH); - temp = E1000_READ_REG(hw, RNBC); - temp = E1000_READ_REG(hw, RUC); - temp = E1000_READ_REG(hw, RFC); - temp = E1000_READ_REG(hw, ROC); - temp = E1000_READ_REG(hw, RJC); - temp = E1000_READ_REG(hw, TORL); - temp = E1000_READ_REG(hw, TORH); - temp = E1000_READ_REG(hw, TOTL); - temp = E1000_READ_REG(hw, TOTH); - temp = E1000_READ_REG(hw, TPR); - temp = E1000_READ_REG(hw, TPT); - - if (hw->mac_type != e1000_ich8lan) { - temp = E1000_READ_REG(hw, PTC64); - temp = E1000_READ_REG(hw, PTC127); - temp = E1000_READ_REG(hw, PTC255); - temp = E1000_READ_REG(hw, PTC511); - temp = E1000_READ_REG(hw, PTC1023); - temp = E1000_READ_REG(hw, PTC1522); - } - - temp = E1000_READ_REG(hw, MPTC); - temp = E1000_READ_REG(hw, BPTC); - - if (hw->mac_type < e1000_82543) return; - - temp = E1000_READ_REG(hw, ALGNERRC); - temp = E1000_READ_REG(hw, RXERRC); - temp = E1000_READ_REG(hw, TNCRS); - temp = E1000_READ_REG(hw, CEXTERR); - temp = E1000_READ_REG(hw, TSCTC); - temp = E1000_READ_REG(hw, TSCTFC); - - if (hw->mac_type <= e1000_82544) return; - - temp = E1000_READ_REG(hw, MGTPRC); - temp = E1000_READ_REG(hw, MGTPDC); - temp = E1000_READ_REG(hw, MGTPTC); - - if (hw->mac_type <= e1000_82547_rev_2) return; - - temp = E1000_READ_REG(hw, IAC); - temp = E1000_READ_REG(hw, ICRXOC); - - if (hw->mac_type == e1000_ich8lan) return; - - temp = E1000_READ_REG(hw, ICRXPTC); - temp = E1000_READ_REG(hw, ICRXATC); - temp = E1000_READ_REG(hw, ICTXPTC); - temp = E1000_READ_REG(hw, ICTXATC); - temp = E1000_READ_REG(hw, ICTXQEC); - temp = E1000_READ_REG(hw, ICTXQMTC); - temp = E1000_READ_REG(hw, ICRXDMTC); - -} - -/****************************************************************************** - * Resets Adaptive IFS to its default state. - * - * hw - Struct containing variables accessed by shared code - * - * Call this after e1000_init_hw. You may override the IFS defaults by setting - * hw->ifs_params_forced to TRUE. However, you must initialize hw-> - * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio - * before calling this function. - *****************************************************************************/ -void -e1000_reset_adaptive(struct e1000_hw *hw) -{ - DEBUGFUNC("e1000_reset_adaptive"); - - if (hw->adaptive_ifs) { - if (!hw->ifs_params_forced) { - hw->current_ifs_val = 0; - hw->ifs_min_val = IFS_MIN; - hw->ifs_max_val = IFS_MAX; - hw->ifs_step_size = IFS_STEP; - hw->ifs_ratio = IFS_RATIO; - } - hw->in_ifs_mode = FALSE; - E1000_WRITE_REG(hw, AIT, 0); - } else { - DEBUGOUT("Not in Adaptive IFS mode!\n"); - } -} - -/****************************************************************************** - * Called during the callback/watchdog routine to update IFS value based on - * the ratio of transmits to collisions. - * - * hw - Struct containing variables accessed by shared code - * tx_packets - Number of transmits since last callback - * total_collisions - Number of collisions since last callback - *****************************************************************************/ -void -e1000_update_adaptive(struct e1000_hw *hw) -{ - DEBUGFUNC("e1000_update_adaptive"); - - if (hw->adaptive_ifs) { - if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { - if (hw->tx_packet_delta > MIN_NUM_XMITS) { - hw->in_ifs_mode = TRUE; - if (hw->current_ifs_val < hw->ifs_max_val) { - if (hw->current_ifs_val == 0) - hw->current_ifs_val = hw->ifs_min_val; - else - hw->current_ifs_val += hw->ifs_step_size; - E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); - } - } - } else { - if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { - hw->current_ifs_val = 0; - hw->in_ifs_mode = FALSE; - E1000_WRITE_REG(hw, AIT, 0); - } - } - } else { - DEBUGOUT("Not in Adaptive IFS mode!\n"); - } -} - -/****************************************************************************** - * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT - * - * hw - Struct containing variables accessed by shared code - * frame_len - The length of the frame in question - * mac_addr - The Ethernet destination address of the frame in question - *****************************************************************************/ -void -e1000_tbi_adjust_stats(struct e1000_hw *hw, - struct e1000_hw_stats *stats, - uint32_t frame_len, - uint8_t *mac_addr) -{ - uint64_t carry_bit; - - /* First adjust the frame length. */ - frame_len--; - /* We need to adjust the statistics counters, since the hardware - * counters overcount this packet as a CRC error and undercount - * the packet as a good packet - */ - /* This packet should not be counted as a CRC error. */ - stats->crcerrs--; - /* This packet does count as a Good Packet Received. */ - stats->gprc++; - - /* Adjust the Good Octets received counters */ - carry_bit = 0x80000000 & stats->gorcl; - stats->gorcl += frame_len; - /* If the high bit of Gorcl (the low 32 bits of the Good Octets - * Received Count) was one before the addition, - * AND it is zero after, then we lost the carry out, - * need to add one to Gorch (Good Octets Received Count High). - * This could be simplified if all environments supported - * 64-bit integers. - */ - if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) - stats->gorch++; - /* Is this a broadcast or multicast? Check broadcast first, - * since the test for a multicast frame will test positive on - * a broadcast frame. - */ - if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) - /* Broadcast packet */ - stats->bprc++; - else if (*mac_addr & 0x01) - /* Multicast packet */ - stats->mprc++; - - if (frame_len == hw->max_frame_size) { - /* In this case, the hardware has overcounted the number of - * oversize frames. - */ - if (stats->roc > 0) - stats->roc--; - } - - /* Adjust the bin counters when the extra byte put the frame in the - * wrong bin. Remember that the frame_len was adjusted above. - */ - if (frame_len == 64) { - stats->prc64++; - stats->prc127--; - } else if (frame_len == 127) { - stats->prc127++; - stats->prc255--; - } else if (frame_len == 255) { - stats->prc255++; - stats->prc511--; - } else if (frame_len == 511) { - stats->prc511++; - stats->prc1023--; - } else if (frame_len == 1023) { - stats->prc1023++; - stats->prc1522--; - } else if (frame_len == 1522) { - stats->prc1522++; - } -} - -/****************************************************************************** - * Gets the current PCI bus type, speed, and width of the hardware - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -void -e1000_get_bus_info(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t pci_ex_link_status; - uint32_t status; - - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: - hw->bus_type = e1000_bus_type_unknown; - hw->bus_speed = e1000_bus_speed_unknown; - hw->bus_width = e1000_bus_width_unknown; - break; - case e1000_82571: - case e1000_82572: - case e1000_82573: - case e1000_80003es2lan: - hw->bus_type = e1000_bus_type_pci_express; - hw->bus_speed = e1000_bus_speed_2500; - ret_val = e1000_read_pcie_cap_reg(hw, - PCI_EX_LINK_STATUS, - &pci_ex_link_status); - if (ret_val) - hw->bus_width = e1000_bus_width_unknown; - else - hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> - PCI_EX_LINK_WIDTH_SHIFT; - break; - case e1000_ich8lan: - hw->bus_type = e1000_bus_type_pci_express; - hw->bus_speed = e1000_bus_speed_2500; - hw->bus_width = e1000_bus_width_pciex_1; - break; - default: - status = E1000_READ_REG(hw, STATUS); - hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? - e1000_bus_type_pcix : e1000_bus_type_pci; - - if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { - hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? - e1000_bus_speed_66 : e1000_bus_speed_120; - } else if (hw->bus_type == e1000_bus_type_pci) { - hw->bus_speed = (status & E1000_STATUS_PCI66) ? - e1000_bus_speed_66 : e1000_bus_speed_33; - } else { - switch (status & E1000_STATUS_PCIX_SPEED) { - case E1000_STATUS_PCIX_SPEED_66: - hw->bus_speed = e1000_bus_speed_66; - break; - case E1000_STATUS_PCIX_SPEED_100: - hw->bus_speed = e1000_bus_speed_100; - break; - case E1000_STATUS_PCIX_SPEED_133: - hw->bus_speed = e1000_bus_speed_133; - break; - default: - hw->bus_speed = e1000_bus_speed_reserved; - break; - } - } - hw->bus_width = (status & E1000_STATUS_BUS64) ? - e1000_bus_width_64 : e1000_bus_width_32; - break; - } -} - -#ifndef __sparc -/****************************************************************************** - * Writes a value to one of the devices registers using port I/O (as opposed to - * memory mapped I/O). Only 82544 and newer devices support port I/O. - * - * hw - Struct containing variables accessed by shared code - * offset - offset to write to - * value - value to write - *****************************************************************************/ -STATIC void -e1000_write_reg_io(struct e1000_hw *hw, - uint32_t offset, - uint32_t value) -{ - unsigned long io_addr = hw->io_base; - unsigned long io_data = hw->io_base + 4; - - e1000_io_write(hw, io_addr, offset); - e1000_io_write(hw, io_data, value); -} -#endif - -/****************************************************************************** - * Estimates the cable length. - * - * hw - Struct containing variables accessed by shared code - * min_length - The estimated minimum length - * max_length - The estimated maximum length - * - * returns: - E1000_ERR_XXX - * E1000_SUCCESS - * - * This function always returns a ranged length (minimum & maximum). - * So for M88 phy's, this function interprets the one value returned from the - * register to the minimum and maximum range. - * For IGP phy's, the function calculates the range by the AGC registers. - *****************************************************************************/ -STATIC int32_t -e1000_get_cable_length(struct e1000_hw *hw, - uint16_t *min_length, - uint16_t *max_length) -{ - int32_t ret_val; - uint16_t agc_value = 0; - uint16_t i, phy_data; - uint16_t cable_length; - - DEBUGFUNC("e1000_get_cable_length"); - - *min_length = *max_length = 0; - - /* Use old method for Phy older than IGP */ - if (hw->phy_type == e1000_phy_m88) { - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, - &phy_data); - if (ret_val) - return ret_val; - cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> - M88E1000_PSSR_CABLE_LENGTH_SHIFT; - - /* Convert the enum value to ranged values */ - switch (cable_length) { - case e1000_cable_length_50: - *min_length = 0; - *max_length = e1000_igp_cable_length_50; - break; - case e1000_cable_length_50_80: - *min_length = e1000_igp_cable_length_50; - *max_length = e1000_igp_cable_length_80; - break; - case e1000_cable_length_80_110: - *min_length = e1000_igp_cable_length_80; - *max_length = e1000_igp_cable_length_110; - break; - case e1000_cable_length_110_140: - *min_length = e1000_igp_cable_length_110; - *max_length = e1000_igp_cable_length_140; - break; - case e1000_cable_length_140: - *min_length = e1000_igp_cable_length_140; - *max_length = e1000_igp_cable_length_170; - break; - default: - return -E1000_ERR_PHY; - } - } else if (hw->phy_type == e1000_phy_gg82563) { - ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, - &phy_data); - if (ret_val) - return ret_val; - cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; - - switch (cable_length) { - case e1000_gg_cable_length_60: - *min_length = 0; - *max_length = e1000_igp_cable_length_60; - break; - case e1000_gg_cable_length_60_115: - *min_length = e1000_igp_cable_length_60; - *max_length = e1000_igp_cable_length_115; - break; - case e1000_gg_cable_length_115_150: - *min_length = e1000_igp_cable_length_115; - *max_length = e1000_igp_cable_length_150; - break; - case e1000_gg_cable_length_150: - *min_length = e1000_igp_cable_length_150; - *max_length = e1000_igp_cable_length_180; - break; - default: - return -E1000_ERR_PHY; - } - } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ - uint16_t cur_agc_value; - uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; - uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = - {IGP01E1000_PHY_AGC_A, - IGP01E1000_PHY_AGC_B, - IGP01E1000_PHY_AGC_C, - IGP01E1000_PHY_AGC_D}; - /* Read the AGC registers for all channels */ - for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { - - ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); - if (ret_val) - return ret_val; - - cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; - - /* Value bound check. */ - if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || - (cur_agc_value == 0)) - return -E1000_ERR_PHY; - - agc_value += cur_agc_value; - - /* Update minimal AGC value. */ - if (min_agc_value > cur_agc_value) - min_agc_value = cur_agc_value; - } - - /* Remove the minimal AGC result for length < 50m */ - if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { - agc_value -= min_agc_value; - - /* Get the average length of the remaining 3 channels */ - agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); - } else { - /* Get the average length of all the 4 channels. */ - agc_value /= IGP01E1000_PHY_CHANNEL_NUM; - } - - /* Set the range of the calculated length. */ - *min_length = ((e1000_igp_cable_length_table[agc_value] - - IGP01E1000_AGC_RANGE) > 0) ? - (e1000_igp_cable_length_table[agc_value] - - IGP01E1000_AGC_RANGE) : 0; - *max_length = e1000_igp_cable_length_table[agc_value] + - IGP01E1000_AGC_RANGE; - } else if (hw->phy_type == e1000_phy_igp_2 || - hw->phy_type == e1000_phy_igp_3) { - uint16_t cur_agc_index, max_agc_index = 0; - uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; - uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = - {IGP02E1000_PHY_AGC_A, - IGP02E1000_PHY_AGC_B, - IGP02E1000_PHY_AGC_C, - IGP02E1000_PHY_AGC_D}; - /* Read the AGC registers for all channels */ - for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { - ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); - if (ret_val) - return ret_val; - - /* Getting bits 15:9, which represent the combination of course and - * fine gain values. The result is a number that can be put into - * the lookup table to obtain the approximate cable length. */ - cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & - IGP02E1000_AGC_LENGTH_MASK; - - /* Array index bound check. */ - if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || - (cur_agc_index == 0)) - return -E1000_ERR_PHY; - - /* Remove min & max AGC values from calculation. */ - if (e1000_igp_2_cable_length_table[min_agc_index] > - e1000_igp_2_cable_length_table[cur_agc_index]) - min_agc_index = cur_agc_index; - if (e1000_igp_2_cable_length_table[max_agc_index] < - e1000_igp_2_cable_length_table[cur_agc_index]) - max_agc_index = cur_agc_index; - - agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; - } - - agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + - e1000_igp_2_cable_length_table[max_agc_index]); - agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); - - /* Calculate cable length with the error range of +/- 10 meters. */ - *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? - (agc_value - IGP02E1000_AGC_RANGE) : 0; - *max_length = agc_value + IGP02E1000_AGC_RANGE; - } - - return E1000_SUCCESS; -} - -/****************************************************************************** - * Check the cable polarity - * - * hw - Struct containing variables accessed by shared code - * polarity - output parameter : 0 - Polarity is not reversed - * 1 - Polarity is reversed. - * - * returns: - E1000_ERR_XXX - * E1000_SUCCESS - * - * For phy's older then IGP, this function simply reads the polarity bit in the - * Phy Status register. For IGP phy's, this bit is valid only if link speed is - * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will - * return 0. If the link speed is 1000 Mbps the polarity status is in the - * IGP01E1000_PHY_PCS_INIT_REG. - *****************************************************************************/ -STATIC int32_t -e1000_check_polarity(struct e1000_hw *hw, - e1000_rev_polarity *polarity) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_check_polarity"); - - if ((hw->phy_type == e1000_phy_m88) || - (hw->phy_type == e1000_phy_gg82563)) { - /* return the Polarity bit in the Status register. */ - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, - &phy_data); - if (ret_val) - return ret_val; - *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> - M88E1000_PSSR_REV_POLARITY_SHIFT) ? - e1000_rev_polarity_reversed : e1000_rev_polarity_normal; - - } else if (hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) { - /* Read the Status register to check the speed */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, - &phy_data); - if (ret_val) - return ret_val; - - /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to - * find the polarity status */ - if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == - IGP01E1000_PSSR_SPEED_1000MBPS) { - - /* Read the GIG initialization PCS register (0x00B4) */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, - &phy_data); - if (ret_val) - return ret_val; - - /* Check the polarity bits */ - *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? - e1000_rev_polarity_reversed : e1000_rev_polarity_normal; - } else { - /* For 10 Mbps, read the polarity bit in the status register. (for - * 100 Mbps this bit is always 0) */ - *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? - e1000_rev_polarity_reversed : e1000_rev_polarity_normal; - } - } else if (hw->phy_type == e1000_phy_ife) { - ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, - &phy_data); - if (ret_val) - return ret_val; - *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> - IFE_PESC_POLARITY_REVERSED_SHIFT) ? - e1000_rev_polarity_reversed : e1000_rev_polarity_normal; - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Check if Downshift occured - * - * hw - Struct containing variables accessed by shared code - * downshift - output parameter : 0 - No Downshift ocured. - * 1 - Downshift ocured. - * - * returns: - E1000_ERR_XXX - * E1000_SUCCESS - * - * For phy's older then IGP, this function reads the Downshift bit in the Phy - * Specific Status register. For IGP phy's, it reads the Downgrade bit in the - * Link Health register. In IGP this bit is latched high, so the driver must - * read it immediately after link is established. - *****************************************************************************/ -STATIC int32_t -e1000_check_downshift(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data; - - DEBUGFUNC("e1000_check_downshift"); - - if (hw->phy_type == e1000_phy_igp || - hw->phy_type == e1000_phy_igp_3 || - hw->phy_type == e1000_phy_igp_2) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, - &phy_data); - if (ret_val) - return ret_val; - - hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; - } else if ((hw->phy_type == e1000_phy_m88) || - (hw->phy_type == e1000_phy_gg82563)) { - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, - &phy_data); - if (ret_val) - return ret_val; - - hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> - M88E1000_PSSR_DOWNSHIFT_SHIFT; - } else if (hw->phy_type == e1000_phy_ife) { - /* e1000_phy_ife supports 10/100 speed only */ - hw->speed_downgraded = FALSE; - } - - return E1000_SUCCESS; -} - -#ifndef FIFO_WORKAROUND -/***************************************************************************** - * - * Workaround for the Tanacross TX fifo failure. - * - * hw - Struct containing variables accessed by shared code - * length - Length of next outgoing frame - * - * - * returns: - E1000_ERR_FIFO_WRAP if the next packet cannot be transmitted yet - * E1000_SUCCESS if the next packet can be transmitted - * - *****************************************************************************/ -int32_t -e1000_82547_fifo_workaround(struct e1000_hw *hw, - uint16_t length) -{ - uint32_t tctl; - uint16_t fifo_space, fifo_pkt_len; - - /* get the length as seen by the FIFO of the next real packet to - * be transmitted - */ - fifo_pkt_len = E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, - E1000_FIFO_GRANULARITY); - - if (fifo_pkt_len > E1000_82547_FIFO_PAD + E1000_FIFO_HDR_SIZE) { - fifo_space = hw->tx_fifo_size - hw->tx_fifo_head; - - if ((hw->tx_fifo_head + fifo_pkt_len) >= - (hw->tx_fifo_size + E1000_82547_FIFO_PAD)) { - if (E1000_READ_REG(hw, TDT) != E1000_READ_REG(hw, TDH)) - return -E1000_ERR_FIFO_WRAP; - - if (E1000_READ_REG(hw, TDFT) != E1000_READ_REG(hw, TDFH)) - return -E1000_ERR_FIFO_WRAP; - - if (E1000_READ_REG(hw, TDFTS) != E1000_READ_REG(hw, TDFHS)) - return -E1000_ERR_FIFO_WRAP; - - /* Disable the tx unit to avoid further pointer movement */ - tctl = E1000_READ_REG(hw, TCTL); - E1000_WRITE_REG(hw, TCTL, tctl & ~E1000_TCTL_EN); - - /* Reset the fifo pointers. */ - E1000_WRITE_REG(hw, TDFT, hw->tx_fifo_start); - E1000_WRITE_REG(hw, TDFH, hw->tx_fifo_start); - E1000_WRITE_REG(hw, TDFTS, hw->tx_fifo_start); - E1000_WRITE_REG(hw, TDFHS, hw->tx_fifo_start); - - /* Re-enabling tx unit */ - E1000_WRITE_REG(hw, TCTL, tctl); - E1000_WRITE_FLUSH(hw); - - hw->tx_fifo_head = 0; - - } - } - return E1000_SUCCESS; -} - -/***************************************************************************** - * - * Updates the SW calculated TX FIFO head pointer. - * - * hw - Struct containing variables accessed by shared code - * length - Length of next outgoing frame - ****************************************************************************/ -void -e1000_update_tx_fifo_head(struct e1000_hw *hw, - uint32_t length) -{ - hw->tx_fifo_head += E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, - E1000_FIFO_GRANULARITY); - - if (hw->tx_fifo_head > hw->tx_fifo_size) - hw->tx_fifo_head -= hw->tx_fifo_size; - - return; -} - -#endif /* FIFO_WORKAROUND */ -/***************************************************************************** - * - * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a - * gigabit link is achieved to improve link quality. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_PHY if fail to read/write the PHY - * E1000_SUCCESS at any other case. - * - ****************************************************************************/ - -STATIC int32_t -e1000_config_dsp_after_link_change(struct e1000_hw *hw, - boolean_t link_up) -{ - int32_t ret_val; - uint16_t phy_data, phy_saved_data, speed, duplex, i; - uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = - {IGP01E1000_PHY_AGC_PARAM_A, - IGP01E1000_PHY_AGC_PARAM_B, - IGP01E1000_PHY_AGC_PARAM_C, - IGP01E1000_PHY_AGC_PARAM_D}; - uint16_t min_length, max_length; - - DEBUGFUNC("e1000_config_dsp_after_link_change"); - - if (hw->phy_type != e1000_phy_igp) - return E1000_SUCCESS; - - if (link_up) { - ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); - if (ret_val) { - DEBUGOUT("Error getting link speed and duplex\n"); - return ret_val; - } - - if (speed == SPEED_1000) { - - ret_val = e1000_get_cable_length(hw, &min_length, &max_length); - if (ret_val) - return ret_val; - - if ((hw->dsp_config_state == e1000_dsp_config_enabled) && - min_length >= e1000_igp_cable_length_50) { - - for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { - ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], - &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; - - ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], - phy_data); - if (ret_val) - return ret_val; - } - hw->dsp_config_state = e1000_dsp_config_activated; - } - - if ((hw->ffe_config_state == e1000_ffe_config_enabled) && - (min_length < e1000_igp_cable_length_50)) { - - uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; - uint32_t idle_errs = 0; - - /* clear previous idle error counts */ - ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, - &phy_data); - if (ret_val) - return ret_val; - - for (i = 0; i < ffe_idle_err_timeout; i++) { - usec_delay(1000); - ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, - &phy_data); - if (ret_val) - return ret_val; - - idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); - if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { - hw->ffe_config_state = e1000_ffe_config_active; - - ret_val = e1000_write_phy_reg(hw, - IGP01E1000_PHY_DSP_FFE, - IGP01E1000_PHY_DSP_FFE_CM_CP); - if (ret_val) - return ret_val; - break; - } - - if (idle_errs) - ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; - } - } - } - } else { - if (hw->dsp_config_state == e1000_dsp_config_activated) { - /* Save off the current value of register 0x2F5B to be restored at - * the end of the routines. */ - ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); - - if (ret_val) - return ret_val; - - /* Disable the PHY transmitter */ - ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); - - if (ret_val) - return ret_val; - - msec_delay_irq(20); - - ret_val = e1000_write_phy_reg(hw, 0x0000, - IGP01E1000_IEEE_FORCE_GIGA); - if (ret_val) - return ret_val; - for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { - ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; - phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; - - ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); - if (ret_val) - return ret_val; - } - - ret_val = e1000_write_phy_reg(hw, 0x0000, - IGP01E1000_IEEE_RESTART_AUTONEG); - if (ret_val) - return ret_val; - - msec_delay_irq(20); - - /* Now enable the transmitter */ - ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); - - if (ret_val) - return ret_val; - - hw->dsp_config_state = e1000_dsp_config_enabled; - } - - if (hw->ffe_config_state == e1000_ffe_config_active) { - /* Save off the current value of register 0x2F5B to be restored at - * the end of the routines. */ - ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); - - if (ret_val) - return ret_val; - - /* Disable the PHY transmitter */ - ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); - - if (ret_val) - return ret_val; - - msec_delay_irq(20); - - ret_val = e1000_write_phy_reg(hw, 0x0000, - IGP01E1000_IEEE_FORCE_GIGA); - if (ret_val) - return ret_val; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, - IGP01E1000_PHY_DSP_FFE_DEFAULT); - if (ret_val) - return ret_val; - - ret_val = e1000_write_phy_reg(hw, 0x0000, - IGP01E1000_IEEE_RESTART_AUTONEG); - if (ret_val) - return ret_val; - - msec_delay_irq(20); - - /* Now enable the transmitter */ - ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); - - if (ret_val) - return ret_val; - - hw->ffe_config_state = e1000_ffe_config_enabled; - } - } - return E1000_SUCCESS; -} - -#ifndef FIFO_WORKAROUND -/*************************************************************************** - * - * Workaround for the 82547 long TTL on noisy 100HD hubs. - * - * This function, specific to 82547 hardware only, needs to be called every - * second. It checks if a parallel detect fault has occurred. If a fault - * occurred, disable/enable the DSP reset mechanism up to 5 times (once per - * second). If link is established, stop the workaround and ensure the DSP - * reset is enabled. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_PHY if fail to read/write the PHY - * E1000_SUCCESS in any other case - * - ****************************************************************************/ -int32_t -e1000_igp_ttl_workaround(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t phy_data = 0; - uint16_t dsp_value = DSP_RESET_ENABLE; - - /* The workaround needed only for B-0 silicon HW */ - if (((hw->mac_type != e1000_82541) && (hw->mac_type != e1000_82547)) || - (!hw->ttl_wa_activation)) { - return E1000_SUCCESS; - } - - /* Check for link first */ - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); - if (ret_val) - return ret_val; - - if (phy_data & MII_SR_LINK_STATUS) { - /* If link is established during the workaround, the DSP mechanism must - * be enabled. */ - if (hw->dsp_reset_counter) { - hw->dsp_reset_counter = 0; - dsp_value = DSP_RESET_ENABLE; - } else - return E1000_SUCCESS; - } else { - if (hw->dsp_reset_counter == 0) { - /* Workaround not activated, check if it needs activation */ - ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); - if (ret_val) - return ret_val; - /* Activate the workaround if there was a parallel detect fault */ - if (phy_data & NWAY_ER_PAR_DETECT_FAULT) - hw->dsp_reset_counter++; - else - return E1000_SUCCESS; - } - - if (hw->dsp_reset_counter) { - /* After 5 times, stop the workaround */ - if (hw->dsp_reset_counter > E1000_MAX_DSP_RESETS) { - hw->dsp_reset_counter = 0; - dsp_value = DSP_RESET_ENABLE; - } else { - dsp_value = (hw->dsp_reset_counter & 1) ? DSP_RESET_DISABLE : - DSP_RESET_ENABLE; - hw->dsp_reset_counter++; - } - } - } - - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value); - if (ret_val) - return ret_val; - - return E1000_SUCCESS; -} - -#endif /* FIFO_WORKAROUND */ -/***************************************************************************** - * Set PHY to class A mode - * Assumes the following operations will follow to enable the new class mode. - * 1. Do a PHY soft reset - * 2. Restart auto-negotiation or force link. - * - * hw - Struct containing variables accessed by shared code - ****************************************************************************/ -static int32_t -e1000_set_phy_mode(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t eeprom_data; - - DEBUGFUNC("e1000_set_phy_mode"); - - if ((hw->mac_type == e1000_82545_rev_3) && - (hw->media_type == e1000_media_type_copper)) { - ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); - if (ret_val) { - return ret_val; - } - - if ((eeprom_data != EEPROM_RESERVED_WORD) && - (eeprom_data & EEPROM_PHY_CLASS_A)) { - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); - if (ret_val) - return ret_val; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); - if (ret_val) - return ret_val; - - hw->phy_reset_disable = FALSE; - } - } - - return E1000_SUCCESS; -} - -/***************************************************************************** - * - * This function sets the lplu state according to the active flag. When - * activating lplu this function also disables smart speed and vise versa. - * lplu will not be activated unless the device autonegotiation advertisment - * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. - * hw: Struct containing variables accessed by shared code - * active - true to enable lplu false to disable lplu. - * - * returns: - E1000_ERR_PHY if fail to read/write the PHY - * E1000_SUCCESS at any other case. - * - ****************************************************************************/ - -STATIC int32_t -e1000_set_d3_lplu_state(struct e1000_hw *hw, - boolean_t active) -{ - uint32_t phy_ctrl = 0; - int32_t ret_val; - uint16_t phy_data; - DEBUGFUNC("e1000_set_d3_lplu_state"); - - if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 - && hw->phy_type != e1000_phy_igp_3) - return E1000_SUCCESS; - - /* During driver activity LPLU should not be used or it will attain link - * from the lowest speeds starting from 10Mbps. The capability is used for - * Dx transitions and states */ - if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); - if (ret_val) - return ret_val; - } else if (hw->mac_type == e1000_ich8lan) { - /* MAC writes into PHY register based on the state transition - * and start auto-negotiation. SW driver can overwrite the settings - * in CSR PHY power control E1000_PHY_CTRL register. */ - phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); - } else { - ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); - if (ret_val) - return ret_val; - } - - if (!active) { - if (hw->mac_type == e1000_82541_rev_2 || - hw->mac_type == e1000_82547_rev_2) { - phy_data &= ~IGP01E1000_GMII_FLEX_SPD; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); - if (ret_val) - return ret_val; - } else { - if (hw->mac_type == e1000_ich8lan) { - phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; - E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); - } else { - phy_data &= ~IGP02E1000_PM_D3_LPLU; - ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, - phy_data); - if (ret_val) - return ret_val; - } - } - - /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during - * Dx states where the power conservation is most important. During - * driver activity we should enable SmartSpeed, so performance is - * maintained. */ - if (hw->smart_speed == e1000_smart_speed_on) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - &phy_data); - if (ret_val) - return ret_val; - - phy_data |= IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - phy_data); - if (ret_val) - return ret_val; - } else if (hw->smart_speed == e1000_smart_speed_off) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - phy_data); - if (ret_val) - return ret_val; - } - - } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || - (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || - (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { - - if (hw->mac_type == e1000_82541_rev_2 || - hw->mac_type == e1000_82547_rev_2) { - phy_data |= IGP01E1000_GMII_FLEX_SPD; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); - if (ret_val) - return ret_val; - } else { - if (hw->mac_type == e1000_ich8lan) { - phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; - E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); - } else { - phy_data |= IGP02E1000_PM_D3_LPLU; - ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, - phy_data); - if (ret_val) - return ret_val; - } - } - - /* When LPLU is enabled we should disable SmartSpeed */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); - if (ret_val) - return ret_val; - - } - return E1000_SUCCESS; -} - -/***************************************************************************** - * - * This function sets the lplu d0 state according to the active flag. When - * activating lplu this function also disables smart speed and vise versa. - * lplu will not be activated unless the device autonegotiation advertisment - * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. - * hw: Struct containing variables accessed by shared code - * active - true to enable lplu false to disable lplu. - * - * returns: - E1000_ERR_PHY if fail to read/write the PHY - * E1000_SUCCESS at any other case. - * - ****************************************************************************/ - -STATIC int32_t -e1000_set_d0_lplu_state(struct e1000_hw *hw, - boolean_t active) -{ - uint32_t phy_ctrl = 0; - int32_t ret_val; - uint16_t phy_data; - DEBUGFUNC("e1000_set_d0_lplu_state"); - - if (hw->mac_type <= e1000_82547_rev_2) - return E1000_SUCCESS; - - if (hw->mac_type == e1000_ich8lan) { - phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); - } else { - ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); - if (ret_val) - return ret_val; - } - - if (!active) { - if (hw->mac_type == e1000_ich8lan) { - phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; - E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); - } else { - phy_data &= ~IGP02E1000_PM_D0_LPLU; - ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); - if (ret_val) - return ret_val; - } - - /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during - * Dx states where the power conservation is most important. During - * driver activity we should enable SmartSpeed, so performance is - * maintained. */ - if (hw->smart_speed == e1000_smart_speed_on) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - &phy_data); - if (ret_val) - return ret_val; - - phy_data |= IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - phy_data); - if (ret_val) - return ret_val; - } else if (hw->smart_speed == e1000_smart_speed_off) { - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, - phy_data); - if (ret_val) - return ret_val; - } - - - } else { - - if (hw->mac_type == e1000_ich8lan) { - phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; - E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); - } else { - phy_data |= IGP02E1000_PM_D0_LPLU; - ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); - if (ret_val) - return ret_val; - } - - /* When LPLU is enabled we should disable SmartSpeed */ - ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); - if (ret_val) - return ret_val; - - } - return E1000_SUCCESS; -} - -/****************************************************************************** - * Change VCO speed register to improve Bit Error Rate performance of SERDES. - * - * hw - Struct containing variables accessed by shared code - *****************************************************************************/ -static int32_t -e1000_set_vco_speed(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t default_page = 0; - uint16_t phy_data; - - DEBUGFUNC("e1000_set_vco_speed"); - - switch (hw->mac_type) { - case e1000_82545_rev_3: - case e1000_82546_rev_3: - break; - default: - return E1000_SUCCESS; - } - - /* Set PHY register 30, page 5, bit 8 to 0 */ - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); - if (ret_val) - return ret_val; - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); - if (ret_val) - return ret_val; - - phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); - if (ret_val) - return ret_val; - - /* Set PHY register 30, page 4, bit 11 to 1 */ - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); - if (ret_val) - return ret_val; - - phy_data |= M88E1000_PHY_VCO_REG_BIT11; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); - if (ret_val) - return ret_val; - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); - if (ret_val) - return ret_val; - - return E1000_SUCCESS; -} - - -/***************************************************************************** - * This function reads the cookie from ARC ram. - * - * returns: - E1000_SUCCESS . - ****************************************************************************/ -STATIC int32_t -e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) -{ - uint8_t i; - uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; - uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; - - length = (length >> 2); - offset = (offset >> 2); - - for (i = 0; i < length; i++) { - *((uint32_t *) buffer + i) = - E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); - } - return E1000_SUCCESS; -} - - -/***************************************************************************** - * This function checks whether the HOST IF is enabled for command operaton - * and also checks whether the previous command is completed. - * It busy waits in case of previous command is not completed. - * - * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or - * timeout - * - E1000_SUCCESS for success. - ****************************************************************************/ -STATIC int32_t -e1000_mng_enable_host_if(struct e1000_hw * hw) -{ - uint32_t hicr; - uint8_t i; - - /* Check that the host interface is enabled. */ - hicr = E1000_READ_REG(hw, HICR); - if ((hicr & E1000_HICR_EN) == 0) { - DEBUGOUT("E1000_HOST_EN bit disabled.\n"); - return -E1000_ERR_HOST_INTERFACE_COMMAND; - } - /* check the previous command is completed */ - for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { - hicr = E1000_READ_REG(hw, HICR); - if (!(hicr & E1000_HICR_C)) - break; - msec_delay_irq(1); - } - - if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { - DEBUGOUT("Previous command timeout failed .\n"); - return -E1000_ERR_HOST_INTERFACE_COMMAND; - } - return E1000_SUCCESS; -} - -/***************************************************************************** - * This function writes the buffer content at the offset given on the host if. - * It also does alignment considerations to do the writes in most efficient way. - * Also fills up the sum of the buffer in *buffer parameter. - * - * returns - E1000_SUCCESS for success. - ****************************************************************************/ -STATIC int32_t -e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, - uint16_t length, uint16_t offset, uint8_t *sum) -{ - uint8_t *tmp; - uint8_t *bufptr = buffer; - uint32_t data = 0; - uint16_t remaining, i, j, prev_bytes; - - /* sum = only sum of the data and it is not checksum */ - - if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { - return -E1000_ERR_PARAM; - } - - tmp = (uint8_t *)&data; - prev_bytes = offset & 0x3; - offset &= 0xFFFC; - offset >>= 2; - - if (prev_bytes) { - data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); - for (j = prev_bytes; j < sizeof(uint32_t); j++) { - *(tmp + j) = *bufptr++; - *sum += *(tmp + j); - } - E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); - length -= j - prev_bytes; - offset++; - } - - remaining = length & 0x3; - length -= remaining; - - /* Calculate length in DWORDs */ - length >>= 2; - - /* The device driver writes the relevant command block into the - * ram area. */ - for (i = 0; i < length; i++) { - for (j = 0; j < sizeof(uint32_t); j++) { - *(tmp + j) = *bufptr++; - *sum += *(tmp + j); - } - - E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); - } - if (remaining) { - for (j = 0; j < sizeof(uint32_t); j++) { - if (j < remaining) - *(tmp + j) = *bufptr++; - else - *(tmp + j) = 0; - - *sum += *(tmp + j); - } - E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); - } - - return E1000_SUCCESS; -} - - -/***************************************************************************** - * This function writes the command header after does the checksum calculation. - * - * returns - E1000_SUCCESS for success. - ****************************************************************************/ -STATIC int32_t -e1000_mng_write_cmd_header(struct e1000_hw * hw, - struct e1000_host_mng_command_header * hdr) -{ - uint16_t i; - uint8_t sum; - uint8_t *buffer; - - /* Write the whole command header structure which includes sum of - * the buffer */ - - uint16_t length = sizeof(struct e1000_host_mng_command_header); - - sum = hdr->checksum; - hdr->checksum = 0; - - buffer = (uint8_t *) hdr; - i = length; - while (i--) - sum += buffer[i]; - - hdr->checksum = 0 - sum; - - length >>= 2; - /* The device driver writes the relevant command block into the ram area. */ - for (i = 0; i < length; i++) { - E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); - E1000_WRITE_FLUSH(hw); - } - - return E1000_SUCCESS; -} - - -/***************************************************************************** - * This function indicates to ARC that a new command is pending which completes - * one write operation by the driver. - * - * returns - E1000_SUCCESS for success. - ****************************************************************************/ -STATIC int32_t -e1000_mng_write_commit(struct e1000_hw * hw) -{ - uint32_t hicr; - - hicr = E1000_READ_REG(hw, HICR); - /* Setting this bit tells the ARC that a new command is pending. */ - E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); - - return E1000_SUCCESS; -} - - -/***************************************************************************** - * This function checks the mode of the firmware. - * - * returns - TRUE when the mode is IAMT or FALSE. - ****************************************************************************/ -boolean_t -e1000_check_mng_mode(struct e1000_hw *hw) -{ - uint32_t fwsm; - - fwsm = E1000_READ_REG(hw, FWSM); - - if (hw->mac_type == e1000_ich8lan) { - if ((fwsm & E1000_FWSM_MODE_MASK) == - (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; - } else if ((fwsm & E1000_FWSM_MODE_MASK) == - (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; - - return FALSE; -} - - -/***************************************************************************** - * This function writes the dhcp info . - ****************************************************************************/ -int32_t -e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, - uint16_t length) -{ - int32_t ret_val; - struct e1000_host_mng_command_header hdr; - - hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; - hdr.command_length = length; - hdr.reserved1 = 0; - hdr.reserved2 = 0; - hdr.checksum = 0; - - ret_val = e1000_mng_enable_host_if(hw); - if (ret_val == E1000_SUCCESS) { - ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), - &(hdr.checksum)); - if (ret_val == E1000_SUCCESS) { - ret_val = e1000_mng_write_cmd_header(hw, &hdr); - if (ret_val == E1000_SUCCESS) - ret_val = e1000_mng_write_commit(hw); - } - } - return ret_val; -} - - -/***************************************************************************** - * This function calculates the checksum. - * - * returns - checksum of buffer contents. - ****************************************************************************/ -STATIC uint8_t -e1000_calculate_mng_checksum(char *buffer, uint32_t length) -{ - uint8_t sum = 0; - uint32_t i; - - if (!buffer) - return 0; - - for (i=0; i < length; i++) - sum += buffer[i]; - - return (uint8_t) (0 - sum); -} - -/***************************************************************************** - * This function checks whether tx pkt filtering needs to be enabled or not. - * - * returns - TRUE for packet filtering or FALSE. - ****************************************************************************/ -boolean_t -e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) -{ - /* called in init as well as watchdog timer functions */ - - int32_t ret_val, checksum; - boolean_t tx_filter = FALSE; - struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); - uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); - - if (e1000_check_mng_mode(hw)) { - ret_val = e1000_mng_enable_host_if(hw); - if (ret_val == E1000_SUCCESS) { - ret_val = e1000_host_if_read_cookie(hw, buffer); - if (ret_val == E1000_SUCCESS) { - checksum = hdr->checksum; - hdr->checksum = 0; - if ((hdr->signature == E1000_IAMT_SIGNATURE) && - checksum == e1000_calculate_mng_checksum((char *)buffer, - E1000_MNG_DHCP_COOKIE_LENGTH)) { - if (hdr->status & - E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) - tx_filter = TRUE; - } else - tx_filter = TRUE; - } else - tx_filter = TRUE; - } - } - - hw->tx_pkt_filtering = tx_filter; - return tx_filter; -} - -/****************************************************************************** - * Verifies the hardware needs to allow ARPs to be processed by the host - * - * hw - Struct containing variables accessed by shared code - * - * returns: - TRUE/FALSE - * - *****************************************************************************/ -uint32_t -e1000_enable_mng_pass_thru(struct e1000_hw *hw) -{ - uint32_t manc; - uint32_t fwsm, factps; - - if (hw->asf_firmware_present) { - manc = E1000_READ_REG(hw, MANC); - - if (!(manc & E1000_MANC_RCV_TCO_EN) || - !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) - return FALSE; - if (e1000_arc_subsystem_valid(hw) == TRUE) { - fwsm = E1000_READ_REG(hw, FWSM); - factps = E1000_READ_REG(hw, FACTPS); - - if (((fwsm & E1000_FWSM_MODE_MASK) == - (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && - (factps & E1000_FACTPS_MNGCG)) - return TRUE; - } else - if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) - return TRUE; - } - return FALSE; -} - -static int32_t -e1000_polarity_reversal_workaround(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t mii_status_reg; - uint16_t i; - - /* Polarity reversal workaround for forced 10F/10H links. */ - - /* Disable the transmitter on the PHY */ - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); - if (ret_val) - return ret_val; - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); - if (ret_val) - return ret_val; - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); - if (ret_val) - return ret_val; - - /* This loop will early-out if the NO link condition has been met. */ - for (i = PHY_FORCE_TIME; i > 0; i--) { - /* Read the MII Status Register and wait for Link Status bit - * to be clear. - */ - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; - msec_delay_irq(100); - } - - /* Recommended delay time after link has been lost */ - msec_delay_irq(1000); - - /* Now we will re-enable th transmitter on the PHY */ - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); - if (ret_val) - return ret_val; - msec_delay_irq(50); - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); - if (ret_val) - return ret_val; - msec_delay_irq(50); - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); - if (ret_val) - return ret_val; - msec_delay_irq(50); - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); - if (ret_val) - return ret_val; - - ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); - if (ret_val) - return ret_val; - - /* This loop will early-out if the link condition has been met. */ - for (i = PHY_FORCE_TIME; i > 0; i--) { - /* Read the MII Status Register and wait for Link Status bit - * to be set. - */ - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); - if (ret_val) - return ret_val; - - if (mii_status_reg & MII_SR_LINK_STATUS) break; - msec_delay_irq(100); - } - return E1000_SUCCESS; -} - -/*************************************************************************** - * - * Disables PCI-Express master access. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - none. - * - ***************************************************************************/ -STATIC void -e1000_set_pci_express_master_disable(struct e1000_hw *hw) -{ - uint32_t ctrl; - - DEBUGFUNC("e1000_set_pci_express_master_disable"); - - if (hw->bus_type != e1000_bus_type_pci_express) - return; - - ctrl = E1000_READ_REG(hw, CTRL); - ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; - E1000_WRITE_REG(hw, CTRL, ctrl); -} - -/******************************************************************************* - * - * Disables PCI-Express master access and verifies there are no pending requests - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't - * caused the master requests to be disabled. - * E1000_SUCCESS master requests disabled. - * - ******************************************************************************/ -int32_t -e1000_disable_pciex_master(struct e1000_hw *hw) -{ - int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ - - DEBUGFUNC("e1000_disable_pciex_master"); - - if (hw->bus_type != e1000_bus_type_pci_express) - return E1000_SUCCESS; - - e1000_set_pci_express_master_disable(hw); - - while (timeout) { - if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) - break; - else - usec_delay(100); - timeout--; - } - - if (!timeout) { - DEBUGOUT("Master requests are pending.\n"); - return -E1000_ERR_MASTER_REQUESTS_PENDING; - } - - return E1000_SUCCESS; -} - -/******************************************************************************* - * - * Check for EEPROM Auto Read bit done. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_RESET if fail to reset MAC - * E1000_SUCCESS at any other case. - * - ******************************************************************************/ -STATIC int32_t -e1000_get_auto_rd_done(struct e1000_hw *hw) -{ - int32_t timeout = AUTO_READ_DONE_TIMEOUT; - - DEBUGFUNC("e1000_get_auto_rd_done"); - - switch (hw->mac_type) { - default: - msec_delay(5); - break; - case e1000_82571: - case e1000_82572: - case e1000_82573: - case e1000_80003es2lan: - case e1000_ich8lan: - while (timeout) { - if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) - break; - else msec_delay(1); - timeout--; - } - - if (!timeout) { - DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); - return -E1000_ERR_RESET; - } - break; - } - - /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. - * Need to wait for PHY configuration completion before accessing NVM - * and PHY. */ - if (hw->mac_type == e1000_82573) - msec_delay(25); - - return E1000_SUCCESS; -} - -/*************************************************************************** - * Checks if the PHY configuration is done - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_RESET if fail to reset MAC - * E1000_SUCCESS at any other case. - * - ***************************************************************************/ -STATIC int32_t -e1000_get_phy_cfg_done(struct e1000_hw *hw) -{ - int32_t timeout = PHY_CFG_TIMEOUT; - uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; - - DEBUGFUNC("e1000_get_phy_cfg_done"); - - switch (hw->mac_type) { - default: - msec_delay_irq(10); - break; - case e1000_80003es2lan: - /* Separate *_CFG_DONE_* bit for each port */ - if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) - cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; - /* Fall Through */ - case e1000_82571: - case e1000_82572: - while (timeout) { - if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) - break; - else - msec_delay(1); - timeout--; - } - if (!timeout) { - DEBUGOUT("MNG configuration cycle has not completed.\n"); - } - break; - } - - return E1000_SUCCESS; -} - -/*************************************************************************** - * - * Using the combination of SMBI and SWESMBI semaphore bits when resetting - * adapter or Eeprom access. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_EEPROM if fail to access EEPROM. - * E1000_SUCCESS at any other case. - * - ***************************************************************************/ -STATIC int32_t -e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) -{ - int32_t timeout; - uint32_t swsm; - - DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); - - if (!hw->eeprom_semaphore_present) - return E1000_SUCCESS; - - if (hw->mac_type == e1000_80003es2lan) { - /* Get the SW semaphore. */ - if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) - return -E1000_ERR_EEPROM; - } - - /* Get the FW semaphore. */ - timeout = hw->eeprom.word_size + 1; - while (timeout) { - swsm = E1000_READ_REG(hw, SWSM); - swsm |= E1000_SWSM_SWESMBI; - E1000_WRITE_REG(hw, SWSM, swsm); - /* if we managed to set the bit we got the semaphore. */ - swsm = E1000_READ_REG(hw, SWSM); - if (swsm & E1000_SWSM_SWESMBI) - break; - - usec_delay(50); - timeout--; - } - - if (!timeout) { - /* Release semaphores */ - e1000_put_hw_eeprom_semaphore(hw); - DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); - return -E1000_ERR_EEPROM; - } - - return E1000_SUCCESS; -} - -/*************************************************************************** - * This function clears HW semaphore bits. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - None. - * - ***************************************************************************/ -STATIC void -e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) -{ - uint32_t swsm; - - DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); - - if (!hw->eeprom_semaphore_present) - return; - - swsm = E1000_READ_REG(hw, SWSM); - if (hw->mac_type == e1000_80003es2lan) { - /* Release both semaphores. */ - swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); - } else - swsm &= ~(E1000_SWSM_SWESMBI); - E1000_WRITE_REG(hw, SWSM, swsm); -} - -/*************************************************************************** - * - * Obtaining software semaphore bit (SMBI) before resetting PHY. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - E1000_ERR_RESET if fail to obtain semaphore. - * E1000_SUCCESS at any other case. - * - ***************************************************************************/ -STATIC int32_t -e1000_get_software_semaphore(struct e1000_hw *hw) -{ - int32_t timeout = hw->eeprom.word_size + 1; - uint32_t swsm; - - DEBUGFUNC("e1000_get_software_semaphore"); - - if (hw->mac_type != e1000_80003es2lan) { - return E1000_SUCCESS; - } - - while (timeout) { - swsm = E1000_READ_REG(hw, SWSM); - /* If SMBI bit cleared, it is now set and we hold the semaphore */ - if (!(swsm & E1000_SWSM_SMBI)) - break; - msec_delay_irq(1); - timeout--; - } - - if (!timeout) { - DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); - return -E1000_ERR_RESET; - } - - return E1000_SUCCESS; -} - -/*************************************************************************** - * - * Release semaphore bit (SMBI). - * - * hw: Struct containing variables accessed by shared code - * - ***************************************************************************/ -STATIC void -e1000_release_software_semaphore(struct e1000_hw *hw) -{ - uint32_t swsm; - - DEBUGFUNC("e1000_release_software_semaphore"); - - if (hw->mac_type != e1000_80003es2lan) { - return; - } - - swsm = E1000_READ_REG(hw, SWSM); - /* Release the SW semaphores.*/ - swsm &= ~E1000_SWSM_SMBI; - E1000_WRITE_REG(hw, SWSM, swsm); -} - -/****************************************************************************** - * Checks if PHY reset is blocked due to SOL/IDER session, for example. - * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to - * the caller to figure out how to deal with it. - * - * hw - Struct containing variables accessed by shared code - * - * returns: - E1000_BLK_PHY_RESET - * E1000_SUCCESS - * - *****************************************************************************/ -int32_t -e1000_check_phy_reset_block(struct e1000_hw *hw) -{ - uint32_t manc = 0; - uint32_t fwsm = 0; - - if (hw->mac_type == e1000_ich8lan) { - fwsm = E1000_READ_REG(hw, FWSM); - return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS - : E1000_BLK_PHY_RESET; - } - - if (hw->mac_type > e1000_82547_rev_2) - manc = E1000_READ_REG(hw, MANC); - return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? - E1000_BLK_PHY_RESET : E1000_SUCCESS; -} - -STATIC uint8_t -e1000_arc_subsystem_valid(struct e1000_hw *hw) -{ - uint32_t fwsm; - - /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC - * may not be provided a DMA clock when no manageability features are - * enabled. We do not want to perform any reads/writes to these registers - * if this is the case. We read FWSM to determine the manageability mode. - */ - switch (hw->mac_type) { - case e1000_82571: - case e1000_82572: - case e1000_82573: - case e1000_80003es2lan: - fwsm = E1000_READ_REG(hw, FWSM); - if ((fwsm & E1000_FWSM_MODE_MASK) != 0) - return TRUE; - break; - case e1000_ich8lan: - return TRUE; - default: - break; - } - return FALSE; -} - - -/****************************************************************************** - * Configure PCI-Ex no-snoop - * - * hw - Struct containing variables accessed by shared code. - * no_snoop - Bitmap of no-snoop events. - * - * returns: E1000_SUCCESS - * - *****************************************************************************/ -STATIC int32_t -e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) -{ - uint32_t gcr_reg = 0; - - DEBUGFUNC("e1000_set_pci_ex_no_snoop"); - - if (hw->bus_type == e1000_bus_type_unknown) - e1000_get_bus_info(hw); - - if (hw->bus_type != e1000_bus_type_pci_express) - return E1000_SUCCESS; - - if (no_snoop) { - gcr_reg = E1000_READ_REG(hw, GCR); - gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); - gcr_reg |= no_snoop; - E1000_WRITE_REG(hw, GCR, gcr_reg); - } - if (hw->mac_type == e1000_ich8lan) { - uint32_t ctrl_ext; - - E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); - - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_RO_DIS; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - } - - return E1000_SUCCESS; -} - -/*************************************************************************** - * - * Get software semaphore FLAG bit (SWFLAG). - * SWFLAG is used to synchronize the access to all shared resource between - * SW, FW and HW. - * - * hw: Struct containing variables accessed by shared code - * - ***************************************************************************/ -STATIC int32_t -e1000_get_software_flag(struct e1000_hw *hw) -{ - int32_t timeout = PHY_CFG_TIMEOUT; - uint32_t extcnf_ctrl; - - DEBUGFUNC("e1000_get_software_flag"); - - if (hw->mac_type == e1000_ich8lan) { - while (timeout) { - extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); - extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; - E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); - - extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); - if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) - break; - msec_delay_irq(1); - timeout--; - } - - if (!timeout) { - DEBUGOUT("FW or HW locks the resource too long.\n"); - return -E1000_ERR_CONFIG; - } - } - - return E1000_SUCCESS; -} - -/*************************************************************************** - * - * Release software semaphore FLAG bit (SWFLAG). - * SWFLAG is used to synchronize the access to all shared resource between - * SW, FW and HW. - * - * hw: Struct containing variables accessed by shared code - * - ***************************************************************************/ -STATIC void -e1000_release_software_flag(struct e1000_hw *hw) -{ - uint32_t extcnf_ctrl; - - DEBUGFUNC("e1000_release_software_flag"); - - if (hw->mac_type == e1000_ich8lan) { - extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); - extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; - E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); - } - - return; -} - - -/****************************************************************************** - * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access - * register. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM - * words - number of words to read - *****************************************************************************/ -STATIC int32_t -e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, - uint16_t *data) -{ - int32_t error = E1000_SUCCESS; - uint32_t flash_bank = 0; - uint32_t act_offset = 0; - uint32_t bank_offset = 0; - uint16_t word = 0; - uint16_t i = 0; - - /* We need to know which is the valid flash bank. In the event - * that we didn't allocate eeprom_shadow_ram, we may not be - * managing flash_bank. So it cannot be trusted and needs - * to be updated with each read. - */ - /* Value of bit 22 corresponds to the flash bank we're on. */ - flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; - - /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ - bank_offset = flash_bank * (hw->flash_bank_size * 2); - - error = e1000_get_software_flag(hw); - if (error != E1000_SUCCESS) - return error; - - for (i = 0; i < words; i++) { - if (hw->eeprom_shadow_ram != NULL && - hw->eeprom_shadow_ram[offset+i].modified == TRUE) { - data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; - } else { - /* The NVM part needs a byte offset, hence * 2 */ - act_offset = bank_offset + ((offset + i) * 2); - error = e1000_read_ich8_word(hw, act_offset, &word); - if (error != E1000_SUCCESS) - break; - data[i] = word; - } - } - - e1000_release_software_flag(hw); - - return error; -} - -/****************************************************************************** - * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access - * register. Actually, writes are written to the shadow ram cache in the hw - * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to - * the NVM, which occurs when the NVM checksum is updated. - * - * hw - Struct containing variables accessed by shared code - * offset - offset of word in the EEPROM to write - * words - number of words to write - * data - words to write to the EEPROM - *****************************************************************************/ -STATIC int32_t -e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, - uint16_t *data) -{ - uint32_t i = 0; - int32_t error = E1000_SUCCESS; - - error = e1000_get_software_flag(hw); - if (error != E1000_SUCCESS) - return error; - - /* A driver can write to the NVM only if it has eeprom_shadow_ram - * allocated. Subsequent reads to the modified words are read from - * this cached structure as well. Writes will only go into this - * cached structure unless it's followed by a call to - * e1000_update_eeprom_checksum() where it will commit the changes - * and clear the "modified" field. - */ - if (hw->eeprom_shadow_ram != NULL) { - for (i = 0; i < words; i++) { - if ((offset + i) < E1000_SHADOW_RAM_WORDS) { - hw->eeprom_shadow_ram[offset+i].modified = TRUE; - hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; - } else { - error = -E1000_ERR_EEPROM; - break; - } - } - } else { - /* Drivers have the option to not allocate eeprom_shadow_ram as long - * as they don't perform any NVM writes. An attempt in doing so - * will result in this error. - */ - error = -E1000_ERR_EEPROM; - } - - e1000_release_software_flag(hw); - - return error; -} - -/****************************************************************************** - * This function does initial flash setup so that a new read/write/erase cycle - * can be started. - * - * hw - The pointer to the hw structure - ****************************************************************************/ -STATIC int32_t -e1000_ich8_cycle_init(struct e1000_hw *hw) -{ - union ich8_hws_flash_status hsfsts; - int32_t error = E1000_ERR_EEPROM; - int32_t i = 0; - - DEBUGFUNC("e1000_ich8_cycle_init"); - - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - - /* May be check the Flash Des Valid bit in Hw status */ - if (hsfsts.hsf_status.fldesvalid == 0) { - DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); - return error; - } - - /* Clear FCERR in Hw status by writing 1 */ - /* Clear DAEL in Hw status by writing a 1 */ - hsfsts.hsf_status.flcerr = 1; - hsfsts.hsf_status.dael = 1; - - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); - - /* Either we should have a hardware SPI cycle in progress bit to check - * against, in order to start a new cycle or FDONE bit should be changed - * in the hardware so that it is 1 after harware reset, which can then be - * used as an indication whether a cycle is in progress or has been - * completed .. we should also have some software semaphore mechanism to - * guard FDONE or the cycle in progress bit so that two threads access to - * those bits can be sequentiallized or a way so that 2 threads dont - * start the cycle at the same time */ - - if (hsfsts.hsf_status.flcinprog == 0) { - /* There is no cycle running at present, so we can start a cycle */ - /* Begin by setting Flash Cycle Done. */ - hsfsts.hsf_status.flcdone = 1; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); - error = E1000_SUCCESS; - } else { - /* otherwise poll for sometime so the current cycle has a chance - * to end before giving up. */ - for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcinprog == 0) { - error = E1000_SUCCESS; - break; - } - usec_delay(1); - } - if (error == E1000_SUCCESS) { - /* Successful in waiting for previous cycle to timeout, - * now set the Flash Cycle Done. */ - hsfsts.hsf_status.flcdone = 1; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); - } else { - DEBUGOUT("Flash controller busy, cannot get access"); - } - } - return error; -} - -/****************************************************************************** - * This function starts a flash cycle and waits for its completion - * - * hw - The pointer to the hw structure - ****************************************************************************/ -STATIC int32_t -e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) -{ - union ich8_hws_flash_ctrl hsflctl; - union ich8_hws_flash_status hsfsts; - int32_t error = E1000_ERR_EEPROM; - uint32_t i = 0; - - /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ - hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); - hsflctl.hsf_ctrl.flcgo = 1; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - - /* wait till FDONE bit is set to 1 */ - do { - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcdone == 1) - break; - usec_delay(1); - i++; - } while (i < timeout); - if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { - error = E1000_SUCCESS; - } - return error; -} - -/****************************************************************************** - * Reads a byte or word from the NVM using the ICH8 flash access registers. - * - * hw - The pointer to the hw structure - * index - The index of the byte or word to read. - * size - Size of data to read, 1=byte 2=word - * data - Pointer to the word to store the value read. - *****************************************************************************/ -STATIC int32_t -e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, - uint32_t size, uint16_t* data) -{ - union ich8_hws_flash_status hsfsts; - union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - uint32_t flash_data = 0; - int32_t error = -E1000_ERR_EEPROM; - int32_t count = 0; - - DEBUGFUNC("e1000_read_ich8_data"); - - if (size < 1 || size > 2 || data == 0x0 || - index > ICH_FLASH_LINEAR_ADDR_MASK) - return error; - - flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + - hw->flash_base_addr; - - do { - usec_delay(1); - /* Steps */ - error = e1000_ich8_cycle_init(hw); - if (error != E1000_SUCCESS) - break; - - hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); - /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ - hsflctl.hsf_ctrl.fldbcount = size - 1; - hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - - /* Write the last 24 bits of index into Flash Linear address field in - * Flash Address */ - /* TODO: TBD maybe check the index against the size of flash */ - - E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); - - error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); - - /* Check if FCERR is set to 1, if set to 1, clear it and try the whole - * sequence a few more times, else read in (shift in) the Flash Data0, - * the order is least significant byte first msb to lsb */ - if (error == E1000_SUCCESS) { - flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); - if (size == 1) { - *data = (uint8_t)(flash_data & 0x000000FF); - } else if (size == 2) { - *data = (uint16_t)(flash_data & 0x0000FFFF); - } - break; - } else { - /* If we've gotten here, then things are probably completely hosed, - * but if the error condition is detected, it won't hurt to give - * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. - */ - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) { - /* Repeat for some time before giving up. */ - continue; - } else if (hsfsts.hsf_status.flcdone == 0) { - DEBUGOUT("Timeout error - flash cycle did not complete."); - break; - } - } - } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); - - return error; -} - -/****************************************************************************** - * Writes One /two bytes to the NVM using the ICH8 flash access registers. - * - * hw - The pointer to the hw structure - * index - The index of the byte/word to read. - * size - Size of data to read, 1=byte 2=word - * data - The byte(s) to write to the NVM. - *****************************************************************************/ -STATIC int32_t -e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, - uint16_t data) -{ - union ich8_hws_flash_status hsfsts; - union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - uint32_t flash_data = 0; - int32_t error = -E1000_ERR_EEPROM; - int32_t count = 0; - - DEBUGFUNC("e1000_write_ich8_data"); - - if (size < 1 || size > 2 || data > size * 0xff || - index > ICH_FLASH_LINEAR_ADDR_MASK) - return error; - - flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + - hw->flash_base_addr; - - do { - usec_delay(1); - /* Steps */ - error = e1000_ich8_cycle_init(hw); - if (error != E1000_SUCCESS) - break; - - hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); - /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ - hsflctl.hsf_ctrl.fldbcount = size -1; - hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - - /* Write the last 24 bits of index into Flash Linear address field in - * Flash Address */ - E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); - - if (size == 1) - flash_data = (uint32_t)data & 0x00FF; - else - flash_data = (uint32_t)data; - - E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); - - /* check if FCERR is set to 1 , if set to 1, clear it and try the whole - * sequence a few more times else done */ - error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); - if (error == E1000_SUCCESS) { - break; - } else { - /* If we're here, then things are most likely completely hosed, - * but if the error condition is detected, it won't hurt to give - * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. - */ - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) { - /* Repeat for some time before giving up. */ - continue; - } else if (hsfsts.hsf_status.flcdone == 0) { - DEBUGOUT("Timeout error - flash cycle did not complete."); - break; - } - } - } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); - - return error; -} - -/****************************************************************************** - * Reads a single byte from the NVM using the ICH8 flash access registers. - * - * hw - pointer to e1000_hw structure - * index - The index of the byte to read. - * data - Pointer to a byte to store the value read. - *****************************************************************************/ -STATIC int32_t -e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) -{ - int32_t status = E1000_SUCCESS; - uint16_t word = 0; - - status = e1000_read_ich8_data(hw, index, 1, &word); - if (status == E1000_SUCCESS) { - *data = (uint8_t)word; - } - - return status; -} - -/****************************************************************************** - * Writes a single byte to the NVM using the ICH8 flash access registers. - * Performs verification by reading back the value and then going through - * a retry algorithm before giving up. - * - * hw - pointer to e1000_hw structure - * index - The index of the byte to write. - * byte - The byte to write to the NVM. - *****************************************************************************/ -STATIC int32_t -e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) -{ - int32_t error = E1000_SUCCESS; - int32_t program_retries = 0; - - DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); - - error = e1000_write_ich8_byte(hw, index, byte); - - if (error != E1000_SUCCESS) { - for (program_retries = 0; program_retries < 100; program_retries++) { - DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); - error = e1000_write_ich8_byte(hw, index, byte); - usec_delay(100); - if (error == E1000_SUCCESS) - break; - } - } - - if (program_retries == 100) - error = E1000_ERR_EEPROM; - - return error; -} - -/****************************************************************************** - * Writes a single byte to the NVM using the ICH8 flash access registers. - * - * hw - pointer to e1000_hw structure - * index - The index of the byte to read. - * data - The byte to write to the NVM. - *****************************************************************************/ -STATIC int32_t -e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) -{ - int32_t status = E1000_SUCCESS; - uint16_t word = (uint16_t)data; - - status = e1000_write_ich8_data(hw, index, 1, word); - - return status; -} - -/****************************************************************************** - * Reads a word from the NVM using the ICH8 flash access registers. - * - * hw - pointer to e1000_hw structure - * index - The starting byte index of the word to read. - * data - Pointer to a word to store the value read. - *****************************************************************************/ -STATIC int32_t -e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) -{ - int32_t status = E1000_SUCCESS; - status = e1000_read_ich8_data(hw, index, 2, data); - return status; -} - - -/****************************************************************************** - * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 - * based. - * - * hw - pointer to e1000_hw structure - * bank - 0 for first bank, 1 for second bank - * - * Note that this function may actually erase as much as 8 or 64 KBytes. The - * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the - * bank size may be 4, 8 or 64 KBytes - *****************************************************************************/ -int32_t -e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) -{ - union ich8_hws_flash_status hsfsts; - union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - int32_t count = 0; - int32_t error = E1000_ERR_EEPROM; - int32_t iteration; - int32_t sub_sector_size = 0; - int32_t bank_size; - int32_t j = 0; - int32_t error_flag = 0; - - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - - /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ - /* 00: The Hw sector is 256 bytes, hence we need to erase 16 - * consecutive sectors. The start index for the nth Hw sector can be - * calculated as bank * 4096 + n * 256 - * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. - * The start index for the nth Hw sector can be calculated - * as bank * 4096 - * 10: The HW sector is 8K bytes - * 11: The Hw sector size is 64K bytes */ - if (hsfsts.hsf_status.berasesz == 0x0) { - /* Hw sector size 256 */ - sub_sector_size = ICH_FLASH_SEG_SIZE_256; - bank_size = ICH_FLASH_SECTOR_SIZE; - iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; - } else if (hsfsts.hsf_status.berasesz == 0x1) { - bank_size = ICH_FLASH_SEG_SIZE_4K; - iteration = 1; - } else if (hsfsts.hsf_status.berasesz == 0x3) { - bank_size = ICH_FLASH_SEG_SIZE_64K; - iteration = 1; - } else { - return error; - } - - for (j = 0; j < iteration ; j++) { - do { - count++; - /* Steps */ - error = e1000_ich8_cycle_init(hw); - if (error != E1000_SUCCESS) { - error_flag = 1; - break; - } - - /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash - * Control */ - hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); - hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; - E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - - /* Write the last 24 bits of an index within the block into Flash - * Linear address field in Flash Address. This probably needs to - * be calculated here based off the on-chip erase sector size and - * the software bank size (4, 8 or 64 KBytes) */ - flash_linear_address = bank * bank_size + j * sub_sector_size; - flash_linear_address += hw->flash_base_addr; - flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; - - E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); - - error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); - /* Check if FCERR is set to 1. If 1, clear it and try the whole - * sequence a few more times else Done */ - if (error == E1000_SUCCESS) { - break; - } else { - hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) { - /* repeat for some time before giving up */ - continue; - } else if (hsfsts.hsf_status.flcdone == 0) { - error_flag = 1; - break; - } - } - } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); - if (error_flag == 1) - break; - } - if (error_flag != 1) - error = E1000_SUCCESS; - return error; -} - - -STATIC int32_t -e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, - uint32_t cnf_base_addr, uint32_t cnf_size) -{ - uint32_t ret_val = E1000_SUCCESS; - uint16_t word_addr, reg_data, reg_addr; - uint16_t i; - - /* cnf_base_addr is in DWORD */ - word_addr = (uint16_t)(cnf_base_addr << 1); - - /* cnf_size is returned in size of dwords */ - for (i = 0; i < cnf_size; i++) { - ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); - if (ret_val) - return ret_val; - - ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); - if (ret_val) - return ret_val; - - ret_val = e1000_get_software_flag(hw); - if (ret_val != E1000_SUCCESS) - return ret_val; - - ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); - - e1000_release_software_flag(hw); - } - - return ret_val; -} - - -/****************************************************************************** - * This function initializes the PHY from the NVM on ICH8 platforms. This - * is needed due to an issue where the NVM configuration is not properly - * autoloaded after power transitions. Therefore, after each PHY reset, we - * will load the configuration data out of the NVM manually. - * - * hw: Struct containing variables accessed by shared code - *****************************************************************************/ -STATIC int32_t -e1000_init_lcd_from_nvm(struct e1000_hw *hw) -{ - uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; - - if (hw->phy_type != e1000_phy_igp_3) - return E1000_SUCCESS; - - /* Check if SW needs configure the PHY */ - reg_data = E1000_READ_REG(hw, FEXTNVM); - if (!(reg_data & FEXTNVM_SW_CONFIG)) - return E1000_SUCCESS; - - /* Wait for basic configuration completes before proceeding*/ - loop = 0; - do { - reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; - usec_delay(100); - loop++; - } while ((!reg_data) && (loop < 50)); - - /* Clear the Init Done bit for the next init event */ - reg_data = E1000_READ_REG(hw, STATUS); - reg_data &= ~E1000_STATUS_LAN_INIT_DONE; - E1000_WRITE_REG(hw, STATUS, reg_data); - - /* Make sure HW does not configure LCD from PHY extended configuration - before SW configuration */ - reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); - if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { - reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); - cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; - cnf_size >>= 16; - if (cnf_size) { - reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); - cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; - /* cnf_base_addr is in DWORD */ - cnf_base_addr >>= 16; - - /* Configure LCD from extended configuration region. */ - ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, - cnf_size); - if (ret_val) - return ret_val; - } - } - - return E1000_SUCCESS; -} -
--- a/usr/src/uts/common/io/e1000g/e1000_hw.h Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000_hw.h Tue Aug 21 00:30:10 2007 -0700 @@ -24,3419 +24,700 @@ */ /* - * e1000_hw.h - * Structures, enums, and macros for the MAC - * IntelVersion: 1.290.2.1 + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 */ - #ifndef _E1000_HW_H_ -#define _E1000_HW_H_ +#define _E1000_HW_H_ #pragma ident "%Z%%M% %I% %E% SMI" -#include "e1000_osdep.h" +#ifdef __cplusplus +extern "C" { +#endif +#include "e1000_osdep.h" +#include "e1000_regs.h" +#include "e1000_defines.h" -/* Forward declarations of structures used by the shared code */ struct e1000_hw; -struct e1000_hw_stats; -/* Enumerated types specific to the e1000 hardware */ -/* Media Access Controlers */ +#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82543GC_FIBER 0x1001 +#define E1000_DEV_ID_82543GC_COPPER 0x1004 +#define E1000_DEV_ID_82544EI_COPPER 0x1008 +#define E1000_DEV_ID_82544EI_FIBER 0x1009 +#define E1000_DEV_ID_82544GC_COPPER 0x100C +#define E1000_DEV_ID_82544GC_LOM 0x100D +#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82540EP_LOM 0x1016 +#define E1000_DEV_ID_82540EP 0x1017 +#define E1000_DEV_ID_82540EP_LP 0x101E +#define E1000_DEV_ID_82545EM_COPPER 0x100F +#define E1000_DEV_ID_82545EM_FIBER 0x1011 +#define E1000_DEV_ID_82545GM_COPPER 0x1026 +#define E1000_DEV_ID_82545GM_FIBER 0x1027 +#define E1000_DEV_ID_82545GM_SERDES 0x1028 +#define E1000_DEV_ID_82546EB_COPPER 0x1010 +#define E1000_DEV_ID_82546EB_FIBER 0x1012 +#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D +#define E1000_DEV_ID_82546GB_COPPER 0x1079 +#define E1000_DEV_ID_82546GB_FIBER 0x107A +#define E1000_DEV_ID_82546GB_SERDES 0x107B +#define E1000_DEV_ID_82546GB_PCIE 0x108A +#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 +#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 +#define E1000_DEV_ID_82541EI 0x1013 +#define E1000_DEV_ID_82541EI_MOBILE 0x1018 +#define E1000_DEV_ID_82541ER_LOM 0x1014 +#define E1000_DEV_ID_82541ER 0x1078 +#define E1000_DEV_ID_82541GI 0x1076 +#define E1000_DEV_ID_82541GI_LF 0x107C +#define E1000_DEV_ID_82541GI_MOBILE 0x1077 +#define E1000_DEV_ID_82547EI 0x1019 +#define E1000_DEV_ID_82547EI_MOBILE 0x101A +#define E1000_DEV_ID_82547GI 0x1075 +#define E1000_DEV_ID_82571EB_COPPER 0x105E +#define E1000_DEV_ID_82571EB_FIBER 0x105F +#define E1000_DEV_ID_82571EB_SERDES 0x1060 +#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 +#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC +#define E1000_DEV_ID_82572EI_COPPER 0x107D +#define E1000_DEV_ID_82572EI_FIBER 0x107E +#define E1000_DEV_ID_82572EI_SERDES 0x107F +#define E1000_DEV_ID_82572EI 0x10B9 +#define E1000_DEV_ID_82573E 0x108B +#define E1000_DEV_ID_82573E_IAMT 0x108C +#define E1000_DEV_ID_82573L 0x109A +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A +#define E1000_DEV_ID_ICH8_IGP_C 0x104B +#define E1000_DEV_ID_ICH8_IFE 0x104C +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D +#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD +#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10BE +#define E1000_DEV_ID_ICH9_IGP_M 0x10BF +#define E1000_DEV_ID_ICH9_IGP_C 0x294C +#define E1000_DEV_ID_ICH9_IFE 0x10C0 +#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 +#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 + +#define E1000_REVISION_0 0 +#define E1000_REVISION_1 1 +#define E1000_REVISION_2 2 +#define E1000_REVISION_3 3 +#define E1000_REVISION_4 4 + +#define E1000_FUNC_0 0 +#define E1000_FUNC_1 1 + typedef enum { - e1000_undefined = 0, - e1000_82542_rev2_0, - e1000_82542_rev2_1, - e1000_82543, - e1000_82544, - e1000_82540, - e1000_82545, - e1000_82545_rev_3, - e1000_82546, - e1000_82546_rev_3, - e1000_82541, - e1000_82541_rev_2, - e1000_82547, - e1000_82547_rev_2, - e1000_82571, - e1000_82572, - e1000_82573, - e1000_80003es2lan, - e1000_ich8lan, - e1000_num_macs + e1000_undefined = 0, + e1000_82542, + e1000_82543, + e1000_82544, + e1000_82540, + e1000_82545, + e1000_82545_rev_3, + e1000_82546, + e1000_82546_rev_3, + e1000_82541, + e1000_82541_rev_2, + e1000_82547, + e1000_82547_rev_2, + e1000_82571, + e1000_82572, + e1000_82573, + e1000_80003es2lan, + e1000_ich8lan, + e1000_ich9lan, + e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ } e1000_mac_type; typedef enum { - e1000_eeprom_uninitialized = 0, - e1000_eeprom_spi, - e1000_eeprom_microwire, - e1000_eeprom_flash, - e1000_eeprom_ich8, - e1000_eeprom_none, /* No NVM support */ - e1000_num_eeprom_types -} e1000_eeprom_type; - -/* Media Types */ -typedef enum { - e1000_media_type_copper = 0, - e1000_media_type_fiber = 1, - e1000_media_type_internal_serdes = 2, - e1000_num_media_types + e1000_media_type_unknown = 0, + e1000_media_type_copper = 1, + e1000_media_type_fiber = 2, + e1000_media_type_internal_serdes = 3, + e1000_num_media_types } e1000_media_type; typedef enum { - e1000_10_half = 0, - e1000_10_full = 1, - e1000_100_half = 2, - e1000_100_full = 3 -} e1000_speed_duplex_type; + e1000_nvm_unknown = 0, + e1000_nvm_none, + e1000_nvm_eeprom_spi, + e1000_nvm_eeprom_microwire, + e1000_nvm_flash_hw, + e1000_nvm_flash_sw +} e1000_nvm_type; + +typedef enum { + e1000_nvm_override_none = 0, + e1000_nvm_override_spi_small, + e1000_nvm_override_spi_large, + e1000_nvm_override_microwire_small, + e1000_nvm_override_microwire_large +} e1000_nvm_override; -struct e1000_shadow_ram { - uint16_t eeprom_word; - boolean_t modified; -}; +typedef enum { + e1000_phy_unknown = 0, + e1000_phy_none, + e1000_phy_m88, + e1000_phy_igp, + e1000_phy_igp_2, + e1000_phy_gg82563, + e1000_phy_igp_3, + e1000_phy_ife, + e1000_phy_bm, + e1000_phy_vf +} e1000_phy_type; -/* PCI bus types */ typedef enum { - e1000_bus_type_unknown = 0, - e1000_bus_type_pci, - e1000_bus_type_pcix, - e1000_bus_type_pci_express, - e1000_bus_type_reserved + e1000_bus_type_unknown = 0, + e1000_bus_type_pci, + e1000_bus_type_pcix, + e1000_bus_type_pci_express, + e1000_bus_type_reserved } e1000_bus_type; -/* PCI bus speeds */ typedef enum { - e1000_bus_speed_unknown = 0, - e1000_bus_speed_33, - e1000_bus_speed_66, - e1000_bus_speed_100, - e1000_bus_speed_120, - e1000_bus_speed_133, - e1000_bus_speed_2500, - e1000_bus_speed_reserved + e1000_bus_speed_unknown = 0, + e1000_bus_speed_33, + e1000_bus_speed_66, + e1000_bus_speed_100, + e1000_bus_speed_120, + e1000_bus_speed_133, + e1000_bus_speed_2500, + e1000_bus_speed_reserved } e1000_bus_speed; -/* PCI bus widths */ typedef enum { - e1000_bus_width_unknown = 0, - /* These PCIe values should literally match the possible return values - * from config space */ - e1000_bus_width_pciex_1 = 1, - e1000_bus_width_pciex_2 = 2, - e1000_bus_width_pciex_4 = 4, - e1000_bus_width_32, - e1000_bus_width_64, - e1000_bus_width_reserved + e1000_bus_width_unknown = 0, + e1000_bus_width_pcie_x1, + e1000_bus_width_pcie_x2, + e1000_bus_width_pcie_x4 = 4, + e1000_bus_width_32, + e1000_bus_width_64, + e1000_bus_width_reserved } e1000_bus_width; -/* PHY status info structure and supporting enums */ typedef enum { - e1000_cable_length_50 = 0, - e1000_cable_length_50_80, - e1000_cable_length_80_110, - e1000_cable_length_110_140, - e1000_cable_length_140, - e1000_cable_length_undefined = 0xFF -} e1000_cable_length; - -typedef enum { - e1000_gg_cable_length_60 = 0, - e1000_gg_cable_length_60_115 = 1, - e1000_gg_cable_length_115_150 = 2, - e1000_gg_cable_length_150 = 4 -} e1000_gg_cable_length; + e1000_1000t_rx_status_not_ok = 0, + e1000_1000t_rx_status_ok, + e1000_1000t_rx_status_undefined = 0xFF +} e1000_1000t_rx_status; typedef enum { - e1000_igp_cable_length_10 = 10, - e1000_igp_cable_length_20 = 20, - e1000_igp_cable_length_30 = 30, - e1000_igp_cable_length_40 = 40, - e1000_igp_cable_length_50 = 50, - e1000_igp_cable_length_60 = 60, - e1000_igp_cable_length_70 = 70, - e1000_igp_cable_length_80 = 80, - e1000_igp_cable_length_90 = 90, - e1000_igp_cable_length_100 = 100, - e1000_igp_cable_length_110 = 110, - e1000_igp_cable_length_115 = 115, - e1000_igp_cable_length_120 = 120, - e1000_igp_cable_length_130 = 130, - e1000_igp_cable_length_140 = 140, - e1000_igp_cable_length_150 = 150, - e1000_igp_cable_length_160 = 160, - e1000_igp_cable_length_170 = 170, - e1000_igp_cable_length_180 = 180 -} e1000_igp_cable_length; - -typedef enum { - e1000_10bt_ext_dist_enable_normal = 0, - e1000_10bt_ext_dist_enable_lower, - e1000_10bt_ext_dist_enable_undefined = 0xFF -} e1000_10bt_ext_dist_enable; - -typedef enum { - e1000_rev_polarity_normal = 0, - e1000_rev_polarity_reversed, - e1000_rev_polarity_undefined = 0xFF + e1000_rev_polarity_normal = 0, + e1000_rev_polarity_reversed, + e1000_rev_polarity_undefined = 0xFF } e1000_rev_polarity; typedef enum { - e1000_downshift_normal = 0, - e1000_downshift_activated, - e1000_downshift_undefined = 0xFF -} e1000_downshift; - -typedef enum { - e1000_smart_speed_default = 0, - e1000_smart_speed_on, - e1000_smart_speed_off -} e1000_smart_speed; - -typedef enum { - e1000_polarity_reversal_enabled = 0, - e1000_polarity_reversal_disabled, - e1000_polarity_reversal_undefined = 0xFF -} e1000_polarity_reversal; - -typedef enum { - e1000_auto_x_mode_manual_mdi = 0, - e1000_auto_x_mode_manual_mdix, - e1000_auto_x_mode_auto1, - e1000_auto_x_mode_auto2, - e1000_auto_x_mode_undefined = 0xFF -} e1000_auto_x_mode; + e1000_fc_none = 0, + e1000_fc_rx_pause, + e1000_fc_tx_pause, + e1000_fc_full, + e1000_fc_default = 0xFF +} e1000_fc_mode; typedef enum { - e1000_1000t_rx_status_not_ok = 0, - e1000_1000t_rx_status_ok, - e1000_1000t_rx_status_undefined = 0xFF -} e1000_1000t_rx_status; - -typedef enum { - e1000_phy_m88 = 0, - e1000_phy_igp, - e1000_phy_igp_2, - e1000_phy_gg82563, - e1000_phy_igp_3, - e1000_phy_ife, - e1000_phy_undefined = 0xFF -} e1000_phy_type; - -typedef enum { - e1000_ms_hw_default = 0, - e1000_ms_force_master, - e1000_ms_force_slave, - e1000_ms_auto -} e1000_ms_type; - -typedef enum { - e1000_ffe_config_enabled = 0, - e1000_ffe_config_active, - e1000_ffe_config_blocked + e1000_ffe_config_enabled = 0, + e1000_ffe_config_active, + e1000_ffe_config_blocked } e1000_ffe_config; typedef enum { - e1000_dsp_config_disabled = 0, - e1000_dsp_config_enabled, - e1000_dsp_config_activated, - e1000_dsp_config_undefined = 0xFF + e1000_dsp_config_disabled = 0, + e1000_dsp_config_enabled, + e1000_dsp_config_activated, + e1000_dsp_config_undefined = 0xFF } e1000_dsp_config; -struct e1000_phy_info { - e1000_cable_length cable_length; - e1000_10bt_ext_dist_enable extended_10bt_distance; - e1000_rev_polarity cable_polarity; - e1000_downshift downshift; - e1000_polarity_reversal polarity_correction; - e1000_auto_x_mode mdix_mode; - e1000_1000t_rx_status local_rx; - e1000_1000t_rx_status remote_rx; -}; - -struct e1000_phy_stats { - uint32_t idle_errors; - uint32_t receive_errors; -}; - -struct e1000_eeprom_info { - e1000_eeprom_type type; - uint16_t word_size; - uint16_t opcode_bits; - uint16_t address_bits; - uint16_t delay_usec; - uint16_t page_size; - boolean_t use_eerd; - boolean_t use_eewr; -}; - -/* Flex ASF Information */ -#define E1000_HOST_IF_MAX_SIZE 2048 - -typedef enum { - e1000_byte_align = 0, - e1000_word_align = 1, - e1000_dword_align = 2 -} e1000_align_type; - - - -/* Error Codes */ -#define E1000_SUCCESS 0 -#define E1000_ERR_EEPROM 1 -#define E1000_ERR_PHY 2 -#define E1000_ERR_CONFIG 3 -#define E1000_ERR_PARAM 4 -#define E1000_ERR_MAC_TYPE 5 -#define E1000_ERR_PHY_TYPE 6 -#ifndef FIFO_WORKAROUND -#define E1000_ERR_HOSTIF 7 -#define E1000_ERR_FIFO_WRAP 8 -#endif /* FIFO_WORKAROUND */ -#define E1000_ERR_RESET 9 -#define E1000_ERR_MASTER_REQUESTS_PENDING 10 -#define E1000_ERR_HOST_INTERFACE_COMMAND 11 -#define E1000_BLK_PHY_RESET 12 -#define E1000_ERR_SWFW_SYNC 13 - -#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ - (((_value) & 0xff00) >> 8)) - -/* Function prototypes */ -/* Initialization */ -int32_t e1000_reset_hw(struct e1000_hw *hw); -int32_t e1000_init_hw(struct e1000_hw *hw); -int32_t e1000_set_mac_type(struct e1000_hw *hw); -void e1000_set_media_type(struct e1000_hw *hw); - -/* Link Configuration */ -int32_t e1000_setup_link(struct e1000_hw *hw); -int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw); -void e1000_config_collision_dist(struct e1000_hw *hw); -int32_t e1000_check_for_link(struct e1000_hw *hw); -int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex); -int32_t e1000_force_mac_fc(struct e1000_hw *hw); - - -/* PHY */ -int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); -int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); -int32_t e1000_phy_hw_reset(struct e1000_hw *hw); -int32_t e1000_phy_reset(struct e1000_hw *hw); -int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); - -void e1000_phy_powerdown_workaround(struct e1000_hw *hw); - -/* EEPROM Functions */ -int32_t e1000_init_eeprom_params(struct e1000_hw *hw); - -/* MNG HOST IF functions */ -uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); - -#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 -#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ - -#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ -#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ -#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ -#define E1000_MNG_IAMT_MODE 0x3 -#define E1000_MNG_ICH_IAMT_MODE 0x2 -#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ - -#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ -#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ -#define E1000_VFTA_ENTRY_SHIFT 0x5 -#define E1000_VFTA_ENTRY_MASK 0x7F -#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F - -struct e1000_host_mng_command_header { - uint8_t command_id; - uint8_t checksum; - uint16_t reserved1; - uint16_t reserved2; - uint16_t command_length; -}; - -struct e1000_host_mng_command_info { - struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ - uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ -}; -#ifdef E1000_BIG_ENDIAN -struct e1000_host_mng_dhcp_cookie{ - uint32_t signature; - uint16_t vlan_id; - uint8_t reserved0; - uint8_t status; - uint32_t reserved1; - uint8_t checksum; - uint8_t reserved3; - uint16_t reserved2; -}; -#else -struct e1000_host_mng_dhcp_cookie{ - uint32_t signature; - uint8_t status; - uint8_t reserved0; - uint16_t vlan_id; - uint32_t reserved1; - uint16_t reserved2; - uint8_t reserved3; - uint8_t checksum; -}; -#endif - -int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); -int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, - uint16_t length); -boolean_t e1000_check_mng_mode(struct e1000_hw *hw); -boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); -int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); -int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); -int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); -int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); -int32_t e1000_read_mac_addr(struct e1000_hw * hw); - - -/* Filters (multicast, vlan, receive) */ -void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); -uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); -void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); -void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); -void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value); - -/* LED functions */ -int32_t e1000_setup_led(struct e1000_hw *hw); -int32_t e1000_cleanup_led(struct e1000_hw *hw); -int32_t e1000_led_on(struct e1000_hw *hw); -int32_t e1000_led_off(struct e1000_hw *hw); -int32_t e1000_blink_led_start(struct e1000_hw *hw); - -/* Adaptive IFS Functions */ - -/* Everything else */ -void e1000_clear_hw_cntrs(struct e1000_hw *hw); - -void e1000_reset_adaptive(struct e1000_hw *hw); -void e1000_update_adaptive(struct e1000_hw *hw); -void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); -void e1000_get_bus_info(struct e1000_hw *hw); -void e1000_pci_set_mwi(struct e1000_hw *hw); -void e1000_pci_clear_mwi(struct e1000_hw *hw); -void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); -void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); -int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value); -/* Port I/O is only supported on 82544 and newer */ -uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port); -void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); -int32_t e1000_disable_pciex_master(struct e1000_hw *hw); -int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); - -#ifndef FIFO_WORKAROUND -int32_t e1000_igp_ttl_workaround(struct e1000_hw *hw); -void e1000_update_tx_fifo_head(struct e1000_hw *hw, uint32_t length); -int32_t e1000_82547_fifo_workaround(struct e1000_hw *hw, uint16_t length); -#endif /* FIFO_WORKAROUND */ - - -#ifndef E1000_READ_REG_IO -#define E1000_READ_REG_IO(a, reg) \ - e1000_read_reg_io((a), E1000_##reg) -#define E1000_WRITE_REG_IO(a, reg, val) \ - e1000_write_reg_io((a), E1000_##reg, val) -#endif - -/* PCI Device IDs */ -#define E1000_DEV_ID_82542 0x1000 -#define E1000_DEV_ID_82543GC_FIBER 0x1001 -#define E1000_DEV_ID_82543GC_COPPER 0x1004 -#define E1000_DEV_ID_82544EI_COPPER 0x1008 -#define E1000_DEV_ID_82544EI_FIBER 0x1009 -#define E1000_DEV_ID_82544GC_COPPER 0x100C -#define E1000_DEV_ID_82544GC_LOM 0x100D -#define E1000_DEV_ID_82540EM 0x100E -#define E1000_DEV_ID_82540EM_LOM 0x1015 -#define E1000_DEV_ID_82540EP_LOM 0x1016 -#define E1000_DEV_ID_82540EP 0x1017 -#define E1000_DEV_ID_82540EP_LP 0x101E -#define E1000_DEV_ID_82545EM_COPPER 0x100F -#define E1000_DEV_ID_82545EM_FIBER 0x1011 -#define E1000_DEV_ID_82545GM_COPPER 0x1026 -#define E1000_DEV_ID_82545GM_FIBER 0x1027 -#define E1000_DEV_ID_82545GM_SERDES 0x1028 -#define E1000_DEV_ID_82546EB_COPPER 0x1010 -#define E1000_DEV_ID_82546EB_FIBER 0x1012 -#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D -#define E1000_DEV_ID_82541EI 0x1013 -#define E1000_DEV_ID_82541EI_MOBILE 0x1018 -#define E1000_DEV_ID_82541ER_LOM 0x1014 -#define E1000_DEV_ID_82541ER 0x1078 -#define E1000_DEV_ID_82547GI 0x1075 -#define E1000_DEV_ID_82541GI 0x1076 -#define E1000_DEV_ID_82541GI_MOBILE 0x1077 -#define E1000_DEV_ID_82541GI_LF 0x107C -#define E1000_DEV_ID_82546GB_COPPER 0x1079 -#define E1000_DEV_ID_82546GB_FIBER 0x107A -#define E1000_DEV_ID_82546GB_SERDES 0x107B -#define E1000_DEV_ID_82546GB_PCIE 0x108A -#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 -#define E1000_DEV_ID_82547EI 0x1019 -#define E1000_DEV_ID_82547EI_MOBILE 0x101A -#define E1000_DEV_ID_82571EB_COPPER 0x105E -#define E1000_DEV_ID_82571EB_FIBER 0x105F -#define E1000_DEV_ID_82571EB_SERDES 0x1060 -#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 -#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC -#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 -#define E1000_DEV_ID_82572EI_COPPER 0x107D -#define E1000_DEV_ID_82572EI_FIBER 0x107E -#define E1000_DEV_ID_82572EI_SERDES 0x107F -#define E1000_DEV_ID_82572EI 0x10B9 -#define E1000_DEV_ID_82573E 0x108B -#define E1000_DEV_ID_82573E_IAMT 0x108C -#define E1000_DEV_ID_82573L 0x109A -#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 -#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 -#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 -#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA -#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB - -#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 -#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A -#define E1000_DEV_ID_ICH8_IGP_C 0x104B -#define E1000_DEV_ID_ICH8_IFE 0x104C -#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 -#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 -#define E1000_DEV_ID_ICH8_IGP_M 0x104D - - -#define NODE_ADDRESS_SIZE 6 -#define ETH_LENGTH_OF_ADDRESS 6 - -/* MAC decode size is 128K - This is the size of BAR0 */ -#define MAC_DECODE_SIZE (128 * 1024) - -#define E1000_82542_2_0_REV_ID 2 -#define E1000_82542_2_1_REV_ID 3 -#define E1000_REVISION_0 0 -#define E1000_REVISION_1 1 -#define E1000_REVISION_2 2 -#define E1000_REVISION_3 3 - -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 - -/* The sizes (in bytes) of a ethernet packet */ -#define ENET_HEADER_SIZE 14 -#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ -#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ -#define ETHERNET_FCS_SIZE 4 -#define MAXIMUM_ETHERNET_PACKET_SIZE \ - (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) -#define MINIMUM_ETHERNET_PACKET_SIZE \ - (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) -#define CRC_LENGTH ETHERNET_FCS_SIZE -#define MAX_JUMBO_FRAME_SIZE 0x3F00 - - -/* 802.1q VLAN Packet Sizes */ -#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ - -/* Ethertype field values */ -#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ -#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ -#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ - -/* Packet Header defines */ -#define IP_PROTOCOL_TCP 6 -#define IP_PROTOCOL_UDP 0x11 - -/* This defines the bits that are set in the Interrupt Mask - * Set/Read Register. Each bit is documented below: - * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) - * o RXSEQ = Receive Sequence Error - */ -#define POLL_IMS_ENABLE_MASK ( \ - E1000_IMS_RXDMT0 | \ - E1000_IMS_RXSEQ) - -/* This defines the bits that are set in the Interrupt Mask - * Set/Read Register. Each bit is documented below: - * o RXT0 = Receiver Timer Interrupt (ring 0) - * o TXDW = Transmit Descriptor Written Back - * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) - * o RXSEQ = Receive Sequence Error - * o LSC = Link Status Change - */ -#define IMS_ENABLE_MASK ( \ - E1000_IMS_RXT0 | \ - E1000_IMS_TXDW | \ - E1000_IMS_RXDMT0 | \ - E1000_IMS_RXSEQ | \ - E1000_IMS_LSC) - - -/* Additional interrupts need to be handled for e1000_ich8lan: - DSW = The FW changed the status of the DISSW bit in FWSM - PHYINT = The LAN connected device generates an interrupt - EPRST = Manageability reset event */ -#define IMS_ICH8LAN_ENABLE_MASK (\ - E1000_IMS_DSW | \ - E1000_IMS_PHYINT | \ - E1000_IMS_EPRST) - - -/* Number of high/low register pairs in the RAR. The RAR (Receive Address - * Registers) holds the directed and multicast addresses that we monitor. We - * reserve one of these spots for our directed address, allowing us room for - * E1000_RAR_ENTRIES - 1 multicast addresses. - */ -#define E1000_RAR_ENTRIES 15 - -#define E1000_RAR_ENTRIES_ICH8LAN 6 - -#define MIN_NUMBER_OF_DESCRIPTORS 8 -#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 - /* Receive Descriptor */ struct e1000_rx_desc { - uint64_t buffer_addr; /* Address of the descriptor's data buffer */ - uint16_t length; /* Length of data DMAed into data buffer */ - uint16_t csum; /* Packet checksum */ - uint8_t status; /* Descriptor status */ - uint8_t errors; /* Descriptor Errors */ - uint16_t special; + u64 buffer_addr; /* Address of the descriptor's data buffer */ + u16 length; /* Length of data DMAed into data buffer */ + u16 csum; /* Packet checksum */ + u8 status; /* Descriptor status */ + u8 errors; /* Descriptor Errors */ + u16 special; }; /* Receive Descriptor - Extended */ union e1000_rx_desc_extended { - struct { - uint64_t buffer_addr; - uint64_t reserved; - } read; - struct { - struct { - uint32_t mrq; /* Multiple Rx Queues */ - union { - uint32_t rss; /* RSS Hash */ - struct { - uint16_t ip_id; /* IP id */ - uint16_t csum; /* Packet Checksum */ - } csum_ip; - } hi_dword; - } lower; - struct { - uint32_t status_error; /* ext status/error */ - uint16_t length; - uint16_t vlan; /* VLAN tag */ - } upper; - } wb; /* writeback */ -}; - -#define MAX_PS_BUFFERS 4 -/* Receive Descriptor - Packet Split */ -union e1000_rx_desc_packet_split { - struct { - /* one buffer for protocol header(s), three data buffers */ - uint64_t buffer_addr[MAX_PS_BUFFERS]; - } read; - struct { - struct { - uint32_t mrq; /* Multiple Rx Queues */ - union { - uint32_t rss; /* RSS Hash */ - struct { - uint16_t ip_id; /* IP id */ - uint16_t csum; /* Packet Checksum */ - } csum_ip; - } hi_dword; - } lower; - struct { - uint32_t status_error; /* ext status/error */ - uint16_t length0; /* length of buffer 0 */ - uint16_t vlan; /* VLAN tag */ - } middle; - struct { - uint16_t header_status; - uint16_t length[3]; /* length of buffers 1-3 */ - } upper; - uint64_t reserved; - } wb; /* writeback */ + struct { + u64 buffer_addr; + u64 reserved; + } read; + struct { + struct { + u32 mrq; /* Multiple Rx Queues */ + union { + u32 rss; /* RSS Hash */ + struct { + u16 ip_id; /* IP id */ + u16 csum; /* Packet Checksum */ + } csum_ip; + } hi_dword; + } lower; + struct { + u32 status_error; /* ext status/error */ + u16 length; + u16 vlan; /* VLAN tag */ + } upper; + } wb; /* writeback */ }; -/* Receive Decriptor bit definitions */ -#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ -#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ -#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ -#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ -#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ -#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ -#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ -#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ -#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ -#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ -#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ -#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ -#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ -#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ -#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ -#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ -#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ -#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ -#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ -#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ -#define E1000_RXD_SPC_PRI_SHIFT 13 -#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ -#define E1000_RXD_SPC_CFI_SHIFT 12 - -#define E1000_RXDEXT_STATERR_CE 0x01000000 -#define E1000_RXDEXT_STATERR_SE 0x02000000 -#define E1000_RXDEXT_STATERR_SEQ 0x04000000 -#define E1000_RXDEXT_STATERR_CXE 0x10000000 -#define E1000_RXDEXT_STATERR_TCPE 0x20000000 -#define E1000_RXDEXT_STATERR_IPE 0x40000000 -#define E1000_RXDEXT_STATERR_RXE 0x80000000 - -#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 -#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF - -/* mask to determine if packets should be dropped due to frame errors */ -#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ - E1000_RXD_ERR_CE | \ - E1000_RXD_ERR_SE | \ - E1000_RXD_ERR_SEQ | \ - E1000_RXD_ERR_CXE | \ - E1000_RXD_ERR_RXE) - - -/* Same mask, but for extended and packet split descriptors */ -#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ - E1000_RXDEXT_STATERR_CE | \ - E1000_RXDEXT_STATERR_SE | \ - E1000_RXDEXT_STATERR_SEQ | \ - E1000_RXDEXT_STATERR_CXE | \ - E1000_RXDEXT_STATERR_RXE) - +#define MAX_PS_BUFFERS 4 +/* Receive Descriptor - Packet Split */ +union e1000_rx_desc_packet_split { + struct { + /* one buffer for protocol header(s), three data buffers */ + u64 buffer_addr[MAX_PS_BUFFERS]; + } read; + struct { + struct { + u32 mrq; /* Multiple Rx Queues */ + union { + u32 rss; /* RSS Hash */ + struct { + u16 ip_id; /* IP id */ + u16 csum; /* Packet Checksum */ + } csum_ip; + } hi_dword; + } lower; + struct { + u32 status_error; /* ext status/error */ + u16 length0; /* length of buffer 0 */ + u16 vlan; /* VLAN tag */ + } middle; + struct { + u16 header_status; + u16 length[3]; /* length of buffers 1-3 */ + } upper; + u64 reserved; + } wb; /* writeback */ +}; /* Transmit Descriptor */ struct e1000_tx_desc { - uint64_t buffer_addr; /* Address of the descriptor's data buffer */ - union { - uint32_t data; - struct { - uint16_t length; /* Data buffer length */ - uint8_t cso; /* Checksum offset */ - uint8_t cmd; /* Descriptor control */ - } flags; - } lower; - union { - uint32_t data; - struct { - uint8_t status; /* Descriptor status */ - uint8_t css; /* Checksum start */ - uint16_t special; - } fields; - } upper; + u64 buffer_addr; /* Address of the descriptor's data buffer */ + union { + u32 data; + struct { + u16 length; /* Data buffer length */ + u8 cso; /* Checksum offset */ + u8 cmd; /* Descriptor control */ + } flags; + } lower; + union { + u32 data; + struct { + u8 status; /* Descriptor status */ + u8 css; /* Checksum start */ + u16 special; + } fields; + } upper; }; -/* Transmit Descriptor bit definitions */ -#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ -#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ -#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ -#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ -#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ -#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ -#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ -#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ -#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ -#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ -#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ -#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ -#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ -#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ -#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ -#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ -#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ -#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ -#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ -#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ - /* Offload Context Descriptor */ struct e1000_context_desc { - union { - uint32_t ip_config; - struct { - uint8_t ipcss; /* IP checksum start */ - uint8_t ipcso; /* IP checksum offset */ - uint16_t ipcse; /* IP checksum end */ - } ip_fields; - } lower_setup; - union { - uint32_t tcp_config; - struct { - uint8_t tucss; /* TCP checksum start */ - uint8_t tucso; /* TCP checksum offset */ - uint16_t tucse; /* TCP checksum end */ - } tcp_fields; - } upper_setup; - uint32_t cmd_and_length; /* */ - union { - uint32_t data; - struct { - uint8_t status; /* Descriptor status */ - uint8_t hdr_len; /* Header length */ - uint16_t mss; /* Maximum segment size */ - } fields; - } tcp_seg_setup; + union { + u32 ip_config; + struct { + u8 ipcss; /* IP checksum start */ + u8 ipcso; /* IP checksum offset */ + u16 ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + u32 tcp_config; + struct { + u8 tucss; /* TCP checksum start */ + u8 tucso; /* TCP checksum offset */ + u16 tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; + u32 cmd_and_length; + union { + u32 data; + struct { + u8 status; /* Descriptor status */ + u8 hdr_len; /* Header length */ + u16 mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; }; /* Offload data descriptor */ struct e1000_data_desc { - uint64_t buffer_addr; /* Address of the descriptor's buffer address */ - union { - uint32_t data; - struct { - uint16_t length; /* Data buffer length */ - uint8_t typ_len_ext; /* */ - uint8_t cmd; /* */ - } flags; - } lower; - union { - uint32_t data; - struct { - uint8_t status; /* Descriptor status */ - uint8_t popts; /* Packet Options */ - uint16_t special; /* */ - } fields; - } upper; -}; - -/* Filters */ -#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ -#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ -#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ - -#define E1000_NUM_UNICAST_ICH8LAN 7 -#define E1000_MC_TBL_SIZE_ICH8LAN 32 - - -/* Receive Address Register */ -struct e1000_rar { - volatile uint32_t low; /* receive address low */ - volatile uint32_t high; /* receive address high */ -}; - -/* Number of entries in the Multicast Table Array (MTA). */ -#define E1000_NUM_MTA_REGISTERS 128 -#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32 - -/* IPv4 Address Table Entry */ -struct e1000_ipv4_at_entry { - volatile uint32_t ipv4_addr; /* IP Address (RW) */ - volatile uint32_t reserved; -}; - -/* Four wakeup IP addresses are supported */ -#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 -#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX -#define E1000_IP4AT_SIZE_ICH8LAN 3 -#define E1000_IP6AT_SIZE 1 - -/* IPv6 Address Table Entry */ -struct e1000_ipv6_at_entry { - volatile uint8_t ipv6_addr[16]; -}; - -/* Flexible Filter Length Table Entry */ -struct e1000_fflt_entry { - volatile uint32_t length; /* Flexible Filter Length (RW) */ - volatile uint32_t reserved; -}; - -/* Flexible Filter Mask Table Entry */ -struct e1000_ffmt_entry { - volatile uint32_t mask; /* Flexible Filter Mask (RW) */ - volatile uint32_t reserved; -}; - -/* Flexible Filter Value Table Entry */ -struct e1000_ffvt_entry { - volatile uint32_t value; /* Flexible Filter Value (RW) */ - volatile uint32_t reserved; + u64 buffer_addr; /* Address of the descriptor's buffer address */ + union { + u32 data; + struct { + u16 length; /* Data buffer length */ + u8 typ_len_ext; + u8 cmd; + } flags; + } lower; + union { + u32 data; + struct { + u8 status; /* Descriptor status */ + u8 popts; /* Packet Options */ + u16 special; + } fields; + } upper; }; -/* Four Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 - -/* Each Flexible Filter is at most 128 (0x80) bytes in length */ -#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 - -#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX -#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX -#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX - -#define E1000_DISABLE_SERDES_LOOPBACK 0x0400 - -/* Register Set. (82543, 82544) - * - * Registers are defined to be 32 bits and should be accessed as 32 bit values. - * These registers are physically located on the NIC, but are mapped into the - * host memory address space. - * - * RW - register is both readable and writable - * RO - register is read only - * WO - register is write only - * R/clr - register is read only and is cleared when read - * A - register array - */ -#define E1000_CTRL 0x00000 /* Device Control - RW */ -#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ -#define E1000_STATUS 0x00008 /* Device Status - RO */ -#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ -#define E1000_EERD 0x00014 /* EEPROM Read - RW */ -#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ -#define E1000_FLA 0x0001C /* Flash Access - RW */ -#define E1000_MDIC 0x00020 /* MDI Control - RW */ -#define E1000_SCTL 0x00024 /* SerDes Control - RW */ -#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ -#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ -#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ -#define E1000_FCT 0x00030 /* Flow Control Type - RW */ -#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ -#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ -#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ -#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ -#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ -#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ -#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ -#define E1000_RCTL 0x00100 /* RX Control - RW */ -#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ -#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ -#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ -#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ -#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ -#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ -#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ -#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ -#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ -#define E1000_TCTL 0x00400 /* TX Control - RW */ -#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ -#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ -#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ -#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ -#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ -#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ -#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ -#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ -#define FEXTNVM_SW_CONFIG 0x0001 -#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ -#define E1000_PBS 0x01008 /* Packet Buffer Size */ -#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ -#define E1000_FLASH_UPDATES 1000 -#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ -#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ -#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ -#define E1000_FLSWCTL 0x01030 /* FLASH control register */ -#define E1000_FLSWDATA 0x01034 /* FLASH data register */ -#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ -#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ -#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ -#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ -#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ -#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ -#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ -#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ -#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ -#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ -#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ -#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ -#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ -#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ -#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ -#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ -#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ -#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ -#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ -#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ -#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ -#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ -#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ -#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ -#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ -#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ -#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ -#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ -#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ -#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ -#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ -#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ -#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ -#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ -#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ -#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ -#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ -#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ -#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ -#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ -#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ -#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ -#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ -#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ -#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ -#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ -#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ -#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ -#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ -#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ -#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ -#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ -#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ -#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ -#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ -#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ -#define E1000_COLC 0x04028 /* Collision Count - R/clr */ -#define E1000_DC 0x04030 /* Defer Count - R/clr */ -#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ -#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ -#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ -#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ -#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ -#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ -#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ -#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ -#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ -#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ -#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ -#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ -#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ -#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ -#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ -#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ -#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ -#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ -#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ -#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ -#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ -#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ -#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ -#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ -#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ -#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ -#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ -#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ -#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ -#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ -#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ -#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ -#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ -#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ -#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ -#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ -#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ -#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ -#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ -#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ -#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ -#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ -#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ -#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ -#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ -#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ -#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ -#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ -#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ -#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ -#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ -#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ -#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ -#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ -#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ -#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ -#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ -#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ -#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ -#define E1000_RA 0x05400 /* Receive Address - RW Array */ -#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ -#define E1000_WUC 0x05800 /* Wakeup Control - RW */ -#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ -#define E1000_WUS 0x05810 /* Wakeup Status - RO */ -#define E1000_MANC 0x05820 /* Management Control - RW */ -#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ -#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ -#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ -#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ -#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ -#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ -#define E1000_HOST_IF 0x08800 /* Host Interface */ -#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ -#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ - -#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ -#define E1000_MDPHYA 0x0003C /* PHY address - RW */ -#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ -#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ - -#define E1000_GCR 0x05B00 /* PCI-Ex Control */ -#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ -#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ -#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ -#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ -#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ -#define E1000_SWSM 0x05B50 /* SW Semaphore */ -#define E1000_FWSM 0x05B54 /* FW Semaphore */ -#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ -#define E1000_HICR 0x08F00 /* Host Inteface Control */ - -/* RSS registers */ -#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ -#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ -#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ -#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ -#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ -#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ -/* Register Set (82542) - * - * Some of the 82542 registers are located at different offsets than they are - * in more current versions of the 8254x. Despite the difference in location, - * the registers function in the same manner. - */ -#define E1000_82542_CTRL E1000_CTRL -#define E1000_82542_CTRL_DUP E1000_CTRL_DUP -#define E1000_82542_STATUS E1000_STATUS -#define E1000_82542_EECD E1000_EECD -#define E1000_82542_EERD E1000_EERD -#define E1000_82542_CTRL_EXT E1000_CTRL_EXT -#define E1000_82542_FLA E1000_FLA -#define E1000_82542_MDIC E1000_MDIC -#define E1000_82542_SCTL E1000_SCTL -#define E1000_82542_FEXTNVM E1000_FEXTNVM -#define E1000_82542_FCAL E1000_FCAL -#define E1000_82542_FCAH E1000_FCAH -#define E1000_82542_FCT E1000_FCT -#define E1000_82542_VET E1000_VET -#define E1000_82542_RA 0x00040 -#define E1000_82542_ICR E1000_ICR -#define E1000_82542_ITR E1000_ITR -#define E1000_82542_ICS E1000_ICS -#define E1000_82542_IMS E1000_IMS -#define E1000_82542_IMC E1000_IMC -#define E1000_82542_RCTL E1000_RCTL -#define E1000_82542_RDTR 0x00108 -#define E1000_82542_RDBAL 0x00110 -#define E1000_82542_RDBAH 0x00114 -#define E1000_82542_RDLEN 0x00118 -#define E1000_82542_RDH 0x00120 -#define E1000_82542_RDT 0x00128 -#define E1000_82542_RDTR0 E1000_82542_RDTR -#define E1000_82542_RDBAL0 E1000_82542_RDBAL -#define E1000_82542_RDBAH0 E1000_82542_RDBAH -#define E1000_82542_RDLEN0 E1000_82542_RDLEN -#define E1000_82542_RDH0 E1000_82542_RDH -#define E1000_82542_RDT0 E1000_82542_RDT -#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication - * RX Control - RW */ -#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) -#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ -#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ -#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ -#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ -#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ -#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ -#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ -#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ -#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ -#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ -#define E1000_82542_RDTR1 0x00130 -#define E1000_82542_RDBAL1 0x00138 -#define E1000_82542_RDBAH1 0x0013C -#define E1000_82542_RDLEN1 0x00140 -#define E1000_82542_RDH1 0x00148 -#define E1000_82542_RDT1 0x00150 -#define E1000_82542_FCRTH 0x00160 -#define E1000_82542_FCRTL 0x00168 -#define E1000_82542_FCTTV E1000_FCTTV -#define E1000_82542_TXCW E1000_TXCW -#define E1000_82542_RXCW E1000_RXCW -#define E1000_82542_MTA 0x00200 -#define E1000_82542_TCTL E1000_TCTL -#define E1000_82542_TCTL_EXT E1000_TCTL_EXT -#define E1000_82542_TIPG E1000_TIPG -#define E1000_82542_TDBAL 0x00420 -#define E1000_82542_TDBAH 0x00424 -#define E1000_82542_TDLEN 0x00428 -#define E1000_82542_TDH 0x00430 -#define E1000_82542_TDT 0x00438 -#define E1000_82542_TIDV 0x00440 -#define E1000_82542_TBT E1000_TBT -#define E1000_82542_AIT E1000_AIT -#define E1000_82542_VFTA 0x00600 -#define E1000_82542_LEDCTL E1000_LEDCTL -#define E1000_82542_PBA E1000_PBA -#define E1000_82542_PBS E1000_PBS -#define E1000_82542_EEMNGCTL E1000_EEMNGCTL -#define E1000_82542_EEARBC E1000_EEARBC -#define E1000_82542_FLASHT E1000_FLASHT -#define E1000_82542_EEWR E1000_EEWR -#define E1000_82542_FLSWCTL E1000_FLSWCTL -#define E1000_82542_FLSWDATA E1000_FLSWDATA -#define E1000_82542_FLSWCNT E1000_FLSWCNT -#define E1000_82542_FLOP E1000_FLOP -#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL -#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE -#define E1000_82542_PHY_CTRL E1000_PHY_CTRL -#define E1000_82542_ERT E1000_ERT -#define E1000_82542_RXDCTL E1000_RXDCTL -#define E1000_82542_RXDCTL1 E1000_RXDCTL1 -#define E1000_82542_RADV E1000_RADV -#define E1000_82542_RSRPD E1000_RSRPD -#define E1000_82542_TXDMAC E1000_TXDMAC -#define E1000_82542_KABGTXD E1000_KABGTXD -#define E1000_82542_TDFHS E1000_TDFHS -#define E1000_82542_TDFTS E1000_TDFTS -#define E1000_82542_TDFPC E1000_TDFPC -#define E1000_82542_TXDCTL E1000_TXDCTL -#define E1000_82542_TADV E1000_TADV -#define E1000_82542_TSPMT E1000_TSPMT -#define E1000_82542_CRCERRS E1000_CRCERRS -#define E1000_82542_ALGNERRC E1000_ALGNERRC -#define E1000_82542_SYMERRS E1000_SYMERRS -#define E1000_82542_RXERRC E1000_RXERRC -#define E1000_82542_MPC E1000_MPC -#define E1000_82542_SCC E1000_SCC -#define E1000_82542_ECOL E1000_ECOL -#define E1000_82542_MCC E1000_MCC -#define E1000_82542_LATECOL E1000_LATECOL -#define E1000_82542_COLC E1000_COLC -#define E1000_82542_DC E1000_DC -#define E1000_82542_TNCRS E1000_TNCRS -#define E1000_82542_SEC E1000_SEC -#define E1000_82542_CEXTERR E1000_CEXTERR -#define E1000_82542_RLEC E1000_RLEC -#define E1000_82542_XONRXC E1000_XONRXC -#define E1000_82542_XONTXC E1000_XONTXC -#define E1000_82542_XOFFRXC E1000_XOFFRXC -#define E1000_82542_XOFFTXC E1000_XOFFTXC -#define E1000_82542_FCRUC E1000_FCRUC -#define E1000_82542_PRC64 E1000_PRC64 -#define E1000_82542_PRC127 E1000_PRC127 -#define E1000_82542_PRC255 E1000_PRC255 -#define E1000_82542_PRC511 E1000_PRC511 -#define E1000_82542_PRC1023 E1000_PRC1023 -#define E1000_82542_PRC1522 E1000_PRC1522 -#define E1000_82542_GPRC E1000_GPRC -#define E1000_82542_BPRC E1000_BPRC -#define E1000_82542_MPRC E1000_MPRC -#define E1000_82542_GPTC E1000_GPTC -#define E1000_82542_GORCL E1000_GORCL -#define E1000_82542_GORCH E1000_GORCH -#define E1000_82542_GOTCL E1000_GOTCL -#define E1000_82542_GOTCH E1000_GOTCH -#define E1000_82542_RNBC E1000_RNBC -#define E1000_82542_RUC E1000_RUC -#define E1000_82542_RFC E1000_RFC -#define E1000_82542_ROC E1000_ROC -#define E1000_82542_RJC E1000_RJC -#define E1000_82542_MGTPRC E1000_MGTPRC -#define E1000_82542_MGTPDC E1000_MGTPDC -#define E1000_82542_MGTPTC E1000_MGTPTC -#define E1000_82542_TORL E1000_TORL -#define E1000_82542_TORH E1000_TORH -#define E1000_82542_TOTL E1000_TOTL -#define E1000_82542_TOTH E1000_TOTH -#define E1000_82542_TPR E1000_TPR -#define E1000_82542_TPT E1000_TPT -#define E1000_82542_PTC64 E1000_PTC64 -#define E1000_82542_PTC127 E1000_PTC127 -#define E1000_82542_PTC255 E1000_PTC255 -#define E1000_82542_PTC511 E1000_PTC511 -#define E1000_82542_PTC1023 E1000_PTC1023 -#define E1000_82542_PTC1522 E1000_PTC1522 -#define E1000_82542_MPTC E1000_MPTC -#define E1000_82542_BPTC E1000_BPTC -#define E1000_82542_TSCTC E1000_TSCTC -#define E1000_82542_TSCTFC E1000_TSCTFC -#define E1000_82542_RXCSUM E1000_RXCSUM -#define E1000_82542_WUC E1000_WUC -#define E1000_82542_WUFC E1000_WUFC -#define E1000_82542_WUS E1000_WUS -#define E1000_82542_MANC E1000_MANC -#define E1000_82542_IPAV E1000_IPAV -#define E1000_82542_IP4AT E1000_IP4AT -#define E1000_82542_IP6AT E1000_IP6AT -#define E1000_82542_WUPL E1000_WUPL -#define E1000_82542_WUPM E1000_WUPM -#define E1000_82542_FFLT E1000_FFLT -#define E1000_82542_TDFH 0x08010 -#define E1000_82542_TDFT 0x08018 -#define E1000_82542_FFMT E1000_FFMT -#define E1000_82542_FFVT E1000_FFVT -#define E1000_82542_HOST_IF E1000_HOST_IF -#define E1000_82542_IAM E1000_IAM -#define E1000_82542_EEMNGCTL E1000_EEMNGCTL -#define E1000_82542_PSRCTL E1000_PSRCTL -#define E1000_82542_RAID E1000_RAID -#define E1000_82542_TARC0 E1000_TARC0 -#define E1000_82542_TDBAL1 E1000_TDBAL1 -#define E1000_82542_TDBAH1 E1000_TDBAH1 -#define E1000_82542_TDLEN1 E1000_TDLEN1 -#define E1000_82542_TDH1 E1000_TDH1 -#define E1000_82542_TDT1 E1000_TDT1 -#define E1000_82542_TXDCTL1 E1000_TXDCTL1 -#define E1000_82542_TARC1 E1000_TARC1 -#define E1000_82542_RFCTL E1000_RFCTL -#define E1000_82542_GCR E1000_GCR -#define E1000_82542_GSCL_1 E1000_GSCL_1 -#define E1000_82542_GSCL_2 E1000_GSCL_2 -#define E1000_82542_GSCL_3 E1000_GSCL_3 -#define E1000_82542_GSCL_4 E1000_GSCL_4 -#define E1000_82542_FACTPS E1000_FACTPS -#define E1000_82542_SWSM E1000_SWSM -#define E1000_82542_FWSM E1000_FWSM -#define E1000_82542_FFLT_DBG E1000_FFLT_DBG -#define E1000_82542_IAC E1000_IAC -#define E1000_82542_ICRXPTC E1000_ICRXPTC -#define E1000_82542_ICRXATC E1000_ICRXATC -#define E1000_82542_ICTXPTC E1000_ICTXPTC -#define E1000_82542_ICTXATC E1000_ICTXATC -#define E1000_82542_ICTXQEC E1000_ICTXQEC -#define E1000_82542_ICTXQMTC E1000_ICTXQMTC -#define E1000_82542_ICRXDMTC E1000_ICRXDMTC -#define E1000_82542_ICRXOC E1000_ICRXOC -#define E1000_82542_HICR E1000_HICR - -#define E1000_82542_CPUVEC E1000_CPUVEC -#define E1000_82542_MRQC E1000_MRQC -#define E1000_82542_RETA E1000_RETA -#define E1000_82542_RSSRK E1000_RSSRK -#define E1000_82542_RSSIM E1000_RSSIM -#define E1000_82542_RSSIR E1000_RSSIR -#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA -#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC - /* Statistics counters collected by the MAC */ struct e1000_hw_stats { - uint64_t crcerrs; - uint64_t algnerrc; - uint64_t symerrs; - uint64_t rxerrc; - uint64_t mpc; - uint64_t scc; - uint64_t ecol; - uint64_t mcc; - uint64_t latecol; - uint64_t colc; - uint64_t dc; - uint64_t tncrs; - uint64_t sec; - uint64_t cexterr; - uint64_t rlec; - uint64_t xonrxc; - uint64_t xontxc; - uint64_t xoffrxc; - uint64_t xofftxc; - uint64_t fcruc; - uint64_t prc64; - uint64_t prc127; - uint64_t prc255; - uint64_t prc511; - uint64_t prc1023; - uint64_t prc1522; - uint64_t gprc; - uint64_t bprc; - uint64_t mprc; - uint64_t gptc; - uint64_t gorcl; - uint64_t gorch; - uint64_t gotcl; - uint64_t gotch; - uint64_t rnbc; - uint64_t ruc; - uint64_t rfc; - uint64_t roc; - uint64_t rjc; - uint64_t mgprc; - uint64_t mgpdc; - uint64_t mgptc; - uint64_t torl; - uint64_t torh; - uint64_t totl; - uint64_t toth; - uint64_t tpr; - uint64_t tpt; - uint64_t ptc64; - uint64_t ptc127; - uint64_t ptc255; - uint64_t ptc511; - uint64_t ptc1023; - uint64_t ptc1522; - uint64_t mptc; - uint64_t bptc; - uint64_t tsctc; - uint64_t tsctfc; - uint64_t iac; - uint64_t icrxptc; - uint64_t icrxatc; - uint64_t ictxptc; - uint64_t ictxatc; - uint64_t ictxqec; - uint64_t ictxqmtc; - uint64_t icrxdmtc; - uint64_t icrxoc; -}; - -/* Structure containing variables used by the shared code (e1000_hw.c) */ -struct e1000_hw { - uint8_t *hw_addr; - uint8_t *flash_address; - e1000_mac_type mac_type; - e1000_phy_type phy_type; - uint32_t phy_init_script; - e1000_media_type media_type; - void *back; - struct e1000_shadow_ram *eeprom_shadow_ram; - uint32_t flash_bank_size; - uint32_t flash_base_addr; - uint32_t fc; - e1000_bus_speed bus_speed; - e1000_bus_width bus_width; - e1000_bus_type bus_type; - struct e1000_eeprom_info eeprom; - e1000_ms_type master_slave; - e1000_ms_type original_master_slave; - e1000_ffe_config ffe_config_state; - uint32_t asf_firmware_present; - uint32_t eeprom_semaphore_present; - uint32_t swfw_sync_present; - uint32_t swfwhw_semaphore_present; - - unsigned long io_base; - uint32_t phy_id; - uint32_t phy_revision; - uint32_t phy_addr; - uint32_t original_fc; - uint32_t txcw; - uint32_t autoneg_failed; - uint32_t max_frame_size; - uint32_t min_frame_size; - uint32_t mc_filter_type; - uint32_t num_mc_addrs; - uint32_t collision_delta; - uint32_t tx_packet_delta; - uint32_t ledctl_default; - uint32_t ledctl_mode1; - uint32_t ledctl_mode2; -#ifndef FIFO_WORKAROUND - uint32_t tx_fifo_size; - uint32_t tx_fifo_start; - uint32_t tx_fifo_head; - uint16_t dsp_reset_counter; -#endif /* FIFO_WORKAROUND */ - boolean_t tx_pkt_filtering; - struct e1000_host_mng_dhcp_cookie mng_cookie; - uint16_t phy_spd_default; - uint16_t autoneg_advertised; - uint16_t pci_cmd_word; - uint16_t fc_high_water; - uint16_t fc_low_water; - uint16_t fc_pause_time; - uint16_t current_ifs_val; - uint16_t ifs_min_val; - uint16_t ifs_max_val; - uint16_t ifs_step_size; - uint16_t ifs_ratio; - uint16_t device_id; - uint16_t vendor_id; - uint16_t subsystem_id; - uint16_t subsystem_vendor_id; - uint8_t revision_id; - uint8_t autoneg; - uint8_t mdix; - uint8_t forced_speed_duplex; - uint8_t wait_autoneg_complete; - uint8_t dma_fairness; - uint8_t mac_addr[NODE_ADDRESS_SIZE]; - uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; - boolean_t disable_polarity_correction; - boolean_t speed_downgraded; - e1000_smart_speed smart_speed; - e1000_dsp_config dsp_config_state; - boolean_t get_link_status; - boolean_t serdes_link_down; - boolean_t tbi_compatibility_en; - boolean_t tbi_compatibility_on; -#ifndef FIFO_WORKAROUND - boolean_t ttl_wa_activation; - boolean_t adapter_stopped; -#endif - boolean_t laa_is_present; - boolean_t phy_reset_disable; - boolean_t initialize_hw_bits_disable; - boolean_t fc_send_xon; - boolean_t fc_strict_ieee; - boolean_t report_tx_early; - boolean_t adaptive_ifs; - boolean_t ifs_params_forced; - boolean_t in_ifs_mode; - boolean_t mng_reg_access_disabled; - boolean_t leave_av_bit_off; - boolean_t kmrn_lock_loss_workaround_disabled; + u64 crcerrs; + u64 algnerrc; + u64 symerrs; + u64 rxerrc; + u64 mpc; + u64 scc; + u64 ecol; + u64 mcc; + u64 latecol; + u64 colc; + u64 dc; + u64 tncrs; + u64 sec; + u64 cexterr; + u64 rlec; + u64 xonrxc; + u64 xontxc; + u64 xoffrxc; + u64 xofftxc; + u64 fcruc; + u64 prc64; + u64 prc127; + u64 prc255; + u64 prc511; + u64 prc1023; + u64 prc1522; + u64 gprc; + u64 bprc; + u64 mprc; + u64 gptc; + u64 gorcl; + u64 gorch; + u64 gotcl; + u64 gotch; + u64 rnbc; + u64 ruc; + u64 rfc; + u64 roc; + u64 rjc; + u64 mgprc; + u64 mgpdc; + u64 mgptc; + u64 torl; + u64 torh; + u64 totl; + u64 toth; + u64 tpr; + u64 tpt; + u64 ptc64; + u64 ptc127; + u64 ptc255; + u64 ptc511; + u64 ptc1023; + u64 ptc1522; + u64 mptc; + u64 bptc; + u64 tsctc; + u64 tsctfc; + u64 iac; + u64 icrxptc; + u64 icrxatc; + u64 ictxptc; + u64 ictxatc; + u64 ictxqec; + u64 ictxqmtc; + u64 icrxdmtc; + u64 icrxoc; + u64 cbtmpc; + u64 htdpmc; + u64 cbrdpc; + u64 cbrmpc; + u64 rpthc; + u64 hgptc; + u64 htcbdpc; + u64 hgorcl; + u64 hgorch; + u64 hgotcl; + u64 hgotch; + u64 lenerrs; + u64 scvpc; + u64 hrmpc; }; - -#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ -#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ -#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ -#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ -#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ -#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ -#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ -#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ -/* Register Bit Masks */ -/* Device Control */ -#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ -#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ -#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ -#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ -#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ -#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ -#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ -#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ -#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ -#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ -#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ -#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ -#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ -#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ -#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ -#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ -#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ -#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ -#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ -#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ -#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ -#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ -#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ -#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ -#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ -#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ -#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ -#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ -#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ -#define E1000_CTRL_RST 0x04000000 /* Global reset */ -#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ -#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ -#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ -#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ -#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ -#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ -/* Device Status */ -#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ -#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ -#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ -#define E1000_STATUS_FUNC_SHIFT 2 -#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ -#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ -#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ -#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ -#define E1000_STATUS_SPEED_MASK 0x000000C0 -#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ -#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ -#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ -#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion - by EEPROM/Flash */ -#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ -#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ -#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ -#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ -#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ -#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ -#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ -#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ -#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ -#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ -#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ -#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ -#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ -#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ -#define E1000_STATUS_FUSE_8 0x04000000 -#define E1000_STATUS_FUSE_9 0x08000000 -#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ -#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ - -/* Constants used to intrepret the masked PCI-X bus speed. */ -#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ -#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ -#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ - -/* EEPROM/Flash Control */ -#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ -#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ -#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ -#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ -#define E1000_EECD_FWE_MASK 0x00000030 -#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ -#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ -#define E1000_EECD_FWE_SHIFT 4 -#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ -#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ -#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ -#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ -#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type - * (0-small, 1-large) */ -#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ -#ifndef E1000_EEPROM_GRANT_ATTEMPTS -#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ -#endif -#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ -#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ -#define E1000_EECD_SIZE_EX_SHIFT 11 -#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ -#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ -#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ -#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ -#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ -#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ -#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ -#define E1000_EECD_SECVAL_SHIFT 22 -#define E1000_STM_OPCODE 0xDB00 -#define E1000_HICR_FW_RESET 0xC0 - -#define E1000_SHADOW_RAM_WORDS 2048 -#define E1000_ICH_NVM_SIG_WORD 0x13 -#define E1000_ICH_NVM_SIG_MASK 0xC0 - -/* EEPROM Read */ -#define E1000_EERD_START 0x00000001 /* Start Read */ -#define E1000_EERD_DONE 0x00000010 /* Read Done */ -#define E1000_EERD_ADDR_SHIFT 8 -#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ -#define E1000_EERD_DATA_SHIFT 16 -#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ - -/* SPI EEPROM Status Register */ -#define EEPROM_STATUS_RDY_SPI 0x01 -#define EEPROM_STATUS_WEN_SPI 0x02 -#define EEPROM_STATUS_BP0_SPI 0x04 -#define EEPROM_STATUS_BP1_SPI 0x08 -#define EEPROM_STATUS_WPEN_SPI 0x80 +struct e1000_phy_stats { + u32 idle_errors; + u32 receive_errors; +}; -/* Extended Device Control */ -#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ -#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ -#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN -#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ -#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ -#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ -#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ -#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA -#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ -#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ -#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ -#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ -#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ -#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ -#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ -#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ -#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ -#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ -#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ -#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 -#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 -#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 -#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 -#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 -#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 -#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 -#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 -#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ -#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ -#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ -#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ -#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ -#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 - -/* MDI Control */ -#define E1000_MDIC_DATA_MASK 0x0000FFFF -#define E1000_MDIC_REG_MASK 0x001F0000 -#define E1000_MDIC_REG_SHIFT 16 -#define E1000_MDIC_PHY_MASK 0x03E00000 -#define E1000_MDIC_PHY_SHIFT 21 -#define E1000_MDIC_OP_WRITE 0x04000000 -#define E1000_MDIC_OP_READ 0x08000000 -#define E1000_MDIC_READY 0x10000000 -#define E1000_MDIC_INT_EN 0x20000000 -#define E1000_MDIC_ERROR 0x40000000 - -#define E1000_KUMCTRLSTA_MASK 0x0000FFFF -#define E1000_KUMCTRLSTA_OFFSET 0x001F0000 -#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 -#define E1000_KUMCTRLSTA_REN 0x00200000 - -#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 -#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 -#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 -#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 -#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 -#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 -#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 -#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E -#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F - -/* FIFO Control */ -#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 -#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 - -/* In-Band Control */ -#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 -#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 - -/* Half-Duplex Control */ -#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 -#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 - -#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E - -#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 -#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 - -#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 -#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 -#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 - -#define E1000_KABGTXD_BGSQLBIAS 0x00050000 - -#define E1000_PHY_CTRL_SPD_EN 0x00000001 -#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 -#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 -#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 -#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 -#define E1000_PHY_CTRL_B2B_EN 0x00000080 - -/* LED Control */ -#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F -#define E1000_LEDCTL_LED0_MODE_SHIFT 0 -#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 -#define E1000_LEDCTL_LED0_IVRT 0x00000040 -#define E1000_LEDCTL_LED0_BLINK 0x00000080 -#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 -#define E1000_LEDCTL_LED1_MODE_SHIFT 8 -#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 -#define E1000_LEDCTL_LED1_IVRT 0x00004000 -#define E1000_LEDCTL_LED1_BLINK 0x00008000 -#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 -#define E1000_LEDCTL_LED2_MODE_SHIFT 16 -#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 -#define E1000_LEDCTL_LED2_IVRT 0x00400000 -#define E1000_LEDCTL_LED2_BLINK 0x00800000 -#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 -#define E1000_LEDCTL_LED3_MODE_SHIFT 24 -#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 -#define E1000_LEDCTL_LED3_IVRT 0x40000000 -#define E1000_LEDCTL_LED3_BLINK 0x80000000 - -#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 -#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 -#define E1000_LEDCTL_MODE_LINK_UP 0x2 -#define E1000_LEDCTL_MODE_ACTIVITY 0x3 -#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 -#define E1000_LEDCTL_MODE_LINK_10 0x5 -#define E1000_LEDCTL_MODE_LINK_100 0x6 -#define E1000_LEDCTL_MODE_LINK_1000 0x7 -#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 -#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 -#define E1000_LEDCTL_MODE_COLLISION 0xA -#define E1000_LEDCTL_MODE_BUS_SPEED 0xB -#define E1000_LEDCTL_MODE_BUS_SIZE 0xC -#define E1000_LEDCTL_MODE_PAUSED 0xD -#define E1000_LEDCTL_MODE_LED_ON 0xE -#define E1000_LEDCTL_MODE_LED_OFF 0xF - -/* Receive Address */ -#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ - -/* Interrupt Cause Read */ -#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ -#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ -#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ -#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ -#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ -#define E1000_ICR_RXO 0x00000040 /* rx overrun */ -#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ -#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ -#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ -#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ -#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ -#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ -#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ -#define E1000_ICR_TXD_LOW 0x00008000 -#define E1000_ICR_SRPD 0x00010000 -#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ -#define E1000_ICR_MNG 0x00040000 /* Manageability event */ -#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ -#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ -#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ -#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ -#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ -#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ -#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ -#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ -#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ -#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ - - -/* Interrupt Cause Set */ -#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ -#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ -#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ -#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ -#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_ICS_SRPD E1000_ICR_SRPD -#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ -#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ -#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ -#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ -#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ -#define E1000_ICS_DSW E1000_ICR_DSW -#define E1000_ICS_PHYINT E1000_ICR_PHYINT -#define E1000_ICS_EPRST E1000_ICR_EPRST - +struct e1000_host_mng_dhcp_cookie { + u32 signature; + u8 status; + u8 reserved0; + u16 vlan_id; + u32 reserved1; + u16 reserved2; + u8 reserved3; + u8 checksum; +}; -/* Interrupt Mask Set */ -#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ -#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ -#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ -#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ -#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMS_SRPD E1000_ICR_SRPD -#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ -#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ -#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ -#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ -#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ -#define E1000_IMS_DSW E1000_ICR_DSW -#define E1000_IMS_PHYINT E1000_ICR_PHYINT -#define E1000_IMS_EPRST E1000_ICR_EPRST - - -/* Interrupt Mask Clear */ -#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ -#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ -#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ -#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ -#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMC_SRPD E1000_ICR_SRPD -#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ -#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ -#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ -#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ -#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ -#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ -#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ -#define E1000_IMC_DSW E1000_ICR_DSW -#define E1000_IMC_PHYINT E1000_ICR_PHYINT -#define E1000_IMC_EPRST E1000_ICR_EPRST - +/* Host Interface "Rev 1" */ +struct e1000_host_command_header { + u8 command_id; + u8 command_length; + u8 command_options; + u8 checksum; +}; -/* Receive Control */ -#define E1000_RCTL_RST 0x00000001 /* Software reset */ -#define E1000_RCTL_EN 0x00000002 /* enable */ -#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ -#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ -#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ -#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ -#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ -#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ -#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ -#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ -#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ -#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ -#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ -#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ -#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ -#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ -#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ -#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ -#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ -#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ -#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ -#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ -/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ -#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ -#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ -#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ -#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ -/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ -#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ -#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ -#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ -#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ -#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ -#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ -#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ -#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ -#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ -#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ -#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ -#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ - -/* Use byte values for the following shift parameters - * Usage: - * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & - * E1000_PSRCTL_BSIZE0_MASK) | - * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & - * E1000_PSRCTL_BSIZE1_MASK) | - * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & - * E1000_PSRCTL_BSIZE2_MASK) | - * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; - * E1000_PSRCTL_BSIZE3_MASK)) - * where value0 = [128..16256], default=256 - * value1 = [1024..64512], default=4096 - * value2 = [0..64512], default=4096 - * value3 = [0..64512], default=0 - */ - -#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F -#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 -#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 -#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 - -#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ -#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ -#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ -#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ - -/* SW_W_SYNC definitions */ -#define E1000_SWFW_EEP_SM 0x0001 -#define E1000_SWFW_PHY0_SM 0x0002 -#define E1000_SWFW_PHY1_SM 0x0004 -#define E1000_SWFW_MAC_CSR_SM 0x0008 - -/* Receive Descriptor */ -#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ -#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ -#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ -#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ -#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ - -/* Flow Control */ -#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ -#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ -#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ -#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ - -/* Flow Control Settings */ -#define E1000_FC_NONE 0 -#define E1000_FC_RX_PAUSE 1 -#define E1000_FC_TX_PAUSE 2 -#define E1000_FC_FULL 3 -#define E1000_FC_DEFAULT 0xFF - -/* Header split receive */ -#define E1000_RFCTL_ISCSI_DIS 0x00000001 -#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E -#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 -#define E1000_RFCTL_NFSW_DIS 0x00000040 -#define E1000_RFCTL_NFSR_DIS 0x00000080 -#define E1000_RFCTL_NFS_VER_MASK 0x00000300 -#define E1000_RFCTL_NFS_VER_SHIFT 8 -#define E1000_RFCTL_IPV6_DIS 0x00000400 -#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 -#define E1000_RFCTL_ACK_DIS 0x00001000 -#define E1000_RFCTL_ACKD_DIS 0x00002000 -#define E1000_RFCTL_IPFRSP_DIS 0x00004000 -#define E1000_RFCTL_EXTEN 0x00008000 -#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 -#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 - -/* Receive Descriptor Control */ -#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ -#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ -#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ -#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ +#define E1000_HI_MAX_DATA_LENGTH 252 +struct e1000_host_command_info { + struct e1000_host_command_header command_header; + u8 command_data[E1000_HI_MAX_DATA_LENGTH]; +}; -/* Transmit Descriptor Control */ -#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ -#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ -#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ -#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ -#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ -#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ -#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. - still to be processed. */ -/* Transmit Configuration Word */ -#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ -#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ -#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ -#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ -#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ -#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ -#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ -#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ -#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ -#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ - -/* Receive Configuration Word */ -#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ -#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ -#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ -#define E1000_RXCW_CC 0x10000000 /* Receive config change */ -#define E1000_RXCW_C 0x20000000 /* Receive config */ -#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ -#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ - -/* Transmit Control */ -#define E1000_TCTL_RST 0x00000001 /* software reset */ -#define E1000_TCTL_EN 0x00000002 /* enable tx */ -#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ -#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ -#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ -#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ -#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ -#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ -#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ -#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ -#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ -/* Extended Transmit Control */ -#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ -#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ - -#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 - -/* Receive Checksum Control */ -#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ -#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ -#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ -#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ -#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ -#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ - -/* Multiple Receive Queue Control */ -#define E1000_MRQC_ENABLE_MASK 0x00000003 -#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 -#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 -#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 -#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 -#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 -#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 -#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 -#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 -#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 - -/* Definitions for power management and wakeup registers */ -/* Wake Up Control */ -#define E1000_WUC_APME 0x00000001 /* APM Enable */ -#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ -#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ -#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ -#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ - -/* Wake Up Filter Control */ -#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ -#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ -#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ -#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ -#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ -#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ -#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ -#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ -#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ -#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ -#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ -#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ -#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ -#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ -#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ -#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ +/* Host Interface "Rev 2" */ +struct e1000_host_mng_command_header { + u8 command_id; + u8 checksum; + u16 reserved1; + u16 reserved2; + u16 command_length; +}; -/* Wake Up Status */ -#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ -#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ -#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ -#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ -#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ -#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ -#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ -#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ -#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ -#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ -#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ -#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ -#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ - -/* Management Control */ -#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ -#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ -#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ -#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ -#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ -#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ -#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ -#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ -#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ -#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery - * Filtering */ -#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ -#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ -#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ -#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ -#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ -#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ -#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address - * filtering */ -#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host - * memory */ -#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address - * filtering */ -#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ -#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ -#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ -#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ -#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ -#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ -#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ -#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ - -#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ -#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ - -/* SW Semaphore Register */ -#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ -#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ -#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ -#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ - -/* FW Semaphore Register */ -#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ -#define E1000_FWSM_MODE_SHIFT 1 -#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ - -#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ -#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ -#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ -#define E1000_FWSM_SKUEL_SHIFT 29 -#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ -#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ -#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ -#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ - -/* FFLT Debug Register */ -#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ - -typedef enum { - e1000_mng_mode_none = 0, - e1000_mng_mode_asf, - e1000_mng_mode_pt, - e1000_mng_mode_ipmi, - e1000_mng_mode_host_interface_only -} e1000_mng_mode; - -/* Host Inteface Control Register */ -#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ -#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done - * to put command in RAM */ -#define E1000_HICR_SV 0x00000004 /* Status Validity */ -#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ - -/* Host Interface Command Interface - Address range 0x8800-0x8EFF */ -#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ -#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ -#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ -#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ - -struct e1000_host_command_header { - uint8_t command_id; - uint8_t command_length; - uint8_t command_options; /* I/F bits for command, status for return */ - uint8_t checksum; -}; -struct e1000_host_command_info { - struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ - uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 +struct e1000_host_mng_command_info { + struct e1000_host_mng_command_header command_header; + u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; }; -/* Host SMB register #0 */ -#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ -#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ -#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ -#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ - -/* Host SMB register #1 */ -#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN -#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN -#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT -#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT - -/* FW Status Register */ -#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ - -/* Wake Up Packet Length */ -#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ - -#define E1000_MDALIGN 4096 - -/* PCI-Ex registers*/ - -/* PCI-Ex Control Register */ -#define E1000_GCR_RXD_NO_SNOOP 0x00000001 -#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 -#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 -#define E1000_GCR_TXD_NO_SNOOP 0x00000008 -#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 -#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 - -#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ - E1000_GCR_RXDSCW_NO_SNOOP | \ - E1000_GCR_RXDSCR_NO_SNOOP | \ - E1000_GCR_TXD_NO_SNOOP | \ - E1000_GCR_TXDSCW_NO_SNOOP | \ - E1000_GCR_TXDSCR_NO_SNOOP) - -#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL - -#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 -/* Function Active and Power State to MNG */ -#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 -#define E1000_FACTPS_LAN0_VALID 0x00000004 -#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 -#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 -#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 -#define E1000_FACTPS_LAN1_VALID 0x00000100 -#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 -#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 -#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 -#define E1000_FACTPS_IDE_ENABLE 0x00004000 -#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 -#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 -#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 -#define E1000_FACTPS_SP_ENABLE 0x00100000 -#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 -#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 -#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 -#define E1000_FACTPS_IPMI_ENABLE 0x04000000 -#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 -#define E1000_FACTPS_MNGCG 0x20000000 -#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 -#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 - -/* PCI-Ex Config Space */ -#define PCI_EX_CONF_CAP 0xE0 - -#define PCI_EX_LINK_STATUS 0x12 -#define PCI_EX_LINK_WIDTH_MASK 0x3F0 -#define PCI_EX_LINK_WIDTH_SHIFT 4 - -/* EEPROM Commands - Microwire */ -#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ -#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ -#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ -#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ -#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ - -/* EEPROM Commands - SPI */ -#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ -#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ -#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ -#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ -#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ -#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ -#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ -#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ -#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ -#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ -#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ - -/* EEPROM Size definitions */ -#define EEPROM_WORD_SIZE_SHIFT 6 -#define EEPROM_SIZE_SHIFT 10 -#define EEPROM_SIZE_MASK 0x1C00 - -/* EEPROM Word Offsets */ -#define EEPROM_COMPAT 0x0003 -#define EEPROM_ID_LED_SETTINGS 0x0004 -#define EEPROM_VERSION 0x0005 -#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ -#define EEPROM_PHY_CLASS_WORD 0x0007 -#define EEPROM_INIT_CONTROL1_REG 0x000A -#define EEPROM_INIT_CONTROL2_REG 0x000F -#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 -#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 -#define EEPROM_INIT_3GIO_3 0x001A -#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 -#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 -#define EEPROM_CFG 0x0012 -#define EEPROM_FLASH_VERSION 0x0032 -#define EEPROM_CHECKSUM_REG 0x003F - -#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ -#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ - -/* Word definitions for ID LED Settings */ -#define ID_LED_RESERVED_0000 0x0000 -#define ID_LED_RESERVED_FFFF 0xFFFF -#define ID_LED_RESERVED_82573 0xF746 -#define ID_LED_DEFAULT_82573 0x1811 -#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ - (ID_LED_OFF1_OFF2 << 8) | \ - (ID_LED_DEF1_DEF2 << 4) | \ - (ID_LED_DEF1_DEF2)) -#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ - (ID_LED_DEF1_OFF2 << 8) | \ - (ID_LED_DEF1_ON2 << 4) | \ - (ID_LED_DEF1_DEF2)) -#define ID_LED_DEF1_DEF2 0x1 -#define ID_LED_DEF1_ON2 0x2 -#define ID_LED_DEF1_OFF2 0x3 -#define ID_LED_ON1_DEF2 0x4 -#define ID_LED_ON1_ON2 0x5 -#define ID_LED_ON1_OFF2 0x6 -#define ID_LED_OFF1_DEF2 0x7 -#define ID_LED_OFF1_ON2 0x8 -#define ID_LED_OFF1_OFF2 0x9 - -#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF -#define IGP_ACTIVITY_LED_ENABLE 0x0300 -#define IGP_LED3_MODE 0x07000000 - - -/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ -#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F - -/* Mask bit for PHY class in Word 7 of the EEPROM */ -#define EEPROM_PHY_CLASS_A 0x8000 - -/* Mask bits for fields in Word 0x0a of the EEPROM */ -#define EEPROM_WORD0A_ILOS 0x0010 -#define EEPROM_WORD0A_SWDPIO 0x01E0 -#define EEPROM_WORD0A_LRST 0x0200 -#define EEPROM_WORD0A_FD 0x0400 -#define EEPROM_WORD0A_66MHZ 0x0800 - -/* Mask bits for fields in Word 0x0f of the EEPROM */ -#define EEPROM_WORD0F_PAUSE_MASK 0x3000 -#define EEPROM_WORD0F_PAUSE 0x1000 -#define EEPROM_WORD0F_ASM_DIR 0x2000 -#define EEPROM_WORD0F_ANE 0x0800 -#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 -#define EEPROM_WORD0F_LPLU 0x0001 - -/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */ -#define EEPROM_WORD1020_GIGA_DISABLE 0x0010 -#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008 - -/* Mask bits for fields in Word 0x1a of the EEPROM */ -#define EEPROM_WORD1A_ASPM_MASK 0x000C - -/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ -#define EEPROM_SUM 0xBABA - -/* EEPROM Map defines (WORD OFFSETS)*/ -#define EEPROM_NODE_ADDRESS_BYTE_0 0 -#define EEPROM_PBA_BYTE_1 8 - -#define EEPROM_RESERVED_WORD 0xFFFF - -/* EEPROM Map Sizes (Byte Counts) */ -#define PBA_SIZE 4 - -/* Collision related configuration parameters */ -#define E1000_COLLISION_THRESHOLD 15 -#define E1000_CT_SHIFT 4 -/* Collision distance is a 0-based value that applies to - * half-duplex-capable hardware only. */ -#define E1000_COLLISION_DISTANCE 63 -#define E1000_COLLISION_DISTANCE_82542 64 -#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE -#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE -#define E1000_COLD_SHIFT 12 - -/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ -#define REQ_TX_DESCRIPTOR_MULTIPLE 8 -#define REQ_RX_DESCRIPTOR_MULTIPLE 8 - -/* Default values for the transmit IPG register */ -#define DEFAULT_82542_TIPG_IPGT 10 -#define DEFAULT_82543_TIPG_IPGT_FIBER 9 -#define DEFAULT_82543_TIPG_IPGT_COPPER 8 - -#define E1000_TIPG_IPGT_MASK 0x000003FF -#define E1000_TIPG_IPGR1_MASK 0x000FFC00 -#define E1000_TIPG_IPGR2_MASK 0x3FF00000 - -#define DEFAULT_82542_TIPG_IPGR1 2 -#define DEFAULT_82543_TIPG_IPGR1 8 -#define E1000_TIPG_IPGR1_SHIFT 10 - -#define DEFAULT_82542_TIPG_IPGR2 10 -#define DEFAULT_82543_TIPG_IPGR2 6 -#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 -#define E1000_TIPG_IPGR2_SHIFT 20 - -#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 -#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 -#define E1000_TXDMAC_DPP 0x00000001 - -/* Adaptive IFS defines */ -#define TX_THRESHOLD_START 8 -#define TX_THRESHOLD_INCREMENT 10 -#define TX_THRESHOLD_DECREMENT 1 -#define TX_THRESHOLD_STOP 190 -#define TX_THRESHOLD_DISABLE 0 -#define TX_THRESHOLD_TIMER_MS 10000 -#define MIN_NUM_XMITS 1000 -#define IFS_MAX 80 -#define IFS_STEP 10 -#define IFS_MIN 40 -#define IFS_RATIO 4 - -/* Extended Configuration Control and Size */ -#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 -#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 -#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 -#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 -#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 -#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 -#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 -#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000 - -#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF -#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 -#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 -#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 -#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 - -/* PBA constants */ -#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ -#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ -#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ -#define E1000_PBA_22K 0x0016 -#define E1000_PBA_24K 0x0018 -#define E1000_PBA_30K 0x001E -#define E1000_PBA_32K 0x0020 -#define E1000_PBA_34K 0x0022 -#define E1000_PBA_38K 0x0026 -#define E1000_PBA_40K 0x0028 -#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ - -#define E1000_PBS_16K E1000_PBA_16K - -#ifndef FIFO_WORKAROUND -/* FIFO constants */ -#define E1000_FIFO_GRANULARITY 0x10 -#define E1000_FIFO_MULTIPLIER 0x80 -#define E1000_FIFO_HDR_SIZE 0x10 -#define E1000_82547_FIFO_PAD 0x3E0 - -#define E1000_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) - -#endif /* FIFO_WORKAROUND */ -/* Flow Control Constants */ -#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 -#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 -#define FLOW_CONTROL_TYPE 0x8808 - -/* The historical defaults for the flow control values are given below. */ -#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ -#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ -#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ - -/* PCIX Config space */ -#define PCIX_COMMAND_REGISTER 0xE6 -#define PCIX_STATUS_REGISTER_LO 0xE8 -#define PCIX_STATUS_REGISTER_HI 0xEA - -#define PCIX_COMMAND_MMRBC_MASK 0x000C -#define PCIX_COMMAND_MMRBC_SHIFT 0x2 -#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 -#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 -#define PCIX_STATUS_HI_MMRBC_4K 0x3 -#define PCIX_STATUS_HI_MMRBC_2K 0x2 - - -/* Number of bits required to shift right the "pause" bits from the - * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. - */ -#define PAUSE_SHIFT 5 - -/* Number of bits required to shift left the "SWDPIO" bits from the - * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. - */ -#define SWDPIO_SHIFT 17 - -/* Number of bits required to shift left the "SWDPIO_EXT" bits from the - * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. - */ -#define SWDPIO__EXT_SHIFT 4 - -/* Number of bits required to shift left the "ILOS" bit from the EEPROM - * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. - */ -#define ILOS_SHIFT 3 - - -#define RECEIVE_BUFFER_ALIGN_SIZE (256) - -/* Number of milliseconds we wait for auto-negotiation to complete */ -#define LINK_UP_TIMEOUT 500 - -/* Number of 100 microseconds we wait for PCI Express master disable */ -#define MASTER_DISABLE_TIMEOUT 800 -/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ -#define AUTO_READ_DONE_TIMEOUT 10 -/* Number of milliseconds we wait for PHY configuration done after MAC reset */ -#define PHY_CFG_TIMEOUT 100 - -#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) - -/* The carrier extension symbol, as received by the NIC. */ -#define CARRIER_EXTENSION 0x0F - -/* TBI_ACCEPT macro definition: - * - * This macro requires: - * adapter = a pointer to struct e1000_hw - * status = the 8 bit status field of the RX descriptor with EOP set - * error = the 8 bit error field of the RX descriptor with EOP set - * length = the sum of all the length fields of the RX descriptors that - * make up the current frame - * last_byte = the last byte of the frame DMAed by the hardware - * max_frame_length = the maximum frame length we want to accept. - * min_frame_length = the minimum frame length we want to accept. - * - * This macro is a conditional that should be used in the interrupt - * handler's Rx processing routine when RxErrors have been detected. - * - * Typical use: - * ... - * if (TBI_ACCEPT) { - * accept_frame = TRUE; - * e1000_tbi_adjust_stats(adapter, MacAddress); - * frame_length--; - * } else { - * accept_frame = FALSE; - * } - * ... - */ - -#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ - ((adapter)->tbi_compatibility_on && \ - (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ - ((last_byte) == CARRIER_EXTENSION) && \ - (((status) & E1000_RXD_STAT_VP) ? \ - (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ - ((length) <= ((adapter)->max_frame_size + 1))) : \ - (((length) > (adapter)->min_frame_size) && \ - ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) - - -/* Structures, enums, and macros for the PHY */ - -/* Bit definitions for the Management Data IO (MDIO) and Management Data - * Clock (MDC) pins in the Device Control Register. - */ -#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 -#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 -#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 -#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 -#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 -#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 -#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR -#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA - - -/* PHY 1000 MII Register/Bit Definitions */ -/* PHY Registers defined by IEEE */ -#define PHY_CTRL 0x00 /* Control Register */ -#define PHY_STATUS 0x01 /* Status Regiser */ -#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ -#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ -#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ -#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ -#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ -#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ -#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ -#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ -#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ -#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ - -#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ -#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ - -/* M88E1000 Specific Registers */ -#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ -#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ -#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ -#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ -#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ -#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ - -#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ -#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ -#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ -#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ -#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ - -#define IGP01E1000_IEEE_REGS_PAGE 0x0000 -#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 -#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 - -/* IGP01E1000 Specific Registers */ -#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ -#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ -#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ -#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ -#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ -#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ -#define IGP02E1000_PHY_POWER_MGMT 0x19 -#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ - -/* IGP01E1000 AGC Registers - stores the cable length values*/ -#define IGP01E1000_PHY_AGC_A 0x1172 -#define IGP01E1000_PHY_AGC_B 0x1272 -#define IGP01E1000_PHY_AGC_C 0x1472 -#define IGP01E1000_PHY_AGC_D 0x1872 - -/* IGP02E1000 AGC Registers for cable length values */ -#define IGP02E1000_PHY_AGC_A 0x11B1 -#define IGP02E1000_PHY_AGC_B 0x12B1 -#define IGP02E1000_PHY_AGC_C 0x14B1 -#define IGP02E1000_PHY_AGC_D 0x18B1 - -/* IGP01E1000 DSP Reset Register */ -#define IGP01E1000_PHY_DSP_RESET 0x1F33 -#define IGP01E1000_PHY_DSP_SET 0x1F71 -#define IGP01E1000_PHY_DSP_FFE 0x1F35 - -#define IGP01E1000_PHY_CHANNEL_NUM 4 -#define IGP02E1000_PHY_CHANNEL_NUM 4 - -#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 -#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 -#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 -#define IGP01E1000_PHY_AGC_PARAM_D 0x1871 - -#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 -#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 - -#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 -#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 -#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 -#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 - -#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A -/* IGP01E1000 PCS Initialization register - stores the polarity status when - * speed = 1000 Mbps. */ -#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 -#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 - -#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 - -/* Bits... - * 15-5: page - * 4-0: register offset - */ -#define GG82563_PAGE_SHIFT 5 -#define GG82563_REG(page, reg) \ - (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) -#define GG82563_MIN_ALT_REG 30 - -/* GG82563 Specific Registers */ -#define GG82563_PHY_SPEC_CTRL \ - GG82563_REG(0, 16) /* PHY Specific Control */ -#define GG82563_PHY_SPEC_STATUS \ - GG82563_REG(0, 17) /* PHY Specific Status */ -#define GG82563_PHY_INT_ENABLE \ - GG82563_REG(0, 18) /* Interrupt Enable */ -#define GG82563_PHY_SPEC_STATUS_2 \ - GG82563_REG(0, 19) /* PHY Specific Status 2 */ -#define GG82563_PHY_RX_ERR_CNTR \ - GG82563_REG(0, 21) /* Receive Error Counter */ -#define GG82563_PHY_PAGE_SELECT \ - GG82563_REG(0, 22) /* Page Select */ -#define GG82563_PHY_SPEC_CTRL_2 \ - GG82563_REG(0, 26) /* PHY Specific Control 2 */ -#define GG82563_PHY_PAGE_SELECT_ALT \ - GG82563_REG(0, 29) /* Alternate Page Select */ -#define GG82563_PHY_TEST_CLK_CTRL \ - GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ - -#define GG82563_PHY_MAC_SPEC_CTRL \ - GG82563_REG(2, 21) /* MAC Specific Control Register */ -#define GG82563_PHY_MAC_SPEC_CTRL_2 \ - GG82563_REG(2, 26) /* MAC Specific Control 2 */ - -#define GG82563_PHY_DSP_DISTANCE \ - GG82563_REG(5, 26) /* DSP Distance */ - -/* Page 193 - Port Control Registers */ -#define GG82563_PHY_KMRN_MODE_CTRL \ - GG82563_REG(193, 16) /* Kumeran Mode Control */ -#define GG82563_PHY_PORT_RESET \ - GG82563_REG(193, 17) /* Port Reset */ -#define GG82563_PHY_REVISION_ID \ - GG82563_REG(193, 18) /* Revision ID */ -#define GG82563_PHY_DEVICE_ID \ - GG82563_REG(193, 19) /* Device ID */ -#define GG82563_PHY_PWR_MGMT_CTRL \ - GG82563_REG(193, 20) /* Power Management Control */ -#define GG82563_PHY_RATE_ADAPT_CTRL \ - GG82563_REG(193, 25) /* Rate Adaptation Control */ - -/* Page 194 - KMRN Registers */ -#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ - GG82563_REG(194, 16) /* FIFO's Control/Status */ -#define GG82563_PHY_KMRN_CTRL \ - GG82563_REG(194, 17) /* Control */ -#define GG82563_PHY_INBAND_CTRL \ - GG82563_REG(194, 18) /* Inband Control */ -#define GG82563_PHY_KMRN_DIAGNOSTIC \ - GG82563_REG(194, 19) /* Diagnostic */ -#define GG82563_PHY_ACK_TIMEOUTS \ - GG82563_REG(194, 20) /* Acknowledge Timeouts */ -#define GG82563_PHY_ADV_ABILITY \ - GG82563_REG(194, 21) /* Advertised Ability */ -#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ - GG82563_REG(194, 23) /* Link Partner Advertised Ability */ -#define GG82563_PHY_ADV_NEXT_PAGE \ - GG82563_REG(194, 24) /* Advertised Next Page */ -#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ - GG82563_REG(194, 25) /* Link Partner Advertised Next page */ -#define GG82563_PHY_KMRN_MISC \ - GG82563_REG(194, 26) /* Misc. */ - -/* PHY Control Register */ -#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ -#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ -#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ -#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ -#define MII_CR_POWER_DOWN 0x0800 /* Power down */ -#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ -#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ -#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ - -/* PHY Status Register */ -#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ -#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ -#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ -#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ -#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ -#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ -#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ -#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ -#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ -#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ -#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ -#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ -#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ -#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ -#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ +#include "e1000_mac.h" +#include "e1000_phy.h" +#include "e1000_nvm.h" +#include "e1000_manage.h" -/* Autoneg Advertisement Register */ -#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ -#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ -#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ -#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ -#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ -#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ -#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ -#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ -#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ -#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ - -/* Link Partner Ability Register (Base Page) */ -#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ -#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ -#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ -#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ -#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ -#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ -#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ -#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ -#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ -#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ -#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ - -/* Autoneg Expansion Register */ -#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ -#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ -#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ -#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ -#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ - -/* Next Page TX Register */ -#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ -#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges - * of different NP - */ -#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg - * 0 = cannot comply with msg - */ -#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ -#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow - * 0 = sending last NP - */ - -/* Link Partner Next Page Register */ -#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ -#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges - * of different NP - */ -#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg - * 0 = cannot comply with msg - */ -#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ -#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ -#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow - * 0 = sending last NP - */ - -/* 1000BASE-T Control Register */ -#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ -#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ -#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ -#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ - /* 0=DTE device */ -#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ - /* 0=Configure PHY as Slave */ -#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ - /* 0=Automatic Master/Slave config */ -#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ -#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ -#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ -#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ -#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ - -/* 1000BASE-T Status Register */ -#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ -#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ -#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ -#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ -#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ -#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ -#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ -#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ -#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 -#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 -#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 -#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 -#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 - -/* Extended Status Register */ -#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ -#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ -#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ -#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ - -#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ -#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ - -#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ - /* (0=enable, 1=disable) */ - -/* M88E1000 PHY Specific Control Register */ -#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ -#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ -#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ -#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, - * 0=CLK125 toggling - */ -#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ -#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ -#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, - * 100BASE-TX/10BASE-T: - * MDI Mode - */ -#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled - * all speeds. - */ -#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 - /* 1=Enable Extended 10BASE-T distance - * (Lower 10BASE-T RX Threshold) - * 0=Normal 10BASE-T RX Threshold */ -#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 - /* 1=5-Bit interface in 100BASE-TX - * 0=MII interface in 100BASE-TX */ -#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ -#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ -#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ - -#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 -#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 -#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 - -/* M88E1000 PHY Specific Status Register */ -#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ -#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ -#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ -#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ -#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; - * 3=110-140M;4=>140M */ -#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ -#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ -#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ -#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ -#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ -#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ -#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ -#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ - -#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 -#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 -#define M88E1000_PSSR_MDIX_SHIFT 6 -#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 - -/* M88E1000 Extended PHY Specific Control Register */ -#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ -#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. - * Will assert lost lock and bring - * link down if idle not seen - * within 1ms in 1000BASE-T - */ -/* Number of times we will attempt to autonegotiate before downshifting if we - * are the master */ -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 -/* Number of times we will attempt to autonegotiate before downshifting if we - * are the slave */ -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 -#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ - -/* M88EC018 Rev 2 specific DownShift settings */ -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 - -/* IGP01E1000 Specific Port Config Register - R/W */ -#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 -#define IGP01E1000_PSCFR_PRE_EN 0x0020 -#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 -#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 -#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 -#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 - -/* IGP01E1000 Specific Port Status Register - R/O */ -#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ -#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 -#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C -#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 -#define IGP01E1000_PSSR_LINK_UP 0x0400 -#define IGP01E1000_PSSR_MDIX 0x0800 -#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ -#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 -#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 -#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 -#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ -#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ - -/* IGP01E1000 Specific Port Control Register - R/W */ -#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 -#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 -#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 -#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 -#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 -#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ - -/* IGP01E1000 Specific Port Link Health Register */ -#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 -#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 -#define IGP01E1000_PLHR_MASTER_FAULT 0x2000 -#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 -#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ -#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ -#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ -#define IGP01E1000_PLHR_DATA_ERR_0 0x0100 -#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 -#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 -#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 -#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 -#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 -#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 - -/* IGP01E1000 Channel Quality Register */ -#define IGP01E1000_MSE_CHANNEL_D 0x000F -#define IGP01E1000_MSE_CHANNEL_C 0x00F0 -#define IGP01E1000_MSE_CHANNEL_B 0x0F00 -#define IGP01E1000_MSE_CHANNEL_A 0xF000 - -#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ -#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ -#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ - -/* IGP01E1000 DSP reset macros */ -#define DSP_RESET_ENABLE 0x0 -#define DSP_RESET_DISABLE 0x2 -#define E1000_MAX_DSP_RESETS 10 - -/* IGP01E1000 & IGP02E1000 AGC Registers */ - -#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ -#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ - -/* IGP02E1000 AGC Register Length 9-bit mask */ -#define IGP02E1000_AGC_LENGTH_MASK 0x7F - -/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ -#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 -#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 - -/* The precision error of the cable length is +/- 10 meters */ -#define IGP01E1000_AGC_RANGE 10 -#define IGP02E1000_AGC_RANGE 15 - -/* IGP01E1000 PCS Initialization register */ -/* bits 3:6 in the PCS registers stores the channels polarity */ -#define IGP01E1000_PHY_POLARITY_MASK 0x0078 - -/* IGP01E1000 GMII FIFO Register */ -#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed - * on Link-Up */ -#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ - -/* IGP01E1000 Analog Register */ -#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 -#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 -#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC -#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE - -#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 -#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 -#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 -#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 -#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 - -#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 -#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 -#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 -#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 +struct e1000_functions { + /* Function pointers for the MAC. */ + s32 (*init_mac_params)(struct e1000_hw *); + s32 (*blink_led)(struct e1000_hw *); + s32 (*check_for_link)(struct e1000_hw *); + boolean_t (*check_mng_mode)(struct e1000_hw *hw); + s32 (*cleanup_led)(struct e1000_hw *); + void (*clear_hw_cntrs)(struct e1000_hw *); + void (*clear_vfta)(struct e1000_hw *); + s32 (*get_bus_info)(struct e1000_hw *); + s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); + s32 (*led_on)(struct e1000_hw *); + s32 (*led_off)(struct e1000_hw *); + void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32, u32); + void (*remove_device)(struct e1000_hw *); + s32 (*reset_hw)(struct e1000_hw *); + s32 (*init_hw)(struct e1000_hw *); + s32 (*setup_link)(struct e1000_hw *); + s32 (*setup_physical_interface)(struct e1000_hw *); + s32 (*setup_led)(struct e1000_hw *); + void (*write_vfta)(struct e1000_hw *, u32, u32); + void (*mta_set)(struct e1000_hw *, u32); + void (*config_collision_dist)(struct e1000_hw *); + void (*rar_set)(struct e1000_hw *, u8 *, u32); + s32 (*validate_mdi_setting)(struct e1000_hw *); + s32 (*mng_host_if_write)(struct e1000_hw *, u8 *, u16, u16, u8 *); + s32 (*mng_write_cmd_header)(struct e1000_hw *hw, + struct e1000_host_mng_command_header *); + s32 (*mng_enable_host_if)(struct e1000_hw *); + s32 (*wait_autoneg) (struct e1000_hw *); -/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ -#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ -#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ -#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ -#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ -#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 -#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ -#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ -#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ -#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ -#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 -#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ -#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ -#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ -#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ -#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ -#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 -#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 - -/* PHY Specific Status Register (Page 0, Register 17) */ -#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ -#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ -#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ -#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ -#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ -#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ -#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ -#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ -#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ -#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ -#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ -#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ -#define GG82563_PSSR_SPEED_MASK 0xC000 -#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ -#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ -#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ - -/* PHY Specific Status Register 2 (Page 0, Register 19) */ -#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ -#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ -#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ -#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ -#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ -#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ -#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ -#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ -#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ -#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ -#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ -#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ -#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ - -/* PHY Specific Control Register 2 (Page 0, Register 26) */ -#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ -#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C -#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ -#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ -#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ -#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ -#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ -#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 -#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ -#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ - -/* MAC Specific Control Register (Page 2, Register 21) */ -/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ -#define GG82563_MSCR_TX_CLK_MASK 0x0007 -#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 -#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 -#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 -#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 - -#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ - -/* DSP Distance Register (Page 5, Register 26) */ -#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; - 1 = 50-80M; - 2 = 80-110M; - 3 = 110-140M; - 4 = >140M */ - -/* Kumeran Mode Control Register (Page 193, Register 16) */ -#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ -#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ -#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 -#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 -#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ -#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 - -/* Power Management Control Register (Page 193, Register 20) */ -#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */ -#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ -#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ -#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ -#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ -#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ -#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ -#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ -#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 -#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ -#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ -#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ -#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ - -/* In-Band Control Register (Page 194, Register 18) */ -#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ - - -/* Bit definitions for valid PHY IDs. */ -/* I = Integrated - * E = External - */ -#define M88_VENDOR 0x0141 -#define M88E1000_E_PHY_ID 0x01410C50 -#define M88E1000_I_PHY_ID 0x01410C30 -#define M88E1011_I_PHY_ID 0x01410C20 -#define IGP01E1000_I_PHY_ID 0x02A80380 -#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID -#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID -#define M88E1011_I_REV_4 0x04 -#define M88E1111_I_PHY_ID 0x01410CC0 -#define L1LXT971A_PHY_ID 0x001378E0 -#define GG82563_E_PHY_ID 0x01410CA0 - - -/* Bits... - * 15-5: page - * 4-0: register offset - */ -#define PHY_PAGE_SHIFT 5 -#define PHY_REG(page, reg) \ - (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) - -#define IGP3_PHY_PORT_CTRL \ - PHY_REG(769, 17) /* Port General Configuration */ -#define IGP3_PHY_RATE_ADAPT_CTRL \ - PHY_REG(769, 25) /* Rate Adapter Control Register */ - -#define IGP3_KMRN_FIFO_CTRL_STATS \ - PHY_REG(770, 16) /* KMRN FIFO's control/status register */ -#define IGP3_KMRN_POWER_MNG_CTRL \ - PHY_REG(770, 17) /* KMRN Power Management Control Register */ -#define IGP3_KMRN_INBAND_CTRL \ - PHY_REG(770, 18) /* KMRN Inband Control Register */ -#define IGP3_KMRN_DIAG \ - PHY_REG(770, 19) /* KMRN Diagnostic register */ -#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ -#define IGP3_KMRN_ACK_TIMEOUT \ - PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ + /* Function pointers for the PHY. */ + s32 (*init_phy_params)(struct e1000_hw *); + s32 (*acquire_phy)(struct e1000_hw *); + s32 (*check_polarity)(struct e1000_hw *); + s32 (*check_reset_block)(struct e1000_hw *); + s32 (*commit_phy)(struct e1000_hw *); + s32 (*force_speed_duplex)(struct e1000_hw *); + s32 (*get_cfg_done)(struct e1000_hw *hw); + s32 (*get_cable_length)(struct e1000_hw *); + s32 (*get_phy_info)(struct e1000_hw *); + s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); + void (*release_phy)(struct e1000_hw *); + s32 (*reset_phy)(struct e1000_hw *); + s32 (*set_d0_lplu_state)(struct e1000_hw *, boolean_t); + s32 (*set_d3_lplu_state)(struct e1000_hw *, boolean_t); + s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); -#define IGP3_VR_CTRL \ - PHY_REG(776, 18) /* Voltage regulator control register */ -#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ -#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ - -#define IGP3_CAPABILITY \ - PHY_REG(776, 19) /* IGP3 Capability Register */ - -/* Capabilities for SKU Control */ -#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ -#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ -#define IGP3_CAP_ASF 0x0004 /* Support ASF */ -#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ -#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ -#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ -#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ -#define IGP3_CAP_RSS 0x0080 /* Support RSS */ -#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ -#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ - -#define IGP3_PPC_JORDAN_EN 0x0001 -#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 - -#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001 -#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E -#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 -#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 - -#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ -#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ - -#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) -#define IGP3_KMRN_EC_DIS_INBAND 0x0080 - -#define IGP03E1000_E_PHY_ID 0x02A80390 -#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ -#define IFE_PLUS_E_PHY_ID 0x02A80320 -#define IFE_C_E_PHY_ID 0x02A80310 - -#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ -#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ -#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ -#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ -#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ -#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ -#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ -#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ -#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ -#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ -#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ -#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ -#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ - -#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ -#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ -#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ -#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ -#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ -#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ -#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ -#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 - -#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ -#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ -#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ -#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ -#define IFE_PSC_FORCE_POLARITY_SHIFT 5 -#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 - -#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ -#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ -#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ -#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */ -#define IFE_PMC_MDIX_MODE_SHIFT 6 -#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ - -#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ -#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ -#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ -#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ -#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ -#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ -#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ -#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ -#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ -#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ -#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ - -#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ -#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ -#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ -#define ICH_FLASH_SEG_SIZE_256 256 -#define ICH_FLASH_SEG_SIZE_4K 4096 -#define ICH_FLASH_SEG_SIZE_64K 65536 - -#define ICH_CYCLE_READ 0x0 -#define ICH_CYCLE_RESERVED 0x1 -#define ICH_CYCLE_WRITE 0x2 -#define ICH_CYCLE_ERASE 0x3 - -#define ICH_FLASH_GFPREG 0x0000 -#define ICH_FLASH_HSFSTS 0x0004 -#define ICH_FLASH_HSFCTL 0x0006 -#define ICH_FLASH_FADDR 0x0008 -#define ICH_FLASH_FDATA0 0x0010 -#define ICH_FLASH_FRACC 0x0050 -#define ICH_FLASH_FREG0 0x0054 -#define ICH_FLASH_FREG1 0x0058 -#define ICH_FLASH_FREG2 0x005C -#define ICH_FLASH_FREG3 0x0060 -#define ICH_FLASH_FPR0 0x0074 -#define ICH_FLASH_FPR1 0x0078 -#define ICH_FLASH_SSFSTS 0x0090 -#define ICH_FLASH_SSFCTL 0x0092 -#define ICH_FLASH_PREOP 0x0094 -#define ICH_FLASH_OPTYPE 0x0096 -#define ICH_FLASH_OPMENU 0x0098 - -#define ICH_FLASH_REG_MAPSIZE 0x00A0 -#define ICH_FLASH_SECTOR_SIZE 4096 -#define ICH_GFPREG_BASE_MASK 0x1FFF -#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF - -/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ -/* Offset 04h HSFSTS */ -union ich8_hws_flash_status { - struct ich8_hsfsts { -#ifdef E1000_BIG_ENDIAN - uint16_t reserved2 :6; - uint16_t fldesvalid :1; - uint16_t flockdn :1; - uint16_t flcdone :1; - uint16_t flcerr :1; - uint16_t dael :1; - uint16_t berasesz :2; - uint16_t flcinprog :1; - uint16_t reserved1 :2; -#else - uint16_t flcdone :1; /* bit 0 Flash Cycle Done */ - uint16_t flcerr :1; /* bit 1 Flash Cycle Error */ - uint16_t dael :1; /* bit 2 Direct Access error Log */ - uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */ - uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */ - uint16_t reserved1 :2; /* bit 13:6 Reserved */ - uint16_t reserved2 :6; /* bit 13:6 Reserved */ - uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */ - uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */ -#endif - } hsf_status; - uint16_t regval; + /* Function pointers for the NVM. */ + s32 (*init_nvm_params)(struct e1000_hw *); + s32 (*acquire_nvm)(struct e1000_hw *); + s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); + void (*release_nvm)(struct e1000_hw *); + void (*reload_nvm)(struct e1000_hw *); + s32 (*update_nvm)(struct e1000_hw *); + s32 (*valid_led_default)(struct e1000_hw *, u16 *); + s32 (*validate_nvm)(struct e1000_hw *); + s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); }; -/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ -/* Offset 06h FLCTL */ -union ich8_hws_flash_ctrl { - struct ich8_hsflctl { -#ifdef E1000_BIG_ENDIAN - uint16_t fldbcount :2; - uint16_t flockdn :6; - uint16_t flcgo :1; - uint16_t flcycle :2; - uint16_t reserved :5; -#else - uint16_t flcgo :1; /* 0 Flash Cycle Go */ - uint16_t flcycle :2; /* 2:1 Flash Cycle */ - uint16_t reserved :5; /* 7:3 Reserved */ - uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */ - uint16_t flockdn :6; /* 15:10 Reserved */ -#endif - } hsf_ctrl; - uint16_t regval; +struct e1000_mac_info { + u8 addr[6]; + u8 perm_addr[6]; + + e1000_mac_type type; + e1000_fc_mode fc; + e1000_fc_mode original_fc; + + u32 collision_delta; + u32 ledctl_default; + u32 ledctl_mode1; + u32 ledctl_mode2; + u32 max_frame_size; + u32 mc_filter_type; + u32 min_frame_size; + u32 tx_packet_delta; + u32 txcw; + + u16 current_ifs_val; + u16 ifs_max_val; + u16 ifs_min_val; + u16 ifs_ratio; + u16 ifs_step_size; + u16 mta_reg_count; + u16 rar_entry_count; + u16 fc_high_water; + u16 fc_low_water; + u16 fc_pause_time; + + u8 forced_speed_duplex; + + boolean_t adaptive_ifs; + boolean_t arc_subsystem_valid; + boolean_t asf_firmware_present; + boolean_t autoneg; + boolean_t autoneg_failed; + boolean_t disable_av; + boolean_t disable_hw_init_bits; + boolean_t fc_send_xon; + boolean_t fc_strict_ieee; + boolean_t get_link_status; + boolean_t ifs_params_forced; + boolean_t in_ifs_mode; + boolean_t report_tx_early; + boolean_t serdes_has_link; + boolean_t tx_pkt_filtering; }; -/* ICH8 Flash Region Access Permissions */ -union ich8_hws_flash_regacc { - struct ich8_flracc { -#ifdef E1000_BIG_ENDIAN - uint32_t gmwag :8; - uint32_t gmrag :8; - uint32_t grwa :8; - uint32_t grra :8; -#else - uint32_t grra :8; /* 0:7 GbE region Read Access */ - uint32_t grwa :8; /* 8:15 GbE region Write Access */ - uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */ - uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */ -#endif - } hsf_flregacc; - uint16_t regval; +struct e1000_phy_info { + e1000_phy_type type; + + e1000_1000t_rx_status local_rx; + e1000_1000t_rx_status remote_rx; + e1000_ms_type ms_type; + e1000_ms_type original_ms_type; + e1000_rev_polarity cable_polarity; + e1000_smart_speed smart_speed; + + u32 addr; + u32 id; + u32 reset_delay_us; /* in usec */ + u32 revision; + + u16 autoneg_advertised; + u16 autoneg_mask; + u16 cable_length; + u16 max_cable_length; + u16 min_cable_length; + + u8 mdix; + + boolean_t disable_polarity_correction; + boolean_t is_mdix; + boolean_t polarity_correction; + boolean_t reset_disable; + boolean_t speed_downgraded; + boolean_t wait_for_link; +}; + +struct e1000_nvm_info { + e1000_nvm_type type; + e1000_nvm_override override; + + u32 flash_bank_size; + u32 flash_base_addr; + + u16 word_size; + u16 delay_usec; + u16 address_bits; + u16 opcode_bits; + u16 page_size; }; -/* Miscellaneous PHY bit definitions. */ -#define PHY_PREAMBLE 0xFFFFFFFF -#define PHY_SOF 0x01 -#define PHY_OP_READ 0x02 -#define PHY_OP_WRITE 0x01 -#define PHY_TURNAROUND 0x02 -#define PHY_PREAMBLE_SIZE 32 -#define MII_CR_SPEED_1000 0x0040 -#define MII_CR_SPEED_100 0x2000 -#define MII_CR_SPEED_10 0x0000 -#define E1000_PHY_ADDRESS 0x01 -#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ -#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ -#define PHY_REVISION_MASK 0xFFFFFFF0 -#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ -#define REG4_SPEED_MASK 0x01E0 -#define REG9_SPEED_MASK 0x0300 -#define ADVERTISE_10_HALF 0x0001 -#define ADVERTISE_10_FULL 0x0002 -#define ADVERTISE_100_HALF 0x0004 -#define ADVERTISE_100_FULL 0x0008 -#define ADVERTISE_1000_HALF 0x0010 -#define ADVERTISE_1000_FULL 0x0020 -#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ -#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ -#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ +struct e1000_bus_info { + e1000_bus_type type; + e1000_bus_speed speed; + e1000_bus_width width; + + u32 snoop; + + u16 func; + u16 pci_cmd_word; +}; + +struct e1000_hw { + void *back; + void *dev_spec; + + u8 *hw_addr; + u8 *flash_address; + unsigned long io_base; + + struct e1000_functions func; + struct e1000_mac_info mac; + struct e1000_phy_info phy; + struct e1000_nvm_info nvm; + struct e1000_bus_info bus; + struct e1000_host_mng_dhcp_cookie mng_cookie; -#endif /* _E1000_HW_H_ */ + e1000_media_type media_type; + + u32 dev_spec_size; + + u16 device_id; + u16 subsystem_vendor_id; + u16 subsystem_device_id; + u16 vendor_id; + + u8 revision_id; +}; + +/* These functions must be implemented by drivers */ +void e1000_pci_clear_mwi(struct e1000_hw *hw); +void e1000_pci_set_mwi(struct e1000_hw *hw); +s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size); +s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); +void e1000_free_dev_spec_struct(struct e1000_hw *hw); +void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); +void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_HW_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_ich8lan.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,2552 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +/* + * e1000_ich8lan + * e1000_ich9lan + */ + +#include "e1000_api.h" +#include "e1000_ich8lan.h" + +void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw); + +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); +static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); +static boolean_t e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); +static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, + boolean_t active); +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, + boolean_t active); +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, + u16 *data); +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, + u16 *speed, u16 *duplex); +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + u8 size, u16 *data); +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, + u32 offset, u16 *data); +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, + u32 offset, u8 byte); +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, + u32 offset, u8 data); +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + u8 size, u16 data); +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); + +/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ +/* Offset 04h HSFSTS */ +union ich8_hws_flash_status { + struct ich8_hsfsts { + u16 flcdone:1; /* bit 0 Flash Cycle Done */ + u16 flcerr:1; /* bit 1 Flash Cycle Error */ + u16 dael:1; /* bit 2 Direct Access error Log */ + u16 berasesz:2; /* bit 4:3 Sector Erase Size */ + u16 flcinprog:1; /* bit 5 flash cycle in Progress */ + u16 reserved1:2; /* bit 13:6 Reserved */ + u16 reserved2:6; /* bit 13:6 Reserved */ + u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ + u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ + } hsf_status; + u16 regval; +}; + +/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ +/* Offset 06h FLCTL */ +union ich8_hws_flash_ctrl { + struct ich8_hsflctl { + u16 flcgo:1; /* 0 Flash Cycle Go */ + u16 flcycle:2; /* 2:1 Flash Cycle */ + u16 reserved:5; /* 7:3 Reserved */ + u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ + u16 flockdn:6; /* 15:10 Reserved */ + } hsf_ctrl; + u16 regval; +}; + +/* ICH Flash Region Access Permissions */ +union ich8_hws_flash_regacc { + struct ich8_flracc { + u32 grra:8; /* 0:7 GbE region Read Access */ + u32 grwa:8; /* 8:15 GbE region Write Access */ + u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ + u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ + } hsf_flregacc; + u16 regval; +}; + +struct e1000_shadow_ram { + u16 value; + boolean_t modified; +}; + +struct e1000_dev_spec_ich8lan { + boolean_t kmrn_lock_loss_workaround_enabled; + struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; +}; + +/* + * e1000_init_phy_params_ich8lan - Initialize PHY function pointers + * @hw: pointer to the HW structure + * + * Initialize family-specific PHY parameters and function pointers. + */ +static s32 +e1000_init_phy_params_ich8lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + u16 i = 0; + + DEBUGFUNC("e1000_init_phy_params_ich8lan"); + + phy->addr = 1; + phy->reset_delay_us = 100; + + func->acquire_phy = e1000_acquire_swflag_ich8lan; + func->check_polarity = e1000_check_polarity_ife_ich8lan; + func->check_reset_block = e1000_check_reset_block_ich8lan; + func->force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; + func->get_cable_length = e1000_get_cable_length_igp_2; + func->get_cfg_done = e1000_get_cfg_done_ich8lan; + func->get_phy_info = e1000_get_phy_info_ich8lan; + func->read_phy_reg = e1000_read_phy_reg_igp; + func->release_phy = e1000_release_swflag_ich8lan; + func->reset_phy = e1000_phy_hw_reset_ich8lan; + func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; + func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; + func->write_phy_reg = e1000_write_phy_reg_igp; + + /* + * We may need to do this twice - once for IGP and if that fails, + * we'll set BM func pointers and try again + */ + ret_val = e1000_determine_phy_address(hw); + if (ret_val) { + func->write_phy_reg = e1000_write_phy_reg_bm; + func->read_phy_reg = e1000_read_phy_reg_bm; + ret_val = e1000_determine_phy_address(hw); + if (ret_val) { + DEBUGOUT("Can't determine PHY address. Erroring out\n"); + goto out; + } + } + + phy->id = 0; + while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && + (i++ < 100)) { + msec_delay(1); + ret_val = e1000_get_phy_id(hw); + if (ret_val) + goto out; + } + + /* Verify phy id */ + switch (phy->id) { + case IGP03E1000_E_PHY_ID: + phy->type = e1000_phy_igp_3; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + break; + case IFE_E_PHY_ID: + case IFE_PLUS_E_PHY_ID: + case IFE_C_E_PHY_ID: + phy->type = e1000_phy_ife; + phy->autoneg_mask = E1000_ALL_NOT_GIG; + break; + case BME1000_E_PHY_ID: + phy->type = e1000_phy_bm; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + func->read_phy_reg = e1000_read_phy_reg_bm; + func->write_phy_reg = e1000_write_phy_reg_bm; + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers + * @hw: pointer to the HW structure + * + * Initialize family-specific NVM parameters and function + * pointers. + */ +static s32 +e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_functions *func = &hw->func; + struct e1000_dev_spec_ich8lan *dev_spec; + u32 gfpreg, sector_base_addr, sector_end_addr; + s32 ret_val = E1000_SUCCESS; + u16 i; + + DEBUGFUNC("e1000_init_nvm_params_ich8lan"); + + /* Can't read flash registers if the register set isn't mapped. */ + if (!hw->flash_address) { + DEBUGOUT("ERROR: Flash registers not mapped\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + nvm->type = e1000_nvm_flash_sw; + + gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); + + /* + * sector_X_addr is a "sector"-aligned address (4096 bytes) Add 1 to + * sector_end_addr since this sector is included in the overall size. + */ + sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; + sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; + + /* flash_base_addr is byte-aligned */ + nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; + + /* + * find total size of the NVM, then cut in half since the total size + * represents two separate NVM banks. + */ + nvm->flash_bank_size = (sector_end_addr - sector_base_addr) + << FLASH_SECTOR_ADDR_SHIFT; + nvm->flash_bank_size /= 2; + /* Adjust to word count */ + nvm->flash_bank_size /= sizeof (u16); + + nvm->word_size = E1000_SHADOW_RAM_WORDS; + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + /* Clear shadow ram */ + for (i = 0; i < nvm->word_size; i++) { + dev_spec->shadow_ram[i].modified = FALSE; + dev_spec->shadow_ram[i].value = 0xFFFF; + } + + /* Function Pointers */ + func->acquire_nvm = e1000_acquire_swflag_ich8lan; + func->read_nvm = e1000_read_nvm_ich8lan; + func->release_nvm = e1000_release_swflag_ich8lan; + func->update_nvm = e1000_update_nvm_checksum_ich8lan; + func->valid_led_default = e1000_valid_led_default_ich8lan; + func->validate_nvm = e1000_validate_nvm_checksum_ich8lan; + func->write_nvm = e1000_write_nvm_ich8lan; + +out: + return (ret_val); +} + +/* + * e1000_init_mac_params_ich8lan - Initialize MAC function pointers + * @hw: pointer to the HW structure + * + * Initialize family-specific MAC parameters and function + * pointers. + */ +static s32 +e1000_init_mac_params_ich8lan(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_init_mac_params_ich8lan"); + + /* Set media type function pointer */ + hw->media_type = e1000_media_type_copper; + + /* Set mta register count */ + mac->mta_reg_count = 32; + /* Set rar entry count */ + mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; + if (mac->type == e1000_ich8lan) + mac->rar_entry_count--; + /* Set if part includes ASF firmware */ + mac->asf_firmware_present = TRUE; + /* Set if manageability features are enabled. */ + mac->arc_subsystem_valid = TRUE; + + /* Function pointers */ + + /* bus type/speed/width */ + func->get_bus_info = e1000_get_bus_info_ich8lan; + /* reset */ + func->reset_hw = e1000_reset_hw_ich8lan; + /* hw initialization */ + func->init_hw = e1000_init_hw_ich8lan; + /* link setup */ + func->setup_link = e1000_setup_link_ich8lan; + /* physical interface setup */ + func->setup_physical_interface = e1000_setup_copper_link_ich8lan; + /* check for link */ + func->check_for_link = e1000_check_for_copper_link_generic; + /* check management mode */ + func->check_mng_mode = e1000_check_mng_mode_ich8lan; + /* link info */ + func->get_link_up_info = e1000_get_link_up_info_ich8lan; + /* multicast address update */ + func->mc_addr_list_update = e1000_mc_addr_list_update_generic; + /* setting MTA */ + func->mta_set = e1000_mta_set_generic; + /* blink LED */ + func->blink_led = e1000_blink_led_generic; + /* setup LED */ + func->setup_led = e1000_setup_led_generic; + /* cleanup LED */ + func->cleanup_led = e1000_cleanup_led_ich8lan; + /* turn on/off LED */ + func->led_on = e1000_led_on_ich8lan; + func->led_off = e1000_led_off_ich8lan; + /* remove device */ + func->remove_device = e1000_remove_device_generic; + /* clear hardware counters */ + func->clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; + + hw->dev_spec_size = sizeof (struct e1000_dev_spec_ich8lan); + + /* Device-specific structure allocation */ + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); + if (ret_val) + goto out; + + /* Enable PCS Lock-loss workaround for ICH8 */ + if (mac->type == e1000_ich8lan) + e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); + + +out: + return (ret_val); +} + +/* + * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers + * @hw: pointer to the HW structure + * + * Initialize family-specific function pointers for PHY, MAC, and NVM. + */ +void +e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_init_function_pointers_ich8lan"); + + hw->func.init_mac_params = e1000_init_mac_params_ich8lan; + hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan; + hw->func.init_phy_params = e1000_init_phy_params_ich8lan; +} + +/* + * e1000_acquire_swflag_ich8lan - Acquire software control flag + * @hw: pointer to the HW structure + * + * Acquires the software control flag for performing NVM and PHY + * operations. This is a function pointer entry point only called by + * read/write routines for the PHY and NVM parts. + */ +static s32 +e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) +{ + u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_acquire_swflag_ich8lan"); + + while (timeout) { + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); + + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) + break; + msec_delay_irq(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("FW or HW has locked the resource for too long.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_release_swflag_ich8lan - Release software control flag + * @hw: pointer to the HW structure + * + * Releases the software control flag for performing NVM and PHY operations. + * This is a function pointer entry point only called by read/write + * routines for the PHY and NVM parts. + */ +static void +e1000_release_swflag_ich8lan(struct e1000_hw *hw) +{ + u32 extcnf_ctrl; + + DEBUGFUNC("e1000_release_swflag_ich8lan"); + + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); +} + +/* + * e1000_check_mng_mode_ich8lan - Checks management mode + * @hw: pointer to the HW structure + * + * This checks if the adapter has manageability enabled. + * This is a function pointer entry point only called by read/write + * routines for the PHY and NVM parts. + */ +static boolean_t +e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) +{ + u32 fwsm; + + DEBUGFUNC("e1000_check_mng_mode_ich8lan"); + + fwsm = E1000_READ_REG(hw, E1000_FWSM); + + return ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); +} + +/* + * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked + * @hw: pointer to the HW structure + * + * Checks if firmware is blocking the reset of the PHY. + * This is a function pointer entry point only called by + * reset routines. + */ +static s32 +e1000_check_reset_block_ich8lan(struct e1000_hw *hw) +{ + u32 fwsm; + + DEBUGFUNC("e1000_check_reset_block_ich8lan"); + + fwsm = E1000_READ_REG(hw, E1000_FWSM); + + return ((fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS + : E1000_BLK_PHY_RESET); +} + +/* + * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex + * @hw: pointer to the HW structure + * + * Forces the speed and duplex settings of the PHY. + * This is a function pointer entry point only called by + * PHY setup routines. + */ +static s32 +e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + boolean_t link; + + DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); + + if (phy->type != e1000_phy_ife) { + ret_val = e1000_phy_force_speed_duplex_igp(hw); + goto out; + } + + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &data); + if (ret_val) + goto out; + + e1000_phy_force_speed_duplex_setup(hw, &data); + + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, data); + if (ret_val) + goto out; + + /* Disable MDI-X support for 10/100 */ + ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); + if (ret_val) + goto out; + + data &= ~IFE_PMC_AUTO_MDIX; + data &= ~IFE_PMC_FORCE_MDIX; + + ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data); + if (ret_val) + goto out; + + DEBUGOUT1("IFE PMC: %X\n", data); + + usec_delay(1); + + if (phy->wait_for_link) { + DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); + + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + + if (!link) { + DEBUGOUT("Link taking longer than expected.\n"); + } + + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_phy_hw_reset_ich8lan - Performs a PHY reset + * @hw: pointer to the HW structure + * + * Resets the PHY + * This is a function pointer entry point called by drivers + * or other shared routines. + */ +static s32 +e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; + s32 ret_val; + u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; + u16 word_addr, reg_data, reg_addr, phy_page = 0; + + DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); + + ret_val = e1000_phy_hw_reset_generic(hw); + if (ret_val) + goto out; + + /* + * Initialize the PHY from the NVM on ICH platforms. This is needed + * due to an issue where the NVM configuration is not properly + * autoloaded after power transitions. Therefore, after each PHY + * reset, we will load the configuration data out of the NVM manually. + */ + if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { + /* Check if SW needs configure the PHY */ + if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || + (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; + else + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; + + data = E1000_READ_REG(hw, E1000_FEXTNVM); + if (!(data & sw_cfg_mask)) + goto out; + + /* Wait for basic configuration completes before proceeding */ + do { + data = E1000_READ_REG(hw, E1000_STATUS); + data &= E1000_STATUS_LAN_INIT_DONE; + usec_delay(100); + } while ((!data) && --loop); + + /* + * If basic configuration is incomplete before the above loop + * count reaches 0, loading the configuration from NVM will + * leave the PHY in a bad state possibly resulting in no link. + */ + if (loop == 0) { + DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); + } + + /* Clear the Init Done bit for the next init event */ + data = E1000_READ_REG(hw, E1000_STATUS); + data &= ~E1000_STATUS_LAN_INIT_DONE; + E1000_WRITE_REG(hw, E1000_STATUS, data); + + /* + * Make sure HW does not configure LCD from PHY extended + * configuration before SW configuration + */ + data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) + goto out; + + cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; + if (!cnf_size) + goto out; + + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; + + /* + * Configure LCD from extended configuration region. + */ + + /* cnf_base_addr is in DWORD */ + word_addr = (u16)(cnf_base_addr << 1); + + for (i = 0; i < cnf_size; i++) { + ret_val = e1000_read_nvm(hw, + (word_addr + i * 2), + 1, + ®_data); + if (ret_val) + goto out; + + ret_val = e1000_read_nvm(hw, + (word_addr + i * 2 + 1), + 1, + ®_addr); + if (ret_val) + goto out; + + /* Save off the PHY page for future writes. */ + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { + phy_page = reg_data; + continue; + } + + reg_addr |= phy_page; + + ret_val = e1000_write_phy_reg(hw, + (u32)reg_addr, + reg_data); + if (ret_val) + goto out; + } + } + +out: + return (ret_val); +} + +/* + * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info + * @hw: pointer to the HW structure + * + * Wrapper for calling the get_phy_info routines for the appropriate phy type. + * This is a function pointer entry point called by drivers + * or other shared routines. + */ +static s32 +e1000_get_phy_info_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = -E1000_ERR_PHY_TYPE; + + DEBUGFUNC("e1000_get_phy_info_ich8lan"); + + switch (hw->phy.type) { + case e1000_phy_ife: + ret_val = e1000_get_phy_info_ife_ich8lan(hw); + break; + case e1000_phy_igp_3: + case e1000_phy_bm: + ret_val = e1000_get_phy_info_igp(hw); + break; + default: + break; + } + + return (ret_val); +} + +/* + * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states + * @hw: pointer to the HW structure + * + * Populates "phy" structure with various feature states. + * This function is only called by other family-specific + * routines. + */ +static s32 +e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + boolean_t link; + + DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { + DEBUGOUT("Phy info is only valid if link is up\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); + if (ret_val) + goto out; + phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) + ? FALSE : TRUE; + + if (phy->polarity_correction) { + ret_val = e1000_check_polarity_ife_ich8lan(hw); + if (ret_val) + goto out; + } else { + /* Polarity is forced */ + phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) + ? e1000_rev_polarity_reversed + : e1000_rev_polarity_normal; + } + + ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); + if (ret_val) + goto out; + + phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; + + /* The following parameters are undefined for 10/100 operation. */ + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; + phy->local_rx = e1000_1000t_rx_status_undefined; + phy->remote_rx = e1000_1000t_rx_status_undefined; + +out: + return (ret_val); +} + +/* + * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY + * @hw: pointer to the HW structure + * + * Polarity is determined on the polarity reveral feature being enabled. + * This function is only called by other family-specific + * routines. + */ +static s32 +e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, offset, mask; + + DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); + + /* + * Polarity is determined based on the reversal feature being enabled. + */ + if (phy->polarity_correction) { + offset = IFE_PHY_EXTENDED_STATUS_CONTROL; + mask = IFE_PESC_POLARITY_REVERSED; + } else { + offset = IFE_PHY_SPECIAL_CONTROL; + mask = IFE_PSC_FORCE_POLARITY; + } + + ret_val = e1000_read_phy_reg(hw, offset, &phy_data); + + if (!ret_val) + phy->cable_polarity = (phy_data & mask) + ? e1000_rev_polarity_reversed + : e1000_rev_polarity_normal; + + return (ret_val); +} + +/* + * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D0 state according to the active flag. When + * activating LPLU this function also disables smart speed + * and vice versa. LPLU will not be activated unless the + * device autonegotiation advertisement meets standards of + * either 10 or 10/100 or 10/100/1000 at all duplexes. + * This is a function pointer entry point only called by + * PHY setup routines. + */ +static s32 +e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active) +{ + struct e1000_phy_info *phy = &hw->phy; + u32 phy_ctrl; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); + + if (phy->type != e1000_phy_igp_3) + goto out; + + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); + + if (active) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + + /* + * Call gig speed drop workaround on LPLU before accessing any + * PHY registers + */ + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3)) + e1000_gig_downshift_workaround_ich8lan(hw); + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } + } + +out: + return (ret_val); +} + +/* + * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D3 state according to the active flag. When + * activating LPLU this function also disables smart speed + * and vice versa. LPLU will not be activated unless the + * device autonegotiation advertisement meets standards of + * either 10 or 10/100 or 10/100/1000 at all duplexes. + * This is a function pointer entry point only called by + * PHY setup routines. + */ +static s32 +e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active) +{ + struct e1000_phy_info *phy = &hw->phy; + u32 phy_ctrl; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); + + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); + + if (!active) { + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + + /* + * Call gig speed drop workaround on LPLU before accessing any + * PHY registers + */ + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3)) + e1000_gig_downshift_workaround_ich8lan(hw); + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + } + +out: + return (ret_val); +} + +/* + * e1000_read_nvm_ich8lan - Read word(s) from the NVM + * @hw: pointer to the HW structure + * @offset: The offset (in bytes) of the word(s) to read. + * @words: Size of data to read in words + * @data: Pointer to the word(s) to read at offset. + * + * Reads a word(s) from the NVM using the flash access registers. + */ +static s32 +e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_dev_spec_ich8lan *dev_spec; + u32 act_offset; + s32 ret_val = E1000_SUCCESS; + u16 i, word; + + DEBUGFUNC("e1000_read_nvm_ich8lan"); + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + /* Start with the bank offset, then add the relative offset. */ + act_offset = (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) + ? nvm->flash_bank_size + : 0; + act_offset += offset; + + for (i = 0; i < words; i++) { + if ((dev_spec->shadow_ram) && + (dev_spec->shadow_ram[offset + i].modified)) { + data[i] = dev_spec->shadow_ram[offset + i].value; + } else { + ret_val = e1000_read_flash_word_ich8lan(hw, + act_offset + i, + &word); + if (ret_val) + break; + data[i] = word; + } + } + + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_flash_cycle_init_ich8lan - Initialize flash + * @hw: pointer to the HW structure + * + * This function does initial flash setup so that a new read/write/erase cycle + * can be started. + */ +static s32 +e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) +{ + union ich8_hws_flash_status hsfsts; + s32 ret_val = -E1000_ERR_NVM; + s32 i = 0; + + DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); + + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + + /* Check if the flash descriptor is valid */ + if (hsfsts.hsf_status.fldesvalid == 0) { + DEBUGOUT("Flash descriptor invalid. " + "SW Sequencing must be used."); + goto out; + } + + /* Clear FCERR and DAEL in hw status by writing 1 */ + hsfsts.hsf_status.flcerr = 1; + hsfsts.hsf_status.dael = 1; + + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); + + /* + * Either we should have a hardware SPI cycle in progress bit to check + * against, in order to start a new cycle or FDONE bit should be + * changed in the hardware so that it is 1 after harware reset, which + * can then be used as an indication whether a cycle is in progress or + * has been completed. + */ + + if (hsfsts.hsf_status.flcinprog == 0) { + /* + * There is no cycle running at present, so we can start a + * cycle. Begin by setting Flash Cycle Done. + */ + hsfsts.hsf_status.flcdone = 1; + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); + ret_val = E1000_SUCCESS; + } else { + /* + * Otherwise poll for sometime so the current cycle has a + * chance to end before giving up. + */ + for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { + hsfsts.regval = E1000_READ_FLASH_REG16(hw, + ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcinprog == 0) { + ret_val = E1000_SUCCESS; + break; + } + usec_delay(1); + } + if (ret_val == E1000_SUCCESS) { + /* + * Successful in waiting for previous cycle to + * timeout, now set the Flash Cycle Done. + */ + hsfsts.hsf_status.flcdone = 1; + E1000_WRITE_FLASH_REG16(hw, + ICH_FLASH_HSFSTS, + hsfsts.regval); + } else { + DEBUGOUT("Flash controller busy, cannot get access"); + } + } + +out: + return (ret_val); +} + +/* + * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) + * @hw: pointer to the HW structure + * @timeout: maximum time to wait for completion + * + * This function starts a flash cycle and waits for its completion. + */ +static s32 +e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) +{ + union ich8_hws_flash_ctrl hsflctl; + union ich8_hws_flash_status hsfsts; + s32 ret_val = -E1000_ERR_NVM; + u32 i = 0; + + DEBUGFUNC("e1000_flash_cycle_ich8lan"); + + /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + hsflctl.hsf_ctrl.flcgo = 1; + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + /* wait till FDONE bit is set to 1 */ + do { + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcdone == 1) + break; + usec_delay(1); + } while (i++ < timeout); + + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) + ret_val = E1000_SUCCESS; + + return (ret_val); +} + +/* + * e1000_read_flash_word_ich8lan - Read word from flash + * @hw: pointer to the HW structure + * @offset: offset to data location + * @data: pointer to the location for storing the data + * + * Reads the flash word at offset into data. Offset is converted + * to bytes before read. + */ +static s32 +e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_read_flash_word_ich8lan"); + + if (!data) { + ret_val = -E1000_ERR_NVM; + goto out; + } + + /* Must convert offset into bytes. */ + offset <<= 1; + + ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); + +out: + return (ret_val); +} + +/* + * e1000_read_flash_data_ich8lan - Read byte or word from NVM + * @hw: pointer to the HW structure + * @offset: The offset (in bytes) of the byte or word to read. + * @size: Size of data to read, 1=byte 2=word + * @data: Pointer to the word to store the value read. + * + * Reads a byte or word from the NVM using the flash access registers. + */ +static s32 +e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + u8 size, u16 *data) +{ + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + u32 flash_linear_addr; + u32 flash_data = 0; + s32 ret_val = -E1000_ERR_NVM; + u8 count = 0; + + DEBUGFUNC("e1000_read_flash_data_ich8lan"); + + if (size < 1 || size > 2 || data == 0x0 || + offset > ICH_FLASH_LINEAR_ADDR_MASK) + goto out; + + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + + hw->nvm.flash_base_addr; + + do { + usec_delay(1); + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); + if (ret_val != E1000_SUCCESS) + break; + + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ + hsflctl.hsf_ctrl.fldbcount = size - 1; + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); + + ret_val = e1000_flash_cycle_ich8lan(hw, + ICH_FLASH_READ_COMMAND_TIMEOUT); + + /* + * Check if FCERR is set to 1, if set to 1, clear it and try + * the whole sequence a few more times, else read in (shift + * in) the Flash Data0, the order is least significant byte + * first msb to lsb + */ + if (ret_val == E1000_SUCCESS) { + flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); + if (size == 1) { + *data = (u8)(flash_data & 0x000000FF); + } else if (size == 2) { + *data = (u16)(flash_data & 0x0000FFFF); + } + break; + } else { + /* + * If we've gotten here, then things are probably + * completely hosed, but if the error condition is + * detected, it won't hurt to give it another try... + * ICH_FLASH_CYCLE_REPEAT_COUNT times. + */ + hsfsts.regval = E1000_READ_FLASH_REG16(hw, + ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* Repeat for some time before giving up. */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) { + DEBUGOUT("Timeout error - flash cycle " + "did not complete."); + break; + } + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + +out: + return (ret_val); +} + +/* + * e1000_write_nvm_ich8lan - Write word(s) to the NVM + * @hw: pointer to the HW structure + * @offset: The offset (in bytes) of the word(s) to write. + * @words: Size of data to write in words + * @data: Pointer to the word(s) to write at offset. + * + * Writes a byte or word to the NVM using the flash access registers. + */ +static s32 +e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_dev_spec_ich8lan *dev_spec; + s32 ret_val = E1000_SUCCESS; + u16 i; + + DEBUGFUNC("e1000_write_nvm_ich8lan"); + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + for (i = 0; i < words; i++) { + dev_spec->shadow_ram[offset + i].modified = TRUE; + dev_spec->shadow_ram[offset + i].value = data[i]; + } + + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM + * @hw: pointer to the HW structure + * + * The NVM checksum is updated by calling the generic update_nvm_checksum, + * which writes the checksum to the shadow ram. The changes in the shadow + * ram are then committed to the EEPROM by processing each bank at a time + * checking for the modified bit and writing only the pending changes. + * After a succesful commit, the shadow ram is cleared and is ready for + * future writes. + */ +static s32 +e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_dev_spec_ich8lan *dev_spec; + u32 i, act_offset, new_bank_offset, old_bank_offset; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + ret_val = e1000_update_nvm_checksum_generic(hw); + if (ret_val) + goto out; + + if (nvm->type != e1000_nvm_flash_sw) + goto out; + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + /* + * We're writing to the opposite bank so if we're on bank 1, write to + * bank 0 etc. We also need to erase the segment that is going to be + * written + */ + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)) { + new_bank_offset = nvm->flash_bank_size; + old_bank_offset = 0; + e1000_erase_flash_bank_ich8lan(hw, 1); + } else { + old_bank_offset = nvm->flash_bank_size; + new_bank_offset = 0; + e1000_erase_flash_bank_ich8lan(hw, 0); + } + + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + /* + * Determine whether to write the value stored in the other + * NVM bank or a modified value stored in the shadow RAM + */ + if (dev_spec->shadow_ram[i].modified) { + data = dev_spec->shadow_ram[i].value; + } else { + e1000_read_flash_word_ich8lan(hw, + i + old_bank_offset, + &data); + } + + /* + * If the word is 0x13, then make sure the signature bits + * (15:14) are 11b until the commit has completed. This will + * allow us to write 10b which indicates the signature is + * valid. We want to do this after the write has completed so + * that we don't mark the segment valid while the write is + * still in progress + */ + if (i == E1000_ICH_NVM_SIG_WORD) + data |= E1000_ICH_NVM_SIG_MASK; + + /* Convert offset to bytes. */ + act_offset = (i + new_bank_offset) << 1; + + usec_delay(100); + /* Write the bytes to the new bank. */ + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, + act_offset, + (u8)data); + if (ret_val) + break; + + usec_delay(100); + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, + act_offset + 1, + (u8)(data >> 8)); + if (ret_val) + break; + } + + /* + * Don't bother writing the segment valid bits if sector programming + * failed. + */ + if (ret_val) { + DEBUGOUT("Flash commit failed.\n"); + e1000_release_nvm(hw); + goto out; + } + + /* + * Finally validate the new segment by setting bit 15:14 to 10b in + * word 0x13 , this can be done without an erase as well since these + * bits are 11 to start with and we need to change bit 14 to 0b + */ + act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; + e1000_read_flash_word_ich8lan(hw, act_offset, &data); + data &= 0xBFFF; + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, + act_offset * 2 + 1, + (u8)(data >> 8)); + if (ret_val) { + e1000_release_nvm(hw); + goto out; + } + + /* + * And invalidate the previously valid segment by setting its + * signature word (0x13) high_byte to 0b. This can be done without an + * erase because flash erase sets all bits to 1's. We can write 1's to + * 0's without an erase + */ + act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); + if (ret_val) { + e1000_release_nvm(hw); + goto out; + } + /* Great! Everything worked, we can now clear the cached entries. */ + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + dev_spec->shadow_ram[i].modified = FALSE; + dev_spec->shadow_ram[i].value = 0xFFFF; + } + + e1000_release_nvm(hw); + + /* + * Reload the EEPROM, or else modifications will not appear until + * after the next adapter reset. + */ + e1000_reload_nvm(hw); + msec_delay(10); + +out: + return (ret_val); +} + +/* + * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. + * If the bit is 0, that the EEPROM had been modified, but the checksum was not + * calculated, in which case we need to calculate the checksum and set bit 6. + */ +static s32 +e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); + + /* + * Read 0x19 and check bit 6. If this bit is 0, the checksum needs to + * be fixed. This bit is an indication that the NVM was prepared by + * OEM software and did not calculate the checksum...a likely + * scenario. + */ + ret_val = e1000_read_nvm(hw, 0x19, 1, &data); + if (ret_val) + goto out; + + if ((data & 0x40) == 0) { + data |= 0x40; + ret_val = e1000_write_nvm(hw, 0x19, 1, &data); + if (ret_val) + goto out; + ret_val = e1000_update_nvm_checksum(hw); + if (ret_val) + goto out; + } + + ret_val = e1000_validate_nvm_checksum_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_flash_data_ich8lan - Writes bytes to the NVM + * @hw: pointer to the HW structure + * @offset: The offset (in bytes) of the byte/word to read. + * @size: Size of data to read, 1=byte 2=word + * @data: The byte(s) to write to the NVM. + * + * Writes one/two bytes to the NVM using the flash access registers. + */ +static s32 +e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + u8 size, u16 data) +{ + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + u32 flash_linear_addr; + u32 flash_data = 0; + s32 ret_val = -E1000_ERR_NVM; + u8 count = 0; + + DEBUGFUNC("e1000_write_ich8_data"); + + if (size < 1 || size > 2 || data > size * 0xff || + offset > ICH_FLASH_LINEAR_ADDR_MASK) + goto out; + + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + + hw->nvm.flash_base_addr; + + do { + usec_delay(1); + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); + if (ret_val != E1000_SUCCESS) + break; + + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ + hsflctl.hsf_ctrl.fldbcount = size - 1; + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); + + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); + + if (size == 1) + flash_data = (u32)data & 0x00FF; + else + flash_data = (u32)data; + + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); + + /* + * check if FCERR is set to 1 , if set to 1, clear it and try + * the whole sequence a few more times else done + */ + ret_val = e1000_flash_cycle_ich8lan(hw, + ICH_FLASH_WRITE_COMMAND_TIMEOUT); + if (ret_val == E1000_SUCCESS) { + break; + } else { + /* + * If we're here, then things are most likely + * completely hosed, but if the error condition is + * detected, it won't hurt to give it another + * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. + */ + hsfsts.regval = E1000_READ_FLASH_REG16(hw, + ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* Repeat for some time before giving up. */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) { + DEBUGOUT("Timeout error - flash cycle " + "did not complete."); + break; + } + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + +out: + return (ret_val); +} + +/* + * e1000_write_flash_byte_ich8lan - Write a single byte to NVM + * @hw: pointer to the HW structure + * @offset: The index of the byte to read. + * @data: The byte to write to the NVM. + * + * Writes a single byte to the NVM using the flash access registers. + */ +static s32 +e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data) +{ + u16 word = (u16)data; + + DEBUGFUNC("e1000_write_flash_byte_ich8lan"); + + return (e1000_write_flash_data_ich8lan(hw, offset, 1, word)); +} + +/* + * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM + * @hw: pointer to the HW structure + * @offset: The offset of the byte to write. + * @byte: The byte to write to the NVM. + * + * Writes a single byte to the NVM using the flash access registers. + * Goes through a retry algorithm before giving up. + */ +static s32 +e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte) +{ + s32 ret_val; + u16 program_retries; + + DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); + + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); + if (ret_val == E1000_SUCCESS) + goto out; + + for (program_retries = 0; program_retries < 100; program_retries++) { + DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); + usec_delay(100); + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); + if (ret_val == E1000_SUCCESS) + break; + } + if (program_retries == 100) { + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM + * @hw: pointer to the HW structure + * @bank: 0 for first bank, 1 for second bank, etc. + * + * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. + * bank N is 4096 * N + flash_reg_addr. + */ +static s32 +e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + union ich8_hws_flash_status hsfsts; + union ich8_hws_flash_ctrl hsflctl; + u32 flash_linear_addr; + + /* bank size is in 16bit words - adjust to bytes */ + u32 flash_bank_size = nvm->flash_bank_size * 2; + s32 ret_val = E1000_SUCCESS; + s32 count = 0; + s32 j, iteration, sector_size; + + DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); + + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); + + /* + * Determine HW Sector size: Read BERASE bits of hw flash status + * register + * 00: The Hw sector is 256 bytes, hence we need to erase 16 + * consecutive sectors. The start index for the nth Hw sector + * can be calculated as = bank * 4096 + n * 256 + * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. + * The start index for the nth Hw sector can be calculated + * as = bank * 4096 + * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 + * (ich9 only, otherwise error condition) + * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 + */ + switch (hsfsts.hsf_status.berasesz) { + case 0: + /* Hw sector size 256 */ + sector_size = ICH_FLASH_SEG_SIZE_256; + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; + break; + case 1: + sector_size = ICH_FLASH_SEG_SIZE_4K; + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; + break; + case 2: + if (hw->mac.type == e1000_ich9lan) { + sector_size = ICH_FLASH_SEG_SIZE_8K; + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; + } else { + ret_val = -E1000_ERR_NVM; + goto out; + } + break; + case 3: + sector_size = ICH_FLASH_SEG_SIZE_64K; + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; + break; + default: + ret_val = -E1000_ERR_NVM; + goto out; + } + + /* Start with the base address, then add the sector offset. */ + flash_linear_addr = hw->nvm.flash_base_addr; + flash_linear_addr += (bank) ? (sector_size * iteration) : 0; + + for (j = 0; j < iteration; j++) { + do { + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); + if (ret_val) + goto out; + + /* + * Write a value 11 (block Erase) in Flash Cycle field + * in hw flash control + */ + hsflctl.regval = E1000_READ_FLASH_REG16(hw, + ICH_FLASH_HSFCTL); + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; + E1000_WRITE_FLASH_REG16(hw, + ICH_FLASH_HSFCTL, + hsflctl.regval); + + /* + * Write the last 24 bits of an index within the block + * into Flash Linear address field in Flash Address. + */ + flash_linear_addr += (j * sector_size); + E1000_WRITE_FLASH_REG(hw, + ICH_FLASH_FADDR, + flash_linear_addr); + + ret_val = e1000_flash_cycle_ich8lan(hw, + ICH_FLASH_ERASE_COMMAND_TIMEOUT); + if (ret_val == E1000_SUCCESS) { + break; + } else { + /* + * Check if FCERR is set to 1. If 1, clear it + * and try the whole sequence a few more times + * else Done + */ + hsfsts.regval = E1000_READ_FLASH_REG16(hw, + ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcerr == 1) { + /* + * repeat for some time before giving up + */ + continue; + } else if (hsfsts.hsf_status.flcdone == 0) + goto out; + } + } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); + } + +out: + return (ret_val); +} + +/* + * e1000_valid_led_default_ich8lan - Set the default LED settings + * @hw: pointer to the HW structure + * @data: Pointer to the LED settings + * + * Reads the LED default settings from the NVM to data. If the NVM LED + * settings is all 0's or F's, set the LED default to a valid LED default + * setting. + */ +static s32 +e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 * data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_valid_led_default_ich8lan"); + + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if (*data == ID_LED_RESERVED_0000 || + *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT_ICH8LAN; + +out: + return (ret_val); +} + +/* + * e1000_get_bus_info_ich8lan - Get/Set the bus type and width + * @hw: pointer to the HW structure + * + * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability + * register, so the the bus width is hard coded. + */ +static s32 +e1000_get_bus_info_ich8lan(struct e1000_hw *hw) +{ + struct e1000_bus_info *bus = &hw->bus; + s32 ret_val; + + DEBUGFUNC("e1000_get_bus_info_ich8lan"); + + ret_val = e1000_get_bus_info_pcie_generic(hw); + + /* + * ICH devices are "PCI Express"-ish. They have a configuration + * space, but do not contain PCI Express Capability registers, so bus + * width must be hardcoded. + */ + if (bus->width == e1000_bus_width_unknown) + bus->width = e1000_bus_width_pcie_x1; + + return (ret_val); +} + +/* + * e1000_reset_hw_ich8lan - Reset the hardware + * @hw: pointer to the HW structure + * + * Does a full reset of the hardware which includes a reset of the PHY and + * MAC. + */ +static s32 +e1000_reset_hw_ich8lan(struct e1000_hw *hw) +{ + u32 ctrl, icr, kab; + s32 ret_val; + + DEBUGFUNC("e1000_reset_hw_ich8lan"); + + /* + * Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ + ret_val = e1000_disable_pcie_master_generic(hw); + if (ret_val) { + DEBUGOUT("PCI-E Master disable polling has failed.\n"); + } + + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + + /* + * Disable the Transmit and Receive units. Then delay to allow any + * pending transactions to complete before we hit the MAC with the + * global reset. + */ + E1000_WRITE_REG(hw, E1000_RCTL, 0); + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + msec_delay(10); + + /* Workaround for ICH8 bit corruption issue in FIFO memory */ + if (hw->mac.type == e1000_ich8lan) { + /* Set Tx and Rx buffer allocation to 8k apiece. */ + E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); + /* Set Packet Buffer Size to 16k. */ + E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); + } + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) { + /* + * PHY HW reset requires MAC CORE reset at the same time to + * make sure the interface between MAC and the external PHY is + * reset. + */ + ctrl |= E1000_CTRL_PHY_RST; + } + + ret_val = e1000_acquire_swflag_ich8lan(hw); + DEBUGOUT("Issuing a global reset to ich8lan"); + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); + msec_delay(20); + + ret_val = e1000_get_auto_rd_done_generic(hw); + if (ret_val) { + /* + * When auto config read does not complete, do not return with + * an error. This can happen in situations where there is no + * eeprom and prevents getting link. + */ + DEBUGOUT("Auto Read Done did not complete\n"); + } + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); + icr = E1000_READ_REG(hw, E1000_ICR); + + kab = E1000_READ_REG(hw, E1000_KABGTXD); + kab |= E1000_KABGTXD_BGSQLBIAS; + E1000_WRITE_REG(hw, E1000_KABGTXD, kab); + + return (ret_val); +} + +/* + * e1000_init_hw_ich8lan - Initialize the hardware + * @hw: pointer to the HW structure + * + * Prepares the hardware for transmit and receive by doing the following: + * - initialize hardware bits + * - initialize LED identification + * - setup receive address registers + * - setup flow control + * - setup transmit discriptors + * - clear statistics + */ +static s32 +e1000_init_hw_ich8lan(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl_ext, txdctl, snoop; + s32 ret_val; + u16 i; + + DEBUGFUNC("e1000_init_hw_ich8lan"); + + e1000_initialize_hw_bits_ich8lan(hw); + + /* Initialize identification LED */ + ret_val = e1000_id_led_init_generic(hw); + if (ret_val) { + DEBUGOUT("Error initializing identification LED\n"); + goto out; + } + + /* Setup the receive address. */ + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Setup link and flow control */ + ret_val = e1000_setup_link(hw); + + /* Set the transmit descriptor write-back policy for both queues */ + txdctl = E1000_READ_REG(hw, E1000_TXDCTL); + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | + E1000_TXDCTL_MAX_TX_DESC_PREFETCH; + E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl); + txdctl = E1000_READ_REG(hw, E1000_TXDCTL1); + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | + E1000_TXDCTL_MAX_TX_DESC_PREFETCH; + E1000_WRITE_REG(hw, E1000_TXDCTL1, txdctl); + + /* + * ICH8 has opposite polarity of no_snoop bits. By default, we should + * use snoop behavior. + */ + if (mac->type == e1000_ich8lan) + snoop = PCIE_ICH8_SNOOP_ALL; + else + snoop = (u32)~(PCIE_NO_SNOOP_ALL); + e1000_set_pcie_no_snoop_generic(hw, snoop); + + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_ich8lan(hw); + +out: + return (ret_val); +} + +/* + * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits + * @hw: pointer to the HW structure + * + * Sets/Clears required hardware bits necessary for correctly setting up the + * hardware for transmit and receive. + */ +static void +e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) +{ + u32 reg; + + DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); + + if (hw->mac.disable_hw_init_bits) + return; + + /* Extended Device Control */ + reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); + + /* Transmit Descriptor Control 0 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL, reg); + + /* Transmit Descriptor Control 1 */ + reg = E1000_READ_REG(hw, E1000_TXDCTL1); + reg |= (1 << 22); + E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); + + /* Transmit Arbitration Control 0 */ + reg = E1000_READ_REG(hw, E1000_TARC0); + if (hw->mac.type == e1000_ich8lan) + reg |= (1 << 28) | (1 << 29); + reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); + E1000_WRITE_REG(hw, E1000_TARC0, reg); + + /* Transmit Arbitration Control 1 */ + reg = E1000_READ_REG(hw, E1000_TARC1); + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) + reg &= ~(1 << 28); + else + reg |= (1 << 28); + reg |= (1 << 24) | (1 << 26) | (1 << 30); + E1000_WRITE_REG(hw, E1000_TARC1, reg); + + /* Device Status */ + if (hw->mac.type == e1000_ich8lan) { + reg = E1000_READ_REG(hw, E1000_STATUS); + reg &= ~((u32)1 << 31); + E1000_WRITE_REG(hw, E1000_STATUS, reg); + } +} + +/* + * e1000_setup_link_ich8lan - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow + * control. Calls the appropriate media-specific link configuration + * function. Assuming the adapter has a valid link partner, a valid link + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + */ +static s32 +e1000_setup_link_ich8lan(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_link_ich8lan"); + + if (e1000_check_reset_block(hw)) + goto out; + + /* + * ICH parts do not have a word in the NVM to determine the default + * flow control setting, so we explicitly set it to full. + */ + if (mac->fc == e1000_fc_default) + mac->fc = e1000_fc_full; + + mac->original_fc = mac->fc; + + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); + + /* Continue to configure the copper link. */ + ret_val = func->setup_physical_interface(hw); + if (ret_val) + goto out; + + E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); + + ret_val = e1000_set_fc_watermarks_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface + * @hw: pointer to the HW structure + * + * Configures the kumeran interface to the PHY to wait the appropriate time + * when polling the PHY, then call the generic setup_copper_link to finish + * configuring the copper link. + */ +static s32 +e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + u16 reg_data; + + DEBUGFUNC("e1000_setup_copper_link_ich8lan"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* + * Set the mac to wait the maximum time between each iteration and + * increase the max iterations when polling the phy; this fixes + * erroneous timeouts at 10Mbps. + */ + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + goto out; + ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) + goto out; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) + goto out; + + if (hw->phy.type == e1000_phy_igp_3) { + ret_val = e1000_copper_link_setup_igp(hw); + if (ret_val) + goto out; + } else if (hw->phy.type == e1000_phy_bm) { + ret_val = e1000_copper_link_setup_m88(hw); + if (ret_val) + goto out; + } + + ret_val = e1000_setup_copper_link_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_get_link_up_info_ich8lan - Get current link speed and duplex + * @hw: pointer to the HW structure + * @speed: pointer to store current link speed + * @duplex: pointer to store the current link duplex + * + * Calls the generic get_speed_and_duplex to retreive the current link + * information and then calls the Kumeran lock loss workaround for links at + * gigabit speeds. + */ +static s32 +e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) +{ + s32 ret_val; + + DEBUGFUNC("e1000_get_link_up_info_ich8lan"); + + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); + if (ret_val) + goto out; + + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3) && + (*speed == SPEED_1000)) { + ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); + } + +out: + return (ret_val); +} + +/* + * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround + * @hw: pointer to the HW structure + * + * Work-around for 82566 Kumeran PCS lock loss: + * On link status change (i.e. PCI reset, speed change) and link is up and + * speed is gigabit- + * 0) if workaround is optionally disabled do nothing + * 1) wait 1ms for Kumeran link to come up + * 2) check Kumeran Diagnostic register PCS lock loss bit + * 3) if not set the link is locked (all is good), otherwise... + * 4) reset the PHY + * 5) repeat up to 10 times + * Note: this is only called for IGP3 copper when speed is 1gb. + */ +static s32 +e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) +{ + struct e1000_dev_spec_ich8lan *dev_spec; + u32 phy_ctrl; + s32 ret_val = E1000_SUCCESS; + u16 i, data; + boolean_t link; + + DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) + goto out; + + /* + * Make sure link is up before proceeding. If not just return. + * Attempting this while link is negotiating fouled up link stability + */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (!link) { + ret_val = E1000_SUCCESS; + goto out; + } + + for (i = 0; i < 10; i++) { + /* read once to clear */ + ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); + if (ret_val) + goto out; + /* and again to get new status */ + ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); + if (ret_val) + goto out; + + /* check for PCS lock */ + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* Issue PHY reset */ + e1000_phy_hw_reset(hw); + msec_delay_irq(5); + } + /* Disable GigE link negotiation */ + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); + phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | + E1000_PHY_CTRL_NOND0A_GBE_DISABLE); + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + + /* + * Call gig speed drop workaround on Giga disable before accessing any + * PHY registers + */ + e1000_gig_downshift_workaround_ich8lan(hw); + + /* unable to acquire PCS lock */ + ret_val = -E1000_ERR_PHY; + +out: + return (ret_val); +} + +/* + * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state + * @hw: pointer to the HW structure + * @state: boolean value used to set the current Kumaran workaround state + * + * If ICH8, set the current Kumeran workaround state (enabled - TRUE + * /disabled - FALSE). + */ +void +e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + boolean_t state) +{ + struct e1000_dev_spec_ich8lan *dev_spec; + + DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); + + if (hw->mac.type != e1000_ich8lan) { + DEBUGOUT("Workaround applies to ICH8 only.\n"); + return; + } + + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; + + if (!dev_spec) { + DEBUGOUT("dev_spec pointer is set to NULL.\n"); + return; + } + + dev_spec->kmrn_lock_loss_workaround_enabled = state; +} + +/* + * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 + * @hw: pointer to the HW structure + * + * Workaround for 82566 power-down on D3 entry: + * 1) disable gigabit link + * 2) write VR power-down enable + * 3) read it back + * Continue if successful, else issue LCD reset and repeat + */ +void +e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) +{ + u32 reg; + u16 data; + u8 retry = 0; + + DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); + + if (hw->phy.type != e1000_phy_igp_3) + return; + + /* Try the workaround twice (if needed) */ + do { + /* Disable link */ + reg = E1000_READ_REG(hw, E1000_PHY_CTRL); + reg |= (E1000_PHY_CTRL_GBE_DISABLE | + E1000_PHY_CTRL_NOND0A_GBE_DISABLE); + E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); + + /* + * Call gig speed drop workaround on Giga disable before + * accessing any PHY registers + */ + if (hw->mac.type == e1000_ich8lan) + e1000_gig_downshift_workaround_ich8lan(hw); + + /* Write VR power-down enable */ + e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); + data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; + e1000_write_phy_reg(hw, + IGP3_VR_CTRL, + data | IGP3_VR_CTRL_MODE_SHUTDOWN); + + /* Read it back and test */ + e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); + data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; + if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) + break; + + /* Issue PHY reset and repeat at most one more time */ + reg = E1000_READ_REG(hw, E1000_CTRL); + E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); + retry++; + } while (retry); +} + +/* + * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working + * @hw: pointer to the HW structure + * + * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), + * LPLU, Giga disable, MDIC PHY reset): + * 1) Set Kumeran Near-end loopback + * 2) Clear Kumeran Near-end loopback + * Should only be called for ICH8[m] devices with IGP_3 Phy. + */ +void +e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 reg_data; + + DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); + + if ((hw->mac.type != e1000_ich8lan) || + (hw->phy.type != e1000_phy_igp_3)) + return; + + ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + ®_data); + if (ret_val) + return; + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; + ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); + if (ret_val) + return; + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; + ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); +} + +/* + * e1000_cleanup_led_ich8lan - Restore the default LED operation + * @hw: pointer to the HW structure + * + * Return the LED back to the default configuration. + */ +static s32 +e1000_cleanup_led_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_cleanup_led_ich8lan"); + + if (hw->phy.type == e1000_phy_ife) + ret_val = e1000_write_phy_reg(hw, + IFE_PHY_SPECIAL_CONTROL_LED, + 0); + else + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); + + return (ret_val); +} + +/* + * e1000_led_on_ich8lan - Turn LED's on + * @hw: pointer to the HW structure + * + * Turn on the LED's. + */ +static s32 +e1000_led_on_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_led_on_ich8lan"); + + if (hw->phy.type == e1000_phy_ife) + ret_val = e1000_write_phy_reg(hw, + IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); + else + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); + + return (ret_val); +} + +/* + * e1000_led_off_ich8lan - Turn LED's off + * @hw: pointer to the HW structure + * + * Turn off the LED's. + */ +static s32 +e1000_led_off_ich8lan(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_led_off_ich8lan"); + + if (hw->phy.type == e1000_phy_ife) + ret_val = e1000_write_phy_reg(hw, + IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); + else + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); + + return (ret_val); +} + +/* + * e1000_get_cfg_done_ich8lan - Read config done bit + * @hw: pointer to the HW structure + * + * Read the management control register for the config done bit for + * completion status. NOTE: silicon which is EEPROM-less will fail trying + * to read the config done bit, so an error is *ONLY* logged and returns + * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon + * would not be able to be reset or change link. + */ +static s32 +e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) +{ + e1000_get_cfg_done_generic(hw); + + /* If EEPROM is not marked present, init the IGP 3 PHY manually */ + if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && + (hw->phy.type == e1000_phy_igp_3)) { + e1000_phy_init_script_igp3(hw); + } + return (E1000_SUCCESS); +} + +/* + * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters + * @hw: pointer to the HW structure + * + * Clears hardware counters specific to the silicon family and calls + * clear_hw_cntrs_generic to clear all general purpose counters. + */ +static void +e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); + + e1000_clear_hw_cntrs_base_generic(hw); + + temp = E1000_READ_REG(hw, E1000_ALGNERRC); + temp = E1000_READ_REG(hw, E1000_RXERRC); + temp = E1000_READ_REG(hw, E1000_TNCRS); + temp = E1000_READ_REG(hw, E1000_CEXTERR); + temp = E1000_READ_REG(hw, E1000_TSCTC); + temp = E1000_READ_REG(hw, E1000_TSCTFC); + + temp = E1000_READ_REG(hw, E1000_MGTPRC); + temp = E1000_READ_REG(hw, E1000_MGTPDC); + temp = E1000_READ_REG(hw, E1000_MGTPTC); + + temp = E1000_READ_REG(hw, E1000_IAC); + temp = E1000_READ_REG(hw, E1000_ICRXOC); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_ich8lan.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,119 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_ICH8LAN_H_ +#define _E1000_ICH8LAN_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICH_FLASH_GFPREG 0x0000 +#define ICH_FLASH_HSFSTS 0x0004 +#define ICH_FLASH_HSFCTL 0x0006 +#define ICH_FLASH_FADDR 0x0008 +#define ICH_FLASH_FDATA0 0x0010 + +#define ICH_FLASH_READ_COMMAND_TIMEOUT 500 +#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 +#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 + +#define ICH_CYCLE_READ 0 +#define ICH_CYCLE_WRITE 2 +#define ICH_CYCLE_ERASE 3 + +#define FLASH_GFPREG_BASE_MASK 0x1FFF +#define FLASH_SECTOR_ADDR_SHIFT 12 + +#define E1000_SHADOW_RAM_WORDS 2048 + +#define ICH_FLASH_SEG_SIZE_256 256 +#define ICH_FLASH_SEG_SIZE_4K 4096 +#define ICH_FLASH_SEG_SIZE_8K 8192 +#define ICH_FLASH_SEG_SIZE_64K 65536 +#define ICH_FLASH_SECTOR_SIZE 4096 + +#define ICH_FLASH_REG_MAPSIZE 0x00A0 + +#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ +#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ +/* FW established a valid mode */ +#define E1000_ICH_FWSM_FW_VALID 0x00008000 + +#define E1000_ICH_MNG_IAMT_MODE 0x2 + +#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ + (ID_LED_DEF1_OFF2 << 8) | \ + (ID_LED_DEF1_ON2 << 4) | \ + (ID_LED_DEF1_DEF2)) + +#define E1000_ICH_NVM_SIG_WORD 0x13 +#define E1000_ICH_NVM_SIG_MASK 0xC000 + +#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 + +#define E1000_FEXTNVM_SW_CONFIG 1 +#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ + +#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL + +#define E1000_ICH_RAR_ENTRIES 7 + +#define PHY_PAGE_SHIFT 5 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ + ((reg) & MAX_PHY_REG_ADDRESS)) +#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ +#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ +#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ +#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ + +#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 +#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 +#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 +#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 + +/* + * Additional interrupts need to be handled for ICH family: + * DSW = The FW changed the status of the DISSW bit in FWSM + * PHYINT = The LAN connected device generates an interrupt + * EPRST = Manageability reset event + */ +#define IMS_ICH_ENABLE_MASK (\ + E1000_IMS_DSW | \ + E1000_IMS_PHYINT | \ + E1000_IMS_EPRST) + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_ICH8LAN_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_mac.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,2030 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#include "e1000_api.h" +#include "e1000_mac.h" + +/* + * e1000_remove_device_generic - Free device specific structure + * @hw: pointer to the HW structure + * + * If a device specific structure was allocated, this function will + * free it. + */ +void +e1000_remove_device_generic(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_remove_device_generic"); + + /* Freeing the dev_spec member of e1000_hw structure */ + e1000_free_dev_spec_struct(hw); +} + +/* + * e1000_get_bus_info_pci_generic - Get PCI(x) bus information + * @hw: pointer to the HW structure + * + * Determines and stores the system bus information for a particular + * network interface. The following bus information is determined and stored: + * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. + */ +s32 +e1000_get_bus_info_pci_generic(struct e1000_hw *hw) +{ + struct e1000_bus_info *bus = &hw->bus; + u32 status = E1000_READ_REG(hw, E1000_STATUS); + s32 ret_val = E1000_SUCCESS; + u16 pci_header_type; + + DEBUGFUNC("e1000_get_bus_info_pci_generic"); + + /* PCI or PCI-X? */ + bus->type = (status & E1000_STATUS_PCIX_MODE) + ? e1000_bus_type_pcix + : e1000_bus_type_pci; + + /* Bus speed */ + if (bus->type == e1000_bus_type_pci) { + bus->speed = (status & E1000_STATUS_PCI66) + ? e1000_bus_speed_66 + : e1000_bus_speed_33; + } else { + switch (status & E1000_STATUS_PCIX_SPEED) { + case E1000_STATUS_PCIX_SPEED_66: + bus->speed = e1000_bus_speed_66; + break; + case E1000_STATUS_PCIX_SPEED_100: + bus->speed = e1000_bus_speed_100; + break; + case E1000_STATUS_PCIX_SPEED_133: + bus->speed = e1000_bus_speed_133; + break; + default: + bus->speed = e1000_bus_speed_reserved; + break; + } + } + + /* Bus width */ + bus->width = (status & E1000_STATUS_BUS64) + ? e1000_bus_width_64 + : e1000_bus_width_32; + + /* Which PCI(-X) function? */ + e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); + if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) + bus->func = (status & E1000_STATUS_FUNC_MASK) + >> E1000_STATUS_FUNC_SHIFT; + else + bus->func = 0; + + return (ret_val); +} + +/* + * e1000_get_bus_info_pcie_generic - Get PCIe bus information + * @hw: pointer to the HW structure + * + * Determines and stores the system bus information for a particular + * network interface. The following bus information is determined and stored: + * bus speed, bus width, type (PCIe), and PCIe function. + */ +s32 +e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) +{ + struct e1000_bus_info *bus = &hw->bus; + s32 ret_val; + u32 status; + u16 pcie_link_status, pci_header_type; + + DEBUGFUNC("e1000_get_bus_info_pcie_generic"); + + bus->type = e1000_bus_type_pci_express; + bus->speed = e1000_bus_speed_2500; + + ret_val = e1000_read_pcie_cap_reg(hw, + PCIE_LINK_STATUS, + &pcie_link_status); + if (ret_val) + bus->width = e1000_bus_width_unknown; + else + bus->width = (e1000_bus_width)((pcie_link_status & + PCIE_LINK_WIDTH_MASK) >> + PCIE_LINK_WIDTH_SHIFT); + + e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); + if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { + status = E1000_READ_REG(hw, E1000_STATUS); + bus->func = (status & E1000_STATUS_FUNC_MASK) + >> E1000_STATUS_FUNC_SHIFT; + } else { + bus->func = 0; + } + + return (E1000_SUCCESS); +} + +/* + * e1000_clear_vfta_generic - Clear VLAN filter table + * @hw: pointer to the HW structure + * + * Clears the register array which contains the VLAN filter table by + * setting all the values to 0. + */ +void +e1000_clear_vfta_generic(struct e1000_hw *hw) +{ + u32 offset; + + DEBUGFUNC("e1000_clear_vfta_generic"); + + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); + E1000_WRITE_FLUSH(hw); + } +} + +/* + * e1000_write_vfta_generic - Write value to VLAN filter table + * @hw: pointer to the HW structure + * @offset: register offset in VLAN filter table + * @value: register value written to VLAN filter table + * + * Writes value at the given offset in the register array which stores + * the VLAN filter table. + */ +void +e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) +{ + DEBUGFUNC("e1000_write_vfta_generic"); + + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); + E1000_WRITE_FLUSH(hw); +} + +/* + * e1000_init_rx_addrs_generic - Initialize receive address's + * @hw: pointer to the HW structure + * @rar_count: receive address registers + * + * Setups the receive address registers by setting the base receive address + * register to the devices MAC address and clearing all the other receive + * address registers to 0. + */ +void +e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) +{ + u32 i; + + DEBUGFUNC("e1000_init_rx_addrs_generic"); + + /* Setup the receive address */ + DEBUGOUT("Programming MAC Address into RAR[0]\n"); + + e1000_rar_set_generic(hw, hw->mac.addr, 0); + + /* Zero out the other (rar_entry_count - 1) receive addresses */ + DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count - 1); + for (i = 1; i < rar_count; i++) { + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); + E1000_WRITE_FLUSH(hw); + } +} + +/* + * e1000_rar_set_generic - Set receive address register + * @hw: pointer to the HW structure + * @addr: pointer to the receive address + * @index: receive address array register + * + * Sets the receive address array register at index to the address passed + * in by addr. + */ +void +e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) +{ + u32 rar_low, rar_high; + + DEBUGFUNC("e1000_rar_set_generic"); + + /* + * HW expects these in little endian so we reverse the byte order from + * network order (big endian) to little endian + */ + rar_low = ((u32) addr[0] | + ((u32) addr[1] << 8) | + ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); + + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); + + if (!hw->mac.disable_av) + rar_high |= E1000_RAH_AV; + + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); + E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); +} + +/* + * e1000_mta_set_generic - Set multicast filter table address + * @hw: pointer to the HW structure + * @hash_value: determines the MTA register and bit to set + * + * The multicast table address is a register array of 32-bit registers. + * The hash_value is used to determine what register the bit is in, the + * current value is read, the new bit is OR'd in and the new value is + * written back into the register. + */ +void +e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) +{ + u32 hash_bit, hash_reg, mta; + + DEBUGFUNC("e1000_mta_set_generic"); + /* + * The MTA is a register array of 32-bit registers. It is treated like + * an array of (32*mta_reg_count) bits. We want to set bit + * BitArray[hash_value]. So we figure out what register the bit is in, + * read it, OR in the new bit, then write back the new value. The + * (hw->mac.mta_reg_count - 1) serves as a mask to bits 31:5 of the + * hash value which gives us the register we're modifying. The hash + * bit within that register is determined by the lower 5 bits of the + * hash value. + */ + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); + hash_bit = hash_value & 0x1F; + + mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); + + mta |= (1 << hash_bit); + + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); + E1000_WRITE_FLUSH(hw); +} + +/* + * e1000_mc_addr_list_update_generic - Update Multicast addresses + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program + * @rar_used_count: the first RAR register free to program + * @rar_count: total number of supported Receive Address Registers + * + * Updates the Receive Address Registers and Multicast Table Array. + * The caller must have a packed mc_addr_list of multicast addresses. + * The parameter rar_count will usually be hw->mac.rar_entry_count + * unless there are workarounds that change this. + */ +void +e1000_mc_addr_list_update_generic(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count) +{ + u32 hash_value; + u32 i; + + DEBUGFUNC("e1000_mc_addr_list_update_generic"); + + /* + * Load the first set of multicast addresses into the exact filters + * (RAR). If there are not enough to fill the RAR array, clear the + * filters. + */ + for (i = rar_used_count; i < rar_count; i++) { + if (mc_addr_count) { + e1000_rar_set(hw, mc_addr_list, i); + mc_addr_count--; + mc_addr_list += ETH_ADDR_LEN; + } else { + E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); + E1000_WRITE_FLUSH(hw); + } + } + + /* Clear the old settings from the MTA */ + DEBUGOUT("Clearing MTA\n"); + for (i = 0; i < hw->mac.mta_reg_count; i++) { + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + E1000_WRITE_FLUSH(hw); + } + + /* Load any remaining multicast addresses into the hash table. */ + for (; mc_addr_count > 0; mc_addr_count--) { + hash_value = e1000_hash_mc_addr(hw, mc_addr_list); + DEBUGOUT1("Hash value = 0x%03X\n", hash_value); + e1000_mta_set(hw, hash_value); + mc_addr_list += ETH_ADDR_LEN; + } +} + +/* + * e1000_hash_mc_addr_generic - Generate a multicast hash value + * @hw: pointer to the HW structure + * @mc_addr: pointer to a multicast address + * + * Generates a multicast address hash value which is used to determine + * the multicast filter table array address and new table value. See + * e1000_mta_set_generic() + */ +u32 +e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) +{ + u32 hash_value, hash_mask; + u8 bit_shift = 0; + + DEBUGFUNC("e1000_hash_mc_addr_generic"); + + /* Register count multiplied by bits per register */ + hash_mask = (hw->mac.mta_reg_count * 32) - 1; + + /* + * For a mc_filter_type of 0, bit_shift is the number of left-shifts + * where 0xFF would still fall within the hash mask. + */ + while (hash_mask >> bit_shift != 0xFF) + bit_shift++; + + /* + * The portion of the address that is used for the hash table is + * determined by the mc_filter_type setting. The algorithm is such + * that there is a total of 8 bits of shifting. The bit_shift for a + * mc_filter_type of 0 represents the number of left-shifts where the + * MSB of mc_addr[5] would still fall within the hash_mask. Case 0 + * does this exactly. Since there are a total of 8 bits of shifting, + * then mc_addr[4] will shift right the remaining number of bits. Thus + * 8 - bit_shift. The rest of the cases are a variation of this + * algorithm...essentially raising the number of bits to shift + * mc_addr[5] left, while still keeping the 8-bit shifting total. + * + * For example, given the following Destination MAC Address and an mta + * register count of 128 (thus a 4096-bit vector and 0xFFF mask), we + * can see that the bit_shift for case 0 is 4. These are the hash + * values resulting from each mc_filter_type... + * [0] [1] [2] [3] [4] [5] + * 01 AA 00 12 34 56 + * LSB MSB + * + * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 + * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 + * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 + * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 + */ + switch (hw->mac.mc_filter_type) { + default: + case 0: + break; + case 1: + bit_shift += 1; + break; + case 2: + bit_shift += 2; + break; + case 3: + bit_shift += 4; + break; + } + + hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | + (((u16) mc_addr[5]) << bit_shift))); + + return (hash_value); +} + +/* + * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value + * @hw: pointer to the HW structure + * + * In certain situations, a system BIOS may report that the PCIx maximum + * memory read byte count (MMRBC) value is higher than than the actual + * value. We check the PCIx command regsiter with the current PCIx status + * regsiter. + */ +void +e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) +{ + u16 cmd_mmrbc; + u16 pcix_cmd; + u16 pcix_stat_hi_word; + u16 stat_mmrbc; + + DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); + + /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ + if (hw->bus.type != e1000_bus_type_pcix) + return; + + e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); + e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); + cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> + PCIX_COMMAND_MMRBC_SHIFT; + stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> + PCIX_STATUS_HI_MMRBC_SHIFT; + if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) + stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; + if (cmd_mmrbc > stat_mmrbc) { + pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; + pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; + e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); + } +} + +/* + * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters + * @hw: pointer to the HW structure + * + * Clears the base hardware counters by reading the counter registers. + */ +void +e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) +{ + volatile u32 temp; + + DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); + + temp = E1000_READ_REG(hw, E1000_CRCERRS); + temp = E1000_READ_REG(hw, E1000_SYMERRS); + temp = E1000_READ_REG(hw, E1000_MPC); + temp = E1000_READ_REG(hw, E1000_SCC); + temp = E1000_READ_REG(hw, E1000_ECOL); + temp = E1000_READ_REG(hw, E1000_MCC); + temp = E1000_READ_REG(hw, E1000_LATECOL); + temp = E1000_READ_REG(hw, E1000_COLC); + temp = E1000_READ_REG(hw, E1000_DC); + temp = E1000_READ_REG(hw, E1000_SEC); + temp = E1000_READ_REG(hw, E1000_RLEC); + temp = E1000_READ_REG(hw, E1000_XONRXC); + temp = E1000_READ_REG(hw, E1000_XONTXC); + temp = E1000_READ_REG(hw, E1000_XOFFRXC); + temp = E1000_READ_REG(hw, E1000_XOFFTXC); + temp = E1000_READ_REG(hw, E1000_FCRUC); + temp = E1000_READ_REG(hw, E1000_GPRC); + temp = E1000_READ_REG(hw, E1000_BPRC); + temp = E1000_READ_REG(hw, E1000_MPRC); + temp = E1000_READ_REG(hw, E1000_GPTC); + temp = E1000_READ_REG(hw, E1000_GORCL); + temp = E1000_READ_REG(hw, E1000_GORCH); + temp = E1000_READ_REG(hw, E1000_GOTCL); + temp = E1000_READ_REG(hw, E1000_GOTCH); + temp = E1000_READ_REG(hw, E1000_RNBC); + temp = E1000_READ_REG(hw, E1000_RUC); + temp = E1000_READ_REG(hw, E1000_RFC); + temp = E1000_READ_REG(hw, E1000_ROC); + temp = E1000_READ_REG(hw, E1000_RJC); + temp = E1000_READ_REG(hw, E1000_TORL); + temp = E1000_READ_REG(hw, E1000_TORH); + temp = E1000_READ_REG(hw, E1000_TOTL); + temp = E1000_READ_REG(hw, E1000_TOTH); + temp = E1000_READ_REG(hw, E1000_TPR); + temp = E1000_READ_REG(hw, E1000_TPT); + temp = E1000_READ_REG(hw, E1000_MPTC); + temp = E1000_READ_REG(hw, E1000_BPTC); +} + +/* + * e1000_check_for_copper_link_generic - Check for link (Copper) + * @hw: pointer to the HW structure + * + * Checks to see of the link status of the hardware has changed. If a + * change in link status has been detected, then we read the PHY registers + * to get the current speed/duplex if link exists. + */ +s32 +e1000_check_for_copper_link_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + boolean_t link; + + DEBUGFUNC("e1000_check_for_copper_link"); + + /* + * We only want to go out to the PHY registers to see if Auto-Neg has + * completed and/or if our link status has changed. The + * get_link_status flag is set upon receiving a Link Status Change or + * Rx Sequence Error interrupt. + */ + if (!mac->get_link_status) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* + * First we want to see if the MII Status Register reports link. If + * so, then we want to get the current speed/duplex of the PHY. + */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) + goto out; /* No link detected */ + + mac->get_link_status = FALSE; + + /* + * Check if there was DownShift, must be checked immediately after + * link-up + */ + e1000_check_downshift_generic(hw); + + /* + * If we are forcing speed/duplex, then we simply return since we have + * already determined whether we have link or not. + */ + if (!mac->autoneg) { + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + /* + * Auto-Neg is enabled. Auto Speed Detection takes care of MAC + * speed/duplex configuration. So we only need to configure Collision + * Distance in the MAC. + */ + e1000_config_collision_dist_generic(hw); + + /* + * Configure Flow Control now that Auto-Neg has completed. First, we + * need to restore the desired flow control settings because we may + * have had to re-autoneg with a different link partner. + */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_check_for_fiber_link_generic - Check for link (Fiber) + * @hw: pointer to the HW structure + * + * Checks for link up on the hardware. If link is not up and we have + * a signal, then we need to force link up. + */ +s32 +e1000_check_for_fiber_link_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 rxcw; + u32 ctrl; + u32 status; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_check_for_fiber_link_generic"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + status = E1000_READ_REG(hw, E1000_STATUS); + rxcw = E1000_READ_REG(hw, E1000_RXCW); + + /* + * If we don't have link (auto-negotiation failed or link partner + * cannot auto-negotiate), the cable is plugged in (we have signal), + * and our link partner is not trying to auto-negotiate with us (we + * are receiving idles or data), we need to force link up. We also + * need to give auto-negotiation time to complete, in case the cable + * was just plugged in. The autoneg_failed flag does this. + */ + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ + if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && + (!(rxcw & E1000_RXCW_C))) { + if (mac->autoneg_failed == 0) { + mac->autoneg_failed = 1; + goto out; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + goto out; + } + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + /* + * If we are forcing link and we are receiving /C/ ordered + * sets, re-enable auto-negotiation in the TXCW register and + * disable forced link in the Device Control register in an + * attempt to auto-negotiate with our link partner. + */ + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); + E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); + + mac->serdes_has_link = TRUE; + } + +out: + return (ret_val); +} + +/* + * e1000_check_for_serdes_link_generic - Check for link (Serdes) + * @hw: pointer to the HW structure + * + * Checks for link up on the hardware. If link is not up and we have + * a signal, then we need to force link up. + */ +s32 +e1000_check_for_serdes_link_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 rxcw; + u32 ctrl; + u32 status; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_check_for_serdes_link_generic"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + status = E1000_READ_REG(hw, E1000_STATUS); + rxcw = E1000_READ_REG(hw, E1000_RXCW); + + /* + * If we don't have link (auto-negotiation failed or link partner + * cannot auto-negotiate), and our link partner is not trying to + * auto-negotiate with us (we are receiving idles or data), we need to + * force link up. We also need to give auto-negotiation time to + * complete. + */ + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ + if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { + if (mac->autoneg_failed == 0) { + mac->autoneg_failed = 1; + goto out; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) { + DEBUGOUT("Error configuring flow control\n"); + goto out; + } + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + /* + * If we are forcing link and we are receiving /C/ ordered + * sets, re-enable auto-negotiation in the TXCW register and + * disable forced link in the Device Control register in an + * attempt to auto-negotiate with our link partner. + */ + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); + E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); + + mac->serdes_has_link = TRUE; + } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { + /* + * If we force link for non-auto-negotiation switch, check + * link status based on MAC synchronization for internal + * serdes media type. + */ + /* SYNCH bit and IV bit are sticky. */ + usec_delay(10); + if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { + if (!(rxcw & E1000_RXCW_IV)) { + mac->serdes_has_link = TRUE; + DEBUGOUT("SERDES: Link is up.\n"); + } + } else { + mac->serdes_has_link = FALSE; + DEBUGOUT("SERDES: Link is down.\n"); + } + } + + if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { + status = E1000_READ_REG(hw, E1000_STATUS); + mac->serdes_has_link = (status & E1000_STATUS_LU) + ? TRUE + : FALSE; + } + +out: + return (ret_val); +} + +/* + * e1000_setup_link_generic - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow + * control. Calls the appropriate media-specific link configuration + * function. Assuming the adapter has a valid link partner, a valid link + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + */ +s32 +e1000_setup_link_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + struct e1000_functions *func = &hw->func; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_link_generic"); + + /* + * In the case of the phy reset being blocked, we already have a link. + * We do not need to set it up again. + */ + if (e1000_check_reset_block(hw)) + goto out; + + ret_val = e1000_set_default_fc_generic(hw); + if (ret_val) + goto out; + + /* + * We want to save off the original Flow Control configuration just in + * case we get disconnected and then reconnected into a different hub + * or switch with different Flow Control capabilities. + */ + mac->original_fc = mac->fc; + + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); + + /* Call the necessary media_type subroutine to configure the link. */ + ret_val = func->setup_physical_interface(hw); + if (ret_val) + goto out; + + /* + * Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); + E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); + E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); + + E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); + + ret_val = e1000_set_fc_watermarks_generic(hw); + +out: + return (ret_val); +} + +/* + * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes + * @hw: pointer to the HW structure + * + * Configures collision distance and flow control for fiber and serdes + * links. Upon successful setup, poll for link. + */ +s32 +e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* Take the link out of reset */ + ctrl &= ~E1000_CTRL_LRST; + + e1000_config_collision_dist_generic(hw); + + ret_val = e1000_commit_fc_settings_generic(hw); + if (ret_val) + goto out; + + /* + * Since auto-negotiation is enabled, take the link out of reset (the + * link will be in reset, because we previously reset the chip). This + * will restart auto-negotiation. If auto-negotiation is successful + * then the link-up status bit will be set and the flow control enable + * bits (RFCE and TFCE) will be set according to their negotiated value. + */ + DEBUGOUT("Auto-negotiation enabled\n"); + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + msec_delay(1); + + /* + * For these adapters, the SW defineable pin 1 is set when the optics + * detect a signal. If we have a signal, then poll for a "Link-Up" + * indication. + */ + if (hw->media_type == e1000_media_type_internal_serdes || + (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { + ret_val = e1000_poll_fiber_serdes_link_generic(hw); + } else { + DEBUGOUT("No signal detected\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_config_collision_dist_generic - Configure collision distance + * @hw: pointer to the HW structure + * + * Configures the collision distance to the default value and is used + * during link setup. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + */ +void +e1000_config_collision_dist_generic(struct e1000_hw *hw) +{ + u32 tctl; + + DEBUGFUNC("e1000_config_collision_dist_generic"); + + tctl = E1000_READ_REG(hw, E1000_TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; + + E1000_WRITE_REG(hw, E1000_TCTL, tctl); + E1000_WRITE_FLUSH(hw); +} + +/* + * e1000_poll_fiber_serdes_link_generic - Poll for link up + * @hw: pointer to the HW structure + * + * Polls for link up by reading the status register, if link fails to come + * up with auto-negotiation, then the link is forced if a signal is detected. + */ +s32 +e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 i, status; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); + + /* + * If we have a signal (the cable is plugged in, or assumed true for + * serdes media) then poll for a "Link-Up" indication in the Device + * Status Register. Time-out if a link isn't seen in 500 milliseconds + * seconds (Auto-negotiation should complete in less than 500 + * milliseconds even if the other end is doing it in SW). + */ + for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { + msec_delay(10); + status = E1000_READ_REG(hw, E1000_STATUS); + if (status & E1000_STATUS_LU) + break; + } + if (i == FIBER_LINK_UP_LIMIT) { + DEBUGOUT("Never got a valid link from auto-neg!!!\n"); + mac->autoneg_failed = 1; + /* + * AutoNeg failed to achieve a link, so we'll call + * mac->check_for_link. This routine will force the link up if + * we detect a signal. This will allow us to communicate with + * non-autonegotiating link partners. + */ + ret_val = e1000_check_for_link(hw); + if (ret_val) { + DEBUGOUT("Error while checking for link\n"); + goto out; + } + mac->autoneg_failed = 0; + } else { + mac->autoneg_failed = 0; + DEBUGOUT("Valid Link Found\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_commit_fc_settings_generic - Configure flow control + * @hw: pointer to the HW structure + * + * Write the flow control settings to the Transmit Config Word Register (TXCW) + * base on the flow control settings in e1000_mac_info. + */ +s32 +e1000_commit_fc_settings_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 txcw; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_commit_fc_settings_generic"); + + /* + * Check for a software override of the flow control settings, and + * setup the device accordingly. If auto-negotiation is enabled, then + * software will have to set the "PAUSE" bits to the correct value in + * the Transmit Config Word Register (TXCW) and re-start auto- + * negotiation. However, if auto-negotiation is disabled, then + * software will have to manually configure the two flow control enable + * bits in the CTRL register. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but we + * do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + */ + switch (mac->fc) { + case e1000_fc_none: + /* Flow control completely disabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); + break; + case e1000_fc_rx_pause: + /* + * RX Flow control is enabled and TX Flow control is disabled + * by a software over-ride. Since there really isn't a way to + * advertise that we are capable of RX Pause ONLY, we will + * advertise that we support both symmetric and asymmetric RX + * PAUSE. Later, we will disable the adapter's ability to send + * PAUSE frames. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + case e1000_fc_tx_pause: + /* + * TX Flow control is enabled, and RX Flow control is disabled, + * by a software over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); + break; + case e1000_fc_full: + /* + * Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + E1000_WRITE_REG(hw, E1000_TXCW, txcw); + mac->txcw = txcw; + +out: + return (ret_val); +} + +/* + * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks + * @hw: pointer to the HW structure + * + * Sets the flow control high/low threshold (watermark) registers. If + * flow control XON frame transmission is enabled, then set XON frame + * tansmission as well. + */ +s32 +e1000_set_fc_watermarks_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = E1000_SUCCESS; + u32 fcrtl = 0, fcrth = 0; + + DEBUGFUNC("e1000_set_fc_watermarks_generic"); + + /* + * Set the flow control receive threshold registers. Normally, these + * registers will be set to a default threshold that may be adjusted + * later by the driver's runtime code. However, if the ability to + * transmit pause frames is not enabled, then these registers will be + * set to 0. + */ + if (mac->fc & e1000_fc_tx_pause) { + /* + * We need to set up the Receive Threshold high and low water + * marks as well as (optionally) enabling the transmission of + * XON frames. + */ + fcrtl = mac->fc_low_water; + if (mac->fc_send_xon) + fcrtl |= E1000_FCRTL_XONE; + + fcrth = mac->fc_high_water; + } + E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); + E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); + + return (ret_val); +} + +/* + * e1000_set_default_fc_generic - Set flow control default values + * @hw: pointer to the HW structure + * + * Read the EEPROM for the default values for flow control and store the + * values. + */ +s32 +e1000_set_default_fc_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = E1000_SUCCESS; + u16 nvm_data; + + DEBUGFUNC("e1000_set_default_fc_generic"); + + if (mac->fc != e1000_fc_default) + goto out; + + /* + * Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, a + * bit that determines whether the HW defaults to enabling or + * disabling auto-negotiation, and the direction of the SW defined + * pins. If there is no SW over-ride of the flow control setting, then + * the variable hw->fc will be initialized based on a value in the + * EEPROM. + */ + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); + + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) + mac->fc = e1000_fc_none; + else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == + NVM_WORD0F_ASM_DIR) + mac->fc = e1000_fc_tx_pause; + else + mac->fc = e1000_fc_full; + +out: + return (ret_val); +} + +/* + * e1000_force_mac_fc_generic - Force the MAC's flow control settings + * @hw: pointer to the HW structure + * + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the + * device control register to reflect the adapter settings. TFCE and RFCE + * need to be explicitly set by software when a copper PHY is used because + * autonegotiation is managed by the PHY rather than the MAC. Software must + * also configure these bits when link is forced on a fiber connection. + */ +s32 +e1000_force_mac_fc_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_force_mac_fc_generic"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* + * Because we didn't get link via the internal auto-negotiation + * mechanism (we either forced link or we got link via PHY auto-neg), + * we have to manually enable/disable transmit an receive flow + * control. + * + * The "Case" statement below enables/disable flow control according to + * the "mac->fc" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). + * 3: Both Rx and TX flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ + DEBUGOUT1("mac->fc = %u\n", mac->fc); + + switch (mac->fc) { + case e1000_fc_none: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; + case e1000_fc_rx_pause: + ctrl &= (~E1000_CTRL_TFCE); + ctrl |= E1000_CTRL_RFCE; + break; + case e1000_fc_tx_pause: + ctrl &= (~E1000_CTRL_RFCE); + ctrl |= E1000_CTRL_TFCE; + break; + case e1000_fc_full: + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + +out: + return (ret_val); +} + +/* + * e1000_config_fc_after_link_up_generic - Configures flow control after link + * @hw: pointer to the HW structure + * + * Checks the status of auto-negotiation after link up to ensure that the + * speed and duplex were not forced. If the link needed to be forced, then + * flow control needs to be forced also. If auto-negotiation is enabled + * and did not fail, then we configure flow control based on our link + * partner. + */ +s32 +e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = E1000_SUCCESS; + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; + u16 speed, duplex; + + DEBUGFUNC("e1000_config_fc_after_link_up_generic"); + + /* + * Check for the case where we have fiber media and auto-neg failed so + * we had to force link. In this case, we need to force the + * configuration of the MAC to match the "fc" parameter. + */ + if (mac->autoneg_failed) { + if (hw->media_type == e1000_media_type_fiber || + hw->media_type == e1000_media_type_internal_serdes) + ret_val = e1000_force_mac_fc_generic(hw); + } else { + if (hw->media_type == e1000_media_type_copper) + ret_val = e1000_force_mac_fc_generic(hw); + } + + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + goto out; + } + + /* + * Check for the case where we have copper media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg has + * completed, and if so, how the PHY and link partner has flow control + * configured. + */ + if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) { + /* + * Read the MII Status Register and check to see if AutoNeg + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) + goto out; + + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { + DEBUGOUT("Copper PHY and Auto Neg " + "has not completed.\n"); + goto out; + } + /* + * The AutoNeg process has completed, so we now need to read + * both the Auto Negotiation Advertisement Register (Address + * 4) and the Auto_Negotiation Base Page Ability Register + * (Address 5) to determine how flow control was negotiated. + */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, + &mii_nway_adv_reg); + if (ret_val) + goto out; + ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, + &mii_nway_lp_ability_reg); + if (ret_val) + goto out; + + /* + * Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base + * Page Ability Register (Address 5) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + * ------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + * Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + * ------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | E1000_fc_full + * + */ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* + * Now we need to check if the user selected RX ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (mac->original_fc == e1000_fc_full) { + mac->fc = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\r\n"); + } else { + mac->fc = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = " + "RX PAUSE frames only.\r\n"); + } + } + /* + * For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + * ------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { + mac->fc = e1000_fc_tx_pause; + DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); + } + /* + * For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + * ------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { + mac->fc = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); + } + /* + * Per the IEEE spec, at this point flow control should be + * disabled. However, we want to consider that we could be + * connected to a legacy switch that doesn't advertise desired + * flow control, but can be forced on the link partner. So if + * we advertised no flow control, that is what we will resolve + * to. If we advertised some kind of receive capability (Rx + * Pause Only or Full Flow Control) and the link partner + * advertised none, we will configure ourselves to enable Rx + * Flow Control only. We can do this safely for two reasons: + * If the link partner really didn't want flow control + * enabled, and we enable Rx, no harm done since we won't be + * receiving any PAUSE frames anyway. If the intent on the + * link partner was to have flow control enabled, then by us + * enabling RX only, we can at least receive pause frames and + * process them. This is a good idea because in most cases, + * since we are predominantly a server NIC, more times than + * not we will be asked to delay transmission of packets than + * asking our link partner to pause transmission of frames. + */ + else if ((mac->original_fc == e1000_fc_none || + mac->original_fc == e1000_fc_tx_pause) || + mac->fc_strict_ieee) { + mac->fc = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\r\n"); + } else { + mac->fc = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); + } + + /* + * Now we need to do one last check... If we auto- negotiated + * to HALF DUPLEX, flow control should not be enabled per IEEE + * 802.3 spec. + */ + ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); + if (ret_val) { + DEBUGOUT("Error getting link speed and duplex\n"); + goto out; + } + + if (duplex == HALF_DUPLEX) + mac->fc = e1000_fc_none; + + /* + * Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + ret_val = e1000_force_mac_fc_generic(hw); + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + goto out; + } + } + +out: + return (ret_val); +} + +/* + * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex + * + * Read the status register for the current speed/duplex and store the current + * speed and duplex for copper connections. + */ +s32 +e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, + u16 *duplex) +{ + u32 status; + + DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); + + status = E1000_READ_REG(hw, E1000_STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; + DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; + DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; + DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; + DEBUGOUT("Full Duplex\n"); + } else { + *duplex = HALF_DUPLEX; + DEBUGOUT("Half Duplex\n"); + } + + return (E1000_SUCCESS); +} + +/* + * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex + * + * Sets the speed and duplex to gigabit full duplex (the only possible option) + * for fiber/serdes links. + */ +s32 +e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, + u16 *speed, u16 *duplex) +{ + DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); + + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + + return (E1000_SUCCESS); +} + +/* + * e1000_get_hw_semaphore_generic - Acquire hardware semaphore + * @hw: pointer to the HW structure + * + * Acquire the HW semaphore to access the PHY or NVM + */ +s32 +e1000_get_hw_semaphore_generic(struct e1000_hw *hw) +{ + u32 swsm; + s32 ret_val = E1000_SUCCESS; + s32 timeout = hw->nvm.word_size + 1; + s32 i = 0; + + DEBUGFUNC("e1000_get_hw_semaphore_generic"); + + /* Get the SW semaphore */ + while (i < timeout) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + + usec_delay(50); + i++; + } + + if (i == timeout) { + DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + /* Get the FW semaphore. */ + for (i = 0; i < timeout; i++) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); + + /* Semaphore acquired if bit latched */ + if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) + break; + + usec_delay(50); + } + + if (i == timeout) { + /* Release semaphores */ + e1000_put_hw_semaphore_generic(hw); + DEBUGOUT("Driver can't access the NVM\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_put_hw_semaphore_generic - Release hardware semaphore + * @hw: pointer to the HW structure + * + * Release hardware semaphore used to access the PHY or NVM + */ +void +e1000_put_hw_semaphore_generic(struct e1000_hw *hw) +{ + u32 swsm; + + DEBUGFUNC("e1000_put_hw_semaphore_generic"); + + swsm = E1000_READ_REG(hw, E1000_SWSM); + + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + + E1000_WRITE_REG(hw, E1000_SWSM, swsm); +} + +/* + * e1000_get_auto_rd_done_generic - Check for auto read completion + * @hw: pointer to the HW structure + * + * Check EEPROM for Auto Read done bit. + */ +s32 +e1000_get_auto_rd_done_generic(struct e1000_hw *hw) +{ + s32 i = 0; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_get_auto_rd_done_generic"); + + while (i < AUTO_READ_DONE_TIMEOUT) { + if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) + break; + msec_delay(1); + i++; + } + + if (i == AUTO_READ_DONE_TIMEOUT) { + DEBUGOUT("Auto read by HW from NVM has not completed.\n"); + ret_val = -E1000_ERR_RESET; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_valid_led_default_generic - Verify a valid default LED config + * @hw: pointer to the HW structure + * @data: pointer to the NVM (EEPROM) + * + * Read the EEPROM for the current default LED configuration. If the + * LED configuration is not valid, set to a valid LED configuration. + */ +s32 +e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_valid_led_default_generic"); + + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT; + +out: + return (ret_val); +} + +/* + * e1000_id_led_init_generic - + * @hw: pointer to the HW structure + * + */ +s32 +e1000_id_led_init_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + const u32 ledctl_mask = 0x000000FF; + const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; + const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; + u16 data, i, temp; + const u16 led_mask = 0x0F; + + DEBUGFUNC("e1000_id_led_init_generic"); + + ret_val = hw->func.valid_led_default(hw, &data); + if (ret_val) + goto out; + + mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); + mac->ledctl_mode1 = mac->ledctl_default; + mac->ledctl_mode2 = mac->ledctl_default; + + for (i = 0; i < 4; i++) { + temp = (data >> (i << 2)) & led_mask; + switch (temp) { + case ID_LED_ON1_DEF2: + case ID_LED_ON1_ON2: + case ID_LED_ON1_OFF2: + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); + mac->ledctl_mode1 |= ledctl_on << (i << 3); + break; + case ID_LED_OFF1_DEF2: + case ID_LED_OFF1_ON2: + case ID_LED_OFF1_OFF2: + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); + mac->ledctl_mode1 |= ledctl_off << (i << 3); + break; + default: + /* Do nothing */ + break; + } + switch (temp) { + case ID_LED_DEF1_ON2: + case ID_LED_ON1_ON2: + case ID_LED_OFF1_ON2: + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); + mac->ledctl_mode2 |= ledctl_on << (i << 3); + break; + case ID_LED_DEF1_OFF2: + case ID_LED_ON1_OFF2: + case ID_LED_OFF1_OFF2: + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); + mac->ledctl_mode2 |= ledctl_off << (i << 3); + break; + default: + /* Do nothing */ + break; + } + } + +out: + return (ret_val); +} + +/* + * e1000_setup_led_generic - Configures SW controllable LED + * @hw: pointer to the HW structure + * + * This prepares the SW controllable LED for use and saves the current state + * of the LED so it can be later restored. + */ +s32 +e1000_setup_led_generic(struct e1000_hw *hw) +{ + u32 ledctl; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_setup_led_generic"); + + if (hw->func.setup_led != e1000_setup_led_generic) { + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + if (hw->media_type == e1000_media_type_fiber) { + ledctl = E1000_READ_REG(hw, E1000_LEDCTL); + hw->mac.ledctl_default = ledctl; + /* Turn off LED0 */ + ledctl &= ~(E1000_LEDCTL_LED0_IVRT | + E1000_LEDCTL_LED0_BLINK | + E1000_LEDCTL_LED0_MODE_MASK); + ledctl |= (E1000_LEDCTL_MODE_LED_OFF << + E1000_LEDCTL_LED0_MODE_SHIFT); + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); + } else if (hw->media_type == e1000_media_type_copper) { + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); + } + +out: + return (ret_val); +} + +/* + * e1000_cleanup_led_generic - Set LED config to default operation + * @hw: pointer to the HW structure + * + * Remove the current LED configuration and set the LED configuration + * to the default value, saved from the EEPROM. + */ +s32 +e1000_cleanup_led_generic(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_cleanup_led_generic"); + + if (hw->func.cleanup_led != e1000_cleanup_led_generic) { + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); + +out: + return (ret_val); +} + +/* + * e1000_blink_led_generic - Blink LED + * @hw: pointer to the HW structure + * + * Blink the led's which are set to be on. + */ +s32 +e1000_blink_led_generic(struct e1000_hw *hw) +{ + u32 ledctl_blink = 0; + u32 i; + + DEBUGFUNC("e1000_blink_led_generic"); + + if (hw->media_type == e1000_media_type_fiber) { + /* always blink LED0 for PCI-E fiber */ + ledctl_blink = E1000_LEDCTL_LED0_BLINK | + (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); + } else { + /* + * set the blink bit for each LED that's "on" (0x0E) + * in ledctl_mode2 + */ + ledctl_blink = hw->mac.ledctl_mode2; + for (i = 0; i < 4; i++) + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == + E1000_LEDCTL_MODE_LED_ON) + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << + (i * 8)); + } + + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); + + return (E1000_SUCCESS); +} + +/* + * e1000_led_on_generic - Turn LED on + * @hw: pointer to the HW structure + * + * Turn LED on. + */ +s32 +e1000_led_on_generic(struct e1000_hw *hw) +{ + u32 ctrl; + + DEBUGFUNC("e1000_led_on_generic"); + + switch (hw->media_type) { + case e1000_media_type_fiber: + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl &= ~E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + break; + case e1000_media_type_copper: + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); + break; + default: + break; + } + + return (E1000_SUCCESS); +} + +/* + * e1000_led_off_generic - Turn LED off + * @hw: pointer to the HW structure + * + * Turn LED off. + */ +s32 +e1000_led_off_generic(struct e1000_hw *hw) +{ + u32 ctrl; + + DEBUGFUNC("e1000_led_off_generic"); + + switch (hw->media_type) { + case e1000_media_type_fiber: + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SWDPIN0; + ctrl |= E1000_CTRL_SWDPIO0; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + break; + case e1000_media_type_copper: + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); + break; + default: + break; + } + + return (E1000_SUCCESS); +} + +/* + * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities + * @hw: pointer to the HW structure + * @no_snoop: bitmap of snoop events + * + * Set the PCI-express register to snoop for events enabled in 'no_snoop'. + */ +void +e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) +{ + u32 gcr; + + DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); + + if (hw->bus.type != e1000_bus_type_pci_express) + return; + + if (no_snoop) { + gcr = E1000_READ_REG(hw, E1000_GCR); + gcr &= ~(PCIE_NO_SNOOP_ALL); + gcr |= no_snoop; + E1000_WRITE_REG(hw, E1000_GCR, gcr); + } +} + +/* + * e1000_disable_pcie_master_generic - Disables PCI-express master access + * @hw: pointer to the HW structure + * + * Returns 0 (E1000_SUCCESS) if successful, else returns -10 + * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued + * the master requests to be disabled. + * + * Disables PCI-Express master access and verifies there are no pending + * requests. + */ +s32 +e1000_disable_pcie_master_generic(struct e1000_hw *hw) +{ + u32 ctrl; + s32 timeout = MASTER_DISABLE_TIMEOUT; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_disable_pcie_master_generic"); + + if (hw->bus.type != e1000_bus_type_pci_express) + goto out; + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + while (timeout) { + if (!(E1000_READ_REG(hw, E1000_STATUS) & + E1000_STATUS_GIO_MASTER_ENABLE)) + break; + usec_delay(100); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Master requests are pending.\n"); + ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Reset the Adaptive Interframe Spacing throttle to default values. + */ +void +e1000_reset_adaptive_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + + DEBUGFUNC("e1000_reset_adaptive_generic"); + + if (!mac->adaptive_ifs) { + DEBUGOUT("Not in Adaptive IFS mode!\n"); + return; + } + + if (!mac->ifs_params_forced) { + mac->current_ifs_val = 0; + mac->ifs_min_val = IFS_MIN; + mac->ifs_max_val = IFS_MAX; + mac->ifs_step_size = IFS_STEP; + mac->ifs_ratio = IFS_RATIO; + } + + mac->in_ifs_mode = FALSE; + E1000_WRITE_REG(hw, E1000_AIT, 0); +} + +/* + * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Update the Adaptive Interframe Spacing Throttle value based on the + * time between transmitted packets and time between collisions. + */ +void +e1000_update_adaptive_generic(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + + DEBUGFUNC("e1000_update_adaptive_generic"); + + if (!mac->adaptive_ifs) { + DEBUGOUT("Not in Adaptive IFS mode!\n"); + return; + } + + if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { + if (mac->tx_packet_delta > MIN_NUM_XMITS) { + mac->in_ifs_mode = TRUE; + if (mac->current_ifs_val < mac->ifs_max_val) { + if (!mac->current_ifs_val) + mac->current_ifs_val = mac->ifs_min_val; + else + mac->current_ifs_val += + mac->ifs_step_size; + E1000_WRITE_REG(hw, E1000_AIT, + mac->current_ifs_val); + } + } + } else { + if (mac->in_ifs_mode && + (mac->tx_packet_delta <= MIN_NUM_XMITS)) { + mac->current_ifs_val = 0; + mac->in_ifs_mode = FALSE; + E1000_WRITE_REG(hw, E1000_AIT, 0); + } + } +} + +/* + * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings + * @hw: pointer to the HW structure + * + * Verify that when not using auto-negotitation that MDI/MDIx is correctly + * set, which is forced to MDI mode only. + */ +s32 +e1000_validate_mdi_setting_generic(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_validate_mdi_setting_generic"); + + if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { + DEBUGOUT("Invalid MDI setting detected\n"); + hw->phy.mdix = 1; + ret_val = -E1000_ERR_CONFIG; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register + * @hw: pointer to the HW structure + * @reg: 32bit register offset such as E1000_SCTL + * @offset: register offset to write to + * @data: data to write at register offset + * + * Writes an address/data control type register. There are several of these + * and they all have the format address << 8 | data and bit 31 is polled for + * completion. + */ +s32 +e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, + u32 offset, u8 data) +{ + u32 i, regvalue = 0; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); + + /* Set up the address and data */ + regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); + E1000_WRITE_REG(hw, reg, regvalue); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { + usec_delay(5); + regvalue = E1000_READ_REG(hw, reg); + if (regvalue & E1000_GEN_CTL_READY) + break; + } + if (!(regvalue & E1000_GEN_CTL_READY)) { + DEBUGOUT1("Reg %08x did not indicate ready\n", reg); + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_mac.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,95 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_MAC_H_ +#define _E1000_MAC_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Functions that should not be called directly from drivers but can be used + * by other files in this 'shared code' + */ +s32 e1000_blink_led_generic(struct e1000_hw *hw); +s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw); +s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); +s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw); +s32 e1000_cleanup_led_generic(struct e1000_hw *hw); +s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); +s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw); +s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw); +s32 e1000_force_mac_fc_generic(struct e1000_hw *hw); +s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw); +s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw); +s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw); +s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw); +s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, + u16 *duplex); +s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, + u16 *speed, u16 *duplex); +s32 e1000_id_led_init_generic(struct e1000_hw *hw); +s32 e1000_led_on_generic(struct e1000_hw *hw); +s32 e1000_led_off_generic(struct e1000_hw *hw); +void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count); +s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); +s32 e1000_set_default_fc_generic(struct e1000_hw *hw); +s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw); +s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw); +s32 e1000_setup_led_generic(struct e1000_hw *hw); +s32 e1000_setup_link_generic(struct e1000_hw *hw); +s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); +s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, + u32 offset, u8 data); + +u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr); + +void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw); +void e1000_clear_vfta_generic(struct e1000_hw *hw); +void e1000_config_collision_dist_generic(struct e1000_hw *hw); +void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count); +void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value); +void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw); +void e1000_put_hw_semaphore_generic(struct e1000_hw *hw); +void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); +void e1000_remove_device_generic(struct e1000_hw *hw); +void e1000_reset_adaptive_generic(struct e1000_hw *hw); +void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop); +void e1000_update_adaptive_generic(struct e1000_hw *hw); +void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_MAC_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_manage.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,393 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#include "e1000_api.h" +#include "e1000_manage.h" + +static u8 e1000_calculate_checksum(u8 *buffer, u32 length); + +/* + * e1000_calculate_checksum - Calculate checksum for buffer + * @buffer: pointer to EEPROM + * @length: size of EEPROM to calculate a checksum for + * + * Calculates the checksum for some buffer on a specified length. The + * checksum calculated is returned. + */ +static u8 +e1000_calculate_checksum(u8 *buffer, u32 length) +{ + u32 i; + u8 sum = 0; + + DEBUGFUNC("e1000_calculate_checksum"); + + if (!buffer) + return (0); + + for (i = 0; i < length; i++) + sum += buffer[i]; + + return (u8)(0 - sum); +} + +/* + * e1000_mng_enable_host_if_generic - Checks host interface is enabled + * @hw: pointer to the HW structure + * + * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND + * + * This function checks whether the HOST IF is enabled for command operaton + * and also checks whether the previous command is completed. It busy waits + * in case of previous command is not completed. + */ +s32 +e1000_mng_enable_host_if_generic(struct e1000_hw *hw) +{ + u32 hicr; + s32 ret_val = E1000_SUCCESS; + u8 i; + + DEBUGFUNC("e1000_mng_enable_host_if_generic"); + + /* Check that the host interface is enabled. */ + hicr = E1000_READ_REG(hw, E1000_HICR); + if ((hicr & E1000_HICR_EN) == 0) { + DEBUGOUT("E1000_HOST_EN bit disabled.\n"); + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; + goto out; + } + /* check the previous command is completed */ + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { + hicr = E1000_READ_REG(hw, E1000_HICR); + if (!(hicr & E1000_HICR_C)) + break; + msec_delay_irq(1); + } + + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { + DEBUGOUT("Previous command timeout failed .\n"); + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; + goto out; + } +out: + return (ret_val); +} + +/* + * e1000_check_mng_mode_generic - Generic check managament mode + * @hw: pointer to the HW structure + * + * Reads the firmware semaphore register and returns true (>0) if + * manageability is enabled, else false (0). + */ +boolean_t +e1000_check_mng_mode_generic(struct e1000_hw *hw) +{ + u32 fwsm; + + DEBUGFUNC("e1000_check_mng_mode_generic"); + + fwsm = E1000_READ_REG(hw, E1000_FWSM); + + return ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); +} + +/* + * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX + * @hw: pointer to the HW structure + * + * Enables packet filtering on transmit packets if manageability is enabled + * and host interface is enabled. + */ +boolean_t +e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) +{ + struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; + u32 *buffer = (u32 *)&hw->mng_cookie; + u32 offset; + s32 ret_val, hdr_csum, csum; + u8 i, len; + boolean_t tx_filter = TRUE; + + DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic"); + + /* No manageability, no filtering */ + if (!e1000_check_mng_mode(hw)) { + tx_filter = FALSE; + goto out; + } + + /* + * If we can't read from the host interface for whatever reason, + * disable filtering. + */ + ret_val = e1000_mng_enable_host_if(hw); + if (ret_val != E1000_SUCCESS) { + tx_filter = FALSE; + goto out; + } + + /* Read in the header. Length and offset are in dwords. */ + len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; + offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; + for (i = 0; i < len; i++) { + *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, + E1000_HOST_IF, + offset + i); + } + hdr_csum = hdr->checksum; + hdr->checksum = 0; + csum = e1000_calculate_checksum((u8 *)hdr, + E1000_MNG_DHCP_COOKIE_LENGTH); + /* + * If either the checksums or signature don't match, then the cookie + * area isn't considered valid, in which case we take the safe route + * of assuming Tx filtering is enabled. + */ + if (hdr_csum != csum) + goto out; + if (hdr->signature != E1000_IAMT_SIGNATURE) + goto out; + + /* Cookie area is valid, make the final check for filtering. */ + if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) + tx_filter = FALSE; + +out: + hw->mac.tx_pkt_filtering = tx_filter; + return (tx_filter); +} + +/* + * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface + * @hw: pointer to the HW structure + * @buffer: pointer to the host interface + * @length: size of the buffer + * + * Writes the DHCP information to the host interface. + */ +s32 +e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer, + u16 length) +{ + struct e1000_host_mng_command_header hdr; + s32 ret_val; + u32 hicr; + + DEBUGFUNC("e1000_mng_write_dhcp_info_generic"); + + hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; + hdr.command_length = length; + hdr.reserved1 = 0; + hdr.reserved2 = 0; + hdr.checksum = 0; + + /* Enable the host interface */ + ret_val = e1000_mng_enable_host_if(hw); + if (ret_val) + goto out; + + /* Populate the host interface with the contents of "buffer". */ + ret_val = e1000_mng_host_if_write(hw, buffer, length, + sizeof (hdr), &(hdr.checksum)); + if (ret_val) + goto out; + + /* Write the manageability command header */ + ret_val = e1000_mng_write_cmd_header(hw, &hdr); + if (ret_val) + goto out; + + /* Tell the ARC a new command is pending. */ + hicr = E1000_READ_REG(hw, E1000_HICR); + E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C); + +out: + return (ret_val); +} + +/* + * e1000_mng_write_cmd_header_generic - Writes manageability command header + * @hw: pointer to the HW structure + * @hdr: pointer to the host interface command header + * + * Writes the command header after does the checksum calculation. + */ +s32 +e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, + struct e1000_host_mng_command_header *hdr) +{ + u16 i, length = sizeof (struct e1000_host_mng_command_header); + + DEBUGFUNC("e1000_mng_write_cmd_header_generic"); + + /* Write the whole command header structure with new checksum. */ + + hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); + + length >>= 2; + /* Write the relevant command block into the ram area. */ + for (i = 0; i < length; i++) { + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i, + *((u32 *) hdr + i)); + E1000_WRITE_FLUSH(hw); + } + + return (E1000_SUCCESS); +} + +/* + * e1000_mng_host_if_write_generic - Writes to the manageability host interface + * @hw: pointer to the HW structure + * @buffer: pointer to the host interface buffer + * @length: size of the buffer + * @offset: location in the buffer to write to + * @sum: sum of the data (not checksum) + * + * This function writes the buffer content at the offset given on the host if. + * It also does alignment considerations to do the writes in most efficient + * way. Also fills up the sum of the buffer in *buffer parameter. + */ +s32 +e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, + u16 length, u16 offset, u8 *sum) +{ + u8 *tmp; + u8 *bufptr = buffer; + u32 data = 0; + s32 ret_val = E1000_SUCCESS; + u16 remaining, i, j, prev_bytes; + + DEBUGFUNC("e1000_mng_host_if_write_generic"); + + /* sum = only sum of the data and it is not checksum */ + + if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { + ret_val = -E1000_ERR_PARAM; + goto out; + } + + tmp = (u8 *)&data; + prev_bytes = offset & 0x3; + offset >>= 2; + + if (prev_bytes) { + data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset); + for (j = prev_bytes; j < sizeof (u32); j++) { + *(tmp + j) = *bufptr++; + *sum += *(tmp + j); + } + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data); + length -= j - prev_bytes; + offset++; + } + + remaining = length & 0x3; + length -= remaining; + + /* Calculate length in DWORDs */ + length >>= 2; + + /* + * The device driver writes the relevant command block into the ram + * area. + */ + for (i = 0; i < length; i++) { + for (j = 0; j < sizeof (u32); j++) { + *(tmp + j) = *bufptr++; + *sum += *(tmp + j); + } + + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, + offset + i, data); + } + if (remaining) { + for (j = 0; j < sizeof (u32); j++) { + if (j < remaining) + *(tmp + j) = *bufptr++; + else + *(tmp + j) = 0; + + *sum += *(tmp + j); + } + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, + offset + i, data); + } +out: + return (ret_val); +} + +/* + * e1000_enable_mng_pass_thru - Enable processing of ARP's + * @hw: pointer to the HW structure + * + * Verifies the hardware needs to allow ARPs to be processed by the host. + */ +boolean_t +e1000_enable_mng_pass_thru(struct e1000_hw *hw) +{ + u32 manc; + u32 fwsm, factps; + boolean_t ret_val = FALSE; + + DEBUGFUNC("e1000_enable_mng_pass_thru"); + + if (!hw->mac.asf_firmware_present) + goto out; + + manc = E1000_READ_REG(hw, E1000_MANC); + + if (!(manc & E1000_MANC_RCV_TCO_EN) || + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) + goto out; + + if (hw->mac.arc_subsystem_valid) { + fwsm = E1000_READ_REG(hw, E1000_FWSM); + factps = E1000_READ_REG(hw, E1000_FACTPS); + + if (!(factps & E1000_FACTPS_MNGCG) && + ((fwsm & E1000_FWSM_MODE_MASK) == + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { + ret_val = TRUE; + goto out; + } + } else { + if ((manc & E1000_MANC_SMBUS_EN) && + !(manc & E1000_MANC_ASF_EN)) { + ret_val = TRUE; + goto out; + } + } + +out: + return (ret_val); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_manage.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,91 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_MANAGE_H_ +#define _E1000_MANAGE_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +boolean_t e1000_check_mng_mode_generic(struct e1000_hw *hw); +boolean_t e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); +s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); +s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, + u16 length, u16 offset, u8 *sum); +s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, + struct e1000_host_mng_command_header *hdr); +s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, + u8 *buffer, u16 length); + +typedef enum { + e1000_mng_mode_none = 0, + e1000_mng_mode_asf, + e1000_mng_mode_pt, + e1000_mng_mode_ipmi, + e1000_mng_mode_host_if_only +} e1000_mng_mode; + +#define E1000_FACTPS_MNGCG 0x20000000 + +#define E1000_FWSM_MODE_MASK 0xE +#define E1000_FWSM_MODE_SHIFT 1 + +#define E1000_MNG_IAMT_MODE 0x3 +#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 +#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 +#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 +#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 + +#define E1000_VFTA_ENTRY_SHIFT 5 +#define E1000_VFTA_ENTRY_MASK 0x7F +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F + +#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ +#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ +#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ + +#define E1000_HICR_EN 0x01 /* Enable bit - RO */ +/* Driver sets this bit when done to put command in RAM */ +#define E1000_HICR_C 0x02 +#define E1000_HICR_SV 0x04 /* Status Validity */ +#define E1000_HICR_FW_RESET_ENABLE 0x40 +#define E1000_HICR_FW_RESET 0x80 + +/* Intel(R) Active Management Technology signature */ +#define E1000_IAMT_SIGNATURE 0x544D4149 + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_MANAGE_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_nvm.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,914 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#include "e1000_api.h" +#include "e1000_nvm.h" + +/* + * e1000_raise_eec_clk - Raise EEPROM clock + * @hw: pointer to the HW structure + * @eecd: pointer to the EEPROM + * + * Enable/Raise the EEPROM clock bit. + */ +static void +e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) +{ + *eecd = *eecd | E1000_EECD_SK; + E1000_WRITE_REG(hw, E1000_EECD, *eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->nvm.delay_usec); +} + +/* + * e1000_lower_eec_clk - Lower EEPROM clock + * @hw: pointer to the HW structure + * @eecd: pointer to the EEPROM + * + * Clear/Lower the EEPROM clock bit. + */ +static void +e1000_lower_eec_clk(struct e1000_hw *hw, u32 * eecd) +{ + *eecd = *eecd & ~E1000_EECD_SK; + E1000_WRITE_REG(hw, E1000_EECD, *eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(hw->nvm.delay_usec); +} + +/* + * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM + * @hw: pointer to the HW structure + * @data: data to send to the EEPROM + * @count: number of bits to shift out + * + * We need to shift 'count' bits out to the EEPROM. So, the value in the + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ +static void +e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u32 mask; + + DEBUGFUNC("e1000_shift_out_eec_bits"); + + mask = 0x01 << (count - 1); + if (nvm->type == e1000_nvm_eeprom_microwire) + eecd &= ~E1000_EECD_DO; + else if (nvm->type == e1000_nvm_eeprom_spi) + eecd |= E1000_EECD_DO; + + do { + eecd &= ~E1000_EECD_DI; + + if (data & mask) + eecd |= E1000_EECD_DI; + + E1000_WRITE_REG(hw, E1000_EECD, eecd); + E1000_WRITE_FLUSH(hw); + + usec_delay(nvm->delay_usec); + + e1000_raise_eec_clk(hw, &eecd); + e1000_lower_eec_clk(hw, &eecd); + + mask >>= 1; + } while (mask); + + eecd &= ~E1000_EECD_DI; + E1000_WRITE_REG(hw, E1000_EECD, eecd); +} + +/* + * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM + * @hw: pointer to the HW structure + * @count: number of bits to shift in + * + * In order to read a register from the EEPROM, we need to shift 'count' bits + * in from the EEPROM. Bits are "shifted in" by raising the clock input to + * the EEPROM (setting the SK bit), and then reading the value of the data out + * "DO" bit. During this "shifting in" process the data in "DI" bit should + * always be clear. + */ +static u16 +e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) +{ + u32 eecd; + u32 i; + u16 data; + + DEBUGFUNC("e1000_shift_in_eec_bits"); + + eecd = E1000_READ_REG(hw, E1000_EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < count; i++) { + data <<= 1; + e1000_raise_eec_clk(hw, &eecd); + + eecd = E1000_READ_REG(hw, E1000_EECD); + + eecd &= ~E1000_EECD_DI; + if (eecd & E1000_EECD_DO) + data |= 1; + + e1000_lower_eec_clk(hw, &eecd); + } + + return (data); +} + +/* + * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion + * @hw: pointer to the HW structure + * @ee_reg: EEPROM flag for polling + * + * Polls the EEPROM status bit for either read or write completion based + * upon the value of 'ee_reg'. + */ +s32 +e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) +{ + u32 attempts = 100000; + u32 i, reg = 0; + s32 ret_val = -E1000_ERR_NVM; + + DEBUGFUNC("e1000_poll_eerd_eewr_done"); + + for (i = 0; i < attempts; i++) { + if (ee_reg == E1000_NVM_POLL_READ) + reg = E1000_READ_REG(hw, E1000_EERD); + else + reg = E1000_READ_REG(hw, E1000_EEWR); + + if (reg & E1000_NVM_RW_REG_DONE) { + ret_val = E1000_SUCCESS; + break; + } + + usec_delay(5); + } + + return (ret_val); +} + +/* + * e1000_acquire_nvm_generic - Generic request for access to EEPROM + * @hw: pointer to the HW structure + * + * Set the EEPROM access request bit and wait for EEPROM access grant bit. + * Return successful if access grant bit set, else clear the request for + * EEPROM access and return -E1000_ERR_NVM (-1). + */ +s32 +e1000_acquire_nvm_generic(struct e1000_hw *hw) +{ + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + s32 timeout = E1000_NVM_GRANT_ATTEMPTS; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_acquire_nvm_generic"); + + E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); + eecd = E1000_READ_REG(hw, E1000_EECD); + + while (timeout) { + if (eecd & E1000_EECD_GNT) + break; + usec_delay(5); + eecd = E1000_READ_REG(hw, E1000_EECD); + timeout--; + } + + if (!timeout) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + DEBUGOUT("Could not acquire NVM grant\n"); + ret_val = -E1000_ERR_NVM; + } + return (ret_val); +} + +/* + * e1000_standby_nvm - Return EEPROM to standby state + * @hw: pointer to the HW structure + * + * Return the EEPROM to a standby state. + */ +static void +e1000_standby_nvm(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + + DEBUGFUNC("e1000_standby_nvm"); + + if (nvm->type == e1000_nvm_eeprom_microwire) { + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(nvm->delay_usec); + + e1000_raise_eec_clk(hw, &eecd); + + /* Select EEPROM */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(nvm->delay_usec); + + e1000_lower_eec_clk(hw, &eecd); + } else if (nvm->type == e1000_nvm_eeprom_spi) { + /* Toggle CS to flush commands */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(nvm->delay_usec); + eecd &= ~E1000_EECD_CS; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + E1000_WRITE_FLUSH(hw); + usec_delay(nvm->delay_usec); + } +} + +/* + * e1000_stop_nvm - Terminate EEPROM command + * @hw: pointer to the HW structure + * + * Terminates the current command by inverting the EEPROM's chip select pin. + */ +void +e1000_stop_nvm(struct e1000_hw *hw) +{ + u32 eecd; + + DEBUGFUNC("e1000_stop_nvm"); + + eecd = E1000_READ_REG(hw, E1000_EECD); + if (hw->nvm.type == e1000_nvm_eeprom_spi) { + /* Pull CS high */ + eecd |= E1000_EECD_CS; + e1000_lower_eec_clk(hw, &eecd); + } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { + /* CS on Microcwire is active-high */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + e1000_raise_eec_clk(hw, &eecd); + e1000_lower_eec_clk(hw, &eecd); + } +} + +/* + * e1000_release_nvm_generic - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * Stop any current commands to the EEPROM and clear the EEPROM request bit. + */ +void +e1000_release_nvm_generic(struct e1000_hw *hw) +{ + u32 eecd; + + DEBUGFUNC("e1000_release_nvm_generic"); + + e1000_stop_nvm(hw); + + eecd = E1000_READ_REG(hw, E1000_EECD); + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, E1000_EECD, eecd); +} + +/* + * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write + * @hw: pointer to the HW structure + * + * Setups the EEPROM for reading and writing. + */ +static s32 +e1000_ready_nvm_eeprom(struct e1000_hw *hw) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + s32 ret_val = E1000_SUCCESS; + u16 timeout = 0; + u8 spi_stat_reg; + + DEBUGFUNC("e1000_ready_nvm_eeprom"); + + if (nvm->type == e1000_nvm_eeprom_microwire) { + /* Clear SK and DI */ + eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + /* Set CS */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, E1000_EECD, eecd); + } else if (nvm->type == e1000_nvm_eeprom_spi) { + /* Clear SK and CS */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + usec_delay(1); + timeout = NVM_MAX_RETRY_SPI; + + /* + * Read "Status Register" repeatedly until the LSB is cleared. + * The EEPROM will signal that the command has been completed + * by clearing bit 0 of the internal status register. If it's + * not cleared within 'timeout', then error out. + */ + while (timeout) { + e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, + hw->nvm.opcode_bits); + spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); + if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) + break; + + usec_delay(5); + e1000_standby_nvm(hw); + timeout--; + } + + if (!timeout) { + DEBUGOUT("SPI NVM Status error\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + } + +out: + return (ret_val); +} + +/* + * e1000_read_nvm_spi - Read EEPROM's using SPI + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read + * @data: word read from the EEPROM + * + * Reads a 16 bit word from the EEPROM. + */ +s32 +e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 * data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i = 0; + s32 ret_val; + u16 word_in; + u8 read_opcode = NVM_READ_OPCODE_SPI; + + DEBUGFUNC("e1000_read_nvm_spi"); + + /* + * A check for invalid values: offset too large, too many words, and + * not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) + goto release; + + e1000_standby_nvm(hw); + + if ((nvm->address_bits == 8) && (offset >= 128)) + read_opcode |= NVM_A8_OPCODE_SPI; + + /* Send the READ command (opcode + addr) */ + e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); + e1000_shift_out_eec_bits(hw, (u16)(offset * 2), nvm->address_bits); + + /* + * Read the data. SPI NVMs increment the address with each byte read + * and will roll over if reading beyond the end. This allows us to + * read the whole NVM from any offset + */ + for (i = 0; i < words; i++) { + word_in = e1000_shift_in_eec_bits(hw, 16); + data[i] = (word_in >> 8) | (word_in << 8); + } + +release: + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_nvm_microwire - Reads EEPROM's using microwire + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read + * @data: word read from the EEPROM + * + * Reads a 16 bit word from the EEPROM. + */ +s32 +e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i = 0; + s32 ret_val; + u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; + + DEBUGFUNC("e1000_read_nvm_microwire"); + + /* + * A check for invalid values: offset too large, too many words, and + * not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) + goto release; + + for (i = 0; i < words; i++) { + /* Send the READ command (opcode + addr) */ + e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); + e1000_shift_out_eec_bits(hw, (u16)(offset + i), + nvm->address_bits); + + /* + * Read the data. For microwire, each word requires the + * overhead of setup and tear-down. + */ + data[i] = e1000_shift_in_eec_bits(hw, 16); + e1000_standby_nvm(hw); + } + +release: + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_nvm_eerd - Reads EEPROM using EERD register + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read + * @data: word read from the EEPROM + * + * Reads a 16 bit word from the EEPROM using the EERD register. + */ +s32 +e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eerd = 0; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_read_nvm_eerd"); + + /* + * A check for invalid values: offset too large, too many words, and + * not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + for (i = 0; i < words; i++) { + eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + + E1000_NVM_RW_REG_START; + + E1000_WRITE_REG(hw, E1000_EERD, eerd); + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); + if (ret_val) + break; + + data[i] = (E1000_READ_REG(hw, E1000_EERD) >> + E1000_NVM_RW_REG_DATA); + } + +out: + return (ret_val); +} + +/* + * e1000_write_nvm_spi - Write to EEPROM using SPI + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write + * @data: 16 bit word(s) to be written to the EEPROM + * + * Writes data to EEPROM at offset using SPI interface. + * + * If e1000_update_nvm_checksum is not called after this function , the + * EEPROM will most likley contain an invalid checksum. + */ +s32 +e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 * data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + s32 ret_val; + u16 widx = 0; + + DEBUGFUNC("e1000_write_nvm_spi"); + + /* + * A check for invalid values: offset too large, too many words, and + * not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + msec_delay(10); + + while (widx < words) { + u8 write_opcode = NVM_WRITE_OPCODE_SPI; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) + goto release; + + e1000_standby_nvm(hw); + + /* Send the WRITE ENABLE command (8 bit opcode) */ + e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, + nvm->opcode_bits); + + e1000_standby_nvm(hw); + + /* + * Some SPI eeproms use the 8th address bit embedded in the + * opcode + */ + if ((nvm->address_bits == 8) && (offset >= 128)) + write_opcode |= NVM_A8_OPCODE_SPI; + + /* Send the Write command (8-bit opcode + addr) */ + e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); + e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), + nvm->address_bits); + + /* Loop to allow for up to whole page write of eeprom */ + while (widx < words) { + u16 word_out = data[widx]; + + word_out = (word_out >> 8) | (word_out << 8); + e1000_shift_out_eec_bits(hw, word_out, 16); + widx++; + + if ((((offset + widx) * 2) % nvm->page_size) == 0) { + e1000_standby_nvm(hw); + break; + } + } + } + + msec_delay(10); +release: + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_nvm_microwire - Writes EEPROM using microwire + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write + * @data: 16 bit word(s) to be written to the EEPROM + * + * Writes data to EEPROM at offset using microwire interface. + * + * If e1000_update_nvm_checksum is not called after this function , the + * EEPROM will most likley contain an invalid checksum. + */ +s32 +e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) +{ + struct e1000_nvm_info *nvm = &hw->nvm; + s32 ret_val; + u32 eecd; + u16 words_written = 0; + u16 widx = 0; + + DEBUGFUNC("e1000_write_nvm_microwire"); + + /* + * A check for invalid values: offset too large, too many words, and + * not enough words. + */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + DEBUGOUT("nvm parameter(s) out of bounds\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + + ret_val = e1000_acquire_nvm(hw); + if (ret_val) + goto out; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) + goto release; + + e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, + (u16)(nvm->opcode_bits + 2)); + + e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); + + e1000_standby_nvm(hw); + + while (words_written < words) { + e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, + nvm->opcode_bits); + + e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), + nvm->address_bits); + + e1000_shift_out_eec_bits(hw, data[words_written], 16); + + e1000_standby_nvm(hw); + + for (widx = 0; widx < 200; widx++) { + eecd = E1000_READ_REG(hw, E1000_EECD); + if (eecd & E1000_EECD_DO) + break; + usec_delay(50); + } + + if (widx == 200) { + DEBUGOUT("NVM Write did not complete\n"); + ret_val = -E1000_ERR_NVM; + goto release; + } + + e1000_standby_nvm(hw); + + words_written++; + } + + e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, + (u16)(nvm->opcode_bits + 2)); + + e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); + +release: + e1000_release_nvm(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_part_num_generic - Read device part number + * @hw: pointer to the HW structure + * @part_num: pointer to device part number + * + * Reads the product board assembly (PBA) number from the EEPROM and stores + * the value in part_num. + */ +s32 +e1000_read_part_num_generic(struct e1000_hw *hw, u32 *part_num) +{ + s32 ret_val; + u16 nvm_data; + + DEBUGFUNC("e1000_read_part_num_generic"); + + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + *part_num = (u32)(nvm_data << 16); + + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + *part_num |= nvm_data; + +out: + return (ret_val); +} + +/* + * e1000_read_mac_addr_generic - Read device MAC address + * @hw: pointer to the HW structure + * + * Reads the device MAC address from the EEPROM and stores the value. + * Since devices with two ports use the same EEPROM, we increment the + * last bit in the MAC address for the second port. + */ +s32 +e1000_read_mac_addr_generic(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 offset, nvm_data, i; + + DEBUGFUNC("e1000_read_mac_addr"); + + for (i = 0; i < ETH_ADDR_LEN; i += 2) { + offset = i >> 1; + ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); + hw->mac.perm_addr[i + 1] = (u8)(nvm_data >> 8); + } + + /* Flip last bit of mac address if we're on second port */ + if (hw->bus.func == E1000_FUNC_1) + hw->mac.perm_addr[5] ^= 1; + + for (i = 0; i < ETH_ADDR_LEN; i++) + hw->mac.addr[i] = hw->mac.perm_addr[i]; + +out: + return (ret_val); +} + +/* + * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM + * and then verifies that the sum of the EEPROM is equal to 0xBABA. + */ +s32 +e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 checksum = 0; + u16 i, nvm_data; + + DEBUGFUNC("e1000_validate_nvm_checksum_generic"); + + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + checksum += nvm_data; + } + + if (checksum != (u16)NVM_SUM) { + DEBUGOUT("NVM Checksum Invalid\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_update_nvm_checksum_generic - Update EEPROM checksum + * @hw: pointer to the HW structure + * + * Updates the EEPROM checksum by reading/adding each word of the EEPROM + * up to the checksum. Then calculates the EEPROM checksum and writes the + * value to the EEPROM. + */ +s32 +e1000_update_nvm_checksum_generic(struct e1000_hw *hw) +{ + s32 ret_val; + u16 checksum = 0; + u16 i, nvm_data; + + DEBUGFUNC("e1000_update_nvm_checksum"); + + for (i = 0; i < NVM_CHECKSUM_REG; i++) { + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error while updating checksum.\n"); + goto out; + } + checksum += nvm_data; + } + checksum = (u16)NVM_SUM - checksum; + ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); + if (ret_val) { + DEBUGOUT("NVM Write Error while updating checksum.\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_reload_nvm_generic - Reloads EEPROM + * @hw: pointer to the HW structure + * + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the + * extended control register. + */ +void +e1000_reload_nvm_generic(struct e1000_hw *hw) +{ + u32 ctrl_ext; + + DEBUGFUNC("e1000_reload_nvm_generic"); + + usec_delay(10); + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); +} + +/* Function pointers local to this file and not intended for public use */ + +/* + * e1000_acquire_nvm - Acquire exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * For those silicon families which have implemented a NVM acquire function, + * run the defined function else return success. + */ +s32 +e1000_acquire_nvm(struct e1000_hw *hw) +{ + if (hw->func.acquire_nvm) + return (hw->func.acquire_nvm(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_release_nvm - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * For those silicon families which have implemented a NVM release function, + * run the defined fucntion else return success. + */ +void +e1000_release_nvm(struct e1000_hw *hw) +{ + if (hw->func.release_nvm) + hw->func.release_nvm(hw); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_nvm.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,69 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_NVM_H_ +#define _E1000_NVM_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +s32 e1000_acquire_nvm_generic(struct e1000_hw *hw); + +s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); +s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); +s32 e1000_read_part_num_generic(struct e1000_hw *hw, u32 *part_num); +s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data); +s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw); +s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw); +void e1000_stop_nvm(struct e1000_hw *hw); +void e1000_release_nvm_generic(struct e1000_hw *hw); +void e1000_reload_nvm_generic(struct e1000_hw *hw); + +/* Function pointers */ +s32 e1000_acquire_nvm(struct e1000_hw *hw); +void e1000_release_nvm(struct e1000_hw *hw); + +#define E1000_STM_OPCODE 0xDB00 + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_NVM_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_osdep.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,153 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#include "e1000_osdep.h" +#include "e1000_api.h" + + +s32 +e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size) +{ + hw->dev_spec = kmem_zalloc(size, KM_SLEEP); + + return (E1000_SUCCESS); +} + +void +e1000_free_dev_spec_struct(struct e1000_hw *hw) +{ + if (hw->dev_spec == NULL) + return; + + kmem_free(hw->dev_spec, hw->dev_spec_size); + hw->dev_spec = NULL; +} + +void +e1000_pci_set_mwi(struct e1000_hw *hw) +{ + uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE; + + e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); +} + +void +e1000_pci_clear_mwi(struct e1000_hw *hw) +{ + uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; + + e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); +} + +void +e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) +{ + pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); +} + +void +e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) +{ + *value = + pci_config_get16(OS_DEP(hw)->cfg_handle, reg); +} + +/* + * phy_spd_state - set smart-power-down (SPD) state + * + * This only acts on the 82541/47 family and the 82571/72 family. + * For any others, return without doing anything. + */ +void +phy_spd_state(struct e1000_hw *hw, boolean_t enable) +{ + int32_t offset; /* offset to register */ + uint16_t spd_bit; /* bit to be set */ + uint16_t reg; /* register contents */ + + switch (hw->mac.type) { + case e1000_82541: + case e1000_82547: + case e1000_82541_rev_2: + case e1000_82547_rev_2: + offset = IGP01E1000_GMII_FIFO; + spd_bit = IGP01E1000_GMII_SPD; + break; + case e1000_82571: + case e1000_82572: + offset = IGP02E1000_PHY_POWER_MGMT; + spd_bit = IGP02E1000_PM_SPD; + break; + default: + return; /* no action */ + } + + e1000_read_phy_reg(hw, offset, ®); + + if (enable) + reg |= spd_bit; /* enable: set the spd bit */ + else + reg &= ~spd_bit; /* disable: clear the spd bit */ + + e1000_write_phy_reg(hw, offset, reg); +} + +/* + * The real intent of this routine is to return the value from pci-e + * config space at offset reg into the capability space. + * ICH devices are "PCI Express"-ish. They have a configuration space, + * but do not contain PCI Express Capability registers, so this returns + * the equivalent of "not supported" + */ +int32_t +e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) +{ + *value = pci_config_get16(OS_DEP(hw)->cfg_handle, + PCI_EX_CONF_CAP + reg); + + return (0); +} + +/* + * Enables PCI-Express master access. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - none. + */ +void +e1000_enable_pciex_master(struct e1000_hw *hw) +{ + uint32_t ctrl; + + if (hw->bus.type != e1000_bus_type_pci_express) + return; + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); +}
--- a/usr/src/uts/common/io/e1000g/e1000_osdep.h Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000_osdep.h Tue Aug 21 00:30:10 2007 -0700 @@ -46,79 +46,118 @@ #include <sys/ddi.h> #include <sys/sunddi.h> #include <sys/pci.h> +#include <sys/atomic.h> +#include "e1000g_debug.h" /* * === BEGIN CONTENT FORMERLY IN FXHW.H === */ -#define DelayInMicroseconds(x) drv_usecwait(x) -#define DelayInMilliseconds(x) drv_usecwait(x * 1000) #define usec_delay(x) drv_usecwait(x) #define msec_delay(x) drv_usecwait(x * 1000) -#ifdef e1000g_DEBUG -#define DEBUGOUT(S) cmn_err(CE_CONT, S) -#define DEBUGOUT1(S, A) cmn_err(CE_CONT, S, A) -#define DEBUGOUT2(S, A, B) cmn_err(CE_CONT, S, A, B) -#define DEBUGOUT3(S, A, B, C) cmn_err(CE_CONT, S, A, B, C) -#define DEBUGOUT7(S, A, B, C, D, E, F, G) \ - cmn_err(CE_CONT, S, A, B, C, D, E, F, G) +#ifdef E1000G_DEBUG +#define DEBUGOUT(S) \ + E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) +#define DEBUGOUT1(S, A) \ + E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) +#define DEBUGOUT2(S, A, B) \ + E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) +#define DEBUGOUT3(S, A, B, C) \ + E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) +#define DEBUGFUNC(F) \ + E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) #else #define DEBUGOUT(S) #define DEBUGOUT1(S, A) #define DEBUGOUT2(S, A, B) #define DEBUGOUT3(S, A, B, C) -#define DEBUGOUT7(S, A, B, C, D, E, F, G) +#define DEBUGFUNC(F) #endif -#define DEBUGFUNC(F) DEBUGOUT(F) +#define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) -#define IN -#define OUT #define FALSE 0 #define TRUE 1 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ #define PCI_COMMAND_REGISTER 0x04 +#define PCI_EX_CONF_CAP 0xE0 +#define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ -#define E1000_WRITE_FLUSH(a) /* NOOP */ +#define RECEIVE_BUFFER_ALIGN_SIZE 256 +#define E1000_MDALIGN 4096 +#define E1000_ERT_2048 0x100 + +/* PHY Extended Status Register */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ + +#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) + +#ifdef NO_82542_SUPPORT +#define E1000_WRITE_REG(hw, reg, value) \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg), (value)) -#define E1000_WRITE_REG(a, reg, value) \ +#define E1000_READ_REG(hw, reg) \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg)) + +#define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2)), \ + (value)) + +#define E1000_READ_REG_ARRAY(hw, reg, offset) \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2))) + +#else /* NO_82542_SUPPORT */ + +#define E1000_WRITE_REG(hw, reg, value) \ {\ - if ((a)->mac_type >= e1000_82543) \ - ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_##reg), \ + if ((hw)->mac.type != e1000_82542) \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg), \ value); \ else \ - ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_82542_##reg), \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + \ + e1000_translate_register_82542(reg)), \ value); \ } -#define E1000_READ_REG(a, reg) (\ - ((a)->mac_type >= e1000_82543) ? \ - ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_##reg)) : \ - ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_82542_##reg))) +#define E1000_READ_REG(hw, reg) (\ + ((hw)->mac.type != e1000_82542) ? \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg)) : \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + \ + e1000_translate_register_82542(reg)))) -#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ +#define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ {\ - if ((a)->mac_type >= e1000_82543) \ - ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2)),\ + if ((hw)->mac.type != e1000_82542) \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2)),\ value); \ else \ - ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ + ddi_put32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + \ + e1000_translate_register_82542(reg) + \ ((offset) << 2)), value); \ } -#define E1000_READ_REG_ARRAY(a, reg, offset) (\ - ((a)->mac_type >= e1000_82543) ? \ - ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \ - ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ - (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ +#define E1000_READ_REG_ARRAY(hw, reg, offset) (\ + ((hw)->mac.type != e1000_82542) ? \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2))) : \ + ddi_get32((OS_DEP(hw))->reg_handle, \ + (uint32_t *)((hw)->hw_addr + \ + e1000_translate_register_82542(reg) + \ ((offset) << 2)))) +#endif /* NO_82542_SUPPORT */ #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) NULL @@ -129,36 +168,21 @@ #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) NULL -#define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ -#define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) - -#define E1000_READ_ICH_FLASH_REG(hw, reg) \ +#define E1000_READ_FLASH_REG(hw, reg) \ ddi_get32((OS_DEP(hw))->ich_flash_handle, \ - (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg))) + (uint32_t *)((hw)->flash_address + (reg))) -#define E1000_READ_ICH_FLASH_REG16(hw, reg) \ +#define E1000_READ_FLASH_REG16(hw, reg) \ ddi_get16((OS_DEP(hw))->ich_flash_handle, \ - (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg))) - -#define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \ - ddi_put32((OS_DEP(hw))->ich_flash_handle, \ - (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) + (uint16_t *)((hw)->flash_address + (reg))) -#define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \ - ddi_put16((OS_DEP(hw))->ich_flash_handle, \ - (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) +#define E1000_WRITE_FLASH_REG(hw, reg, value) \ + ddi_put32((OS_DEP(hw))->ich_flash_handle, \ + (uint32_t *)((hw)->flash_address + (reg)), (value)) -/* - * The size of the receive buffers we allocate, - */ -#define E1000_SIZE_OF_RECEIVE_BUFFERS (2048) - -/* - * Use this define refer to the size of a recieve buffer plus its - * align size - */ -#define E1000_SIZE_OF_UNALIGNED_RECEIVE_BUFFERS \ - E1000_SIZE_OF_RECEIVE_BUFFERS + RECEIVE_BUFFER_ALIGN_SIZE +#define E1000_WRITE_FLASH_REG16(hw, reg, value) \ + ddi_put16((OS_DEP(hw))->ich_flash_handle, \ + (uint16_t *)((hw)->flash_address + (reg)), (value)) /* * === END CONTENT FORMERLY IN FXHW.H === @@ -166,6 +190,15 @@ #define msec_delay_irq msec_delay +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + typedef uint8_t UCHAR; /* 8-bit unsigned */ typedef UCHAR UINT8; /* 8-bit unsigned */ typedef uint16_t USHORT; /* 16-bit unsigned */ @@ -186,26 +219,18 @@ *PFX_64_BIT_PHYSICAL_ADDRESS; struct e1000g_osdep { - ddi_acc_handle_t E1000_handle; - ddi_acc_handle_t handle; - /* flash access */ + ddi_acc_handle_t reg_handle; + ddi_acc_handle_t cfg_handle; ddi_acc_handle_t ich_flash_handle; - caddr_t ich_flash_base; - off_t ich_flash_size; + struct e1000g *adapter; }; #ifdef __sparc /* on SPARC, use only memory-mapped routines */ - -#define E1000_READ_REG_IO E1000_READ_REG #define E1000_WRITE_REG_IO E1000_WRITE_REG - #else /* on x86, use port io routines */ - -#define E1000_READ_REG_IO(a, reg) \ - e1000_read_reg_io((a), E1000_##reg) -#define E1000_WRITE_REG_IO(a, reg, val) \ - e1000_write_reg_io((a), E1000_##reg, val) - +#define E1000_WRITE_REG_IO(a, reg, val) { \ + outl(((a)->io_base), reg); \ + outl(((a)->io_base + 4), val); } #endif /* __sparc */ #ifdef __cplusplus
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_phy.c Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,2384 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#include "e1000_api.h" +#include "e1000_phy.h" + +static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); +static void e1000_release_phy(struct e1000_hw *hw); +static s32 e1000_acquire_phy(struct e1000_hw *hw); +static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); + +/* Cable length tables */ +static const u16 e1000_m88_cable_length_table[] = + {0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED}; + +#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ + (sizeof (e1000_m88_cable_length_table) / \ + sizeof (e1000_m88_cable_length_table[0])) + +static const u16 e1000_igp_2_cable_length_table[] = + {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, + 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, + 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, + 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, + 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, + 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, + 104, 109, 114, 118, 121, 124}; + +#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ + (sizeof (e1000_igp_2_cable_length_table) / \ + sizeof (e1000_igp_2_cable_length_table[0])) + +/* + * e1000_check_reset_block_generic - Check if PHY reset is blocked + * @hw: pointer to the HW structure + * + * Read the PHY management control register and check whether a PHY reset + * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise + * return E1000_BLK_PHY_RESET (12). + */ +s32 +e1000_check_reset_block_generic(struct e1000_hw *hw) +{ + u32 manc; + + DEBUGFUNC("e1000_check_reset_block"); + + manc = E1000_READ_REG(hw, E1000_MANC); + + return ((manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? + E1000_BLK_PHY_RESET : E1000_SUCCESS); +} + +/* + * e1000_get_phy_id - Retrieve the PHY ID and revision + * @hw: pointer to the HW structure + * + * Reads the PHY registers and stores the PHY ID and possibly the PHY + * revision in the hardware structure. + */ +s32 +e1000_get_phy_id(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + u16 phy_id; + + DEBUGFUNC("e1000_get_phy_id"); + + ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id); + if (ret_val) + goto out; + + phy->id = (u32)(phy_id << 16); + usec_delay(20); + ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id); + if (ret_val) + goto out; + + phy->id |= (u32)(phy_id & PHY_REVISION_MASK); + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); + +out: + return (ret_val); +} + +/* + * e1000_phy_reset_dsp_generic - Reset PHY DSP + * @hw: pointer to the HW structure + * + * Reset the digital signal processor. + */ +s32 +e1000_phy_reset_dsp_generic(struct e1000_hw *hw) +{ + s32 ret_val; + + DEBUGFUNC("e1000_phy_reset_dsp_generic"); + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); + +out: + return (ret_val); +} + +/* + * e1000_read_phy_reg_mdic - Read MDI control register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Reads the MDI control regsiter in the PHY at offset and stores the + * information read to data. + */ +static s32 +e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) +{ + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_read_phy_reg_mdic"); + + if (offset > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", offset); + ret_val = -E1000_ERR_PARAM; + goto out; + } + + /* + * Set up Op-code, Phy Address, and register offset in the MDI Control + * register. The MAC will take care of interfacing with the PHY to + * retrieve the desired data. + */ + mdic = ((offset << E1000_MDIC_REG_SHIFT) | + (phy->addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + + E1000_WRITE_REG(hw, E1000_MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + usec_delay(50); + mdic = E1000_READ_REG(hw, E1000_MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Read did not complete\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } + if (mdic & E1000_MDIC_ERROR) { + DEBUGOUT("MDI Error\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } + *data = (u16)mdic; + +out: + return (ret_val); +} + +/* + * e1000_write_phy_reg_mdic - Write MDI control register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write to register at offset + * + * Writes data to MDI control register in the PHY at offset. + */ +static s32 +e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) +{ + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; + s32 ret_val = E1000_SUCCESS; + + DEBUGFUNC("e1000_write_phy_reg_mdic"); + + if (offset > MAX_PHY_REG_ADDRESS) { + DEBUGOUT1("PHY Address %d is out of range\n", offset); + ret_val = -E1000_ERR_PARAM; + goto out; + } + + /* + * Set up Op-code, Phy Address, and register offset in the MDI Control + * register. The MAC will take care of interfacing with the PHY to + * retrieve the desired data. + */ + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | + (phy->addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + + E1000_WRITE_REG(hw, E1000_MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { + usec_delay(5); + mdic = E1000_READ_REG(hw, E1000_MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Write did not complete\n"); + ret_val = -E1000_ERR_PHY; + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_read_phy_reg_m88 - Read m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Acquires semaphore, if necessary, then reads the PHY register at offset + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + */ +s32 +e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_read_phy_reg_m88"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_phy_reg_m88 - Write m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset + * + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + */ +s32 +e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_write_phy_reg_m88"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + ret_val = e1000_write_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_phy_reg_igp - Read igp PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Acquires semaphore, if necessary, then reads the PHY register at offset + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + */ +s32 +e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_read_phy_reg_igp"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + ret_val = e1000_write_phy_reg_mdic(hw, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { + e1000_release_phy(hw); + goto out; + } + } + ret_val = e1000_read_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_phy_reg_igp - Write igp PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset + * + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + */ +s32 +e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) +{ + s32 ret_val; + + DEBUGFUNC("e1000_write_phy_reg_igp"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + ret_val = e1000_write_phy_reg_mdic(hw, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { + e1000_release_phy(hw); + goto out; + } + } + + ret_val = e1000_write_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_kmrn_reg_generic - Read kumeran register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Acquires semaphore, if necessary. Then reads the PHY register at offset + * using the kumeran interface. The information retrieved is stored in data. + * Release any acquired semaphores before exiting. + */ +s32 +e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) +{ + u32 kmrnctrlsta; + s32 ret_val; + + DEBUGFUNC("e1000_read_kmrn_reg_generic"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); + + usec_delay(2); + + kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); + *data = (u16)kmrnctrlsta; + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_write_kmrn_reg_generic - Write kumeran register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset + * + * Acquires semaphore, if necessary. Then write the data to PHY register + * at the offset using the kumeran interface. Release any acquired semaphores + * before exiting. + */ +s32 +e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) +{ + u32 kmrnctrlsta; + s32 ret_val; + + DEBUGFUNC("e1000_write_kmrn_reg_generic"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & + E1000_KMRNCTRLSTA_OFFSET) | data; + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); + + usec_delay(2); + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock + * and downshift values are set also. + */ +s32 +e1000_copper_link_setup_m88(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + + DEBUGFUNC("e1000_copper_link_setup_m88"); + + if (phy->reset_disable) { + ret_val = E1000_SUCCESS; + goto out; + } + + /* Enable CRS on TX. This must be set for half-duplex operation. */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + /* For newer PHYs this bit is downshift enable */ + if (phy->type == e1000_phy_m88) + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + + /* + * Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + + switch (phy->mdix) { + case 1: + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; + break; + case 2: + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; + break; + case 3: + phy_data |= M88E1000_PSCR_AUTO_X_1000T; + break; + case 0: + default: + phy_data |= M88E1000_PSCR_AUTO_X_MODE; + break; + } + + /* + * Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; + if (phy->disable_polarity_correction == 1) + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; + + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + + if (phy->revision < E1000_REVISION_4) { + /* + * Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ + ret_val = e1000_read_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, + &phy_data); + if (ret_val) + goto out; + + phy_data |= M88E1000_EPSCR_TX_CLK_25; + + if ((phy->revision == E1000_REVISION_2) && + (phy->id == M88E1111_I_PHY_ID)) { + /* 82573L PHY - set the downshift counter to 5x. */ + phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; + } else { + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + } + ret_val = e1000_write_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, + phy_data); + if (ret_val) + goto out; + } + + /* Commit the changes. */ + ret_val = e1000_phy_commit(hw); + if (ret_val) { + DEBUGOUT("Error committing the PHY changes\n"); + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_copper_link_setup_igp - Setup igp PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for + * igp PHY's. + */ +s32 +e1000_copper_link_setup_igp(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_copper_link_setup_igp"); + + if (phy->reset_disable) { + ret_val = E1000_SUCCESS; + goto out; + } + + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) { + DEBUGOUT("Error resetting the PHY.\n"); + goto out; + } + + /* Wait 15ms for MAC to configure PHY from NVM settings. */ + msec_delay(15); + + /* + * The NVM settings will configure LPLU in D3 for non-IGP1 PHYs. + */ + if (phy->type == e1000_phy_igp) { + /* disable lplu d3 during driver init */ + ret_val = e1000_set_d3_lplu_state(hw, FALSE); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D3\n"); + goto out; + } + } + + /* disable lplu d0 during driver init */ + ret_val = e1000_set_d0_lplu_state(hw, FALSE); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D0\n"); + goto out; + } + /* Configure mdi-mdix settings */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCR_AUTO_MDIX; + + switch (phy->mdix) { + case 1: + data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 2: + data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 0: + default: + data |= IGP01E1000_PSCR_AUTO_MDIX; + break; + } + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); + if (ret_val) + goto out; + + /* set auto-master slave resolution settings */ + if (hw->mac.autoneg) { + /* + * when autonegotiation advertisement is only 1000Mbps then we + * should disable SmartSpeed and enable Auto MasterSlave + * resolution as hardware default. + */ + if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { + /* Disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + + /* Set auto Master/Slave resolution process */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); + if (ret_val) + goto out; + + data &= ~CR_1000T_MS_ENABLE; + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); + if (ret_val) + goto out; + } + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); + if (ret_val) + goto out; + + /* load defaults for future use */ + phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? + ((data & CR_1000T_MS_VALUE) ? + e1000_ms_force_master : + e1000_ms_force_slave) : + e1000_ms_auto; + + switch (phy->ms_type) { + case e1000_ms_force_master: + data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); + break; + case e1000_ms_force_slave: + data |= CR_1000T_MS_ENABLE; + data &= ~(CR_1000T_MS_VALUE); + break; + case e1000_ms_auto: + data &= ~CR_1000T_MS_ENABLE; + default: + break; + } + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); + if (ret_val) + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link + * @hw: pointer to the HW structure + * + * Performs initial bounds checking on autoneg advertisement parameter, then + * configure to advertise the full capability. Setup the PHY to autoneg + * and restart the negotiation process between the link partner. If + * wait_for_link, then wait for autoneg to complete before exiting. + */ +s32 +e1000_copper_link_autoneg(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_ctrl; + + DEBUGFUNC("e1000_copper_link_autoneg"); + + /* + * Perform some bounds checking on the autoneg advertisement + * parameter. + */ + phy->autoneg_advertised &= phy->autoneg_mask; + + /* + * If autoneg_advertised is zero, we assume it was not defaulted by + * the calling code so we set to advertise full capability. + */ + if (phy->autoneg_advertised == 0) + phy->autoneg_advertised = phy->autoneg_mask; + + DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error Setting up Auto-Negotiation\n"); + goto out; + } + DEBUGOUT("Restarting Auto-Neg\n"); + + /* + * Restart auto-negotiation by setting the Auto Neg Enable bit and the + * Auto Neg Restart bit in the PHY control register. + */ + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) + goto out; + + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) + goto out; + + /* + * Does the user want to wait for Auto-Neg to complete here, or check + * at a later time (for example, callback routine). + */ + if (phy->wait_for_link) { + ret_val = e1000_wait_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error while waiting for " + "autoneg to complete\n"); + goto out; + } + } + + hw->mac.get_link_status = TRUE; + +out: + return (ret_val); +} + +/* + * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation + * @hw: pointer to the HW structure + * + * Reads the MII auto-neg advertisement register and/or the 1000T control + * register and if the PHY is already setup for auto-negotiation, then + * return successful. Otherwise, setup advertisement and flow control to + * the appropriate values for the wanted auto-negotiation. + */ +s32 +e1000_phy_setup_autoneg(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 mii_autoneg_adv_reg; + u16 mii_1000t_ctrl_reg = 0; + + DEBUGFUNC("e1000_phy_setup_autoneg"); + + phy->autoneg_advertised &= phy->autoneg_mask; + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); + if (ret_val) + goto out; + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { + /* Read the MII 1000Base-T Control Register (Address 9). */ + ret_val = e1000_read_phy_reg(hw, + PHY_1000T_CTRL, + &mii_1000t_ctrl_reg); + if (ret_val) + goto out; + } + + /* + * Need to parse both autoneg_advertised and fc and set up the + * appropriate PHY registers. First we will parse for + * autoneg_advertised software override. Since we can advertise a + * plethora of combinations, we need to check each bit individually. + */ + + /* + * First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | + NWAY_AR_100TX_HD_CAPS | + NWAY_AR_10T_FD_CAPS | + NWAY_AR_10T_HD_CAPS); + mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); + + DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_10_HALF) { + DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_10_FULL) { + DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_100_HALF) { + DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_100_FULL) { + DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { + DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); + } + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { + DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + } + + /* + * Check for a software override of the flow control settings, and + * setup the PHY advertisement registers accordingly. If + * auto-negotiation is enabled, then software will have to set the + * "PAUSE" bits to the correct value in the Auto-Negotiation + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- + * negotiation. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ + switch (hw->mac.fc) { + case e1000_fc_none: + /* + * Flow control (RX & TX) is completely disabled by a software + * over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_rx_pause: + /* + * RX Flow control is enabled, and TX Flow control is + * disabled, by a software over-ride. + * + * Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we support + * both symmetric and asymmetric RX PAUSE. Later (in + * e1000_config_fc_after_link_up) we will disable the hw's + * ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_tx_pause: + /* + * TX Flow control is enabled, and RX Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; + break; + case e1000_fc_full: + /* + * Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); + if (ret_val) + goto out; + + DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { + ret_val = e1000_write_phy_reg(hw, + PHY_1000T_CTRL, + mii_1000t_ctrl_reg); + if (ret_val) + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_setup_copper_link_generic - Configure copper link settings + * @hw: pointer to the HW structure + * + * Calls the appropriate function to configure the link for auto-neg or forced + * speed and duplex. Then we check for link, once link is established calls + * to configure collision distance and flow control are called. If link is + * not established, we return -E1000_ERR_PHY (-2). + */ +s32 +e1000_setup_copper_link_generic(struct e1000_hw *hw) +{ + s32 ret_val; + boolean_t link; + + DEBUGFUNC("e1000_setup_copper_link_generic"); + + if (hw->mac.autoneg) { + /* + * Setup autoneg and flow control advertisement and perform + * autonegotiation. + */ + ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) + goto out; + } else { + /* + * PHY will be set to 10H, 10F, 100H or 100F depending on user + * settings. + */ + DEBUGOUT("Forcing Speed and Duplex\n"); + ret_val = e1000_phy_force_speed_duplex(hw); + if (ret_val) { + DEBUGOUT("Error Forcing Speed and Duplex\n"); + goto out; + } + } + + /* + * Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + ret_val = e1000_phy_has_link_generic(hw, + COPPER_LINK_UP_LIMIT, + 10, + &link); + if (ret_val) + goto out; + + if (link) { + DEBUGOUT("Valid link established!!!\n"); + e1000_config_collision_dist_generic(hw); + ret_val = e1000_config_fc_after_link_up_generic(hw); + } else { + DEBUGOUT("Unable to establish link!!!\n"); + } + +out: + return (ret_val); +} + +/* + * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the + * auto-crossover to force MDI manually. Waits for link and returns + * successful if link up is successful, else -E1000_ERR_PHY (-2). + */ +s32 +e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + boolean_t link; + + DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); + + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); + if (ret_val) + goto out; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); + if (ret_val) + goto out; + + /* + * Clear Auto-Crossover to force MDI manually. IGP requires MDI + * forced whenever speed and duplex are forced. + */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) + goto out; + + DEBUGOUT1("IGP PSCR: %X\n", phy_data); + + usec_delay(1); + + if (phy->wait_for_link) { + DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); + + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + + if (!link) { + DEBUGOUT("Link taking longer than expected.\n"); + } + + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + } + +out: + return (ret_val); +} + +/* + * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the + * auto-crossover to force MDI manually. Resets the PHY to commit the + * changes. If time expires while waiting for link up, we reset the DSP. + * After reset, TX_CLK and CRS on TX must be set. Return successful upon + * successful completion, else return corresponding error code. + */ +s32 +e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + boolean_t link; + + DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); + + /* + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI + * forced whenever speed and duplex are forced. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + + DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); + + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); + if (ret_val) + goto out; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + + /* Reset the phy to commit changes. */ + phy_data |= MII_CR_RESET; + + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); + if (ret_val) + goto out; + + usec_delay(1); + + if (phy->wait_for_link) { + DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); + + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + + if (!link) { + /* + * We didn't get link. Reset the DSP and cross our + * fingers. + */ + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_PAGE_SELECT, + 0x001d); + if (ret_val) + goto out; + ret_val = e1000_phy_reset_dsp_generic(hw); + if (ret_val) + goto out; + } + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); + if (ret_val) + goto out; + } + ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + /* + * Resetting the phy means we need to re-force TX_CLK in the Extended + * PHY Specific Control Register to 25MHz clock from the reset value + * of 2.5MHz. + */ + phy_data |= M88E1000_EPSCR_TX_CLK_25; + ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + goto out; + + /* + * In addition, we must re-enable CRS on Tx for both half and full + * duplex. + */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + +out: + return (ret_val); +} + +/* + * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex + * @hw: pointer to the HW structure + * @phy_ctrl: pointer to current value of PHY_CONTROL + * + * Forces speed and duplex on the PHY by doing the following: disable flow + * control, force speed/duplex on the MAC, disable auto speed detection, + * disable auto-negotiation, configure duplex, configure speed, configure + * the collision distance, write configuration to CTRL register. The + * caller must write to the PHY_CONTROL register for these settings to + * take affect. + */ +void +e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) +{ + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; + + DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); + + /* Turn off flow control when forcing speed/duplex */ + mac->fc = e1000_fc_none; + + /* Force speed/duplex on the mac */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~E1000_CTRL_SPD_SEL; + + /* Disable Auto Speed Detection */ + ctrl &= ~E1000_CTRL_ASDE; + + /* Disable autoneg on the phy */ + *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; + + /* Forcing Full or Half Duplex? */ + if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { + ctrl &= ~E1000_CTRL_FD; + *phy_ctrl &= ~MII_CR_FULL_DUPLEX; + DEBUGOUT("Half Duplex\n"); + } else { + ctrl |= E1000_CTRL_FD; + *phy_ctrl |= MII_CR_FULL_DUPLEX; + DEBUGOUT("Full Duplex\n"); + } + + /* Forcing 10mb or 100mb? */ + if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { + ctrl |= E1000_CTRL_SPD_100; + *phy_ctrl |= MII_CR_SPEED_100; + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); + DEBUGOUT("Forcing 100mb\n"); + } else { + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); + *phy_ctrl |= MII_CR_SPEED_10; + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); + DEBUGOUT("Forcing 10mb\n"); + } + + e1000_config_collision_dist_generic(hw); + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); +} + +/* + * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * Success returns 0, Failure returns 1 + * + * The low power link up (lplu) state is set to the power management level D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + */ +s32 +e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_set_d3_lplu_state_generic"); + + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) + goto out; + + if (!active) { + data &= ~IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, + data); + if (ret_val) + goto out; + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) + goto out; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, + data); + if (ret_val) + goto out; + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) + goto out; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + } + +out: + return (ret_val); +} + +/* + * e1000_check_downshift_generic - Checks whether a downshift in speed occured + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns 1 + * + * A downshift is detected by querying the PHY link health. + */ +s32 +e1000_check_downshift_generic(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, offset, mask; + + DEBUGFUNC("e1000_check_downshift_generic"); + + switch (phy->type) { + case e1000_phy_m88: + case e1000_phy_gg82563: + case e1000_phy_bm: + offset = M88E1000_PHY_SPEC_STATUS; + mask = M88E1000_PSSR_DOWNSHIFT; + break; + case e1000_phy_igp_2: + case e1000_phy_igp: + case e1000_phy_igp_3: + offset = IGP01E1000_PHY_LINK_HEALTH; + mask = IGP01E1000_PLHR_SS_DOWNGRADE; + break; + default: + /* speed downshift not supported */ + phy->speed_downgraded = FALSE; + ret_val = E1000_SUCCESS; + goto out; + } + + ret_val = e1000_read_phy_reg(hw, offset, &phy_data); + + if (!ret_val) + phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; + +out: + return (ret_val); +} + +/* + * e1000_check_polarity_m88 - Checks the polarity. + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns -E1000_ERR_PHY (-2) + * + * Polarity is determined based on the PHY specific status register. + */ +s32 +e1000_check_polarity_m88(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + + DEBUGFUNC("e1000_check_polarity_m88"); + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); + + if (!ret_val) + phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) + ? e1000_rev_polarity_reversed + : e1000_rev_polarity_normal; + + return (ret_val); +} + +/* + * e1000_check_polarity_igp - Checks the polarity. + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns -E1000_ERR_PHY (-2) + * + * Polarity is determined based on the PHY port status register, and the + * current speed (since there is no polarity at 100Mbps). + */ +s32 +e1000_check_polarity_igp(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data, offset, mask; + + DEBUGFUNC("e1000_check_polarity_igp"); + + /* + * Polarity is determined based on the speed of our connection. + */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) + goto out; + + if ((data & IGP01E1000_PSSR_SPEED_MASK) == + IGP01E1000_PSSR_SPEED_1000MBPS) { + offset = IGP01E1000_PHY_PCS_INIT_REG; + mask = IGP01E1000_PHY_POLARITY_MASK; + } else { + /* + * This really only applies to 10Mbps since there is no + * polarity for 100Mbps (always 0). + */ + offset = IGP01E1000_PHY_PORT_STATUS; + mask = IGP01E1000_PSSR_POLARITY_REVERSED; + } + + ret_val = e1000_read_phy_reg(hw, offset, &data); + + if (!ret_val) + phy->cable_polarity = (data & mask) + ? e1000_rev_polarity_reversed + : e1000_rev_polarity_normal; + +out: + return (ret_val); +} + +/* + * e1000_wait_autoneg_generic - Wait for auto-neg compeletion + * @hw: pointer to the HW structure + * + * Waits for auto-negotiation to complete or for the auto-negotiation time + * limit to expire, which ever happens first. + */ +s32 +e1000_wait_autoneg_generic(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 i, phy_status; + + DEBUGFUNC("e1000_wait_autoneg_generic"); + + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ + for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + if (phy_status & MII_SR_AUTONEG_COMPLETE) + break; + msec_delay(100); + } + + /* + * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation has + * completed. + */ + return (ret_val); +} + +/* + * e1000_phy_has_link_generic - Polls PHY for link + * @hw: pointer to the HW structure + * @iterations: number of times to poll for link + * @usec_interval: delay between polling attempts + * @success: pointer to whether polling was successful or not + * + * Polls the PHY status register for link, 'iterations' number of times. + */ +s32 +e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, boolean_t *success) +{ + s32 ret_val = E1000_SUCCESS; + u16 i, phy_status; + + DEBUGFUNC("e1000_phy_has_link_generic"); + + for (i = 0; i < iterations; i++) { + /* + * Some PHYs require the PHY_STATUS register to be read twice + * due to the link bit being sticky. No harm doing it across + * the board. + */ + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); + if (ret_val) + break; + if (phy_status & MII_SR_LINK_STATUS) + break; + if (usec_interval >= 1000) + msec_delay_irq(usec_interval / 1000); + else + usec_delay(usec_interval); + } + + *success = (i < iterations) ? TRUE : FALSE; + + return (ret_val); +} + +/* + * e1000_get_cable_length_m88 - Determine cable length for m88 PHY + * @hw: pointer to the HW structure + * + * Reads the PHY specific status register to retrieve the cable length + * information. The cable length is determined by averaging the minimum and + * maximum values to get the "average" cable length. The m88 PHY has four + * possible cable length values, which are: + * Register Value Cable Length + * 0 < 50 meters + * 1 50 - 80 meters + * 2 80 - 110 meters + * 3 110 - 140 meters + * 4 > 140 meters + */ +s32 +e1000_get_cable_length_m88(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, index; + + DEBUGFUNC("e1000_get_cable_length_m88"); + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + goto out; + + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> + M88E1000_PSSR_CABLE_LENGTH_SHIFT; + phy->min_cable_length = e1000_m88_cable_length_table[index]; + phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +out: + return (ret_val); +} + +/* + * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY + * @hw: pointer to the HW structure + * + * The automatic gain control (agc) normalizes the amplitude of the + * received signal, adjusting for the attenuation produced by the + * cable. By reading the AGC registers, which reperesent the + * cobination of course and fine gain value, the value can be put + * into a lookup table to obtain the approximate cable length + * for each channel. + */ +s32 +e1000_get_cable_length_igp_2(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data, i, agc_value = 0; + u16 cur_agc_index, max_agc_index = 0; + u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = + {IGP02E1000_PHY_AGC_A, + IGP02E1000_PHY_AGC_B, + IGP02E1000_PHY_AGC_C, + IGP02E1000_PHY_AGC_D}; + + DEBUGFUNC("e1000_get_cable_length_igp_2"); + + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); + if (ret_val) + goto out; + + /* + * Getting bits 15:9, which represent the combination of + * course and fine gain values. The result is a number that + * can be put into the lookup table to obtain the approximate + * cable length. + */ + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & + IGP02E1000_AGC_LENGTH_MASK; + + /* Array index bound check. */ + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || + (cur_agc_index == 0)) { + ret_val = -E1000_ERR_PHY; + goto out; + } + + /* Remove min & max AGC values from calculation. */ + if (e1000_igp_2_cable_length_table[min_agc_index] > + e1000_igp_2_cable_length_table[cur_agc_index]) + min_agc_index = cur_agc_index; + if (e1000_igp_2_cable_length_table[max_agc_index] < + e1000_igp_2_cable_length_table[cur_agc_index]) + max_agc_index = cur_agc_index; + + agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; + } + + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + + e1000_igp_2_cable_length_table[max_agc_index]); + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); + + /* Calculate cable length with the error range of +/- 10 meters. */ + phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? + (agc_value - IGP02E1000_AGC_RANGE) : 0; + phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +out: + return (ret_val); +} + +/* + * e1000_get_phy_info_m88 - Retrieve PHY information + * @hw: pointer to the HW structure + * + * Valid for only copper links. Read the PHY status register (sticky read) + * to verify that link is up. Read the PHY special control register to + * determine the polarity and 10base-T extended distance. Read the PHY + * special status register to determine MDI/MDIx and current speed. If + * speed is 1000, then determine cable length, local and remote receiver. + */ +s32 +e1000_get_phy_info_m88(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 phy_data; + boolean_t link; + + DEBUGFUNC("e1000_get_phy_info_m88"); + + if (hw->media_type != e1000_media_type_copper) { + DEBUGOUT("Phy info is only valid for copper media\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { + DEBUGOUT("Phy info is only valid if link is up\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + goto out; + + phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) + ? TRUE + : FALSE; + + ret_val = e1000_check_polarity_m88(hw); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) + goto out; + + phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; + + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { + ret_val = e1000_get_cable_length(hw); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) + goto out; + + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) + ? e1000_1000t_rx_status_ok + : e1000_1000t_rx_status_not_ok; + + phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) + ? e1000_1000t_rx_status_ok + : e1000_1000t_rx_status_not_ok; + } else { + /* Set values to "undefined" */ + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; + phy->local_rx = e1000_1000t_rx_status_undefined; + phy->remote_rx = e1000_1000t_rx_status_undefined; + } + +out: + return (ret_val); +} + +/* + * e1000_get_phy_info_igp - Retrieve igp PHY information + * @hw: pointer to the HW structure + * + * Read PHY status to determine if link is up. If link is up, then + * set/determine 10base-T extended distance and polarity correction. Read + * PHY port status to determine MDI/MDIx and speed. Based on the speed, + * determine on the cable length, local and remote receiver. + */ +s32 +e1000_get_phy_info_igp(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + boolean_t link; + + DEBUGFUNC("e1000_get_phy_info_igp"); + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + goto out; + + if (!link) { + DEBUGOUT("Phy info is only valid if link is up\n"); + ret_val = -E1000_ERR_CONFIG; + goto out; + } + + phy->polarity_correction = TRUE; + + ret_val = e1000_check_polarity_igp(hw); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) + goto out; + + phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; + + if ((data & IGP01E1000_PSSR_SPEED_MASK) == + IGP01E1000_PSSR_SPEED_1000MBPS) { + ret_val = e1000_get_cable_length(hw); + if (ret_val) + goto out; + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &data); + if (ret_val) + goto out; + + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) + ? e1000_1000t_rx_status_ok + : e1000_1000t_rx_status_not_ok; + + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) + ? e1000_1000t_rx_status_ok + : e1000_1000t_rx_status_not_ok; + } else { + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; + phy->local_rx = e1000_1000t_rx_status_undefined; + phy->remote_rx = e1000_1000t_rx_status_undefined; + } + +out: + return (ret_val); +} + +/* + * e1000_phy_sw_reset_generic - PHY software reset + * @hw: pointer to the HW structure + * + * Does a software reset of the PHY by reading the PHY control register and + * setting/write the control register reset bit to the PHY. + */ +s32 +e1000_phy_sw_reset_generic(struct e1000_hw *hw) +{ + s32 ret_val; + u16 phy_ctrl; + + DEBUGFUNC("e1000_phy_sw_reset_generic"); + + ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) + goto out; + + phy_ctrl |= MII_CR_RESET; + ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) + goto out; + + usec_delay(1); + +out: + return (ret_val); +} + +/* + * e1000_phy_hw_reset_generic - PHY hardware reset + * @hw: pointer to the HW structure + * + * Verify the reset block is not blocking us from resetting. Acquire + * semaphore (if necessary) and read/set/write the device control reset + * bit in the PHY. Wait the appropriate delay time for the device to + * reset and relase the semaphore (if necessary). + */ +s32 +e1000_phy_hw_reset_generic(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u32 ctrl; + + DEBUGFUNC("e1000_phy_hw_reset_generic"); + + ret_val = e1000_check_reset_block(hw); + if (ret_val) { + ret_val = E1000_SUCCESS; + goto out; + } + + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + + usec_delay(phy->reset_delay_us); + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + usec_delay(150); + + e1000_release_phy(hw); + + ret_val = e1000_get_phy_cfg_done(hw); + +out: + return (ret_val); +} + +/* + * e1000_get_cfg_done_generic - Generic configuration done + * @hw: pointer to the HW structure + * + * Generic function to wait 10 milli-seconds for configuration to complete + * and return success. + */ +s32 +e1000_get_cfg_done_generic(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_get_cfg_done_generic"); + + msec_delay_irq(10); + + return (E1000_SUCCESS); +} + +/* Internal function pointers */ + +/* + * e1000_get_phy_cfg_done - Generic PHY configuration done + * @hw: pointer to the HW structure + * + * Return success if silicon family did not implement a family specific + * get_cfg_done function. + */ +s32 +e1000_get_phy_cfg_done(struct e1000_hw *hw) +{ + if (hw->func.get_cfg_done) + return (hw->func.get_cfg_done(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_release_phy - Generic release PHY + * @hw: pointer to the HW structure + * + * Return if silicon family does not require a semaphore when accessing the + * PHY. + */ +void +e1000_release_phy(struct e1000_hw *hw) +{ + if (hw->func.release_phy) + hw->func.release_phy(hw); +} + +/* + * e1000_acquire_phy - Generic acquire PHY + * @hw: pointer to the HW structure + * + * Return success if silicon family does not require a semaphore when + * accessing the PHY. + */ +s32 +e1000_acquire_phy(struct e1000_hw *hw) +{ + if (hw->func.acquire_phy) + return (hw->func.acquire_phy(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex + * @hw: pointer to the HW structure + * + * When the silicon family has not implemented a forced speed/duplex + * function for the PHY, simply return E1000_SUCCESS. + */ +s32 +e1000_phy_force_speed_duplex(struct e1000_hw *hw) +{ + if (hw->func.force_speed_duplex) + return (hw->func.force_speed_duplex(hw)); + + return (E1000_SUCCESS); +} + +/* + * e1000_phy_init_script_igp3 - Inits the IGP3 PHY + * @hw: pointer to the HW structure + * + * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. + */ +s32 +e1000_phy_init_script_igp3(struct e1000_hw *hw) +{ + DEBUGOUT("Running IGP 3 PHY init script\n"); + + /* PHY init IGP 3 */ + /* Enable rise/fall, 10-mode work in class-A */ + e1000_write_phy_reg(hw, 0x2F5B, 0x9018); + /* Remove all caps from Replica path filter */ + e1000_write_phy_reg(hw, 0x2F52, 0x0000); + /* Bias trimming for ADC, AFE and Driver (Default) */ + e1000_write_phy_reg(hw, 0x2FB1, 0x8B24); + /* Increase Hybrid poly bias */ + e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0); + /* Add 4% to TX amplitude in Giga mode */ + e1000_write_phy_reg(hw, 0x2010, 0x10B0); + /* Disable trimming (TTT) */ + e1000_write_phy_reg(hw, 0x2011, 0x0000); + /* Poly DC correction to 94.6% + 2% for all channels */ + e1000_write_phy_reg(hw, 0x20DD, 0x249A); + /* ABS DC correction to 95.9% */ + e1000_write_phy_reg(hw, 0x20DE, 0x00D3); + /* BG temp curve trim */ + e1000_write_phy_reg(hw, 0x28B4, 0x04CE); + /* Increasing ADC OPAMP stage 1 currents to max */ + e1000_write_phy_reg(hw, 0x2F70, 0x29E4); + /* Force 1000 ( required for enabling PHY regs configuration) */ + e1000_write_phy_reg(hw, 0x0000, 0x0140); + /* Set upd_freq to 6 */ + e1000_write_phy_reg(hw, 0x1F30, 0x1606); + /* Disable NPDFE */ + e1000_write_phy_reg(hw, 0x1F31, 0xB814); + /* Disable adaptive fixed FFE (Default) */ + e1000_write_phy_reg(hw, 0x1F35, 0x002A); + /* Enable FFE hysteresis */ + e1000_write_phy_reg(hw, 0x1F3E, 0x0067); + /* Fixed FFE for short cable lengths */ + e1000_write_phy_reg(hw, 0x1F54, 0x0065); + /* Fixed FFE for medium cable lengths */ + e1000_write_phy_reg(hw, 0x1F55, 0x002A); + /* Fixed FFE for long cable lengths */ + e1000_write_phy_reg(hw, 0x1F56, 0x002A); + /* Enable Adaptive Clip Threshold */ + e1000_write_phy_reg(hw, 0x1F72, 0x3FB0); + /* AHT reset limit to 1 */ + e1000_write_phy_reg(hw, 0x1F76, 0xC0FF); + /* Set AHT master delay to 127 msec */ + e1000_write_phy_reg(hw, 0x1F77, 0x1DEC); + /* Set scan bits for AHT */ + e1000_write_phy_reg(hw, 0x1F78, 0xF9EF); + /* Set AHT Preset bits */ + e1000_write_phy_reg(hw, 0x1F79, 0x0210); + /* Change integ_factor of channel A to 3 */ + e1000_write_phy_reg(hw, 0x1895, 0x0003); + /* Change prop_factor of channels BCD to 8 */ + e1000_write_phy_reg(hw, 0x1796, 0x0008); + /* Change cg_icount + enable integbp for channels BCD */ + e1000_write_phy_reg(hw, 0x1798, 0xD008); + /* + * Change cg_icount + enable integbp + change prop_factor_master to 8 + * for channel A + */ + e1000_write_phy_reg(hw, 0x1898, 0xD918); + /* Disable AHT in Slave mode on channel A */ + e1000_write_phy_reg(hw, 0x187A, 0x0800); + /* + * Enable LPLU and disable AN to 1000 in non-D0a states, Enable + * SPD+B2B + */ + e1000_write_phy_reg(hw, 0x0019, 0x008D); + /* Enable restart AN on an1000_dis change */ + e1000_write_phy_reg(hw, 0x001B, 0x2080); + /* Enable wh_fifo read clock in 10/100 modes */ + e1000_write_phy_reg(hw, 0x0014, 0x0045); + /* Restart AN, Speed selection is 1000 */ + e1000_write_phy_reg(hw, 0x0000, 0x1340); + + return (E1000_SUCCESS); +} + +/* + * e1000_get_phy_type_from_id - Get PHY type from id + * @phy_id: phy_id read from the phy + * + * Returns the phy type from the id. + */ +e1000_phy_type +e1000_get_phy_type_from_id(u32 phy_id) +{ + e1000_phy_type phy_type = e1000_phy_unknown; + + switch (phy_id) { + case M88E1000_I_PHY_ID: + case M88E1000_E_PHY_ID: + case M88E1111_I_PHY_ID: + case M88E1011_I_PHY_ID: + phy_type = e1000_phy_m88; + break; + case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ + phy_type = e1000_phy_igp_2; + break; + case GG82563_E_PHY_ID: + phy_type = e1000_phy_gg82563; + break; + case IGP03E1000_E_PHY_ID: + phy_type = e1000_phy_igp_3; + break; + case IFE_E_PHY_ID: + case IFE_PLUS_E_PHY_ID: + case IFE_C_E_PHY_ID: + phy_type = e1000_phy_ife; + break; + case BME1000_E_PHY_ID: + phy_type = e1000_phy_bm; + break; + default: + phy_type = e1000_phy_unknown; + break; + } + return (phy_type); +} + +/* + * e1000_determine_phy_address - Determines PHY address. + * @hw: pointer to the HW structure + * + * This uses a trial and error method to loop through possible PHY + * addresses. It tests each by reading the PHY ID registers and + * checking for a match. + */ +s32 +e1000_determine_phy_address(struct e1000_hw *hw) +{ + s32 ret_val = -E1000_ERR_PHY_TYPE; + u32 phy_addr = 0; + e1000_phy_type phy_type = e1000_phy_unknown; + + for (phy_addr = 1; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { + hw->phy.addr = phy_addr; + e1000_get_phy_id(hw); + phy_type = e1000_get_phy_type_from_id(hw->phy.id); + + /* if phy_type is valid, break - we found our PHY address */ + if (phy_type != e1000_phy_unknown) { + ret_val = E1000_SUCCESS; + break; + } + } + + return (ret_val); +} + +/* + * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address + * @page: page to access + * + * Returns the phy address for the page requested. + */ +static u32 +e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) +{ + u32 phy_addr = 2; + + if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) + phy_addr = 1; + + return (phy_addr); +} + +/* + * e1000_write_phy_reg_bm - Write BM PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset + * + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + */ +s32 +e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) +{ + s32 ret_val; + u32 page_select = 0; + u32 page = offset >> IGP_PAGE_SHIFT; + u32 page_shift = 0; + + DEBUGFUNC("e1000_write_phy_reg_bm"); + + /* Page 800 works differently than the rest so it has its own func */ + if (page == BM_WUC_PAGE) { + ret_val = e1000_access_phy_wakeup_reg_bm(hw, + offset, &data, FALSE); + goto out; + } + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + /* + * Page select is register 31 for phy address 1 and 22 for phy + * address 2 and 3. Page select is shifted only for phy + * address 1. + */ + if (hw->phy.addr == 1) { + page_shift = IGP_PAGE_SHIFT; + page_select = IGP01E1000_PHY_PAGE_SELECT; + } else { + page_shift = 0; + page_select = BM_PHY_PAGE_SELECT; + } + + /* Page is shifted left, PHY expects (page x 32) */ + ret_val = e1000_write_phy_reg_mdic(hw, page_select, + (page << page_shift)); + if (ret_val) { + e1000_release_phy(hw); + goto out; + } + } + + ret_val = e1000_write_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_read_phy_reg_bm - Read BM PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data + * + * Acquires semaphore, if necessary, then reads the PHY register at offset + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + */ +s32 +e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) +{ + s32 ret_val; + u32 page_select = 0; + u32 page = offset >> IGP_PAGE_SHIFT; + u32 page_shift = 0; + + DEBUGFUNC("e1000_write_phy_reg_bm"); + + /* Page 800 works differently than the rest so it has its own func */ + if (page == BM_WUC_PAGE) { + ret_val = e1000_access_phy_wakeup_reg_bm(hw, + offset, data, TRUE); + goto out; + } + ret_val = e1000_acquire_phy(hw); + if (ret_val) + goto out; + + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + /* + * Page select is register 31 for phy address 1 and 22 for phy + * address 2 and 3. Page select is shifted only for phy + * address 1. + */ + if (hw->phy.addr == 1) { + page_shift = IGP_PAGE_SHIFT; + page_select = IGP01E1000_PHY_PAGE_SELECT; + } else { + page_shift = 0; + page_select = BM_PHY_PAGE_SELECT; + } + + /* Page is shifted left, PHY expects (page x 32) */ + ret_val = e1000_write_phy_reg_mdic(hw, page_select, + (page << page_shift)); + if (ret_val) { + e1000_release_phy(hw); + goto out; + } + } + + ret_val = e1000_read_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + e1000_release_phy(hw); + +out: + return (ret_val); +} + +/* + * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register + * @hw: pointer to the HW structure + * @offset: register offset to be read or written + * @data: pointer to the data to read or write + * @read: determines if operation is read or write + * + * Acquires semaphore, if necessary, then reads the PHY register at offset + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. Note that procedure to read the wakeup + * registers are different. It works as such: + * 1) Set page 769, register 17, bit 2 = 1 + * 2) Set page to 800 for host (801 if we were manageability) + * 3) Write the address using the address opcode (0x11) + * 4) Read or write the data using the data opcode (0x12) + * 5) Restore 769_17.2 to its original value + */ +s32 +e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, + u32 offset, u16 *data, boolean_t read) +{ + s32 ret_val; + u16 reg = ((u16)offset) & PHY_REG_MASK; + u16 phy_reg = 0; + u8 phy_acquired = 1; + + DEBUGFUNC("e1000_read_phy_wakeup_reg_bm"); + + ret_val = e1000_acquire_phy(hw); + if (ret_val) { + DEBUGOUT("Couldnt acquire PHY\n"); + phy_acquired = 0; + goto out; + } + + /* All operations in this function are phy address 1 */ + hw->phy.addr = 1; + + /* Set page 769 */ + e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); + + ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); + if (ret_val) { + DEBUGOUT("Couldnt read PHY page 769\n"); + goto out; + } + + /* First clear bit 4 to avoid a power state change */ + phy_reg &= ~(BM_WUC_HOST_WU_BIT); + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); + if (ret_val) { + DEBUGOUT("Couldnt clear PHY page 769 bit 4\n"); + goto out; + } + + /* Write bit 2 = 1, and clear bit 4 to 769_17 */ + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, + phy_reg | BM_WUC_ENABLE_BIT); + if (ret_val) { + DEBUGOUT("Couldnt write PHY page 769 bit 2\n"); + goto out; + } + + /* Select page 800 */ + ret_val = e1000_write_phy_reg_mdic(hw, + IGP01E1000_PHY_PAGE_SELECT, + (BM_WUC_PAGE << IGP_PAGE_SHIFT)); + + /* Write the page 800 offset value using opcode 0x11 */ + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); + if (ret_val) { + DEBUGOUT("Couldnt write address opcode to page 800\n"); + goto out; + } + + if (read) { + /* Read the page 800 value using opcode 0x12 */ + ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, + data); + } else { + /* Read the page 800 value using opcode 0x12 */ + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, + *data); + } + + if (ret_val) { + DEBUGOUT("Couldnt read data value from page 800\n"); + goto out; + } + + /* + * Restore 769_17.2 to its original value Set page 769 + */ + e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); + + /* Clear 769_17.2 */ + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); + if (ret_val) { + DEBUGOUT("Couldnt clear PHY page 769 bit 2\n"); + goto out; + } + +out: + if (phy_acquired == 1) + e1000_release_phy(hw); + return (ret_val); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_phy.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,186 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_PHY_H_ +#define _E1000_PHY_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + e1000_ms_hw_default = 0, + e1000_ms_force_master, + e1000_ms_force_slave, + e1000_ms_auto +} e1000_ms_type; + +typedef enum { + e1000_smart_speed_default = 0, + e1000_smart_speed_on, + e1000_smart_speed_off +} e1000_smart_speed; + +s32 e1000_check_downshift_generic(struct e1000_hw *hw); +s32 e1000_check_polarity_m88(struct e1000_hw *hw); +s32 e1000_check_polarity_igp(struct e1000_hw *hw); +s32 e1000_check_reset_block_generic(struct e1000_hw *hw); +s32 e1000_copper_link_autoneg(struct e1000_hw *hw); +s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); +s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); +s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); +s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); +s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); +s32 e1000_get_cable_length_m88(struct e1000_hw *hw); +s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); +s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); +s32 e1000_get_phy_id(struct e1000_hw *hw); +s32 e1000_get_phy_info_igp(struct e1000_hw *hw); +s32 e1000_get_phy_info_m88(struct e1000_hw *hw); +s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); +void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); +s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); +s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); +s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); +s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active); +s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); +s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); +s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_phy_reset_dsp(struct e1000_hw *hw); +s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, boolean_t *success); +s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); +e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); +s32 e1000_determine_phy_address(struct e1000_hw *hw); +s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); +s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); +s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data, + boolean_t read); + +#define E1000_MAX_PHY_ADDR 4 + +/* IGP01E1000 Specific Registers */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ +#define BM_PHY_PAGE_SELECT 22 /* Page Select for IGP 4 */ +#define IGP_PAGE_SHIFT 5 +#define PHY_REG_MASK 0x1F + +#define BM_WUC_PAGE 800 +#define BM_WUC_ADDRESS_OPCODE 0x11 +#define BM_WUC_DATA_OPCODE 0x12 +#define BM_WUC_ENABLE_PAGE 769 +#define BM_WUC_ENABLE_REG 17 +#define BM_WUC_ENABLE_BIT (1 << 2) +#define BM_WUC_HOST_WU_BIT (1 << 4) + +#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 +#define IGP01E1000_PHY_POLARITY_MASK 0x0078 + +#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ + +#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 + +/* Enable flexible speed on link-up */ +#define IGP01E1000_GMII_FLEX_SPD 0x0010 +#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ + +#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ +#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ +#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ + +#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 + +#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 +#define IGP01E1000_PSSR_MDIX 0x0008 +#define IGP01E1000_PSSR_SPEED_MASK 0xC000 +#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 + +#define IGP02E1000_PHY_CHANNEL_NUM 4 +#define IGP02E1000_PHY_AGC_A 0x11B1 +#define IGP02E1000_PHY_AGC_B 0x12B1 +#define IGP02E1000_PHY_AGC_C 0x14B1 +#define IGP02E1000_PHY_AGC_D 0x18B1 + +#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ +#define IGP02E1000_AGC_LENGTH_MASK 0x7F +#define IGP02E1000_AGC_RANGE 15 + +#define IGP03E1000_PHY_MISC_CTRL 0x1B +#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ + +#define E1000_CABLE_LENGTH_UNDEFINED 0xFF + +#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 +#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 +#define E1000_KMRNCTRLSTA_REN 0x00200000 +#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ +#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ + +#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 +#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ +#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ +#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ + +/* IFE PHY Extended Status Control */ +#define IFE_PESC_POLARITY_REVERSED 0x0100 + +/* IFE PHY Special Control */ +#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 +#define IFE_PSC_FORCE_POLARITY 0x0020 +#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 + +/* IFE PHY Special Control and LED Control */ +#define IFE_PSCL_PROBE_MODE 0x0020 +#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ +#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ + +/* IFE PHY MDIX Control */ +#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ +#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ +#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_PHY_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/e1000g/e1000_regs.h Tue Aug 21 00:30:10 2007 -0700 @@ -0,0 +1,651 @@ +/* + * This file is provided under a CDDLv1 license. When using or + * redistributing this file, you may do so under this license. + * In redistributing this file this license must be included + * and no other modification of this header file is permitted. + * + * CDDL LICENSE SUMMARY + * + * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. + * + * The contents of this file are subject to the terms of Version + * 1.0 of the Common Development and Distribution License (the "License"). + * + * You should have received a copy of the License with this software. + * You can obtain a copy of the License at + * http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + */ + +/* + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms of the CDDLv1. + */ + +/* + * IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3 + */ +#ifndef _E1000_REGS_H_ +#define _E1000_REGS_H_ + +#pragma ident "%Z%%M% %I% %E% SMI" + +#ifdef __cplusplus +extern "C" { +#endif + +#define E1000_CTRL 0x00000 /* Device Control - RW */ +#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ +#define E1000_STATUS 0x00008 /* Device Status - RO */ +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define E1000_FLA 0x0001C /* Flash Access - RW */ +#define E1000_MDIC 0x00020 /* MDI Control - RW */ +#define E1000_SCTL 0x00024 /* SerDes Control - RW */ +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ +#define E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ +#define E1000_RCTL 0x00100 /* RX Control - RW */ +#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ +#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ +#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ +#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ +#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ +#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ +#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ +#define E1000_EITR0 0x01680 /* Ext. Int. Throttling Rate Vector 0 - RW */ +#define E1000_EITR1 0x01684 /* Ext. Int. Throttling Rate Vector 1 - RW */ +#define E1000_EITR2 0x01688 /* Ext. Int. Throttling Rate Vector 2 - RW */ +#define E1000_EITR3 0x0168C /* Ext. Int. Throttling Rate Vector 3 - RW */ +#define E1000_EITR4 0x01690 /* Ext. Int. Throttling Rate Vector 4 - RW */ +#define E1000_EITR5 0x01694 /* Ext. Int. Throttling Rate Vector 5 - RW */ +#define E1000_EITR6 0x01698 /* Ext. Int. Throttling Rate Vector 6 - RW */ +#define E1000_EITR7 0x0169C /* Ext. Int. Throttling Rate Vector 7 - RW */ +#define E1000_EITR8 0x016A0 /* Ext. Int. Throttling Rate Vector 8 - RW */ +#define E1000_EITR9 0x016A4 /* Ext. Int. Throttling Rate Vector 9 - RW */ +#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ +#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ +#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ +#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ +#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ +#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ +#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ +#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ +#define E1000_TCTL 0x00400 /* TX Control - RW */ +#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ +#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ +#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define E1000_PBS 0x01008 /* Packet Buffer Size */ +#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ +#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ +#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define E1000_FLSWCTL 0x01030 /* FLASH control register */ +#define E1000_FLSWDATA 0x01034 /* FLASH data register */ +#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ +#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ +#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ +#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ +#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ +#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ +#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ +#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ +#define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ +#define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */ +#define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */ +#define E1000_IMS_V2 0x01508 /* Interrupt Mask Set/Read -new location -RW */ +#define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */ +#define E1000_IAM_V2 0x01510 /* Interrupt Ack Auto Mask -new location -RW */ +#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ +#define E1000_RDFPCQ0 0x02430 +#define E1000_RDFPCQ1 0x02434 +#define E1000_RDFPCQ2 0x02438 +#define E1000_RDFPCQ3 0x0243C +#define E1000_PBRTH 0x02458 /* PB RX Arbitration Threshold - RW */ +#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ +#define E1000_SRRCTL0 0x0280C +/* Split and Replication RX Control - RW */ +#define E1000_SRRCTL(_n) (0x280C + (_n << 8)) +#define E1000_RDPUMB 0x025CC /* DMA RX Descriptor uC Mailbox - RW */ +#define E1000_RDPUAD 0x025D0 /* DMA RX Descriptor uC Addr Command - RW */ +#define E1000_RDPUWD 0x025D4 /* DMA RX Descriptor uC Data Write - RW */ +#define E1000_RDPURD 0x025D8 /* DMA RX Descriptor uC Data Read - RW */ +#define E1000_RDPUCTL 0x025DC /* DMA RX Descriptor uC Control - RW */ +#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ +#define E1000_RXPBS 0x02404 /* RX Packet Buffer Size - RW */ +#define E1000_RDBAL_REG_V2(_n) (0x0C000 + (0x40 * (_n))) +#define E1000_RDBAH_REG_V2(_n) (0x0C004 + (0x40 * (_n))) +#define E1000_RDLEN_REG_V2(_n) (0x0C008 + (0x40 * (_n))) +#define E1000_SRRCTL_REG_V2(_n) (0x0C00C + (0x40 * (_n))) +#define E1000_RDH_REG_V2(_n) (0x0C010 + (0x40 * (_n))) +#define E1000_RXCTL_REG_V2(_n) (0x0C014 + (0x40 * (_n))) +#define E1000_RDT_REG_V2(_n) (0x0C018 + (0x40 * (_n))) +#define E1000_RXDCTL_REG_V2(_n) (0x0C028 + (0x40 * (_n))) +#define E1000_RQDPC_REG(_n) (0x0C030 + (0x40 * (_n))) +#define E1000_TDBAL_REG_V2(_n) (0x0E000 + (0x40 * (_n))) +#define E1000_TDBAH_REG_V2(_n) (0x0E004 + (0x40 * (_n))) +#define E1000_TDLEN_REG_V2(_n) (0x0E008 + (0x40 * (_n))) +#define E1000_TDH_REG_V2(_n) (0x0E010 + (0x40 * (_n))) +#define E1000_TXCTL_REG_V2(_n) (0x0E014 + (0x40 * (_n))) +#define E1000_TDT_REG_V2(_n) (0x0E018 + (0x40 * (_n))) +#define E1000_TXDCTL_REG_V2(_n) (0x0E028 + (0x40 * (_n))) +#define E1000_TDWBAL_REG_V2(_n) (0x0E038 + (0x40 * (_n))) +#define E1000_TDWBAH_REG_V2(_n) (0x0E03C + (0x40 * (_n))) +#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ +#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ +#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ +#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ +#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ +#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ +#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ +#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ +#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ +#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ +#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ +#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ +#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ +#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ +/* + * Convenience macros + * + * Note: "_n" is the queue number of the register to be written to. + * + * Example usage: + * E1000_RDBAL_REG(current_rx_queue) + */ +#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8)) +#define E1000_RDBAH_REG(_n) (E1000_RDBAH + (_n << 8)) +#define E1000_RDLEN_REG(_n) (E1000_RDLEN + (_n << 8)) +#define E1000_RDH_REG(_n) (E1000_RDH + (_n << 8)) +#define E1000_RDT_REG(_n) (E1000_RDT + (_n << 8)) +#define E1000_RXDCTL_REG(_n) (E1000_RXDCTL + (_n << 8)) +#define E1000_TDBAL_REG(_n) (E1000_TDBAL + (_n << 8)) +#define E1000_TDBAH_REG(_n) (E1000_TDBAH + (_n << 8)) +#define E1000_TDLEN_REG(_n) (E1000_TDLEN + (_n << 8)) +#define E1000_TDH_REG(_n) (E1000_TDH + (_n << 8)) +#define E1000_TDT_REG(_n) (E1000_TDT + (_n << 8)) +#define E1000_TXDCTL_REG(_n) (E1000_TXDCTL + (_n << 8)) +#define E1000_TARC_REG(_n) (E1000_TARC0 + (_n << 8)) +#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) +#define E1000_DCA_RXCTRL0 0x02814 /* RX Queue 0 DCA CTRL - RW */ +#define E1000_DCA_RXCTRL1 0x02914 /* RX Queue 1 DCA CTRL - RW */ +#define E1000_RDBAL2 0x02A00 /* RX Descriptor Base Low Queue 2 - RW */ +#define E1000_RDBAH2 0x02A04 /* RX Descriptor Base High Queue 2 - RW */ +#define E1000_RDLEN2 0x02A08 /* RX Descriptor Length Queue 2 - RW */ +#define E1000_RDH2 0x02A10 /* RX Descriptor Head Queue 2 - RW */ +#define E1000_DCA_RXCTRL2 0x02A14 /* RX Queue 2 DCA CTRL - RW */ +#define E1000_RDT2 0x02A18 /* RX Descriptor Tail Queue 2 - RW */ +#define E1000_RXDCTL2 0x02A28 /* RX Descriptor Control queue 2 - RW */ +#define E1000_RDBAL3 0x02B00 /* RX Descriptor Base Low Queue 3 - RW */ +#define E1000_RDBAH3 0x02B04 /* RX Descriptor Base High Queue 3 - RW */ +#define E1000_RDLEN3 0x02B08 /* RX Descriptor Length Queue 3 - RW */ +#define E1000_RDH3 0x02B10 /* RX Descriptor Head Queue 3 - RW */ +#define E1000_DCA_RXCTRL3 0x02B14 /* RX Queue 3 DCA Control - RW */ +#define E1000_RDT3 0x02B18 /* RX Descriptor Tail Queue 3 - RW */ +#define E1000_RXDCTL3 0x02B28 /* RX Descriptor Control Queue 3 - RW */ +#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ +#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ +#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ +#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */ +#define E1000_PBSLAD0 0x03110 /* Packet Buffer DWORD 0 */ +#define E1000_PBSLAD1 0x03114 /* Packet Buffer DWORD 1 */ +#define E1000_PBSLAD2 0x03118 /* Packet Buffer DWORD 2 */ +#define E1000_PBSLAD3 0x0311C /* Packet Buffer DWORD 3 */ +#define E1000_TXPBS 0x03404 /* TX Packet Buffer Size - RW */ +#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ +#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ +#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ +#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ +#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ +#define E1000_TDPUMB 0x0357C /* DMA TX Descriptor uC Mail Box - RW */ +#define E1000_TDPUAD 0x03580 /* DMA TX Descriptor uC Addr Command - RW */ +#define E1000_TDPUWD 0x03584 /* DMA TX Descriptor uC Data Write - RW */ +#define E1000_TDPURD 0x03588 /* DMA TX Descriptor uC Data Read - RW */ +#define E1000_TDPUCTL 0x0358C /* DMA TX Descriptor uC Control - RW */ +#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ +#define E1000_DTXTCPFLGL 0x0359C /* DMA TX Control flag low - RW */ +#define E1000_DTXTCPFLGH 0x035A0 /* DMA TX Control flag high - RW */ +#define E1000_DTXMXSZRQ 0x03540 /* DMA TX Max Total Allow Size Requests - RW */ +#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ +#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ +#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ +#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ +#define E1000_TDT 0x03818 /* TX Descriptor Tail - RW */ +#define E1000_TDBAL0 E1000_TDBAL /* TX Descriptor Base Address Low - RW */ +#define E1000_TDBAH0 E1000_TDBAH /* TX Descriptor Base Address High - RW */ +#define E1000_TDLEN0 E1000_TDLEN /* TX Descriptor Length - RW */ +#define E1000_TDH0 E1000_TDH /* TX Descriptor Head - RW */ +#define E1000_TDT0 E1000_TDT /* TX Descriptor Tail - RW */ +#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ +#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ +#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ +#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ +#define E1000_DCA_TXCTRL0 0x03814 /* TX Queue 0 DCA CTRL - RW */ +#define E1000_TDWBAL0 0x03838 /* TX Desc. WB Addr Low Queue 0 - RW */ +#define E1000_TDWBAH0 0x0383C /* TX Desc. WB Addr High Queue 0 - RW */ +#define E1000_DCA_TXCTRL(_n) (E1000_DCA_TXCTRL0 + (_n << 8)) +#define E1000_TDWBAL_REG(_n) (E1000_TDWBAL0 + (_n << 8)) +#define E1000_TDWBAH_REG(_n) (E1000_TDWBAH0 + (_n << 8)) +#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ +#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ +#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ +#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ +#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ +#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ +#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ +#define E1000_DCA_TXCTRL1 0x03914 /* TX Queue 0 DCA CTRL - RW */ +#define E1000_TDWBAL1 0x03938 /* TX Descriptor WB Addr Low Queue 1 - RW */ +#define E1000_TDWBAH1 0x0393C /* TX Descriptor WB Addr High Queue 1 - RW */ +#define E1000_TDBAL2 0x03A00 /* TX Descriptor Base Low Queue 2 - RW */ +#define E1000_TDBAH2 0x03A04 /* TX Descriptor Base High Queue 2 - RW */ +#define E1000_TDLEN2 0x03A08 /* TX Descriptor Length Queue 2 - RW */ +#define E1000_TDH2 0x03A10 /* TX Descriptor Head Queue 2 - RW */ +#define E1000_DCA_TXCTRL2 0x03A14 /* TX Queue 2 DCA Control - RW */ +#define E1000_TDT2 0x03A18 /* TX Descriptor Tail Queue 2 - RW */ +#define E1000_TXDCTL2 0x03A28 /* TX Descriptor Control 2 - RW */ +#define E1000_TDWBAL2 0x03A38 /* TX Descriptor WB Addr Low Queue 2 - RW */ +#define E1000_TDWBAH2 0x03A3C /* TX Descriptor WB Addr High Queue 2 - RW */ +#define E1000_TDBAL3 0x03B00 /* TX Descriptor Base Low Queue 3 - RW */ +#define E1000_TDBAH3 0x03B04 /* TX Descriptor Base High Queue 3 - RW */ +#define E1000_TDLEN3 0x03B08 /* TX Descriptor Length Queue 3 - RW */ +#define E1000_TDH3 0x03B10 /* TX Descriptor Head Queue 3 - RW */ +#define E1000_DCA_TXCTRL3 0x03B14 /* TX Queue 3 DCA Control - RW */ +#define E1000_TDT3 0x03B18 /* TX Descriptor Tail Queue 3 - RW */ +#define E1000_TXDCTL3 0x03B28 /* TX Descriptor Control 3 - RW */ +#define E1000_TDWBAL3 0x03B38 /* TX Descriptor WB Addr Low Queue 3 - RW */ +#define E1000_TDWBAH3 0x03B3C /* TX Descriptor WB Addr High Queue 3 - RW */ +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ +#define E1000_COLC 0x04028 /* Collision Count - R/clr */ +#define E1000_DC 0x04030 /* Defer Count - R/clr */ +#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ +#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ +/* Interrupt Cause Rx Packet Timer Expire Count */ +#define E1000_ICRXPTC 0x04104 +/* Interrupt Cause Rx Absolute Timer Expire Count */ +#define E1000_ICRXATC 0x04108 +/* Interrupt Cause Tx Packet Timer Expire Count */ +#define E1000_ICTXPTC 0x0410C +/* Interrupt Cause Tx Absolute Timer Expire Count */ +#define E1000_ICTXATC 0x04110 +/* Interrupt Cause Tx Queue Empty Count */ +#define E1000_ICTXQEC 0x04118 +/* Interrupt Cause Tx Queue Minimum Threshold Count */ +#define E1000_ICTXQMTC 0x0411C +/* Interrupt Cause Rx Descriptor Minimum Threshold Count */ +#define E1000_ICRXDMTC 0x04120 +/* Interrupt Cause Receiver Overrun Count */ +#define E1000_ICRXOC 0x04124 +/* Switch Security Violation Packet Count */ +#define E1000_SSVPC 0x041A0 +/* LinkSec TX Untagged Packet Count */ +#define E1000_LSECTXUT 0x0413C +/* LinkSec Encrypted TX Packets Count */ +#define E1000_LSECTXPKTE 0x04140 +/* LinkSec Protected TX Packet Count */ +#define E1000_LSECTXPKTP 0x04144 +/* LinkSec Encrypted TX Octets Count */ +#define E1000_LSECTXOCTE 0x04148 +/* LinkSec Protected TX Octets Count */ +#define E1000_LSECTXOCTP 0x0414C +/* LinkSec Untagged non-Strict RX Packet Count */ +#define E1000_LSECRXUTNS 0x04150 +/* LinkSec Untagged Strict RX Packet Count */ +#define E1000_LSECRXUTYS 0x04154 +/* LinkSec RX Octets Decrypted Count */ +#define E1000_LSECRXOCTE 0x04158 +/* LinkSec RX Octets Validated */ +#define E1000_LSECRXOCTP 0x0415C +/* LinkSec RX Bad Tag */ +#define E1000_LSECRXBAD 0x04160 +/* LinkSec non-Strict RX Packet Unknown SCI Count */ +#define E1000_LSECRXNOSCINS 0x04164 +/* LinkSec Strict RX Packet Unknown SCI Count */ +#define E1000_LSECRXNOSCIYS 0x04168 +/* LinkSec RX Unchecked Packets Count */ +#define E1000_LSECRXNOSCI 0x0416C +/* LinkSec RX Delayed Packet Count */ +#define E1000_LSECRXDELAY 0x04170 +/* LinkSec RX Late Packets Count */ +#define E1000_LSECRXLATE 0x04174 +/* LinkSec TX Capabilities Register - RO */ +#define E1000_LSECTXCAP 0x0B000 +/* LinkSec RX Capabilities Register - RO */ +#define E1000_LSECRXCAP 0x0B300 +/* LinkSec TX Control - RW */ +#define E1000_LSECTXCTRL 0x0B004 +/* LinkSec RX Control - RW */ +#define E1000_LSECRXCTRL 0x0B304 +/* LinkSec TX SCI Low - RW */ +#define E1000_LSECTXSCIL 0x0B008 +/* LinkSec TX SCI High - RW */ +#define E1000_LSECTXSCIH 0x0B00C +/* LinkSec TX SA0 - RW */ +#define E1000_LSECTXSA 0x0B010 +/* LinkSec TX SA PN 0 - RW */ +#define E1000_LSECTXPN0 0x0B018 +/* LinkSec TX SA PN 1 - RW */ +#define E1000_LSECTXPN1 0x0B01C +/* LinkSec RX SCI Low - RW */ +#define E1000_LSECRXSCL 0x0B3D0 +/* LinkSec RX SCI High - RW */ +#define E1000_LSECRXSCH 0x0B3E0 +/* LinkSec TX 128-bit Key 0 - WO */ +#define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) +/* LinkSec TX 128-bit Key 1 - WO */ +#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) +/* LinkSec RX SAs - RW */ +#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) +/* LinkSec RX SAs - RW */ +#define E1000_LSECRXPN(_n) (0x0B318 + (0x04 * (_n))) +/* + * LinkSec RX Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit + * key - RW. + */ +#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) +#define E1000_IPSCTRL 0xB430 /* IpSec Control Register */ +#define E1000_IPSRXCMD 0x0B408 /* IPSec RX Command Register - RW */ +#define E1000_IPSRXIDX 0x0B400 /* IPSec RX Index - RW */ +/* IPSec RX IPv4/v6 Address - RW */ +#define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n))) +/* IPSec RX 128-bit Key - RW */ +#define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) +#define E1000_IPSRXSALT 0x0B404 /* IPSec RX Salt - RW */ +#define E1000_IPSRXSPI 0x0B40C /* IPSec RX SPI - RW */ +/* IPSec TX 128-bit Key - RW */ +#define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) +#define E1000_IPSTXSALT 0x0B454 /* IPSec TX Salt - RW */ +#define E1000_IPSTXIDX 0x0B450 /* IPSec TX SA IDX - RW */ +#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ +#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ +#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ +#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */ +#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ +#define E1000_CBRDPC 0x04044 /* Circuit Breaker RX Dropped Count */ +#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */ +#define E1000_RPTHC 0x04104 /* Rx Packets To Host */ +#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */ +#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ +#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ +#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ +#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ +#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ +#define E1000_LENERRS 0x04138 /* Length Errors Count */ +#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ +#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ +#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ +#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ +#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ +#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ +#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ +#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ +#define E1000_RFCTL 0x05008 /* Receive Filter Control */ +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ +#define E1000_RA 0x05400 /* Receive Address - RW Array */ +#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW */ +#define E1000_PSRTYPE 0x05480 /* Packet Split Receive Type - RW */ +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ +#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ +#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ +#define E1000_WUS 0x05810 /* Wakeup Status - RO */ +#define E1000_MANC 0x05820 /* Management Control - RW */ +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ +#define E1000_HOST_IF 0x08800 /* Host Interface */ +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ + +#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ +#define E1000_MDPHYA 0x0003C /* PHY address - RW */ +#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ +#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ +#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ +#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ +#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ +#define E1000_GCR 0x05B00 /* PCI-Ex Control */ +#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ +#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ +#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ +#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ +#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ +#define E1000_SWSM 0x05B50 /* SW Semaphore */ +#define E1000_FWSM 0x05B54 /* FW Semaphore */ +#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ +#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ +#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ +#define E1000_HICR 0x08F00 /* Host Inteface Control */ + +/* RSS registers */ +#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ +#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ +#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ +#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext */ +#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ +#define E1000_MSIXBM0 0x01600 /* MSI-X Allocation Register 0 - RW */ +#define E1000_MSIXBM1 0x01604 /* MSI-X Allocation Register 1 - RW */ +#define E1000_MSIXBM2 0x01608 /* MSI-X Allocation Register 2 - RW */ +#define E1000_MSIXBM3 0x0160C /* MSI-X Allocation Register 3 - RW */ +#define E1000_MSIXBM4 0x01610 /* MSI-X Allocation Register 4 - RW */ +#define E1000_MSIXBM5 0x01614 /* MSI-X Allocation Register 5 - RW */ +#define E1000_MSIXBM6 0x01618 /* MSI-X Allocation Register 6 - RW */ +#define E1000_MSIXBM7 0x0161C /* MSI-X Allocation Register 7 - RW */ +#define E1000_MSIXBM8 0x01620 /* MSI-X Allocation Register 8 - RW */ +#define E1000_MSIXBM9 0x01624 /* MSI-X Allocation Register 9 - RW */ +#define E1000_MSIXTADD0 0x0C000 /* MSI-X Table entry addr low reg 0 - RW */ +#define E1000_MSIXTADD1 0x0C010 /* MSI-X Table entry addr low reg 1 - RW */ +#define E1000_MSIXTADD2 0x0C020 /* MSI-X Table entry addr low reg 2 - RW */ +#define E1000_MSIXTADD3 0x0C030 /* MSI-X Table entry addr low reg 3 - RW */ +#define E1000_MSIXTADD4 0x0C040 /* MSI-X Table entry addr low reg 4 - RW */ +#define E1000_MSIXTADD5 0x0C050 /* MSI-X Table entry addr low reg 5 - RW */ +#define E1000_MSIXTADD6 0x0C060 /* MSI-X Table entry addr low reg 6 - RW */ +#define E1000_MSIXTADD7 0x0C070 /* MSI-X Table entry addr low reg 7 - RW */ +#define E1000_MSIXTADD8 0x0C080 /* MSI-X Table entry addr low reg 8 - RW */ +#define E1000_MSIXTADD9 0x0C090 /* MSI-X Table entry addr low reg 9 - RW */ +#define E1000_MSIXTUADD0 0x0C004 /* MSI-X Table entry addr upper reg 0 - RW */ +#define E1000_MSIXTUADD1 0x0C014 /* MSI-X Table entry addr upper reg 1 - RW */ +#define E1000_MSIXTUADD2 0x0C024 /* MSI-X Table entry addr upper reg 2 - RW */ +#define E1000_MSIXTUADD3 0x0C034 /* MSI-X Table entry addr upper reg 3 - RW */ +#define E1000_MSIXTUADD4 0x0C044 /* MSI-X Table entry addr upper reg 4 - RW */ +#define E1000_MSIXTUADD5 0x0C054 /* MSI-X Table entry addr upper reg 5 - RW */ +#define E1000_MSIXTUADD6 0x0C064 /* MSI-X Table entry addr upper reg 6 - RW */ +#define E1000_MSIXTUADD7 0x0C074 /* MSI-X Table entry addr upper reg 7 - RW */ +#define E1000_MSIXTUADD8 0x0C084 /* MSI-X Table entry addr upper reg 8 - RW */ +#define E1000_MSIXTUADD9 0x0C094 /* MSI-X Table entry addr upper reg 9 - RW */ +#define E1000_MSIXTMSG0 0x0C008 /* MSI-X Table entry message reg 0 - RW */ +#define E1000_MSIXTMSG1 0x0C018 /* MSI-X Table entry message reg 1 - RW */ +#define E1000_MSIXTMSG2 0x0C028 /* MSI-X Table entry message reg 2 - RW */ +#define E1000_MSIXTMSG3 0x0C038 /* MSI-X Table entry message reg 3 - RW */ +#define E1000_MSIXTMSG4 0x0C048 /* MSI-X Table entry message reg 4 - RW */ +#define E1000_MSIXTMSG5 0x0C058 /* MSI-X Table entry message reg 5 - RW */ +#define E1000_MSIXTMSG6 0x0C068 /* MSI-X Table entry message reg 6 - RW */ +#define E1000_MSIXTMSG7 0x0C078 /* MSI-X Table entry message reg 7 - RW */ +#define E1000_MSIXTMSG8 0x0C088 /* MSI-X Table entry message reg 8 - RW */ +#define E1000_MSIXTMSG9 0x0C098 /* MSI-X Table entry message reg 9 - RW */ +#define E1000_MSIXVCTRL0 0x0C00C /* MSI-X Table entry vector ctrl reg 0 - RW */ +#define E1000_MSIXVCTRL1 0x0C01C /* MSI-X Table entry vector ctrl reg 1 - RW */ +#define E1000_MSIXVCTRL2 0x0C02C /* MSI-X Table entry vector ctrl reg 2 - RW */ +#define E1000_MSIXVCTRL3 0x0C03C /* MSI-X Table entry vector ctrl reg 3 - RW */ +#define E1000_MSIXVCTRL4 0x0C04C /* MSI-X Table entry vector ctrl reg 4 - RW */ +#define E1000_MSIXVCTRL5 0x0C05C /* MSI-X Table entry vector ctrl reg 5 - RW */ +#define E1000_MSIXVCTRL6 0x0C06C /* MSI-X Table entry vector ctrl reg 6 - RW */ +#define E1000_MSIXVCTRL7 0x0C07C /* MSI-X Table entry vector ctrl reg 7 - RW */ +#define E1000_MSIXVCTRL8 0x0C08C /* MSI-X Table entry vector ctrl reg 8 - RW */ +#define E1000_MSIXVCTRL9 0x0C09C /* MSI-X Table entry vector ctrl reg 9 - RW */ +#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ +#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ +#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ +#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ +#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ +/* VT Registers */ +#define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */ +#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ +#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ +#define E1000_VFRE 0x00C8C /* VF Receive Enables */ +#define E1000_VFTE 0x00C90 /* VF Transmit Enables */ +#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ +#define E1000_DTXSWC 0x03500 /* DMA TX Switch Control - RW */ +#define E1000_VLVF 0x05D00 /* VLAN Virtual Machine Filter - RW */ +#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ +#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ +#define E1000_IOVTCL 0x05BBC /* IOV Control Register */ +/* These act per VF so an array friendly macro is used */ +#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) +#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) +#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) +#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) +/* Time Sync */ +#define E1000_TSYNCRXCTL 0x0B620 /* RX Time Sync Control register - RW */ +#define E1000_RXSTMPL 0x0B624 /* RX timestamp Low - RO */ +#define E1000_RXSTMPH 0x0B628 /* RX timestamp High - RO */ +#define E1000_RXSATRL 0x0B62C /* RX timestamp attribute low - RO */ +#define E1000_RXSATRH 0x0B630 /* RX timestamp attribute high - RO */ +#define E1000_TSYNCTXCTL 0x0B614 /* TX Time Sync Control register - RW */ +#define E1000_TXSTMPL 0x0B618 /* TX timestamp value Low - RO */ +#define E1000_TXSTMPH 0x0B61C /* TX timestamp value High - RO */ +#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ +#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ +#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ +#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync RX Configuration - RW */ + +/* Filtering Registers */ +#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ +#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ +#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ +#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ +#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ +#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ + +#define E1000_RTTDCS 0x3600 /* Reedtown TX Desc plane control and status */ +#define E1000_RTTPCS 0x3474 /* Reedtown TX Packet Plane control and status */ +#define E1000_RTRPCS 0x2474 /* RX packet plane control and status */ +#define E1000_RTRUP2TC 0x05AC4 /* RX User Priority to Traffic Class */ +#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ +/* Tx Desc plane TC Rate-scheduler config */ +#define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) +/* Tx Packet plane TC Rate-Scheduler Config */ +#define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler Config */ +#define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) +/* Tx Desc Plane TC Rate-Scheduler Status */ +#define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) +/* Tx Desc Plane TC Rate-Scheduler MMW */ +#define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) +/* Tx Packet plane TC Rate-Scheduler Status */ +#define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) +/* Tx Packet plane TC Rate-scheduler MMW */ +#define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler Status */ +#define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler MMW */ +#define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) +/* Tx Desc plane VM Rate-Scheduler MMW */ +#define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) +/* Tx BCN Rate-Scheduler MMW */ +#define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) +#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ +#define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ +#define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ +#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */ +#define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */ +#define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */ +#define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */ +#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ +#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ +#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ +#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ +#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ +#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ +#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ + +#ifdef __cplusplus +} +#endif + +#endif /* _E1000_REGS_H_ */
--- a/usr/src/uts/common/io/e1000g/e1000g_alloc.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_alloc.c Tue Aug 21 00:30:10 2007 -0700 @@ -28,18 +28,11 @@ /* * ********************************************************************** * Module Name: * - * e1000galloc.c * + * e1000g_alloc.c * * * * Abstract: * - * This file contains some routines that take care of init, * - * uninit, and memory allocation. * - * * - * * - * This driver runs on the following hardware: * - * - Wiseman based PCI gigabit ethernet adapters * - * * - * Environment: * - * Kernel Mode - * + * This file contains some routines that take care of * + * memory allocation for descriptors and buffers. * * * * ********************************************************************** */ @@ -48,7 +41,7 @@ #include "e1000g_debug.h" #define TX_SW_PKT_AREA_SZ \ - (sizeof (TX_SW_PACKET) * Adapter->NumTxSwPacket) + (sizeof (tx_sw_packet_t) * Adapter->tx_freelist_num) static int e1000g_alloc_tx_descriptors(e1000g_tx_ring_t *); static int e1000g_alloc_rx_descriptors(e1000g_rx_ring_t *); @@ -58,15 +51,89 @@ static int e1000g_alloc_rx_packets(e1000g_rx_ring_t *); static void e1000g_free_tx_packets(e1000g_tx_ring_t *); static void e1000g_free_rx_packets(e1000g_rx_ring_t *); -static int e1000g_alloc_dma_buffer(struct e1000g *, dma_buffer_t *, size_t); +static int e1000g_alloc_dma_buffer(struct e1000g *, + dma_buffer_t *, size_t, ddi_dma_attr_t *p_dma_attr); static void e1000g_free_dma_buffer(dma_buffer_t *); #ifdef __sparc static int e1000g_alloc_dvma_buffer(struct e1000g *, dma_buffer_t *, size_t); static void e1000g_free_dvma_buffer(dma_buffer_t *); #endif static int e1000g_alloc_descriptors(struct e1000g *Adapter); +static void e1000g_free_descriptors(struct e1000g *Adapter); static int e1000g_alloc_packets(struct e1000g *Adapter); -static PRX_SW_PACKET e1000g_alloc_rx_sw_packet(e1000g_rx_ring_t *); +static void e1000g_free_packets(struct e1000g *Adapter); +static p_rx_sw_packet_t e1000g_alloc_rx_sw_packet(e1000g_rx_ring_t *, + ddi_dma_attr_t *p_dma_attr); + +/* DMA access attributes for descriptors <Little Endian> */ +static ddi_device_acc_attr_t e1000g_desc_acc_attr = { + DDI_DEVICE_ATTR_V0, + DDI_STRUCTURE_LE_ACC, + DDI_STRICTORDER_ACC, +}; + +/* DMA access attributes for DMA buffers */ +#ifdef __sparc +static ddi_device_acc_attr_t e1000g_buf_acc_attr = { + DDI_DEVICE_ATTR_V0, + DDI_STRUCTURE_BE_ACC, + DDI_STRICTORDER_ACC, +}; +#else +static ddi_device_acc_attr_t e1000g_buf_acc_attr = { + DDI_DEVICE_ATTR_V0, + DDI_STRUCTURE_LE_ACC, + DDI_STRICTORDER_ACC, +}; +#endif + +/* DMA attributes for tx mblk buffers */ +static ddi_dma_attr_t e1000g_tx_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffffffffffULL, /* highest usable address */ + 0x7fffffff, /* maximum DMAable byte count */ + 1, /* alignment in bytes */ + 0x7ff, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffffffffffULL, /* maximum segment length */ + 16, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* DMA attributes for pre-allocated rx/tx buffers */ +static ddi_dma_attr_t e1000g_buf_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffffffffffULL, /* highest usable address */ + 0x7fffffff, /* maximum DMAable byte count */ + 1, /* alignment in bytes */ + 0x7ff, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffffffffffULL, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* DMA attributes for rx/tx descriptors */ +static ddi_dma_attr_t e1000g_desc_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffffffffffULL, /* highest usable address */ + 0x7fffffff, /* maximum DMAable byte count */ + E1000_MDALIGN, /* alignment in bytes 4K! */ + 0x7ff, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffffffffffULL, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; #ifdef __sparc static ddi_dma_lim_t e1000g_dma_limits = { @@ -87,93 +154,58 @@ extern krwlock_t e1000g_dma_type_lock; + int e1000g_alloc_dma_resources(struct e1000g *Adapter) { - e1000g_tx_ring_t *tx_ring; - e1000g_rx_ring_t *rx_ring; + int result; + + result = DDI_FAILURE; - tx_ring = Adapter->tx_ring; - rx_ring = Adapter->rx_ring; + while ((result != DDI_SUCCESS) && + (Adapter->tx_desc_num >= MIN_NUM_TX_DESCRIPTOR) && + (Adapter->rx_desc_num >= MIN_NUM_RX_DESCRIPTOR) && + (Adapter->tx_freelist_num >= MIN_NUM_TX_FREELIST) && + (Adapter->rx_freelist_num >= MIN_NUM_RX_FREELIST)) { + + result = e1000g_alloc_descriptors(Adapter); + + if (result == DDI_SUCCESS) { + result = e1000g_alloc_packets(Adapter); + + if (result != DDI_SUCCESS) + e1000g_free_descriptors(Adapter); + } - if (e1000g_alloc_descriptors(Adapter) != DDI_SUCCESS) - return (DDI_FAILURE); + /* + * If the allocation fails due to resource shortage, + * we'll reduce the numbers of descriptors/buffers by + * half, and try the allocation again. + */ + if (result != DDI_SUCCESS) { + /* + * We must ensure the number of descriptors + * is always a multiple of 8. + */ + Adapter->tx_desc_num = + (Adapter->tx_desc_num >> 4) << 3; + Adapter->rx_desc_num = + (Adapter->rx_desc_num >> 4) << 3; - if (e1000g_alloc_packets(Adapter) != DDI_SUCCESS) { - e1000g_free_tx_descriptors(tx_ring); - e1000g_free_rx_descriptors(rx_ring); - return (DDI_FAILURE); + Adapter->tx_freelist_num >>= 1; + Adapter->rx_freelist_num >>= 1; + } } - return (DDI_SUCCESS); + return (result); } /* - * ********************************************************************** - * Name: e1000g_alloc_descriptors * - * * - * Description: * - * This routine Allocates Neccesary Buffers for the device * - * It allocates memory for * - * Transmit Descriptor Area * - * Receive Descrpitor Area * - * * - * NOTE -- The device must have been reset before this routine * - * is called. * - * * - * Author: Hari Seshadri * - * Functions Called : * - * DDI mem functions called * - * ddi_dma_alloc_handle() allocates a new DMA handle. A DMA * - * handle is an opaque object used as a reference to subse- * - * quently allocated DMA resources. ddi_dma_alloc_handle() * - * accepts as parameters the device information referred to by * - * dip and the device's DMA attributes described by a * - * ddi_dma_attr(9S) structure. A successful call to * - * ddi_dma_alloc_handle() fills in the value pointed to by * - * handlep. A DMA handle must only be used by the device for * - * which it was allocated and is only valid for one I/O tran- * - * saction at a time. * - * * - * ddi_dma_mem_alloc() allocates memory for DMA transfers to or * - * from a device. The allocation will obey the alignment, pad- * - * ding constraints and device granularity as specified by the * - * DMA attributes (see ddi_dma_attr(9S)) passed to * - * ddi_dma_alloc_handle(9F) and the more restrictive attributes * - * imposed by the system.Flags should be set to DDI_DMA_STREAMING * - * if the device is doing sequential, unidirectional, * - * block-sized, and block- aligned transfers to or from memory. * - * * - * * - * ddi_dma_addr_bind_handle() allocates DMA resources for a * - * memory object such that a device can perform DMA to or from * - * the object. DMA resources are allocated considering the * - * device's DMA attributes as expressed by ddi_dma_attr(9S) * - * (see ddi_dma_alloc_handle(9F)). * - * ddi_dma_addr_bind_handle() fills in the first DMA cookie * - * pointed to by cookiep with the appropriate address, length, * - * and bus type. *ccountp is set to the number of DMA cookies * - * representing this DMA object. Subsequent DMA cookies must be * - * retrieved by calling ddi_dma_nextcookie(9F) the number of * - * times specified by *countp - 1. * - * * - * Arguments: * - * Adapter - A pointer to context sensitive "Adapter" structure. * - * * - * * - * Returns: * - * DDI_SUCCESS on success * - * DDI_FAILURE on error * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * 11/11/98 Vinay Cleaned the entire function to prevents panics and * - * memory corruption * - * 17/11/98 Vinay Optimized it for proper usages of function calls * - * 30/04/99 Vinay Resolved some more memory problems related to race * - * conditions * - * ********************************************************************** + * e1000g_alloc_descriptors - allocate DMA buffers for descriptors + * + * This routine allocates neccesary DMA buffers for + * Transmit Descriptor Area + * Receive Descrpitor Area */ static int e1000g_alloc_descriptors(struct e1000g *Adapter) @@ -199,6 +231,19 @@ return (DDI_SUCCESS); } +static void +e1000g_free_descriptors(struct e1000g *Adapter) +{ + e1000g_tx_ring_t *tx_ring; + e1000g_rx_ring_t *rx_ring; + + tx_ring = Adapter->tx_ring; + rx_ring = Adapter->rx_ring; + + e1000g_free_tx_descriptors(tx_ring); + e1000g_free_rx_descriptors(rx_ring); +} + static int e1000g_alloc_tx_descriptors(e1000g_tx_ring_t *tx_ring) { @@ -211,12 +256,13 @@ dev_info_t *devinfo; ddi_dma_cookie_t cookie; struct e1000g *Adapter; + ddi_dma_attr_t dma_attr; Adapter = tx_ring->adapter; + devinfo = Adapter->dip; alloc_flag = B_FALSE; - - devinfo = Adapter->dip; + dma_attr = e1000g_desc_dma_attr; /* * Solaris 7 has a problem with allocating physically contiguous memory @@ -231,29 +277,23 @@ * 4K, ie more than 256 descriptors, we allocate 4k extra memory and * and then align the memory at a 4k boundary. */ - size = sizeof (struct e1000_tx_desc) * Adapter->NumTxDescriptors; + size = sizeof (struct e1000_tx_desc) * Adapter->tx_desc_num; /* * Memory allocation for the transmit buffer descriptors. */ - /* - * DMA attributes set to asking for 4k alignment and no - * scatter/gather specified. - * This typically does not succeed for Solaris 7, but - * might work for Solaris 2.6 - */ - tbd_dma_attr.dma_attr_sgllen = 1; + dma_attr.dma_attr_sgllen = 1; /* * Allocate a new DMA handle for the transmit descriptor * memory area. */ - mystat = ddi_dma_alloc_handle(devinfo, &tbd_dma_attr, + mystat = ddi_dma_alloc_handle(devinfo, &dma_attr, DDI_DMA_DONTWAIT, 0, &tx_ring->tbd_dma_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate tbd dma handle: %d", mystat); tx_ring->tbd_dma_handle = NULL; return (DDI_FAILURE); @@ -265,7 +305,7 @@ */ mystat = ddi_dma_mem_alloc(tx_ring->tbd_dma_handle, size, - &accattr, DDI_DMA_CONSISTENT, + &e1000g_desc_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, 0, (caddr_t *)&tx_ring->tbd_area, &len, &tx_ring->tbd_acc_handle); @@ -302,19 +342,19 @@ /* * DMA attributes set to no scatter/gather and 16 bit alignment */ - tbd_dma_attr.dma_attr_align = 1; - tbd_dma_attr.dma_attr_sgllen = 1; + dma_attr.dma_attr_align = 1; + dma_attr.dma_attr_sgllen = 1; /* * Allocate a new DMA handle for the transmit descriptor memory * area. */ - mystat = ddi_dma_alloc_handle(devinfo, &tbd_dma_attr, + mystat = ddi_dma_alloc_handle(devinfo, &dma_attr, DDI_DMA_DONTWAIT, 0, &tx_ring->tbd_dma_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not re-allocate tbd dma handle: %d", mystat); tx_ring->tbd_dma_handle = NULL; return (DDI_FAILURE); @@ -326,13 +366,13 @@ */ mystat = ddi_dma_mem_alloc(tx_ring->tbd_dma_handle, size, - &accattr, DDI_DMA_CONSISTENT, + &e1000g_desc_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, 0, (caddr_t *)&tx_ring->tbd_area, &len, &tx_ring->tbd_acc_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate tbd dma memory: %d", mystat); tx_ring->tbd_acc_handle = NULL; tx_ring->tbd_area = NULL; @@ -371,10 +411,10 @@ mystat = ddi_dma_addr_bind_handle(tx_ring->tbd_dma_handle, (struct as *)NULL, (caddr_t)tx_ring->tbd_area, len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, - DDI_DMA_SLEEP, 0, &cookie, &cookie_count); + DDI_DMA_DONTWAIT, 0, &cookie, &cookie_count); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not bind tbd dma resource: %d", mystat); if (tx_ring->tbd_acc_handle != NULL) { ddi_dma_mem_free(&tx_ring->tbd_acc_handle); @@ -391,21 +431,17 @@ ASSERT(cookie_count == 1); /* 1 cookie */ if (cookie_count != 1) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Could not bind tbd dma resource in a single frag. " "Count - %d Len - %d", cookie_count, len); e1000g_free_tx_descriptors(tx_ring); return (DDI_FAILURE); } - /* - * The FirstTxDescriptor is initialized to the physical address that - * is obtained from the ddi_dma_addr_bind_handle call - */ tx_ring->tbd_dma_addr = cookie.dmac_laddress; tx_ring->tbd_first = tx_ring->tbd_area; tx_ring->tbd_last = tx_ring->tbd_first + - (Adapter->NumTxDescriptors - 1); + (Adapter->tx_desc_num - 1); return (DDI_SUCCESS); } @@ -422,35 +458,34 @@ dev_info_t *devinfo; ddi_dma_cookie_t cookie; struct e1000g *Adapter; + ddi_dma_attr_t dma_attr; Adapter = rx_ring->adapter; + devinfo = Adapter->dip; alloc_flag = B_FALSE; - - devinfo = Adapter->dip; + dma_attr = e1000g_desc_dma_attr; /* * Memory allocation for the receive buffer descriptors. */ - size = (sizeof (struct e1000_rx_desc)) * Adapter->NumRxDescriptors; + size = (sizeof (struct e1000_rx_desc)) * Adapter->rx_desc_num; /* * Asking for aligned memory with DMA attributes set for 4k alignment */ - tbd_dma_attr.dma_attr_sgllen = 1; - tbd_dma_attr.dma_attr_align = E1000_MDALIGN; + dma_attr.dma_attr_sgllen = 1; + dma_attr.dma_attr_align = E1000_MDALIGN; /* - * Allocate a new DMA handle for the receive descriptor - * memory area. re-use the tbd_dma_attr since rbd has - * same attributes. + * Allocate a new DMA handle for the receive descriptors */ - mystat = ddi_dma_alloc_handle(devinfo, &tbd_dma_attr, + mystat = ddi_dma_alloc_handle(devinfo, &dma_attr, DDI_DMA_DONTWAIT, 0, &rx_ring->rbd_dma_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate rbd dma handle: %d", mystat); rx_ring->rbd_dma_handle = NULL; return (DDI_FAILURE); @@ -461,7 +496,7 @@ */ mystat = ddi_dma_mem_alloc(rx_ring->rbd_dma_handle, size, - &accattr, DDI_DMA_CONSISTENT, + &e1000g_desc_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, 0, (caddr_t *)&rx_ring->rbd_area, &len, &rx_ring->rbd_acc_handle); @@ -492,24 +527,21 @@ bzero((caddr_t)rx_ring->rbd_area, len); /* - * If memory allocation did not succeed or if number of descriptors is - * greater than a page size ( more than 256 descriptors ), do the - * alignment yourself + * If memory allocation did not succeed, do the alignment ourselves */ if (!alloc_flag) { - tbd_dma_attr.dma_attr_align = 1; - tbd_dma_attr.dma_attr_sgllen = 1; + dma_attr.dma_attr_align = 1; + dma_attr.dma_attr_sgllen = 1; size = size + ROUNDOFF; /* - * Allocate a new DMA handle for the receive descriptor memory - * area. re-use the tbd_dma_attr since rbd has same attributes. + * Allocate a new DMA handle for the receive descriptor. */ - mystat = ddi_dma_alloc_handle(devinfo, &tbd_dma_attr, + mystat = ddi_dma_alloc_handle(devinfo, &dma_attr, DDI_DMA_DONTWAIT, 0, &rx_ring->rbd_dma_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not re-allocate rbd dma handle: %d", mystat); rx_ring->rbd_dma_handle = NULL; return (DDI_FAILURE); @@ -520,13 +552,13 @@ */ mystat = ddi_dma_mem_alloc(rx_ring->rbd_dma_handle, size, - &accattr, DDI_DMA_CONSISTENT, + &e1000g_desc_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, 0, (caddr_t *)&rx_ring->rbd_area, &len, &rx_ring->rbd_acc_handle); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate rbd dma memory: %d", mystat); rx_ring->rbd_acc_handle = NULL; rx_ring->rbd_area = NULL; @@ -560,10 +592,10 @@ mystat = ddi_dma_addr_bind_handle(rx_ring->rbd_dma_handle, (struct as *)NULL, (caddr_t)rx_ring->rbd_area, len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, - DDI_DMA_SLEEP, 0, &cookie, &cookie_count); + DDI_DMA_DONTWAIT, 0, &cookie, &cookie_count); if (mystat != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not bind rbd dma resource: %d", mystat); if (rx_ring->rbd_acc_handle != NULL) { ddi_dma_mem_free(&rx_ring->rbd_acc_handle); @@ -579,20 +611,17 @@ ASSERT(cookie_count == 1); if (cookie_count != 1) { - e1000g_log(Adapter, CE_WARN, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Could not bind rbd dma resource in a single frag. " "Count - %d Len - %d", cookie_count, len); e1000g_free_rx_descriptors(rx_ring); return (DDI_FAILURE); } - /* - * Initialize the FirstRxDescriptor to the cookie address obtained - * from the ddi_dma_addr_bind_handle call. - */ + rx_ring->rbd_dma_addr = cookie.dmac_laddress; rx_ring->rbd_first = rx_ring->rbd_area; rx_ring->rbd_last = rx_ring->rbd_first + - (Adapter->NumRxDescriptors - 1); + (Adapter->rx_desc_num - 1); return (DDI_SUCCESS); } @@ -639,44 +668,14 @@ /* - * ********************************************************************** - * Name: e1000g_alloc_packets * - * * - * Description: This routine Allocates Neccesary Buffers for the device * - * It allocates memory for * - * * - * Transmit packet Structure * - * Handle for Transmit buffers * - * Receive packet structure * - * Buffer for Receive packet * - * * - * * - * For ddi memory alloc routine see e1000g_Txalloc description * - * NOTE -- The device must have been reset before this routine * - * is called. * - * * - * Author: Hari Seshadri * - * Functions Called : * - * * - * * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * * - * Returns: * - * DDI_SUCCESS on sucess * - * DDI_FAILURE on error * - * * - * * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * 30/04/99 VA Cleaned code for memory corruptions, invalid DMA * - * attributes and prevent panics * - * ********************************************************************** + * e1000g_alloc_packets - allocate DMA buffers for rx/tx + * + * This routine allocates neccesary buffers for + * Transmit sw packet structure + * DMA handle for Transmit + * DMA buffer for Transmit + * Receive sw packet structure + * DMA buffer for Receive */ static int e1000g_alloc_packets(struct e1000g *Adapter) @@ -700,14 +699,14 @@ e1000g_dma_type = USE_DMA; rw_exit(&e1000g_dma_type_lock); - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "No enough dvma resource for Tx packets, " "trying to allocate dma buffers...\n"); goto again; } rw_exit(&e1000g_dma_type_lock); - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Failed to allocate dma buffers for Tx packets\n"); return (DDI_FAILURE); } @@ -722,14 +721,14 @@ e1000g_dma_type = USE_DMA; rw_exit(&e1000g_dma_type_lock); - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "No enough dvma resource for Rx packets, " "trying to allocate dma buffers...\n"); goto again; } rw_exit(&e1000g_dma_type_lock); - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Failed to allocate dma buffers for Rx packets\n"); return (DDI_FAILURE); } @@ -739,6 +738,19 @@ return (DDI_SUCCESS); } +static void +e1000g_free_packets(struct e1000g *Adapter) +{ + e1000g_tx_ring_t *tx_ring; + e1000g_rx_ring_t *rx_ring; + + tx_ring = Adapter->tx_ring; + rx_ring = Adapter->rx_ring; + + e1000g_free_tx_packets(tx_ring); + e1000g_free_rx_packets(rx_ring); +} + #ifdef __sparc static int e1000g_alloc_dvma_buffer(struct e1000g *Adapter, @@ -760,7 +772,7 @@ if (mystat != DDI_SUCCESS) { buf->dma_handle = NULL; - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate dvma buffer handle: %d\n", mystat); return (DDI_FAILURE); } @@ -772,7 +784,7 @@ dvma_release(buf->dma_handle); buf->dma_handle = NULL; } - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Could not allocate dvma buffer memory\n"); return (DDI_FAILURE); } @@ -815,7 +827,7 @@ static int e1000g_alloc_dma_buffer(struct e1000g *Adapter, - dma_buffer_t *buf, size_t size) + dma_buffer_t *buf, size_t size, ddi_dma_attr_t *p_dma_attr) { int mystat; dev_info_t *devinfo; @@ -829,19 +841,19 @@ devinfo = Adapter->dip; mystat = ddi_dma_alloc_handle(devinfo, - &buf_dma_attr, + p_dma_attr, DDI_DMA_DONTWAIT, 0, &buf->dma_handle); if (mystat != DDI_SUCCESS) { buf->dma_handle = NULL; - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate dma buffer handle: %d\n", mystat); return (DDI_FAILURE); } mystat = ddi_dma_mem_alloc(buf->dma_handle, - size, &accattr2, DDI_DMA_STREAMING, + size, &e1000g_buf_acc_attr, DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, 0, &buf->address, &len, &buf->acc_handle); @@ -853,7 +865,7 @@ ddi_dma_free_handle(&buf->dma_handle); buf->dma_handle = NULL; } - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate dma buffer memory: %d\n", mystat); return (DDI_FAILURE); } @@ -862,7 +874,7 @@ (struct as *)NULL, buf->address, len, DDI_DMA_READ | DDI_DMA_STREAMING, - DDI_DMA_SLEEP, 0, &cookie, &count); + DDI_DMA_DONTWAIT, 0, &cookie, &count); if (mystat != DDI_SUCCESS) { if (buf->acc_handle != NULL) { @@ -874,7 +886,7 @@ ddi_dma_free_handle(&buf->dma_handle); buf->dma_handle = NULL; } - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not bind buffer dma handle: %d\n", mystat); return (DDI_FAILURE); } @@ -893,7 +905,7 @@ ddi_dma_free_handle(&buf->dma_handle); buf->dma_handle = NULL; } - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not bind buffer as a single frag. " "Count = %d\n", count); return (DDI_FAILURE); @@ -936,11 +948,16 @@ e1000g_alloc_tx_packets(e1000g_tx_ring_t *tx_ring) { int j; - PTX_SW_PACKET packet; + p_tx_sw_packet_t packet; int mystat; dma_buffer_t *tx_buf; - struct e1000g *Adapter = tx_ring->adapter; - dev_info_t *devinfo = Adapter->dip; + struct e1000g *Adapter; + dev_info_t *devinfo; + ddi_dma_attr_t dma_attr; + + Adapter = tx_ring->adapter; + devinfo = Adapter->dip; + dma_attr = e1000g_buf_dma_attr; /* * Memory allocation for the Transmit software structure, the transmit @@ -954,7 +971,7 @@ return (DDI_FAILURE); for (j = 0, packet = tx_ring->packet_area; - j < Adapter->NumTxSwPacket; j++, packet++) { + j < Adapter->tx_freelist_num; j++, packet++) { ASSERT(packet != NULL); @@ -976,7 +993,7 @@ #endif case USE_DMA: mystat = ddi_dma_alloc_handle(devinfo, - &tx_dma_attr, + &e1000g_tx_dma_attr, DDI_DMA_DONTWAIT, 0, &packet->tx_dma_handle); break; @@ -986,7 +1003,7 @@ } if (mystat != DDI_SUCCESS) { packet->tx_dma_handle = NULL; - e1000g_DEBUGLOG_1(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Could not allocate tx dma handle: %d\n", mystat); goto tx_pkt_fail; } @@ -1004,12 +1021,12 @@ #ifdef __sparc case USE_DVMA: mystat = e1000g_alloc_dvma_buffer(Adapter, - tx_buf, Adapter->TxBufferSize); + tx_buf, Adapter->tx_buffer_size); break; #endif case USE_DMA: mystat = e1000g_alloc_dma_buffer(Adapter, - tx_buf, Adapter->TxBufferSize); + tx_buf, Adapter->tx_buffer_size, &dma_attr); break; default: ASSERT(B_FALSE); @@ -1031,7 +1048,7 @@ break; } packet->tx_dma_handle = NULL; - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Allocate Tx buffer fail\n"); goto tx_pkt_fail; } @@ -1051,32 +1068,30 @@ e1000g_alloc_rx_packets(e1000g_rx_ring_t *rx_ring) { int i; - PRX_SW_PACKET packet; + p_rx_sw_packet_t packet; struct e1000g *Adapter; uint32_t packet_num; + ddi_dma_attr_t dma_attr; Adapter = rx_ring->adapter; + dma_attr = e1000g_buf_dma_attr; +#ifndef NO_82542_SUPPORT + dma_attr.dma_attr_align = Adapter->rx_buf_align; +#endif /* - * Allocate memory for the RX_SW_PACKET structures. Each one of these + * Allocate memory for the rx_sw_packet structures. Each one of these * structures will contain a virtual and physical address to an actual - * receive buffer in host memory. Since we use one RX_SW_PACKET per - * received packet, the maximum number of RX_SW_PACKETs that we'll + * receive buffer in host memory. Since we use one rx_sw_packet per + * received packet, the maximum number of rx_sw_packet that we'll * need is equal to the number of receive descriptors that we've * allocated. - * - * Pre allocation for recv packet buffer. The Recv intr constructs - * a new mp using this buffer - * - * On Wiseman these Receive buffers must be aligned with 256 byte - * boundary - * Vinay, Apr19,2000 */ - packet_num = Adapter->NumRxDescriptors + Adapter->NumRxFreeList; + packet_num = Adapter->rx_desc_num + Adapter->rx_freelist_num; rx_ring->packet_area = NULL; for (i = 0; i < packet_num; i++) { - packet = e1000g_alloc_rx_sw_packet(rx_ring); + packet = e1000g_alloc_rx_sw_packet(rx_ring, &dma_attr); if (packet == NULL) goto rx_pkt_fail; @@ -1092,40 +1107,35 @@ return (DDI_FAILURE); } -static PRX_SW_PACKET -e1000g_alloc_rx_sw_packet(e1000g_rx_ring_t *rx_ring) +static p_rx_sw_packet_t +e1000g_alloc_rx_sw_packet(e1000g_rx_ring_t *rx_ring, ddi_dma_attr_t *p_dma_attr) { int mystat; - PRX_SW_PACKET packet; + p_rx_sw_packet_t packet; dma_buffer_t *rx_buf; struct e1000g *Adapter; Adapter = rx_ring->adapter; - packet = kmem_zalloc(sizeof (RX_SW_PACKET), KM_NOSLEEP); + packet = kmem_zalloc(sizeof (rx_sw_packet_t), KM_NOSLEEP); if (packet == NULL) { - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Cound not allocate memory for Rx SwPacket\n"); return (NULL); } rx_buf = packet->rx_buf; - /* - * Make sure that receive buffers are 256 byte aligned - */ - buf_dma_attr.dma_attr_align = Adapter->RcvBufferAlignment; - switch (e1000g_dma_type) { #ifdef __sparc case USE_DVMA: mystat = e1000g_alloc_dvma_buffer(Adapter, - rx_buf, Adapter->RxBufferSize); + rx_buf, Adapter->rx_buffer_size); break; #endif case USE_DMA: mystat = e1000g_alloc_dma_buffer(Adapter, - rx_buf, Adapter->RxBufferSize); + rx_buf, Adapter->rx_buffer_size, p_dma_attr); break; default: ASSERT(B_FALSE); @@ -1134,9 +1144,9 @@ if (mystat != DDI_SUCCESS) { if (packet != NULL) - kmem_free(packet, sizeof (RX_SW_PACKET)); + kmem_free(packet, sizeof (rx_sw_packet_t)); - e1000g_DEBUGLOG_0(Adapter, e1000g_CALLTRACE_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Failed to allocate Rx buffer\n"); return (NULL); } @@ -1169,7 +1179,7 @@ } void -e1000g_free_rx_sw_packet(PRX_SW_PACKET packet) +e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet) { dma_buffer_t *rx_buf; @@ -1200,13 +1210,13 @@ packet->dma_type = USE_NONE; - kmem_free(packet, sizeof (RX_SW_PACKET)); + kmem_free(packet, sizeof (rx_sw_packet_t)); } static void e1000g_free_rx_packets(e1000g_rx_ring_t *rx_ring) { - PRX_SW_PACKET packet, next_packet, free_list; + p_rx_sw_packet_t packet, next_packet, free_list; rw_enter(&e1000g_rx_detach_lock, RW_WRITER); @@ -1215,10 +1225,12 @@ for (; packet != NULL; packet = next_packet) { next_packet = packet->next; - if (packet->flag & E1000G_RX_SW_SENDUP) { + if (packet->flag == E1000G_RX_SW_SENDUP) { + rx_ring->pending_count++; e1000g_mblks_pending++; - packet->flag |= E1000G_RX_SW_DETACHED; - packet->next = NULL; + packet->flag = E1000G_RX_SW_STOP; + packet->next = rx_ring->pending_list; + rx_ring->pending_list = packet; } else { packet->next = free_list; free_list = packet; @@ -1242,13 +1254,13 @@ { int j; struct e1000g *Adapter; - PTX_SW_PACKET packet; + p_tx_sw_packet_t packet; dma_buffer_t *tx_buf; Adapter = tx_ring->adapter; for (j = 0, packet = tx_ring->packet_area; - j < Adapter->NumTxSwPacket; j++, packet++) { + j < Adapter->tx_freelist_num; j++, packet++) { if (packet == NULL) break; @@ -1303,50 +1315,14 @@ } /* - * ********************************************************************** - * Name: e1000g_release_dma_resources * - * * - * Description: * - * This function release any pending buffers. that has been * - * previously allocated * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * * - * * - * ********************************************************************** + * e1000g_release_dma_resources - release allocated DMA resources + * + * This function releases any pending buffers that has been + * previously allocated */ void -e1000g_release_dma_resources(register struct e1000g *Adapter) +e1000g_release_dma_resources(struct e1000g *Adapter) { - e1000g_tx_ring_t *tx_ring; - e1000g_rx_ring_t *rx_ring; - - tx_ring = Adapter->tx_ring; - rx_ring = Adapter->rx_ring; - - /* - * Release all the handles, memory and DMA resources that are - * allocated for the transmit buffer descriptors. - */ - e1000g_free_tx_descriptors(tx_ring); - - /* - * Release all the handles, memory and DMA resources that are - * allocated for the receive buffer descriptors. - */ - e1000g_free_rx_descriptors(rx_ring); - - /* - * Free Tx packet resources - */ - e1000g_free_tx_packets(tx_ring); - - /* - * TX resources done, now free RX resources - */ - e1000g_free_rx_packets(rx_ring); + e1000g_free_descriptors(Adapter); + e1000g_free_packets(Adapter); }
--- a/usr/src/uts/common/io/e1000g/e1000g_debug.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_debug.c Tue Aug 21 00:30:10 2007 -0700 @@ -29,15 +29,10 @@ * ********************************************************************** * * * Module Name: * - * e1000g_debug.c * + * e1000g_debug.c * * * * Abstract: * - * * - * This driver runs on the following hardware: * - * - Wiseman based PCI gigabit ethernet adapters * - * * - * Environment: * - * Kernel Mode - * + * This module includes the debug routines * * * * ********************************************************************** */ @@ -50,23 +45,69 @@ #define _SYS_VARARGS_H #endif +#include "e1000g_debug.h" #include "e1000g_sw.h" -#include "e1000g_debug.h" + +#ifdef E1000G_DEBUG +int e1000g_debug = E1000G_WARN_LEVEL; +#endif +int e1000g_log_mode = E1000G_LOG_PRINT; void -e1000g_log(struct e1000g *Adapter, int level, char *fmt, ...) +e1000g_log(void *instance, int level, char *fmt, ...) { + struct e1000g *Adapter = (struct e1000g *)instance; auto char name[NAMELEN]; auto char buf[BUFSZ]; va_list ap; + switch (level) { +#ifdef E1000G_DEBUG + case E1000G_VERBOSE_LEVEL: /* 16 or 0x010 */ + if (e1000g_debug < E1000G_VERBOSE_LEVEL) + return; + level = CE_CONT; + break; + + case E1000G_TRACE_LEVEL: /* 8 or 0x008 */ + if (e1000g_debug < E1000G_TRACE_LEVEL) + return; + level = CE_CONT; + break; + + case E1000G_INFO_LEVEL: /* 4 or 0x004 */ + if (e1000g_debug < E1000G_INFO_LEVEL) + return; + level = CE_CONT; + break; + + case E1000G_WARN_LEVEL: /* 2 or 0x002 */ + if (e1000g_debug < E1000G_WARN_LEVEL) + return; + level = CE_CONT; + break; + + case E1000G_ERRS_LEVEL: /* 1 or 0x001 */ + level = CE_CONT; + break; +#else + case CE_CONT: + case CE_NOTE: + case CE_WARN: + case CE_PANIC: + break; +#endif + default: + level = CE_CONT; + break; + } + if (Adapter != NULL) { (void) sprintf(name, "%s - e1000g[%d] ", ddi_get_name(Adapter->dip), ddi_get_instance(Adapter->dip)); } else { (void) sprintf(name, "e1000g"); } -#ifdef GCC /* * va_start uses built in macro __builtin_va_alist from the * compiler libs which requires compiler system to have @@ -92,111 +133,15 @@ * Using GNU gcc compiler it doesn't expand to va_start.... */ va_start(ap, fmt); -#else - va_start(ap, fmt); -#endif /* GCC */ (void) vsprintf(buf, fmt, ap); va_end(ap); - switch (level) { - case CE_CONT: - case CE_NOTE: - case CE_WARN: - case CE_PANIC: - if (e1000g_display_only == 1 && e1000g_print_only == 1) { - cmn_err(level, "%s: %s", name, buf); - break; - } - if (e1000g_display_only == 1) { - cmn_err(level, "^%s: %s", name, buf); - break; - } - if (e1000g_print_only == 1) { - cmn_err(level, "!%s: %s", name, buf); - break; - } - /* - * if they are not set properly then do both - */ + if ((e1000g_log_mode & E1000G_LOG_ALL) == E1000G_LOG_ALL) cmn_err(level, "%s: %s", name, buf); - break; - -#ifdef e1000g_DEBUG - case e1000g_DDI_LEVEL: /* 256 or 0x100 */ - if (e1000g_debug != e1000g_DDI_LEVEL) - break; - - case e1000g_INT_LEVEL: /* 128 or 0x080 */ - if ((e1000g_debug != e1000g_INT_LEVEL) && - (e1000g_debug < e1000g_INT_LEVEL)) - break; - - case e1000g_SEND_LEVEL: /* 64 or 0x040 */ - if ((e1000g_debug != e1000g_SEND_LEVEL) && - (e1000g_debug < e1000g_SEND_LEVEL)) - break; - - case e1000g_RECV_LEVEL: /* 32 or 0x020 */ - if ((e1000g_debug != e1000g_RECV_LEVEL) && - (e1000g_debug < e1000g_RECV_LEVEL)) - break; - - case e1000g_CALLTRACE_LEVEL: /* 8 or 0x008 */ - if ((e1000g_debug != e1000g_CALLTRACE_LEVEL) && - (e1000g_debug < e1000g_CALLTRACE_LEVEL)) - break; - - case e1000g_INFO_LEVEL: /* 4 or 0x004 */ - if ((e1000g_debug != e1000g_INFO_LEVEL) && - (e1000g_debug < e1000g_INFO_LEVEL)) - break; - - case e1000g_VERBOSE_LEVEL: /* 16 or 0x010 */ -#endif - default: - if (e1000g_display_only == 1 && e1000g_print_only == 1) { - cmn_err(CE_CONT, "%s:\t%s", name, buf); - break; - } - - if (e1000g_display_only == 1) { - cmn_err(CE_CONT, "^%s:\t%s", name, buf); - break; - } - - if (e1000g_print_only == 1) { - cmn_err(CE_CONT, "!%s:\t%s", name, buf); - break; - } - - /* - * if they are not set properly then do both - */ - cmn_err(CE_CONT, "%s:\t%s", name, buf); - break; - } + else if (e1000g_log_mode & E1000G_LOG_DISPLAY) + cmn_err(level, "^%s: %s", name, buf); + else if (e1000g_log_mode & E1000G_LOG_PRINT) + cmn_err(level, "!%s: %s", name, buf); + else /* if they are not set properly then do both */ + cmn_err(level, "%s: %s", name, buf); } - -void -e1000g_log_hw(char *msg, void *cptr, int length) -{ - int i = 0, j; - char buf[BUFSZ]; - char *cp = cptr; - - bzero(buf, BUFSZ); - for (i = 0; i < length; i++) { - /* - * make sure there is room for longest %x (i.e. 8 for a - * negative number) plus space (1) plus zero (1) - */ - if ((j = strlen(buf)) >= (BUFSZ - 10)) { - buf[BUFSZ - 2] = '>'; - buf[BUFSZ - 1] = 0; - break; - } - - (void) sprintf(&buf[j], "%x ", cp[i]); - } - cmn_err(CE_CONT, "^%s: %s\n", msg, buf); -}
--- a/usr/src/uts/common/io/e1000g/e1000g_debug.h Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_debug.h Tue Aug 21 00:30:10 2007 -0700 @@ -33,23 +33,6 @@ #endif /* - * ********************************************************************** - * * - * Module Name: * - * e1000g_debug.h * - * * - * Abstract: * - * * - * This driver runs on the following hardware: * - * - Wiseman based PCI gigabit ethernet adapters * - * * - * Environment: * - * Kernel Mode - * - * * - * ********************************************************************** - */ - -/* * Debug message control * Debug Levels: * 0x000 - (0) no messages @@ -58,19 +41,9 @@ * 0x004 - (4) Information * 0x008 - (8) Subroutine calls and control flow * 0x010 - (16) I/O Data (verbose!) - * Speacialised Debug Levels: - * 0x020 - (32) Receive Debug Info - * 0x040 - (64) Send Debug Info - * 0x080 - (128) Interrupt Debug Info - * 0x100 - (256) DDI Debug Info * Variables can be set with entries in the /etc/system file with - * "set e1000g:e1000g_debug=<value>" - * "set e1000g:e1000g_debug_hw=<value>" - * "set e1000g:e1000g_display_only=<value>" - * "set e1000g:e1000g_print_only=<value>" - * Alternatively, you can use adb to set variables and debug as - * follows: - * # adb -kw /dev/ksyms /dev/mem + * "set e1000g:e1000g_debug=<value>" + * "set e1000g:e1000g_log_mode=<value>" * The /etc/system file is read only once at boot time, if you change * it you must reboot for the change to take effect. * @@ -78,68 +51,74 @@ * enables other debugging code as ASSERT statements... */ -#ifdef e1000g_DEBUG - -static int e1000g_debug = DEFAULTDEBUGLEVEL; -static int e1000g_debug_hw = 1; +#ifdef DEBUG +#define E1000G_DEBUG +#endif -#define e1000g_ERRS_LEVEL 0x001 /* (1) Errors */ -#define e1000g_WARN_LEVEL 0x002 /* (2) Warnings */ -#define e1000g_INFO_LEVEL 0x004 /* (4) Information */ -#define e1000g_CALLTRACE_LEVEL 0x008 /* (8) Subroutine calls and */ - /* control flow */ -#define e1000g_VERBOSE_LEVEL 0x010 /* (16) I/O Data (verbose!) */ -#define e1000g_RECV_LEVEL 0x020 /* (32) Receive Debug Info */ -#define e1000g_SEND_LEVEL 0x040 /* (64) Send Debug Info */ -#define e1000g_INT_LEVEL 0x080 /* (128) Interrupt Debug Info */ -#define e1000g_DDI_LEVEL 0x100 /* (256) DDI Debug Info */ +/* + * By default it will print only to log + */ +#define E1000G_LOG_DISPLAY 0x1 +#define E1000G_LOG_PRINT 0x2 +#define E1000G_LOG_ALL 0x3 -#define e1000g_DEBUGLOG_0(Adapter, Level, fmt) \ +#ifdef E1000G_DEBUG + +#define E1000G_ERRS_LEVEL 0x001 /* (1) Errors */ +#define E1000G_WARN_LEVEL 0x002 /* (2) Warnings */ +#define E1000G_INFO_LEVEL 0x004 /* (4) Information */ +#define E1000G_TRACE_LEVEL 0x008 /* (8) Subroutine calls */ +#define E1000G_VERBOSE_LEVEL 0x010 /* (16) I/O Data (verbose!) */ + +#define E1000G_DEBUGLOG_0(Adapter, Level, fmt) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt)) -#define e1000g_DEBUGLOG_1(Adapter, Level, fmt, d1) \ +#define E1000G_DEBUGLOG_1(Adapter, Level, fmt, d1) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt), (d1)) -#define e1000g_DEBUGLOG_2(Adapter, Level, fmt, d1, d2) \ +#define E1000G_DEBUGLOG_2(Adapter, Level, fmt, d1, d2) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt), (d1), (d2)) -#define e1000g_DEBUGLOG_3(Adapter, Level, fmt, d1, d2, d3) \ +#define E1000G_DEBUGLOG_3(Adapter, Level, fmt, d1, d2, d3) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt), (d1),\ (d2), (d3)) -#define e1000g_DEBUGLOG_4(Adapter, Level, fmt, d1, d2, d3, d4) \ +#define E1000G_DEBUGLOG_4(Adapter, Level, fmt, d1, d2, d3, d4) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt), (d1),\ (d2), (d3), (d4)) -#define e1000g_DEBUGLOG_5(Adapter, Level, fmt, d1, d2, d3, d4, d5) \ +#define E1000G_DEBUGLOG_5(Adapter, Level, fmt, d1, d2, d3, d4, d5) \ if (e1000g_debug) e1000g_log((Adapter), (Level), (fmt), (d1),\ (d2), (d3), (d4), (d5)) -#define e1000g_HW_DEBUGLOG if (e1000g_debug_hw) e1000g_log_hw +#define E1000G_DEBUG_STAT_COND(val, cond) if (cond) (val)++; +#define E1000G_DEBUG_STAT(val) (val)++; #else -static int e1000g_debug = 0; -static int e1000g_debug_hw = 0; +#define E1000G_DEBUGLOG_0(Adapter, Level, fmt) +#define E1000G_DEBUGLOG_1(Adapter, Level, fmt, d1) +#define E1000G_DEBUGLOG_2(Adapter, Level, fmt, d1, d2) +#define E1000G_DEBUGLOG_3(Adapter, Level, fmt, d1, d2, d3) +#define E1000G_DEBUGLOG_4(Adapter, Level, fmt, d1, d2, d3, d4) +#define E1000G_DEBUGLOG_5(Adapter, Level, fmt, d1, d2, d3, d4, d5) -#define e1000g_DEBUGLOG_0(Adapter, Level, fmt) -#define e1000g_DEBUGLOG_1(Adapter, Level, fmt, d1) -#define e1000g_DEBUGLOG_2(Adapter, Level, fmt, d1, d2) -#define e1000g_DEBUGLOG_3(Adapter, Level, fmt, d1, d2, d3) -#define e1000g_DEBUGLOG_4(Adapter, Level, fmt, d1, d2, d3, d4) -#define e1000g_DEBUGLOG_5(Adapter, Level, fmt, d1, d2, d3, d4, d5) -#define e1000g_HW_DEBUGLOG +#define E1000G_DEBUG_STAT_COND(val, cond) +#define E1000G_DEBUG_STAT(val) -#endif /* e1000g_DEBUG */ +#endif /* E1000G_DEBUG */ #define NAMELEN 31 #define BUFSZ 256 -void e1000g_log(struct e1000g *Adapter, int level, char *fmt, ...); -void e1000g_log_hw(char *msg, void *cptr, int length); +#define E1000G_STAT(val) (val)++; + +void e1000g_log(void *instance, int level, char *fmt, ...); -static int e1000g_display_only = DEFAULTDISPLAYONLY; -static int e1000g_print_only = DEFAULTPRINTONLY; +#ifdef E1000G_DEBUG +extern int e1000g_debug; +#endif +extern int e1000g_log_mode; #ifdef __cplusplus }
--- a/usr/src/uts/common/io/e1000g/e1000g_main.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_main.c Tue Aug 21 00:30:10 2007 -0700 @@ -32,15 +32,11 @@ * e1000g_main.c * * * * Abstract: * - * This file contains the interface routine for the solaris OS. * - * It has all DDI entry point routines and GLD entry point * - * routines. * - * This file also contains routines that takes care of initialization * - * uninit routine and interrupt routine * + * This file contains the interface routines for the solaris OS. * + * It has all DDI entry point routines and GLD entry point routines. * * * - * * - * Environment: * - * Kernel Mode - * + * This file also contains routines that take care of initialization * + * uninit routine and interrupt routine. * * * * ********************************************************************** */ @@ -53,28 +49,28 @@ #define E1000_RX_INTPT_TIME 128 #define E1000_RX_PKT_CNT 8 -static char ident[] = "Intel PRO/1000 Ethernet 5.1.11"; +static char ident[] = "Intel PRO/1000 Ethernet 5.2.0"; static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; -static char e1000g_version[] = "Driver Ver. 5.1.11"; +static char e1000g_version[] = "Driver Ver. 5.2.0"; /* * Proto types for DDI entry points */ -static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); -static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); +static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); +static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); /* * init and intr routines prototype */ -static int e1000g_resume(dev_info_t *devinfo); -static int e1000g_suspend(dev_info_t *devinfo); +static int e1000g_resume(dev_info_t *); +static int e1000g_suspend(dev_info_t *); static uint_t e1000g_intr_pciexpress(caddr_t); static uint_t e1000g_intr(caddr_t); static void e1000g_intr_work(struct e1000g *, uint32_t); #pragma inline(e1000g_intr_work) static int e1000g_init(struct e1000g *); -static int e1000g_start(struct e1000g *); -static void e1000g_stop(struct e1000g *); +static int e1000g_start(struct e1000g *, boolean_t); +static void e1000g_stop(struct e1000g *, boolean_t); static int e1000g_m_start(void *); static void e1000g_m_stop(void *); static int e1000g_m_promisc(void *, boolean_t); @@ -88,59 +84,63 @@ static void e1000g_m_blank(void *, time_t, uint32_t); static void e1000g_m_resources(void *); static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); -static void e1000g_init_locks(struct e1000g *Adapter); -static void e1000g_destroy_locks(struct e1000g *Adapter); -static int e1000g_set_driver_params(struct e1000g *Adapter); -static int e1000g_register_mac(struct e1000g *Adapter); -static boolean_t e1000g_rx_drain(struct e1000g *Adapter); -static boolean_t e1000g_tx_drain(struct e1000g *Adapter); -static void e1000g_init_unicst(struct e1000g *Adapter); +static void e1000g_init_locks(struct e1000g *); +static void e1000g_destroy_locks(struct e1000g *); +static int e1000g_identify_hardware(struct e1000g *); +static int e1000g_regs_map(struct e1000g *); +static int e1000g_set_driver_params(struct e1000g *); +static int e1000g_register_mac(struct e1000g *); +static boolean_t e1000g_rx_drain(struct e1000g *); +static boolean_t e1000g_tx_drain(struct e1000g *); +static void e1000g_init_unicst(struct e1000g *); static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); /* * Local routines */ -static void e1000g_tx_drop(struct e1000g *Adapter); +static void e1000g_tx_clean(struct e1000g *); +static void e1000g_rx_clean(struct e1000g *); static void e1000g_link_timer(void *); -static void e1000g_LocalTimer(void *); +static void e1000g_local_timer(void *); static boolean_t e1000g_link_check(struct e1000g *); static boolean_t e1000g_stall_check(struct e1000g *); static void e1000g_smartspeed(struct e1000g *); -static void e1000g_getparam(struct e1000g *Adapter); -static int e1000g_getprop(struct e1000g *, char *, int, int, int); -static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, - char *a2, char *a3, char *a4, char *a5, char *a6); -static void enable_timeout(struct e1000g *Adapter); -static void disable_timeout(struct e1000g *Adapter); -static void start_timeout(struct e1000g *Adapter); -static void restart_timeout(struct e1000g *Adapter); -static void stop_timeout(struct e1000g *Adapter); -static void e1000g_force_speed_duplex(struct e1000g *Adapter); -static void e1000g_get_max_frame_size(struct e1000g *Adapter); -static boolean_t is_valid_mac_addr(uint8_t *mac_addr); +static void e1000g_get_conf(struct e1000g *); +static int e1000g_get_prop(struct e1000g *, char *, int, int, int); +static void enable_watchdog_timer(struct e1000g *); +static void disable_watchdog_timer(struct e1000g *); +static void start_watchdog_timer(struct e1000g *); +static void restart_watchdog_timer(struct e1000g *); +static void stop_watchdog_timer(struct e1000g *); +static void stop_link_timer(struct e1000g *); +static void stop_82547_timer(e1000g_tx_ring_t *); +static void e1000g_force_speed_duplex(struct e1000g *); +static void e1000g_get_max_frame_size(struct e1000g *); +static boolean_t is_valid_mac_addr(uint8_t *); static void e1000g_unattach(dev_info_t *, struct e1000g *); -static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); -static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); -static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); -static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); -static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, - struct iocblk *iocp, mblk_t *mp); -static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, - struct iocblk *iocp, mblk_t *mp); -static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, - uint32_t mode); -static void e1000g_set_internal_loopback(struct e1000g *Adapter); -static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); -static void e1000g_set_external_loopback_100(struct e1000g *Adapter); -static void e1000g_set_external_loopback_10(struct e1000g *Adapter); -static int e1000g_add_intrs(struct e1000g *Adapter); -static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); -static int e1000g_rem_intrs(struct e1000g *Adapter); -static int e1000g_enable_intrs(struct e1000g *Adapter); -static int e1000g_disable_intrs(struct e1000g *Adapter); -static boolean_t e1000g_link_up(struct e1000g *Adapter); +#ifdef E1000G_DEBUG +static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); +static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); +static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); +static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); +static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, + struct iocblk *, mblk_t *); +#endif +static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, + struct iocblk *, mblk_t *); +static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); +static void e1000g_set_internal_loopback(struct e1000g *); +static void e1000g_set_external_loopback_1000(struct e1000g *); +static void e1000g_set_external_loopback_100(struct e1000g *); +static void e1000g_set_external_loopback_10(struct e1000g *); +static int e1000g_add_intrs(struct e1000g *); +static int e1000g_intr_add(struct e1000g *, int); +static int e1000g_rem_intrs(struct e1000g *); +static int e1000g_enable_intrs(struct e1000g *); +static int e1000g_disable_intrs(struct e1000g *); +static boolean_t e1000g_link_up(struct e1000g *); #ifdef __sparc -static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); +static boolean_t e1000g_find_mac_address(struct e1000g *); #endif static struct cb_ops cb_ws_ops = { @@ -170,8 +170,8 @@ NULL, /* devo_getinfo */ nulldev, /* devo_identify */ nulldev, /* devo_probe */ - e1000gattach, /* devo_attach */ - e1000gdetach, /* devo_detach */ + e1000g_attach, /* devo_attach */ + e1000g_detach, /* devo_detach */ nodev, /* devo_reset */ &cb_ws_ops, /* devo_cb_ops */ NULL, /* devo_bus_ops */ @@ -188,10 +188,8 @@ MODREV_1, &modldrv, NULL }; -/* - * DMA access attributes <Little Endian Card> - */ -static ddi_device_acc_attr_t accattr1 = { +/* Access attributes for register mapping */ +static ddi_device_acc_attr_t e1000g_regs_acc_attr = { DDI_DEVICE_ATTR_V0, DDI_STRUCTURE_LE_ACC, DDI_STRICTORDER_ACC, @@ -265,23 +263,7 @@ */ /* - * ********************************************************************** - * Name: _init * - * * - * Description: * - * Initializes a loadable module. It is called before * - * any other routine in a loadable module. * - * All global locks are intialised here and it returns the retun * - * value from mod_install() * - * This is mandotary function for the driver * - * Parameter Passed: * - * None * - * Return Value: * - * 0 on success * - * Functions called * - * mod_install() (system call) * - * * - * ********************************************************************** + * _init - module initialization */ int _init(void) @@ -301,23 +283,7 @@ } /* - * ********************************************************************** - * Name: _fini * - * * - * Description: * - * Prepares a loadable module for unloading. It is * - * called when the system wants to unload a module. * - * This is mandotary function for the driver * - * Parameter Passed: * - * None * - * Return Value: * - * 0 on success * - * Functions called * - * mod_remove() (system call) * - * * - * * - * * - * ********************************************************************** + * _fini - module finalization */ int _fini(void) @@ -360,21 +326,7 @@ } /* - * ********************************************************************** - * Name: _info * - * * - * Description: * - * Returns information about a loadable module. * - * This is mandotary function for the driver * - * Parameter Passed: * - * module info structure * - * Return Value: * - * 0 on success * - * Functions called * - * mod_info() (system call) * - * * - * * - * ********************************************************************** + * _info - module information */ int _info(struct modinfo *modinfop) @@ -383,53 +335,32 @@ } /* - * Interface exists: make available by filling in network interface - * record. System will initialize the interface when it is ready - * to accept packets. - */ - -/* - * ********************************************************************** - * Name: e1000gattach * - * * - * Description: * - * This function is the device-specific initialization * - * entry point. This entry point is required and must be writ- * - * ten. The DDI_ATTACH command must be provided in the attach * - * entry point. When attach() is called with cmd set to DDI_ATTACH, * - * all normal kernel services (such as kmem_alloc(9F)) are * - * available for use by the driver. Device interrupts are not * - * blocked when attaching a device to the system. * - * * - * The attach() function will be called once for each instance * - * of the device on the system with cmd set to DDI_ATTACH. * - * Until attach() succeeds, the only driver entry points which * - * may be called are open(9E) and getinfo(9E). * - * * - * * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called * - * * - * * - * ********************************************************************** + * e1000g_attach - driver attach + * + * This function is the device-specific initialization entry + * point. This entry point is required and must be written. + * The DDI_ATTACH command must be provided in the attach entry + * point. When attach() is called with cmd set to DDI_ATTACH, + * all normal kernel services (such as kmem_alloc(9F)) are + * available for use by the driver. + * + * The attach() function will be called once for each instance + * of the device on the system with cmd set to DDI_ATTACH. + * Until attach() succeeds, the only driver entry points which + * may be called are open(9E) and getinfo(9E). */ static int -e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) +e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) { struct e1000g *Adapter; struct e1000_hw *hw; - ddi_acc_handle_t handle; - off_t mem_size; + struct e1000g_osdep *osdep; int instance; switch (cmd) { default: e1000g_log(NULL, CE_WARN, - "Unsupported command send to e1000gattach... "); + "Unsupported command send to e1000g_attach... "); return (DDI_FAILURE); case DDI_RESUME: @@ -451,10 +382,15 @@ (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); Adapter->dip = devinfo; - Adapter->AdapterInstance = instance; + Adapter->instance = instance; Adapter->tx_ring->adapter = Adapter; Adapter->rx_ring->adapter = Adapter; + hw = &Adapter->shared; + osdep = &Adapter->osdep; + hw->back = osdep; + osdep->adapter = Adapter; + ddi_set_driver_private(devinfo, (caddr_t)Adapter); if (e1000g_force_detach) { @@ -476,55 +412,31 @@ rw_exit(&e1000g_rx_detach_lock); } - hw = &Adapter->Shared; + /* + * PCI Configure + */ + if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { + e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); + goto attach_fail; + } + Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; + + /* + * Setup hardware + */ + if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { + e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); + goto attach_fail; + } /* * Map in the device registers. - * - * first get the size of device register to be mapped. The - * second parameter is the register we are interested. I our - * wiseman 0 is for config registers and 1 is for memory mapped - * registers Mem size should have memory mapped region size */ - ddi_dev_regsize(devinfo, 1, /* register of interest */ - (off_t *)&mem_size); - - if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ - (caddr_t *)&hw->hw_addr, - 0, mem_size, &accattr1, &Adapter->E1000_handle)) - != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); + if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { + e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); goto attach_fail; } - Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; - - Adapter->osdep.E1000_handle = Adapter->E1000_handle; - hw->back = &Adapter->osdep; - - /* - * PCI Configure - */ - if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, - "PCI configuration could not be read."); - goto attach_fail; - } - - Adapter->handle = handle; - Adapter->osdep.handle = handle; - - hw->vendor_id = - pci_config_get16(handle, PCI_CONF_VENID); - hw->device_id = - pci_config_get16(handle, PCI_CONF_DEVID); - hw->revision_id = - pci_config_get8(handle, PCI_CONF_REVID); - hw->subsystem_id = - pci_config_get16(handle, PCI_CONF_SUBSYSID); - hw->subsystem_vendor_id = - pci_config_get16(handle, PCI_CONF_SUBVENID); - - Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; + Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; /* * Initialize driver parameters @@ -532,7 +444,7 @@ if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { goto attach_fail; } - Adapter->attach_progress |= ATTACH_PROGRESS_PROP; + Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; /* * Initialize interrupts @@ -541,8 +453,7 @@ e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); goto attach_fail; } - Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; - Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; + Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; /* * Initialize mutex's for this device. @@ -553,33 +464,25 @@ e1000g_init_locks(Adapter); Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; + Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; if (ddi_intr_add_softint(devinfo, &Adapter->tx_softint_handle, Adapter->tx_softint_pri, - e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { + e1000g_tx_softint_worker, (caddr_t)Adapter) != DDI_SUCCESS) { e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); goto attach_fail; } - Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; + Adapter->attach_progress |= ATTACH_PROGRESS_SOFT_INTR; /* * Initialize Driver Counters */ - if (InitStatsCounters(Adapter) != DDI_SUCCESS) { + if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { e1000g_log(Adapter, CE_WARN, "Init stats failed"); goto attach_fail; } Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; /* - * Allocate dma resources for descriptors and buffers - */ - if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); - goto attach_fail; - } - Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; - - /* * Initialize chip hardware and software structures */ if (e1000g_init(Adapter) != DDI_SUCCESS) { @@ -592,7 +495,7 @@ * Initialize NDD parameters */ if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, "Init NDD failed"); + e1000g_log(Adapter, CE_WARN, "Init ndd failed"); goto attach_fail; } Adapter->attach_progress |= ATTACH_PROGRESS_NDD; @@ -604,7 +507,7 @@ e1000g_log(Adapter, CE_WARN, "Register MAC failed"); goto attach_fail; } - Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; + Adapter->attach_progress |= ATTACH_PROGRESS_MAC; /* * Now that mutex locks are initialized, and the chip is also @@ -614,7 +517,7 @@ e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); goto attach_fail; } - Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; + Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); @@ -628,84 +531,157 @@ static int e1000g_register_mac(struct e1000g *Adapter) { - struct e1000_hw *hw = &Adapter->Shared; + struct e1000_hw *hw = &Adapter->shared; mac_register_t *mac; int err; if ((mac = mac_alloc(MAC_VERSION)) == NULL) return (DDI_FAILURE); + mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; mac->m_driver = Adapter; mac->m_dip = Adapter->dip; - mac->m_src_addr = hw->mac_addr; + mac->m_src_addr = hw->mac.addr; mac->m_callbacks = &e1000g_m_callbacks; mac->m_min_sdu = 0; mac->m_max_sdu = - (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? - hw->max_frame_size - 256 : - (hw->max_frame_size != ETHERMAX) ? - hw->max_frame_size - 24 : ETHERMTU; + (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) ? + hw->mac.max_frame_size - 256 : + (hw->mac.max_frame_size != ETHERMAX) ? + hw->mac.max_frame_size - 24 : ETHERMTU; + err = mac_register(mac, &Adapter->mh); mac_free(mac); + return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); } static int +e1000g_identify_hardware(struct e1000g *Adapter) +{ + struct e1000_hw *hw = &Adapter->shared; + struct e1000g_osdep *osdep = &Adapter->osdep; + + /* Get the device id */ + hw->vendor_id = + pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); + hw->device_id = + pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); + hw->revision_id = + pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); + hw->subsystem_device_id = + pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); + hw->subsystem_vendor_id = + pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); + + if (e1000_set_mac_type(hw) != E1000_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, + "MAC type could not be set properly."); + return (DDI_FAILURE); + } + + return (DDI_SUCCESS); +} + +static int +e1000g_regs_map(struct e1000g *Adapter) +{ + dev_info_t *devinfo = Adapter->dip; + struct e1000_hw *hw = &Adapter->shared; + struct e1000g_osdep *osdep = &Adapter->osdep; + off_t mem_size; + + /* + * first get the size of device register to be mapped. The + * second parameter is the register we are interested. I our + * wiseman 0 is for config registers and 1 is for memory mapped + * registers Mem size should have memory mapped region size + */ + if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "ddi_dev_regsize for registers failed"); + return (DDI_FAILURE); + } + + if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ + (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, + &osdep->reg_handle)) != DDI_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "ddi_regs_map_setup for registers failed"); + goto regs_map_fail; + } + + /* ICH needs to map flash memory */ + if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { + /* get flash size */ + if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, + &mem_size) != DDI_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "ddi_dev_regsize for ICH flash failed"); + goto regs_map_fail; + } + + /* map flash in */ + if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, + (caddr_t *)&hw->flash_address, 0, + mem_size, &e1000g_regs_acc_attr, + &osdep->ich_flash_handle) != DDI_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "ddi_regs_map_setup for ICH flash failed"); + goto regs_map_fail; + } + } + + return (DDI_SUCCESS); + +regs_map_fail: + if (osdep->reg_handle != NULL) + ddi_regs_map_free(&osdep->reg_handle); + + return (DDI_FAILURE); +} + +static int e1000g_set_driver_params(struct e1000g *Adapter) { - dev_info_t *devinfo; - ddi_acc_handle_t handle; struct e1000_hw *hw; - uint32_t mem_bar, io_bar; + e1000g_tx_ring_t *tx_ring; + uint32_t mem_bar, io_bar, bar64; #ifdef __sparc + dev_info_t *devinfo = Adapter->dip; ulong_t iommu_pagesize; #endif - devinfo = Adapter->dip; - handle = Adapter->handle; - hw = &Adapter->Shared; - - /* Set Mac Type */ - if (e1000_set_mac_type(hw) != 0) { - e1000g_log(Adapter, CE_WARN, - "Could not identify hardware"); + hw = &Adapter->shared; + + /* Set MAC type and initialize hardware functions */ + if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "Could not setup hardware functions"); return (DDI_FAILURE); } - /* ich8 needs to map flash memory */ - if (hw->mac_type == e1000_ich8lan) { - /* get flash size */ - if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, - &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, - "ddi_dev_regsize for ich8 flash failed"); - return (DDI_FAILURE); - } - - /* map flash in */ - if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, - &Adapter->osdep.ich_flash_base, 0, - Adapter->osdep.ich_flash_size, - &accattr1, - &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, - "ddi_regs_map_setup for for ich8 flash failed"); - return (DDI_FAILURE); - } + /* Get bus information */ + if (e1000_get_bus_info(hw) != E1000_SUCCESS) { + E1000G_DEBUGLOG_0(Adapter, CE_WARN, + "Could not get bus information"); + return (DDI_FAILURE); } /* get mem_base addr */ - mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); - Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; + mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); + bar64 = mem_bar & PCI_BASE_TYPE_ALL; /* get io_base addr */ - if (hw->mac_type >= e1000_82544) { - if (Adapter->bar64) { + if (hw->mac.type >= e1000_82544) { + if (bar64) { /* IO BAR is different for 64 bit BAR mode */ - io_bar = pci_config_get32(handle, PCI_CONF_BASE4); + io_bar = pci_config_get32(Adapter->osdep.cfg_handle, + PCI_CONF_BASE4); } else { /* normal 32-bit BAR mode */ - io_bar = pci_config_get32(handle, PCI_CONF_BASE2); + io_bar = pci_config_get32(Adapter->osdep.cfg_handle, + PCI_CONF_BASE2); } hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; } else { @@ -713,27 +689,25 @@ hw->io_base = 0x0; } - e1000_read_pci_cfg(hw, - PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); - - /* Set the wait_autoneg_complete flag to B_FALSE */ - hw->wait_autoneg_complete = B_FALSE; + e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); + + hw->mac.autoneg_failed = B_TRUE; + + /* Set the wait_for_link flag to B_FALSE */ + hw->phy.wait_for_link = B_FALSE; /* Adaptive IFS related changes */ - hw->adaptive_ifs = B_TRUE; - - /* set phy init script revision */ - if ((hw->mac_type == e1000_82547) || - (hw->mac_type == e1000_82541) || - (hw->mac_type == e1000_82547_rev_2) || - (hw->mac_type == e1000_82541_rev_2)) - hw->phy_init_script = 1; - - /* Enable the TTL workaround for TnT: DCR 49 */ - hw->ttl_wa_activation = 1; - - if (hw->mac_type == e1000_82571) - hw->laa_is_present = B_TRUE; + hw->mac.adaptive_ifs = B_TRUE; + + /* Enable phy init script for IGP phy of 82541/82547 */ + if ((hw->mac.type == e1000_82547) || + (hw->mac.type == e1000_82541) || + (hw->mac.type == e1000_82547_rev_2) || + (hw->mac.type == e1000_82541_rev_2)) + e1000_init_script_state_82541(hw, B_TRUE); + + /* Enable the TTL workaround for 82541/82547 */ + e1000_set_ttl_workaround_state_82541(hw, B_TRUE); #ifdef __sparc Adapter->strip_crc = B_TRUE; @@ -742,14 +716,16 @@ #endif /* Get conf file properties */ - e1000g_getparam(Adapter); - - hw->forced_speed_duplex = e1000_100_full; - hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; + e1000g_get_conf(Adapter); + + /* Get speed/duplex settings in conf file */ + hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; + hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; e1000g_force_speed_duplex(Adapter); + /* Get Jumbo Frames settings in conf file */ e1000g_get_max_frame_size(Adapter); - hw->min_frame_size = + hw->mac.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; #ifdef __sparc @@ -765,37 +741,38 @@ Adapter->sys_page_sz = iommu_pagesize; } } - Adapter->dvma_page_num = hw->max_frame_size / + Adapter->dvma_page_num = hw->mac.max_frame_size / Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); #endif /* Set Rx/Tx buffer size */ - switch (hw->max_frame_size) { + switch (hw->mac.max_frame_size) { case ETHERMAX: - Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; - Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; + Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; + Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; break; case FRAME_SIZE_UPTO_4K: - Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; - Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; + Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; + Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; break; case FRAME_SIZE_UPTO_8K: - Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; - Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; + Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; + Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; break; - case FRAME_SIZE_UPTO_10K: + case FRAME_SIZE_UPTO_9K: case FRAME_SIZE_UPTO_16K: - Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; - Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; + Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; + Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; break; default: - Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; - Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; + Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; + Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; break; } - Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; - + Adapter->rx_buffer_size += E1000G_IPALIGNPRESERVEROOM; + +#ifndef NO_82542_SUPPORT /* * For Wiseman adapters we have an requirement of having receive * buffers aligned at 256 byte boundary. Since Livengood does not @@ -807,73 +784,60 @@ * aligned...so all wiseman boards to have 256 byte aligned * buffers */ - if (hw->mac_type < e1000_82543) - Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; - else - /* - * For livengood, there is no such Rcv buf alignment - * requirement - */ - Adapter->RcvBufferAlignment = 1; - - /* DmaFairness */ - if (hw->mac_type <= e1000_82543) - hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; + if (hw->mac.type < e1000_82543) + Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; else - hw->dma_fairness = 0; - - /* MasterLatencyTimer */ - Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; - - /* MWIEnable */ - Adapter->MWIEnable = DEFAULTMWIENABLEVAL; - - /* profile jumbo traffic */ - Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; - - e1000_set_media_type(hw); + Adapter->rx_buf_align = 1; +#endif + + /* Master Latency Timer */ + Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; + /* copper options */ if (hw->media_type == e1000_media_type_copper) { - hw->mdix = 0; /* AUTO_ALL_MODES */ - hw->disable_polarity_correction = B_FALSE; - hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ + hw->phy.mdix = 0; /* AUTO_ALL_MODES */ + hw->phy.disable_polarity_correction = B_FALSE; + hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ } + /* The initial link state should be "unknown" */ Adapter->link_state = LINK_STATE_UNKNOWN; + /* Initialize tx parameters */ + Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; + Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; + + tx_ring = Adapter->tx_ring; + tx_ring->recycle_low_water = DEFAULT_TX_RECYCLE_LOW_WATER; + tx_ring->recycle_num = DEFAULT_TX_RECYCLE_NUM; + tx_ring->frags_limit = + (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; + if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) + tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); + + /* Initialize rx parameters */ + Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; + return (DDI_SUCCESS); } /* - * ********************************************************************** - * Name: e1000gdettach * - * * - * Description: * - * The detach() function is the complement of the attach routine. * - * If cmd is set to DDI_DETACH, detach() is used to remove the * - * state associated with a given instance of a device node * - * prior to the removal of that instance from the system. * - * * - * The detach() function will be called once for each instance * - * of the device for which there has been a successful attach() * - * once there are no longer any opens on the device. * - * * - * Interrupts routine are disabled, All memory allocated by this * - * driver are freed. * - * * - * Parameter Passed: * - * devinfo structure, cmd * - * * - * Return Value: * - * DDI_SUCCESS on success * - * * - * Functions called * - * * - * * - * ********************************************************************** + * e1000g_detach - driver detach + * + * The detach() function is the complement of the attach routine. + * If cmd is set to DDI_DETACH, detach() is used to remove the + * state associated with a given instance of a device node + * prior to the removal of that instance from the system. + * + * The detach() function will be called once for each instance + * of the device for which there has been a successful attach() + * once there are no longer any opens on the device. + * + * Interrupts routine are disabled, All memory allocated by this + * driver are freed. */ static int -e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) +e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) { struct e1000g *Adapter; @@ -892,28 +856,20 @@ if (Adapter == NULL) return (DDI_FAILURE); + if (mac_unregister(Adapter->mh) != 0) { + e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); + return (DDI_FAILURE); + } + Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; + if (Adapter->started) - e1000g_stop(Adapter); + e1000g_stop(Adapter, B_TRUE); if (!e1000g_rx_drain(Adapter)) { if (!e1000g_force_detach) return (DDI_FAILURE); } - if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { - e1000g_log(Adapter, CE_WARN, - "Disable DDI interrupts failed"); - return (DDI_FAILURE); - } - Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; - - if (mac_unregister(Adapter->mh) != 0) { - e1000g_log(Adapter, CE_WARN, - "Unregister MAC failed"); - return (DDI_FAILURE); - } - Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; - e1000g_unattach(devinfo, Adapter); return (DDI_SUCCESS); @@ -922,11 +878,11 @@ static void e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) { - if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { + if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { (void) e1000g_disable_intrs(Adapter); } - if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { + if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { (void) mac_unregister(Adapter->mh); } @@ -934,15 +890,15 @@ e1000g_nd_cleanup(Adapter); } - if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { + if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { (void) e1000g_rem_intrs(Adapter); } - if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { + if (Adapter->attach_progress & ATTACH_PROGRESS_SOFT_INTR) { (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); } - if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { + if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { (void) ddi_prop_remove_all(devinfo); } @@ -951,36 +907,28 @@ } if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { - timeout_id_t tid = 0; - - /* Disable the link timer */ - mutex_enter(&Adapter->e1000g_linklock); - tid = Adapter->link_tid; - Adapter->link_tid = 0; - mutex_exit(&Adapter->e1000g_linklock); - - if (tid != 0) - (void) untimeout(tid); - - e1000_reset_hw(&Adapter->Shared); + stop_link_timer(Adapter); + e1000_reset_hw(&Adapter->shared); } - if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { - ddi_regs_map_free(&Adapter->E1000_handle); + if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { + if (Adapter->osdep.reg_handle != NULL) + ddi_regs_map_free(&Adapter->osdep.reg_handle); + if (Adapter->osdep.ich_flash_handle != NULL) + ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); } - if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { - pci_config_teardown(&Adapter->handle); - } - - if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { - e1000g_release_dma_resources(Adapter); + if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { + if (Adapter->osdep.cfg_handle != NULL) + pci_config_teardown(&Adapter->osdep.cfg_handle); } if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { e1000g_destroy_locks(Adapter); } + e1000_remove_device(&Adapter->shared); + kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); /* @@ -998,16 +946,11 @@ rw_init(&Adapter->chip_lock, NULL, RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); - mutex_init(&Adapter->e1000g_linklock, NULL, - MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); - mutex_init(&Adapter->e1000g_timeout_lock, NULL, + mutex_init(&Adapter->link_lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); - mutex_init(&Adapter->TbiCntrMutex, NULL, + mutex_init(&Adapter->watchdog_lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); - mutex_init(&Adapter->tx_msg_chain->lock, NULL, - MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); - tx_ring = Adapter->tx_ring; mutex_init(&tx_ring->tx_lock, NULL, @@ -1016,6 +959,8 @@ MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); mutex_init(&tx_ring->freelist_lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); + mutex_init(&tx_ring->mblks_lock, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); rx_ring = Adapter->rx_ring; @@ -1035,15 +980,14 @@ mutex_destroy(&tx_ring->tx_lock); mutex_destroy(&tx_ring->usedlist_lock); mutex_destroy(&tx_ring->freelist_lock); + mutex_destroy(&tx_ring->mblks_lock); rx_ring = Adapter->rx_ring; mutex_destroy(&rx_ring->rx_lock); mutex_destroy(&rx_ring->freelist_lock); - mutex_destroy(&Adapter->tx_msg_chain->lock); - mutex_destroy(&Adapter->e1000g_linklock); - mutex_destroy(&Adapter->TbiCntrMutex); - mutex_destroy(&Adapter->e1000g_timeout_lock); + mutex_destroy(&Adapter->link_lock); + mutex_destroy(&Adapter->watchdog_lock); rw_destroy(&Adapter->chip_lock); } @@ -1056,7 +1000,7 @@ if (Adapter == NULL) return (DDI_FAILURE); - if (e1000g_start(Adapter)) + if (e1000g_start(Adapter, B_TRUE)) return (DDI_FAILURE); return (DDI_SUCCESS); @@ -1071,7 +1015,7 @@ if (Adapter == NULL) return (DDI_FAILURE); - e1000g_stop(Adapter); + e1000g_stop(Adapter, B_TRUE); return (DDI_SUCCESS); } @@ -1080,35 +1024,30 @@ e1000g_init(struct e1000g *Adapter) { uint32_t pba; - uint32_t ctrl; + uint32_t high_water; struct e1000_hw *hw; clock_t link_timeout; - hw = &Adapter->Shared; + hw = &Adapter->shared; rw_enter(&Adapter->chip_lock, RW_WRITER); - /* Preserve manageability features */ - e1000_check_phy_reset_block(hw); - /* * reset to put the hardware in a known state * before we try to do anything with the eeprom */ (void) e1000_reset_hw(hw); - (void) e1000_init_eeprom_params(hw); - - if (e1000_validate_eeprom_checksum(hw) < 0) { + if (e1000_validate_nvm_checksum(hw) < 0) { /* * Some PCI-E parts fail the first check due to * the link being in sleep state. Call it again, * if it fails a second time its a real issue. */ - if (e1000_validate_eeprom_checksum(hw) < 0) { + if (e1000_validate_nvm_checksum(hw) < 0) { e1000g_log(Adapter, CE_WARN, - "Invalid EEPROM checksum. Please contact " - "the vendor to update the EEPROM."); + "Invalid NVM checksum. Please contact " + "the vendor to update the NVM."); goto init_fail; } } @@ -1133,48 +1072,51 @@ #endif /* check for valid mac address */ - if (!is_valid_mac_addr(hw->mac_addr)) { + if (!is_valid_mac_addr(hw->mac.addr)) { e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); goto init_fail; } - e1000_get_bus_info(hw); + /* Set LAA state for 82571 chipset */ + e1000_set_laa_state_82571(hw, B_TRUE); /* Master Latency Timer implementation */ - if (Adapter->MasterLatencyTimer) { - pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, - Adapter->MasterLatencyTimer); + if (Adapter->master_latency_timer) { + pci_config_put8(Adapter->osdep.cfg_handle, + PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); } - if (hw->mac_type < e1000_82547) { + if (hw->mac.type < e1000_82547) { /* * Total FIFO is 64K */ - if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) + if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ else pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ - } else if (hw->mac_type >= e1000_82571 && - hw->mac_type <= e1000_82572) { + } else if (hw->mac.type >= e1000_82571 && + hw->mac.type <= e1000_82572) { /* * Total FIFO is 48K */ - if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) + if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ else pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ - } else if (hw->mac_type == e1000_ich8lan) { + } else if (hw->mac.type == e1000_ich8lan) { pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ + } else if (hw->mac.type == e1000_ich9lan) { + pba = E1000_PBA_12K; } else { /* * Total FIFO is 40K */ - if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) + if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ else pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ } - E1000_WRITE_REG(hw, PBA, pba); + E1000_WRITE_REG(hw, E1000_PBA, pba); /* * These parameters set thresholds for the adapter's generation(Tx) @@ -1184,15 +1126,26 @@ * High-water mark is set down from the top of the rx fifo (not * sensitive to max_frame_size) and low-water is set just below * high-water mark. + * The high water mark must be low enough to fit one full frame above + * it in the rx FIFO. Should be the lower of: + * 90% of the Rx FIFO size and the full Rx FIFO size minus the early + * receive size (assuming ERT set to E1000_ERT_2048), or the full + * Rx FIFO size minus one full frame. */ - hw->fc_high_water = - ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - - E1000_FC_HIGH_DIFF; - hw->fc_low_water = - ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - - E1000_FC_LOW_DIFF; - hw->fc_pause_time = E1000_FC_PAUSE_TIME; - hw->fc_send_xon = B_TRUE; + high_water = min(((pba << 10) * 9 / 10), + ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? + ((pba << 10) - (E1000_ERT_2048 << 3)) : + ((pba << 10) - hw->mac.max_frame_size))); + + hw->mac.fc_high_water = high_water & 0xFFF8; + hw->mac.fc_low_water = hw->mac.fc_high_water - 8; + + if (hw->mac.type == e1000_80003es2lan) + hw->mac.fc_pause_time = 0xFFFF; + else + hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; + hw->mac.fc_send_xon = B_TRUE; + hw->mac.fc = hw->mac.original_fc; /* * Reset the adapter hardware the second time. @@ -1200,15 +1153,11 @@ (void) e1000_reset_hw(hw); /* disable wakeup control by default */ - if (hw->mac_type >= e1000_82544) - E1000_WRITE_REG(hw, WUC, 0); + if (hw->mac.type >= e1000_82544) + E1000_WRITE_REG(hw, E1000_WUC, 0); /* MWI setup */ - if (Adapter->MWIEnable) { - hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; - e1000_pci_set_mwi(hw); - } else - e1000_pci_clear_mwi(hw); + e1000_pci_set_mwi(hw); /* * Configure/Initialize hardware @@ -1227,24 +1176,11 @@ e1000g_init_unicst(Adapter); /* - * Setup and initialize the transmit structures. - */ - SetupTransmitStructures(Adapter); - DelayInMilliseconds(5); - - /* * Setup and initialize the mctable structures. After this routine * completes Multicast table will be set */ - SetupMulticastTable(Adapter); - DelayInMilliseconds(5); - - /* - * Setup and initialize the receive structures. After this routine - * completes we can receive packets off of the wire. - */ - SetupReceiveStructures(Adapter); - DelayInMilliseconds(5); + e1000g_setup_multicast(Adapter); + msec_delay(5); /* * Implement Adaptive IFS @@ -1252,26 +1188,26 @@ e1000_reset_adaptive(hw); /* Setup Interrupt Throttling Register */ - E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); + E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); /* Start the timer for link setup */ - if (hw->autoneg) - link_timeout = PHY_AUTO_NEG_TIME * drv_usectohz(100000); + if (hw->mac.autoneg) + link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); else - link_timeout = PHY_FORCE_TIME * drv_usectohz(100000); - - mutex_enter(&Adapter->e1000g_linklock); - if (hw->wait_autoneg_complete) { + link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); + + mutex_enter(&Adapter->link_lock); + if (hw->phy.wait_for_link) { Adapter->link_complete = B_TRUE; } else { Adapter->link_complete = B_FALSE; Adapter->link_tid = timeout(e1000g_link_timer, (void *)Adapter, link_timeout); } - mutex_exit(&Adapter->e1000g_linklock); + mutex_exit(&Adapter->link_lock); /* Enable PCI-Ex master */ - if (hw->bus_type == e1000_bus_type_pci_express) { + if (hw->bus.type == e1000_bus_type_pci_express) { e1000_enable_pciex_master(hw); } @@ -1295,17 +1231,17 @@ struct e1000_hw *hw; boolean_t link_up; - hw = &Adapter->Shared; + hw = &Adapter->shared; /* Ensure this is set to get accurate copper link status */ - hw->get_link_status = B_TRUE; + hw->mac.get_link_status = B_TRUE; e1000_check_for_link(hw); - if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || - ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || + if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || + ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || ((hw->media_type == e1000_media_type_internal_serdes) && - (!hw->serdes_link_down))) { + (hw->mac.serdes_has_link))) { link_up = B_TRUE; } else { link_up = B_FALSE; @@ -1346,6 +1282,7 @@ status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); break; +#ifdef E1000G_DEBUG case E1000G_IOC_REG_PEEK: case E1000G_IOC_REG_POKE: status = e1000g_pp_ioctl(e1000gp, iocp, mp); @@ -1357,6 +1294,7 @@ else status = IOC_INVAL; break; +#endif default: status = IOC_INVAL; break; @@ -1412,7 +1350,7 @@ */ if (Adapter->intr_adaptive) { Adapter->intr_throttling_rate = count << 5; - E1000_WRITE_REG(&Adapter->Shared, ITR, + E1000_WRITE_REG(&Adapter->shared, E1000_ITR, Adapter->intr_throttling_rate); } } @@ -1437,33 +1375,54 @@ { struct e1000g *Adapter = (struct e1000g *)arg; - return (e1000g_start(Adapter)); + return (e1000g_start(Adapter, B_TRUE)); } static int -e1000g_start(struct e1000g *Adapter) +e1000g_start(struct e1000g *Adapter, boolean_t global) { + if (global) { + /* Allocate dma resources for descriptors and buffers */ + if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { + e1000g_log(Adapter, CE_WARN, + "Alloc DMA resources failed"); + return (ENOTACTIVE); + } + Adapter->rx_buffer_setup = B_FALSE; + } + if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { if (e1000g_init(Adapter) != DDI_SUCCESS) { e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); + if (global) + e1000g_release_dma_resources(Adapter); return (ENOTACTIVE); } } - enable_timeout(Adapter); - rw_enter(&Adapter->chip_lock, RW_WRITER); - e1000g_EnableInterrupt(Adapter); + /* Setup and initialize the transmit structures */ + e1000g_tx_setup(Adapter); + msec_delay(5); + + /* Setup and initialize the receive structures */ + e1000g_rx_setup(Adapter); + msec_delay(5); + + e1000g_mask_interrupt(Adapter); if (Adapter->tx_intr_enable) - e1000g_EnableTxInterrupt(Adapter); + e1000g_mask_tx_interrupt(Adapter); Adapter->started = B_TRUE; Adapter->attach_progress |= ATTACH_PROGRESS_INIT; rw_exit(&Adapter->chip_lock); + /* Enable and start the watchdog timer */ + enable_watchdog_timer(Adapter); + return (0); } @@ -1472,18 +1431,12 @@ { struct e1000g *Adapter = (struct e1000g *)arg; - e1000g_stop(Adapter); + e1000g_stop(Adapter, B_TRUE); } static void -e1000g_stop(struct e1000g *Adapter) +e1000g_stop(struct e1000g *Adapter, boolean_t global) { - timeout_id_t tid; - e1000g_tx_ring_t *tx_ring; - boolean_t link_changed; - - tx_ring = Adapter->tx_ring; - /* Set stop flags */ rw_enter(&Adapter->chip_lock, RW_WRITER); @@ -1495,55 +1448,47 @@ /* Drain tx sessions */ (void) e1000g_tx_drain(Adapter); - /* Disable timers */ - disable_timeout(Adapter); - - /* Disable the tx timer for 82547 chipset */ - mutex_enter(&tx_ring->tx_lock); - tx_ring->timer_enable_82547 = B_FALSE; - tid = tx_ring->timer_id_82547; - tx_ring->timer_id_82547 = 0; - mutex_exit(&tx_ring->tx_lock); - - if (tid != 0) - (void) untimeout(tid); - - /* Disable the link timer */ - mutex_enter(&Adapter->e1000g_linklock); - tid = Adapter->link_tid; - Adapter->link_tid = 0; - mutex_exit(&Adapter->e1000g_linklock); - - if (tid != 0) - (void) untimeout(tid); + /* Disable and stop all the timers */ + disable_watchdog_timer(Adapter); + stop_link_timer(Adapter); + stop_82547_timer(Adapter->tx_ring); /* Stop the chip and release pending resources */ rw_enter(&Adapter->chip_lock, RW_WRITER); - e1000g_DisableAllInterrupts(Adapter); - - e1000_reset_hw(&Adapter->Shared); + e1000g_clear_all_interrupts(Adapter); + e1000_reset_hw(&Adapter->shared); /* Release resources still held by the TX descriptors */ - e1000g_tx_drop(Adapter); + e1000g_tx_clean(Adapter); /* Clean the pending rx jumbo packet fragment */ - if (Adapter->rx_mblk != NULL) { - freemsg(Adapter->rx_mblk); - Adapter->rx_mblk = NULL; - Adapter->rx_mblk_tail = NULL; - Adapter->rx_packet_len = 0; - } + e1000g_rx_clean(Adapter); rw_exit(&Adapter->chip_lock); + + if (global) + e1000g_release_dma_resources(Adapter); } static void -e1000g_tx_drop(struct e1000g *Adapter) +e1000g_rx_clean(struct e1000g *Adapter) +{ + e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; + + if (rx_ring->rx_mblk != NULL) { + freemsg(rx_ring->rx_mblk); + rx_ring->rx_mblk = NULL; + rx_ring->rx_mblk_tail = NULL; + rx_ring->rx_mblk_len = 0; + } +} + +static void +e1000g_tx_clean(struct e1000g *Adapter) { e1000g_tx_ring_t *tx_ring; - e1000g_msg_chain_t *msg_chain; - PTX_SW_PACKET packet; + p_tx_sw_packet_t packet; mblk_t *mp; mblk_t *nmp; uint32_t packet_count; @@ -1558,7 +1503,7 @@ mp = NULL; nmp = NULL; packet_count = 0; - packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); + packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); while (packet != NULL) { if (packet->mp != NULL) { /* Assemble the message chain */ @@ -1573,24 +1518,23 @@ packet->mp = NULL; } - FreeTxSwPacket(packet); + e1000g_free_tx_swpkt(packet); packet_count++; - packet = (PTX_SW_PACKET) + packet = (p_tx_sw_packet_t) QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); } if (mp != NULL) { - msg_chain = Adapter->tx_msg_chain; - mutex_enter(&msg_chain->lock); - if (msg_chain->head == NULL) { - msg_chain->head = mp; - msg_chain->tail = nmp; + mutex_enter(&tx_ring->mblks_lock); + if (tx_ring->mblks.head == NULL) { + tx_ring->mblks.head = mp; + tx_ring->mblks.tail = nmp; } else { - msg_chain->tail->b_next = mp; - msg_chain->tail = nmp; + tx_ring->mblks.tail->b_next = mp; + tx_ring->mblks.tail = nmp; } - mutex_exit(&msg_chain->lock); + mutex_exit(&tx_ring->mblks_lock); } ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); @@ -1604,8 +1548,8 @@ tx_ring->tbd_oldest = tx_ring->tbd_first; /* Setup our HW Tx Head & Tail descriptor pointers */ - E1000_WRITE_REG(&Adapter->Shared, TDH, 0); - E1000_WRITE_REG(&Adapter->Shared, TDT, 0); + E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); + E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); } } @@ -1619,7 +1563,7 @@ tx_ring = Adapter->tx_ring; /* Allow up to 'wsdraintime' for pending xmit's to complete. */ - for (i = 0; i < WSDRAINTIME; i++) { + for (i = 0; i < TX_DRAIN_TIME; i++) { mutex_enter(&tx_ring->usedlist_lock); done = IS_QUEUE_EMPTY(&tx_ring->used_list); mutex_exit(&tx_ring->usedlist_lock); @@ -1636,11 +1580,31 @@ static boolean_t e1000g_rx_drain(struct e1000g *Adapter) { + e1000g_rx_ring_t *rx_ring; + p_rx_sw_packet_t packet; boolean_t done; - mutex_enter(&Adapter->rx_ring->freelist_lock); - done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); - mutex_exit(&Adapter->rx_ring->freelist_lock); + rx_ring = Adapter->rx_ring; + done = B_TRUE; + + rw_enter(&e1000g_rx_detach_lock, RW_WRITER); + + while (rx_ring->pending_list != NULL) { + packet = rx_ring->pending_list; + rx_ring->pending_list = + rx_ring->pending_list->next; + + if (packet->flag == E1000G_RX_SW_STOP) { + packet->flag = E1000G_RX_SW_DETACH; + done = B_FALSE; + } else { + ASSERT(packet->flag == E1000G_RX_SW_FREE); + ASSERT(packet->mp == NULL); + e1000g_free_rx_sw_packet(packet); + } + } + + rw_exit(&e1000g_rx_detach_lock); return (done); } @@ -1648,9 +1612,9 @@ boolean_t e1000g_reset(struct e1000g *Adapter) { - e1000g_stop(Adapter); - - if (e1000g_start(Adapter)) { + e1000g_stop(Adapter, B_FALSE); + + if (e1000g_start(Adapter, B_FALSE)) { e1000g_log(Adapter, CE_WARN, "Reset failed"); return (B_FALSE); } @@ -1659,39 +1623,28 @@ } /* - * ********************************************************************** - * Name: e1000g_intr_pciexpress * - * * - * Description: * - * This interrupt service routine is for PCI-Express adapters. * - * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * - * bit is set. * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * e1000g_intr_work * - * * - * ********************************************************************** + * e1000g_intr_pciexpress - ISR for PCI Express chipsets + * + * This interrupt service routine is for PCI-Express adapters. + * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED + * bit is set. */ static uint_t e1000g_intr_pciexpress(caddr_t arg) { struct e1000g *Adapter; - uint32_t ICRContents; + uint32_t icr; Adapter = (struct e1000g *)arg; - ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); - - if (ICRContents & E1000_ICR_INT_ASSERTED) { + icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); + + if (icr & E1000_ICR_INT_ASSERTED) { /* * E1000_ICR_INT_ASSERTED bit was set: * Read(Clear) the ICR, claim this interrupt, * look for work to do. */ - e1000g_intr_work(Adapter, ICRContents); + e1000g_intr_work(Adapter, icr); return (DDI_INTR_CLAIMED); } else { /* @@ -1703,39 +1656,28 @@ } /* - * ********************************************************************** - * Name: e1000g_intr * - * * - * Description: * - * This interrupt service routine is for PCI/PCI-X adapters. * - * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * - * bit is set or not. * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * e1000g_intr_work * - * * - * ********************************************************************** + * e1000g_intr - ISR for PCI/PCI-X chipsets + * + * This interrupt service routine is for PCI/PCI-X adapters. + * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED + * bit is set or not. */ static uint_t e1000g_intr(caddr_t arg) { struct e1000g *Adapter; - uint32_t ICRContents; + uint32_t icr; Adapter = (struct e1000g *)arg; - ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); - - if (ICRContents) { + icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); + + if (icr) { /* * Any bit was set in ICR: * Read(Clear) the ICR, claim this interrupt, * look for work to do. */ - e1000g_intr_work(Adapter, ICRContents); + e1000g_intr_work(Adapter, icr); return (DDI_INTR_CLAIMED); } else { /* @@ -1747,50 +1689,38 @@ } /* - * ********************************************************************** - * Name: e1000g_intr_work * - * * - * Description: * - * Called from interrupt service routines. * - * Read(clear) the ICR contents and call appropriate interrupt * - * processing routines. * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * e1000g_receive * - * e1000g_link_check * - * e1000g_recycle * - * * - * ********************************************************************** + * e1000g_intr_work - actual processing of ISR + * + * Read(clear) the ICR contents and call appropriate interrupt + * processing routines. */ static void -e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) +e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) { - if (ICRContents & E1000_ICR_RXT0) { + rw_enter(&Adapter->chip_lock, RW_READER); + /* + * Here we need to check the "started" flag within the chip_lock to + * ensure the receive routine will not execute when the adapter is + * being reset. + */ + if (!Adapter->started) { + rw_exit(&Adapter->chip_lock); + return; + } + + if (icr & E1000_ICR_RXT0) { mblk_t *mp; - rw_enter(&Adapter->chip_lock, RW_READER); - /* - * Here we need to check the "started" flag to ensure the - * receive routine will not execute when the adapter is - * stopped or being reset. - */ - if (Adapter->started) { - mutex_enter(&Adapter->rx_ring->rx_lock); - mp = e1000g_receive(Adapter); - mutex_exit(&Adapter->rx_ring->rx_lock); - - rw_exit(&Adapter->chip_lock); - - if (mp != NULL) - mac_rx(Adapter->mh, Adapter->mrh, mp); - } else { - rw_exit(&Adapter->chip_lock); - } - } + mutex_enter(&Adapter->rx_ring->rx_lock); + mp = e1000g_receive(Adapter); + mutex_exit(&Adapter->rx_ring->rx_lock); + + rw_exit(&Adapter->chip_lock); + + if (mp != NULL) + mac_rx(Adapter->mh, Adapter->mrh, mp); + } else + rw_exit(&Adapter->chip_lock); /* * The Receive Sequence errors RXSEQ and the link status change LSC @@ -1798,29 +1728,20 @@ * the Wiseman 2.0 silicon, the receive sequence errors interrupt * are an indication that cable is not connected. */ - if ((ICRContents & E1000_ICR_RXSEQ) || - (ICRContents & E1000_ICR_LSC) || - (ICRContents & E1000_ICR_GPI_EN1)) { + if ((icr & E1000_ICR_RXSEQ) || + (icr & E1000_ICR_LSC) || + (icr & E1000_ICR_GPI_EN1)) { boolean_t link_changed; timeout_id_t tid = 0; - /* - * Encountered RX Sequence Error!!! Link maybe forced and - * the cable may have just been disconnected so we will - * read the LOS to see. - */ - if (ICRContents & E1000_ICR_RXSEQ) - Adapter->rx_seq_intr++; - - stop_timeout(Adapter); - - mutex_enter(&Adapter->e1000g_linklock); + stop_watchdog_timer(Adapter); + + mutex_enter(&Adapter->link_lock); /* e1000g_link_check takes care of link status change */ link_changed = e1000g_link_check(Adapter); /* * If the link timer has not timed out, we'll not notify - * the upper layer with any link state until the link - * is up. + * the upper layer with any link state until the link is up. */ if (link_changed && !Adapter->link_complete) { if (Adapter->link_state == LINK_STATE_UP) { @@ -1831,7 +1752,7 @@ link_changed = B_FALSE; } } - mutex_exit(&Adapter->e1000g_linklock); + mutex_exit(&Adapter->link_lock); if (link_changed) { if (tid != 0) @@ -1842,29 +1763,31 @@ * down event. Reset the adapter to recover it. */ if ((Adapter->link_state == LINK_STATE_DOWN) && - (Adapter->Shared.mac_type == e1000_80003es2lan)) + (Adapter->shared.mac.type == e1000_80003es2lan)) (void) e1000g_reset(Adapter); mac_link_update(Adapter->mh, Adapter->link_state); } - start_timeout(Adapter); + start_watchdog_timer(Adapter); } - if (ICRContents & E1000G_ICR_TX_INTR) { + if (icr & E1000G_ICR_TX_INTR) { + e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; + if (!Adapter->tx_intr_enable) - e1000g_DisableTxInterrupt(Adapter); + e1000g_clear_tx_interrupt(Adapter); /* Schedule the re-transmit */ - if (Adapter->resched_needed) { - Adapter->tx_reschedule++; - Adapter->resched_needed = B_FALSE; + if (tx_ring->resched_needed) { + E1000G_STAT(tx_ring->stat_reschedule); + tx_ring->resched_needed = B_FALSE; mac_tx_update(Adapter->mh); } if (Adapter->tx_intr_enable) { /* Recycle the tx descriptors */ rw_enter(&Adapter->chip_lock, RW_READER); - Adapter->tx_recycle_intr++; - e1000g_recycle(Adapter->tx_ring); + E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); + e1000g_recycle(tx_ring); rw_exit(&Adapter->chip_lock); /* Free the recycled messages */ ddi_intr_trigger_softint(Adapter->tx_softint_handle, @@ -1879,23 +1802,25 @@ struct e1000_hw *hw; int slot; - hw = &Adapter->Shared; + hw = &Adapter->shared; if (Adapter->init_count == 0) { /* Initialize the multiple unicast addresses */ Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; - if ((hw->mac_type == e1000_82571) && hw->laa_is_present) + if ((hw->mac.type == e1000_82571) && + (e1000_get_laa_state_82571(hw) == B_TRUE)) Adapter->unicst_total--; Adapter->unicst_avail = Adapter->unicst_total - 1; /* Store the default mac address */ - e1000_rar_set(hw, hw->mac_addr, 0); - if ((hw->mac_type == e1000_82571) && hw->laa_is_present) - e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); - - bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, + e1000_rar_set(hw, hw->mac.addr, 0); + if ((hw->mac.type == e1000_82571) && + (e1000_get_laa_state_82571(hw) == B_TRUE)) + e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); + + bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, ETHERADDRL); Adapter->unicst_addr[0].mac.set = 1; @@ -1903,13 +1828,14 @@ Adapter->unicst_addr[slot].mac.set = 0; } else { /* Recover the default mac address */ - bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, + bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, ETHERADDRL); /* Store the default mac address */ - e1000_rar_set(hw, hw->mac_addr, 0); - if ((hw->mac_type == e1000_82571) && hw->laa_is_present) - e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); + e1000_rar_set(hw, hw->mac.addr, 0); + if ((hw->mac.type == e1000_82571) && + (e1000_get_laa_state_82571(hw) == B_TRUE)) + e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); /* Re-configure the RAR registers */ for (slot = 1; slot < Adapter->unicst_total; slot++) @@ -1926,7 +1852,7 @@ Adapter = (struct e1000g *)arg; /* Store the default MAC address */ - bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); + bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); /* Set MAC address in address slot 0, which is the default address */ return (e1000g_unicst_set(Adapter, mac_addr, 0)); @@ -1938,18 +1864,11 @@ { struct e1000_hw *hw; - hw = &Adapter->Shared; - - /* - * Error if the address specified is a multicast or broadcast - * address. - */ - if (((mac_addr[0] & 01) == 1) || - (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) - return (EINVAL); + hw = &Adapter->shared; rw_enter(&Adapter->chip_lock, RW_WRITER); +#ifndef NO_82542_SUPPORT /* * The first revision of Wiseman silicon (rev 2.0) has an errata * that requires the receiver to be in reset when any of the @@ -1959,33 +1878,39 @@ * initialize the RARs, we check the rev of the Wiseman controller * and work around any necessary HW errata. */ - if (hw->mac_type == e1000_82542_rev2_0) { + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) { e1000_pci_clear_mwi(hw); - E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); - DelayInMilliseconds(5); + E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); + msec_delay(5); } +#endif bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); e1000_rar_set(hw, (uint8_t *)mac_addr, slot); if (slot == 0) { - if ((hw->mac_type == e1000_82571) && hw->laa_is_present) - e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); + if ((hw->mac.type == e1000_82571) && + (e1000_get_laa_state_82571(hw) == B_TRUE)) + e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); } +#ifndef NO_82542_SUPPORT /* * If we are using Wiseman rev 2.0 silicon, we will have previously * put the receive in reset, and disabled MWI, to work around some * HW errata. Now we should take the receiver out of reset, and * re-enabled if MWI if it was previously enabled by the PCI BIOS. */ - if (hw->mac_type == e1000_82542_rev2_0) { - E1000_WRITE_REG(hw, RCTL, 0); - DelayInMilliseconds(1); - if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) { + E1000_WRITE_REG(hw, E1000_RCTL, 0); + msec_delay(1); + if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) e1000_pci_set_mwi(hw); - SetupReceiveStructures(Adapter); + e1000g_rx_setup(Adapter); } +#endif rw_exit(&Adapter->chip_lock); @@ -2152,6 +2077,7 @@ static int multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) { + struct e1000_hw *hw = &Adapter->shared; unsigned i; int res = 0; @@ -2174,14 +2100,17 @@ /* * Update the MC table in the hardware */ - e1000g_DisableInterrupt(Adapter); - - SetupMulticastTable(Adapter); - - if (Adapter->Shared.mac_type == e1000_82542_rev2_0) - SetupReceiveStructures(Adapter); - - e1000g_EnableInterrupt(Adapter); + e1000g_clear_interrupt(Adapter); + + e1000g_setup_multicast(Adapter); + +#ifndef NO_82542_SUPPORT + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) + e1000g_rx_setup(Adapter); +#endif + + e1000g_mask_interrupt(Adapter); done: rw_exit(&Adapter->chip_lock); @@ -2191,6 +2120,7 @@ static int multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) { + struct e1000_hw *hw = &Adapter->shared; unsigned i; rw_enter(&Adapter->chip_lock, RW_WRITER); @@ -2210,20 +2140,128 @@ /* * Update the MC table in the hardware */ - e1000g_DisableInterrupt(Adapter); - - SetupMulticastTable(Adapter); - - if (Adapter->Shared.mac_type == e1000_82542_rev2_0) - SetupReceiveStructures(Adapter); - - e1000g_EnableInterrupt(Adapter); + e1000g_clear_interrupt(Adapter); + + e1000g_setup_multicast(Adapter); + +#ifndef NO_82542_SUPPORT + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) + e1000g_rx_setup(Adapter); +#endif + + e1000g_mask_interrupt(Adapter); done: rw_exit(&Adapter->chip_lock); return (0); } +/* + * e1000g_setup_multicast - setup multicast data structures + * + * This routine initializes all of the multicast related structures. + */ +void +e1000g_setup_multicast(struct e1000g *Adapter) +{ + uint8_t *mc_addr_list; + uint32_t mc_addr_count; + uint32_t rctl; + struct e1000_hw *hw; + + hw = &Adapter->shared; + + /* + * The e1000g has the ability to do perfect filtering of 16 + * addresses. The driver uses one of the e1000g's 16 receive + * address registers for its node/network/mac/individual address. + * So, we have room for up to 15 multicast addresses in the CAM, + * additional MC addresses are handled by the MTA (Multicast Table + * Array) + */ + + rctl = E1000_READ_REG(hw, E1000_RCTL); + + mc_addr_list = (uint8_t *)Adapter->mcast_table; + + if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { + E1000G_DEBUGLOG_1(Adapter, CE_WARN, + "Adapter requested more than %d MC Addresses.\n", + MAX_NUM_MULTICAST_ADDRESSES); + mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; + } else { + /* + * Set the number of MC addresses that we are being + * requested to use + */ + mc_addr_count = Adapter->mcast_count; + } +#ifndef NO_82542_SUPPORT + /* + * The Wiseman 2.0 silicon has an errata by which the receiver will + * hang while writing to the receive address registers if the receiver + * is not in reset before writing to the registers. Updating the RAR + * is done during the setting up of the multicast table, hence the + * receiver has to be put in reset before updating the multicast table + * and then taken out of reset at the end + */ + /* + * if WMI was enabled then dis able it before issueing the global + * reset to the hardware. + */ + /* + * Only required for WISEMAN_2_0 + */ + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) { + e1000_pci_clear_mwi(hw); + /* + * The e1000g must be in reset before changing any RA + * registers. Reset receive unit. The chip will remain in + * the reset state until software explicitly restarts it. + */ + E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); + /* Allow receiver time to go in to reset */ + msec_delay(5); + } +#endif + + e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, + Adapter->unicst_total, hw->mac.rar_entry_count); + +#ifndef NO_82542_SUPPORT + /* + * Only for Wiseman_2_0 + * If MWI was enabled then re-enable it after issueing (as we + * disabled it up there) the receive reset command. + * Wainwright does not have a receive reset command and only thing + * close to it is global reset which will require tx setup also + */ + if ((hw->mac.type == e1000_82542) && + (hw->revision_id == E1000_REVISION_2)) { + /* + * if WMI was enabled then reenable it after issueing the + * global or receive reset to the hardware. + */ + + /* + * Take receiver out of reset + * clear E1000_RCTL_RST bit (and all others) + */ + E1000_WRITE_REG(hw, E1000_RCTL, 0); + msec_delay(5); + if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) + e1000_pci_set_mwi(hw); + } +#endif + + /* + * Restore original value + */ + E1000_WRITE_REG(hw, E1000_RCTL, rctl); +} + int e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) { @@ -2237,19 +2275,19 @@ e1000g_m_promisc(void *arg, boolean_t on) { struct e1000g *Adapter = (struct e1000g *)arg; - ULONG RctlRegValue; + uint32_t rctl; rw_enter(&Adapter->chip_lock, RW_WRITER); - RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); + rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); if (on) - RctlRegValue |= + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); else - RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); - - E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); + rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); + + E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); Adapter->e1000g_promisc = on; @@ -2262,23 +2300,16 @@ e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) { struct e1000g *Adapter = (struct e1000g *)arg; + struct e1000_hw *hw = &Adapter->shared; switch (cap) { case MAC_CAPAB_HCKSUM: { uint32_t *txflags = cap_data; - - /* - * In Jumbo mode, enabling hardware checksum will cause - * port hang. - */ - if (Adapter->Shared.max_frame_size > ETHERMAX) - return (B_FALSE); - /* * Checksum on/off selection via global parameters. * * If the chip is flagged as not capable of (correctly) - * handling FULL checksumming, we don't enable it on either + * handling checksumming, we don't enable it on either * Rx or Tx side. Otherwise, we take this chip's settings * from the patchable global defaults. * @@ -2287,15 +2318,13 @@ * packets anyway, even if we haven't said we can deliver * them. */ - switch (Adapter->Shared.mac_type) { - /* - * Switch on hardware checksum offload of - * chip 82540, 82545, 82546 - */ + switch (hw->mac.type) { case e1000_82540: - case e1000_82544: /* pci8086,1008 */ + case e1000_82544: case e1000_82545: - case e1000_82545_rev_3: /* pci8086,1026 */ + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: case e1000_82571: case e1000_82572: case e1000_82573: @@ -2303,29 +2332,16 @@ *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; break; - case e1000_82546: /* 82546EB. devID: 1010, 101d */ - case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ -#if !defined(__sparc) && !defined(__amd64) - /* Workaround for Galaxy on 32bit */ - return (B_FALSE); -#else - *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; - break; -#endif - /* - * We don't have the following PRO 1000 chip types at - * hand and haven't tested their hardware checksum - * offload capability. We had better switch them off. - * e1000_undefined = 0, - * e1000_82542_rev2_0, - * e1000_82542_rev2_1, + * For the following Intel PRO/1000 chipsets, we have not + * tested the hardware checksum offload capability, so we + * disable the capability for them. + * e1000_82542, * e1000_82543, * e1000_82541, * e1000_82541_rev_2, * e1000_82547, * e1000_82547_rev_2, - * e1000_num_macs */ default: return (B_FALSE); @@ -2368,26 +2384,23 @@ } /* - * ********************************************************************** - * Name: e1000g_getparam * - * * - * Description: This routine gets user-configured values out of the * - * configuration file e1000g.conf. * - * For each configurable value, there is a minimum, a maximum, and a * - * default. * - * If user does not configure a value, use the default. * - * If user configures below the minimum, use the minumum. * - * If user configures above the maximum, use the maxumum. * - * * - * Arguments: * - * Adapter - A pointer to our adapter structure * - * * - * Returns: None * - * ********************************************************************** + * e1000g_get_conf - get configurations set in e1000g.conf + * + * This routine gets user-configured values out of the configuration + * file e1000g.conf. + * + * For each configurable value, there is a minimum, a maximum, and a + * default. + * If user does not configure a value, use the default. + * If user configures below the minimum, use the minumum. + * If user configures above the maximum, use the maxumum. */ static void -e1000g_getparam(struct e1000g *Adapter) +e1000g_get_conf(struct e1000g *Adapter) { + struct e1000_hw *hw = &Adapter->shared; + boolean_t tbi_compatibility = B_FALSE; + /* * get each configurable property from e1000g.conf */ @@ -2395,67 +2408,59 @@ /* * NumTxDescriptors */ - Adapter->NumTxDescriptors = - e1000g_getprop(Adapter, "NumTxDescriptors", - MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, - DEFAULTNUMTXDESCRIPTOR); + Adapter->tx_desc_num = + e1000g_get_prop(Adapter, "NumTxDescriptors", + MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, + DEFAULT_NUM_TX_DESCRIPTOR); /* * NumRxDescriptors */ - Adapter->NumRxDescriptors = - e1000g_getprop(Adapter, "NumRxDescriptors", - MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, - DEFAULTNUMRXDESCRIPTOR); + Adapter->rx_desc_num = + e1000g_get_prop(Adapter, "NumRxDescriptors", + MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, + DEFAULT_NUM_RX_DESCRIPTOR); /* * NumRxFreeList */ - Adapter->NumRxFreeList = - e1000g_getprop(Adapter, "NumRxFreeList", - MINNUMRXFREELIST, MAXNUMRXFREELIST, - DEFAULTNUMRXFREELIST); + Adapter->rx_freelist_num = + e1000g_get_prop(Adapter, "NumRxFreeList", + MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, + DEFAULT_NUM_RX_FREELIST); /* * NumTxPacketList */ - Adapter->NumTxSwPacket = - e1000g_getprop(Adapter, "NumTxPacketList", - MINNUMTXSWPACKET, MAXNUMTXSWPACKET, - DEFAULTNUMTXSWPACKET); + Adapter->tx_freelist_num = + e1000g_get_prop(Adapter, "NumTxPacketList", + MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, + DEFAULT_NUM_TX_FREELIST); /* * FlowControl */ - Adapter->Shared.fc_send_xon = B_TRUE; - Adapter->Shared.fc = - e1000g_getprop(Adapter, "FlowControl", - E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); + hw->mac.fc_send_xon = B_TRUE; + hw->mac.fc = + e1000g_get_prop(Adapter, "FlowControl", + e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); /* 4 is the setting that says "let the eeprom decide" */ - if (Adapter->Shared.fc == 4) - Adapter->Shared.fc = E1000_FC_DEFAULT; + if (hw->mac.fc == 4) + hw->mac.fc = e1000_fc_default; /* - * MaxNumReceivePackets + * Max Num Receive Packets on Interrupt */ - Adapter->MaxNumReceivePackets = - e1000g_getprop(Adapter, "MaxNumReceivePackets", - MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, - DEFAULTMAXNUMRCVPKTONINTR); - - /* - * TxInterruptDelay - */ - Adapter->TxInterruptDelay = - e1000g_getprop(Adapter, "TxInterruptDelay", - MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, - DEFAULTTXINTERRUPTDELAYVAL); + Adapter->rx_limit_onintr = + e1000g_get_prop(Adapter, "MaxNumReceivePackets", + MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, + DEFAULT_RX_LIMIT_ON_INTR); /* * PHY master slave setting */ - Adapter->Shared.master_slave = - e1000g_getprop(Adapter, "SetMasterSlave", + hw->phy.ms_type = + e1000g_get_prop(Adapter, "SetMasterSlave", e1000_ms_hw_default, e1000_ms_auto, e1000_ms_hw_default); @@ -2463,49 +2468,49 @@ * Parameter which controls TBI mode workaround, which is only * needed on certain switches such as Cisco 6500/Foundry */ - Adapter->Shared.tbi_compatibility_en = - e1000g_getprop(Adapter, "TbiCompatibilityEnable", - 0, 1, DEFAULTTBICOMPATIBILITYENABLE); + tbi_compatibility = + e1000g_get_prop(Adapter, "TbiCompatibilityEnable", + 0, 1, DEFAULT_TBI_COMPAT_ENABLE); + e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); /* * MSI Enable */ Adapter->msi_enabled = - e1000g_getprop(Adapter, "MSIEnable", - 0, 1, DEFAULTMSIENABLE); + e1000g_get_prop(Adapter, "MSIEnable", + 0, 1, DEFAULT_MSI_ENABLE); /* * Interrupt Throttling Rate */ Adapter->intr_throttling_rate = - e1000g_getprop(Adapter, "intr_throttling_rate", - MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, - DEFAULTINTERRUPTTHROTTLINGVAL); + e1000g_get_prop(Adapter, "intr_throttling_rate", + MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, + DEFAULT_INTR_THROTTLING); /* * Adaptive Interrupt Blanking Enable/Disable * It is enabled by default */ Adapter->intr_adaptive = - (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? + (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? B_TRUE : B_FALSE; } /* - * ********************************************************************** - * Name: e1000g_getprop * - * * - * Description: get a user-configure property value out of the * - * configuration file e1000g.conf. * - * Caller provides name of the property, a default value, a * - * minimum value, and a maximum value. * - * * - * Returns: configured value of the property, with default, minimum and * - * maximum properly applied. * - * ********************************************************************** + * e1000g_get_prop - routine to read properties + * + * Get a user-configure property value out of the configuration + * file e1000g.conf. + * + * Caller provides name of the property, a default value, a minimum + * value, and a maximum value. + * + * Return configured value of the property, with default, minimum and + * maximum properly applied. */ static int -e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ +e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ char *propname, /* name of the property */ int minval, /* minimum acceptable value */ int maxval, /* maximim acceptable value */ @@ -2521,12 +2526,12 @@ if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { /* got some properties, test if we got enough */ - if (Adapter->AdapterInstance < nprops) { - propval = props[Adapter->AdapterInstance]; + if (Adapter->instance < nprops) { + propval = props[Adapter->instance]; } else { /* not enough properties configured */ propval = defval; - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, "Not Enough %s values found in e1000g.conf" " - set to %d\n", propname, propval); @@ -2544,14 +2549,14 @@ */ if (propval > maxval) { propval = maxval; - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, "Too High %s value in e1000g.conf - set to %d\n", propname, propval); } if (propval < minval) { propval = minval; - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, "Too Low %s value in e1000g.conf - set to %d\n", propname, propval); } @@ -2567,7 +2572,7 @@ struct e1000_hw *hw; uint32_t reg_tarc; - hw = &Adapter->Shared; + hw = &Adapter->shared; if (e1000g_link_up(Adapter)) { /* @@ -2582,14 +2587,14 @@ Adapter->tx_link_down_timeout = 0; - if ((hw->mac_type == e1000_82571) || - (hw->mac_type == e1000_82572)) { - reg_tarc = E1000_READ_REG(hw, TARC0); + if ((hw->mac.type == e1000_82571) || + (hw->mac.type == e1000_82572)) { + reg_tarc = E1000_READ_REG(hw, E1000_TARC0); if (speed == SPEED_1000) reg_tarc |= (1 << 21); else reg_tarc &= ~(1 << 21); - E1000_WRITE_REG(hw, TARC0, reg_tarc); + E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); } } Adapter->smartspeed = 0; @@ -2605,7 +2610,7 @@ * driver loses link disable auto master/slave * resolution. */ - if (hw->phy_type == e1000_phy_igp) { + if (hw->phy.type == e1000_phy_igp) { e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phydata); phydata |= CR_1000T_MS_ENABLE; @@ -2623,7 +2628,7 @@ } else if (Adapter->tx_link_down_timeout == MAX_TX_LINK_DOWN_TIMEOUT) { rw_enter(&Adapter->chip_lock, RW_WRITER); - e1000g_tx_drop(Adapter); + e1000g_tx_clean(Adapter); rw_exit(&Adapter->chip_lock); Adapter->tx_link_down_timeout++; } @@ -2634,31 +2639,29 @@ } static void -e1000g_LocalTimer(void *ws) +e1000g_local_timer(void *ws) { struct e1000g *Adapter = (struct e1000g *)ws; struct e1000_hw *hw; e1000g_ether_addr_t ether_addr; boolean_t link_changed; - hw = &Adapter->Shared; - - (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); + hw = &Adapter->shared; + + (void) e1000g_tx_freemsg(Adapter->tx_ring); if (e1000g_stall_check(Adapter)) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "Tx stall detected. Activate automatic recovery.\n"); - Adapter->StallWatchdog = 0; - Adapter->tx_recycle_fail = 0; Adapter->reset_count++; (void) e1000g_reset(Adapter); } link_changed = B_FALSE; - mutex_enter(&Adapter->e1000g_linklock); + mutex_enter(&Adapter->link_lock); if (Adapter->link_complete) link_changed = e1000g_link_check(Adapter); - mutex_exit(&Adapter->e1000g_linklock); + mutex_exit(&Adapter->link_lock); if (link_changed) { /* @@ -2666,7 +2669,7 @@ * down event. Reset the adapter to recover it. */ if ((Adapter->link_state == LINK_STATE_DOWN) && - (hw->mac_type == e1000_80003es2lan)) + (hw->mac.type == e1000_80003es2lan)) (void) e1000g_reset(Adapter); mac_link_update(Adapter->mh, Adapter->link_state); @@ -2677,27 +2680,28 @@ * be overwritten when there is a reset on the other port. * Detect this circumstance and correct it. */ - if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { - ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); - ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); + if ((hw->mac.type == e1000_82571) && + (e1000_get_laa_state_82571(hw) == B_TRUE)) { + ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); + ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); ether_addr.reg.low = ntohl(ether_addr.reg.low); ether_addr.reg.high = ntohl(ether_addr.reg.high); - if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || - (ether_addr.mac.addr[4] != hw->mac_addr[1]) || - (ether_addr.mac.addr[3] != hw->mac_addr[2]) || - (ether_addr.mac.addr[2] != hw->mac_addr[3]) || - (ether_addr.mac.addr[1] != hw->mac_addr[4]) || - (ether_addr.mac.addr[0] != hw->mac_addr[5])) { - e1000_rar_set(hw, hw->mac_addr, 0); + if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || + (ether_addr.mac.addr[4] != hw->mac.addr[1]) || + (ether_addr.mac.addr[3] != hw->mac.addr[2]) || + (ether_addr.mac.addr[2] != hw->mac.addr[3]) || + (ether_addr.mac.addr[1] != hw->mac.addr[4]) || + (ether_addr.mac.addr[0] != hw->mac.addr[5])) { + e1000_rar_set(hw, hw->mac.addr, 0); } } /* - * RP: ttl_workaround : DCR 49 + * Long TTL workaround for 82541/82547 */ - e1000_igp_ttl_workaround(hw); + e1000_igp_ttl_workaround_82547(hw); /* * Check for Adaptive IFS settings If there are lots of collisions @@ -2712,9 +2716,9 @@ /* * Set Timer Interrupts */ - E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); - - restart_timeout(Adapter); + E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); + + restart_watchdog_timer(Adapter); } /* @@ -2730,37 +2734,29 @@ { struct e1000g *Adapter = (struct e1000g *)arg; - mutex_enter(&Adapter->e1000g_linklock); + mutex_enter(&Adapter->link_lock); Adapter->link_complete = B_TRUE; Adapter->link_tid = 0; - mutex_exit(&Adapter->e1000g_linklock); + mutex_exit(&Adapter->link_lock); } /* - * ********************************************************************** - * Name: e1000g_force_speed_duplex * - * * - * Description: * - * This function forces speed and duplex for 10/100 Mbps speeds * - * and also for 1000 Mbps speeds, it advertises half or full duplex * - * * - * Parameter Passed: * - * struct e1000g* (information of adpater) * - * * - * Return Value: * - * * - * Functions called: * - * ********************************************************************** + * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf + * + * This function read the forced speed and duplex for 10/100 Mbps speeds + * and also for 1000 Mbps speeds from the e1000g.conf file */ static void e1000g_force_speed_duplex(struct e1000g *Adapter) { int forced; + struct e1000_mac_info *mac = &Adapter->shared.mac; + struct e1000_phy_info *phy = &Adapter->shared.phy; /* * get value out of config file */ - forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", + forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); switch (forced) { @@ -2768,29 +2764,29 @@ /* * Disable Auto Negotiation */ - Adapter->Shared.autoneg = B_FALSE; - Adapter->Shared.forced_speed_duplex = e1000_10_half; + mac->autoneg = B_FALSE; + mac->forced_speed_duplex = ADVERTISE_10_HALF; break; case GDIAG_10_FULL: /* * Disable Auto Negotiation */ - Adapter->Shared.autoneg = B_FALSE; - Adapter->Shared.forced_speed_duplex = e1000_10_full; + mac->autoneg = B_FALSE; + mac->forced_speed_duplex = ADVERTISE_10_FULL; break; case GDIAG_100_HALF: /* * Disable Auto Negotiation */ - Adapter->Shared.autoneg = B_FALSE; - Adapter->Shared.forced_speed_duplex = e1000_100_half; + mac->autoneg = B_FALSE; + mac->forced_speed_duplex = ADVERTISE_100_HALF; break; case GDIAG_100_FULL: /* * Disable Auto Negotiation */ - Adapter->Shared.autoneg = B_FALSE; - Adapter->Shared.forced_speed_duplex = e1000_100_full; + mac->autoneg = B_FALSE; + mac->forced_speed_duplex = ADVERTISE_100_FULL; break; case GDIAG_1000_FULL: /* @@ -2800,13 +2796,13 @@ * 1000Mbps. This is different from 10/100 operation, where * we are allowed to link without any negotiation. */ - Adapter->Shared.autoneg = B_TRUE; - Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; + mac->autoneg = B_TRUE; + phy->autoneg_advertised = ADVERTISE_1000_FULL; break; default: /* obey the setting of AutoNegAdvertised */ - Adapter->Shared.autoneg = B_TRUE; - Adapter->Shared.autoneg_advertised = - (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", + mac->autoneg = B_TRUE; + phy->autoneg_advertised = + (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, AUTONEG_ADVERTISE_SPEED_DEFAULT); break; @@ -2814,224 +2810,210 @@ } /* - * ********************************************************************** - * Name: e1000g_get_max_frame_size * - * * - * Description: * - * This function reads MaxFrameSize from e1000g.conf and sets it for * - * adapter. * - * * - * Parameter Passed: * - * struct e1000g* (information of adpater) * - * * - * Return Value: * - * * - * Functions called: * - * ********************************************************************** + * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf + * + * This function reads MaxFrameSize from e1000g.conf */ static void e1000g_get_max_frame_size(struct e1000g *Adapter) { int max_frame; + struct e1000_mac_info *mac = &Adapter->shared.mac; + struct e1000_phy_info *phy = &Adapter->shared.phy; /* * get value out of config file */ - max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); + max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); switch (max_frame) { case 0: - Adapter->Shared.max_frame_size = ETHERMAX; + mac->max_frame_size = ETHERMAX; break; case 1: - Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; + mac->max_frame_size = FRAME_SIZE_UPTO_4K; break; case 2: - Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; + mac->max_frame_size = FRAME_SIZE_UPTO_8K; break; case 3: - if (Adapter->Shared.mac_type < e1000_82571) - Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; + if (mac->type < e1000_82571) + mac->max_frame_size = FRAME_SIZE_UPTO_16K; else - Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; + mac->max_frame_size = FRAME_SIZE_UPTO_9K; break; default: - Adapter->Shared.max_frame_size = ETHERMAX; + mac->max_frame_size = ETHERMAX; break; } /* switch */ /* ich8 does not do jumbo frames */ - if (Adapter->Shared.mac_type == e1000_ich8lan) { - Adapter->Shared.max_frame_size = ETHERMAX; + if (mac->type == e1000_ich8lan) { + mac->max_frame_size = ETHERMAX; + } + + /* ich9 does not do jumbo frames on one phy type */ + if ((mac->type == e1000_ich9lan) && + (phy->type == e1000_phy_ife)) { + mac->max_frame_size = ETHERMAX; } } static void -arm_timer(struct e1000g *Adapter) +arm_watchdog_timer(struct e1000g *Adapter) { - Adapter->WatchDogTimer_id = - timeout(e1000g_LocalTimer, + Adapter->watchdog_tid = + timeout(e1000g_local_timer, (void *)Adapter, 1 * drv_usectohz(1000000)); } +#pragma inline(arm_watchdog_timer) + +static void +enable_watchdog_timer(struct e1000g *Adapter) +{ + mutex_enter(&Adapter->watchdog_lock); + + if (!Adapter->watchdog_timer_enabled) { + Adapter->watchdog_timer_enabled = B_TRUE; + Adapter->watchdog_timer_started = B_TRUE; + arm_watchdog_timer(Adapter); + } + + mutex_exit(&Adapter->watchdog_lock); +} static void -enable_timeout(struct e1000g *Adapter) -{ - mutex_enter(&Adapter->e1000g_timeout_lock); - - if (!Adapter->timeout_enabled) { - Adapter->timeout_enabled = B_TRUE; - Adapter->timeout_started = B_TRUE; - - arm_timer(Adapter); - } - - mutex_exit(&Adapter->e1000g_timeout_lock); -} - -static void -disable_timeout(struct e1000g *Adapter) +disable_watchdog_timer(struct e1000g *Adapter) { timeout_id_t tid; - mutex_enter(&Adapter->e1000g_timeout_lock); - - Adapter->timeout_enabled = B_FALSE; - Adapter->timeout_started = B_FALSE; - - tid = Adapter->WatchDogTimer_id; - Adapter->WatchDogTimer_id = 0; - - mutex_exit(&Adapter->e1000g_timeout_lock); + mutex_enter(&Adapter->watchdog_lock); + + Adapter->watchdog_timer_enabled = B_FALSE; + Adapter->watchdog_timer_started = B_FALSE; + tid = Adapter->watchdog_tid; + Adapter->watchdog_tid = 0; + + mutex_exit(&Adapter->watchdog_lock); if (tid != 0) (void) untimeout(tid); } static void -start_timeout(struct e1000g *Adapter) +start_watchdog_timer(struct e1000g *Adapter) { - mutex_enter(&Adapter->e1000g_timeout_lock); - - if (Adapter->timeout_enabled) { - if (!Adapter->timeout_started) { - Adapter->timeout_started = B_TRUE; - arm_timer(Adapter); + mutex_enter(&Adapter->watchdog_lock); + + if (Adapter->watchdog_timer_enabled) { + if (!Adapter->watchdog_timer_started) { + Adapter->watchdog_timer_started = B_TRUE; + arm_watchdog_timer(Adapter); } } - mutex_exit(&Adapter->e1000g_timeout_lock); + mutex_exit(&Adapter->watchdog_lock); +} + +static void +restart_watchdog_timer(struct e1000g *Adapter) +{ + mutex_enter(&Adapter->watchdog_lock); + + if (Adapter->watchdog_timer_started) + arm_watchdog_timer(Adapter); + + mutex_exit(&Adapter->watchdog_lock); } static void -restart_timeout(struct e1000g *Adapter) +stop_watchdog_timer(struct e1000g *Adapter) { - mutex_enter(&Adapter->e1000g_timeout_lock); - - if (Adapter->timeout_started) - arm_timer(Adapter); - - mutex_exit(&Adapter->e1000g_timeout_lock); + timeout_id_t tid; + + mutex_enter(&Adapter->watchdog_lock); + + Adapter->watchdog_timer_started = B_FALSE; + tid = Adapter->watchdog_tid; + Adapter->watchdog_tid = 0; + + mutex_exit(&Adapter->watchdog_lock); + + if (tid != 0) + (void) untimeout(tid); } static void -stop_timeout(struct e1000g *Adapter) +stop_link_timer(struct e1000g *Adapter) { timeout_id_t tid; - mutex_enter(&Adapter->e1000g_timeout_lock); - - Adapter->timeout_started = B_FALSE; - - tid = Adapter->WatchDogTimer_id; - Adapter->WatchDogTimer_id = 0; - - mutex_exit(&Adapter->e1000g_timeout_lock); + /* Disable the link timer */ + mutex_enter(&Adapter->link_lock); + + tid = Adapter->link_tid; + Adapter->link_tid = 0; + + mutex_exit(&Adapter->link_lock); + + if (tid != 0) + (void) untimeout(tid); +} + +static void +stop_82547_timer(e1000g_tx_ring_t *tx_ring) +{ + timeout_id_t tid; + + /* Disable the tx timer for 82547 chipset */ + mutex_enter(&tx_ring->tx_lock); + + tx_ring->timer_enable_82547 = B_FALSE; + tid = tx_ring->timer_id_82547; + tx_ring->timer_id_82547 = 0; + + mutex_exit(&tx_ring->tx_lock); if (tid != 0) (void) untimeout(tid); } void -e1000g_DisableInterrupt(struct e1000g *Adapter) +e1000g_clear_interrupt(struct e1000g *Adapter) { - E1000_WRITE_REG(&Adapter->Shared, IMC, - 0xffffffff & ~E1000_IMC_RXSEQ); + E1000_WRITE_REG(&Adapter->shared, E1000_IMC, + 0xffffffff & ~E1000_IMS_RXSEQ); } void -e1000g_EnableInterrupt(struct e1000g *Adapter) +e1000g_mask_interrupt(struct e1000g *Adapter) { - E1000_WRITE_REG(&Adapter->Shared, IMS, + E1000_WRITE_REG(&Adapter->shared, E1000_IMS, IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); } void -e1000g_DisableAllInterrupts(struct e1000g *Adapter) -{ - E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) -} - -void -e1000g_EnableTxInterrupt(struct e1000g *Adapter) -{ - E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); -} - -void -e1000g_DisableTxInterrupt(struct e1000g *Adapter) +e1000g_clear_all_interrupts(struct e1000g *Adapter) { - E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); -} - -void -e1000_pci_set_mwi(struct e1000_hw *hw) -{ - uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; - e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); -} - -void -e1000_pci_clear_mwi(struct e1000_hw *hw) -{ - uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; - e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); + E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); } void -e1000_write_pci_cfg(struct e1000_hw *adapter, - uint32_t reg, uint16_t *value) +e1000g_mask_tx_interrupt(struct e1000g *Adapter) { - pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, - reg, *value); + E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000G_IMS_TX_INTR); } void -e1000_read_pci_cfg(struct e1000_hw *adapter, - uint32_t reg, uint16_t *value) +e1000g_clear_tx_interrupt(struct e1000g *Adapter) { - *value = - pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> - handle, reg); + E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000G_IMS_TX_INTR); } -#ifndef __sparc -void -e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) -{ - outl(port, value); -} - -uint32_t -e1000_io_read(struct e1000_hw *hw, unsigned long port) -{ - return (inl(port)); -} -#endif - static void -e1000g_smartspeed(struct e1000g *adapter) +e1000g_smartspeed(struct e1000g *Adapter) { + struct e1000_hw *hw = &Adapter->shared; uint16_t phy_status; uint16_t phy_ctrl; @@ -3039,27 +3021,25 @@ * If we're not T-or-T, or we're not autoneg'ing, or we're not * advertising 1000Full, we don't even use the workaround */ - if ((adapter->Shared.phy_type != e1000_phy_igp) || - !adapter->Shared.autoneg || - !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) + if ((hw->phy.type != e1000_phy_igp) || + !hw->mac.autoneg || + !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) return; /* * True if this is the first call of this function or after every * 30 seconds of not having link */ - if (adapter->smartspeed == 0) { + if (Adapter->smartspeed == 0) { /* * If Master/Slave config fault is asserted twice, we * assume back-to-back */ - e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, - &phy_status); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return; - e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, - &phy_status); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return; /* @@ -3067,8 +3047,7 @@ * insists! there's a fault in the master/slave * relationship that was "negotiated" */ - e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, - &phy_ctrl); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); /* * Is the phy configured for manual configuration of * master/slave? @@ -3079,22 +3058,21 @@ * auto configuration) of master/slave */ phy_ctrl &= ~CR_1000T_MS_ENABLE; - e1000_write_phy_reg(&adapter->Shared, + e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); /* * Effectively starting the clock */ - adapter->smartspeed++; + Adapter->smartspeed++; /* * Restart autonegotiation */ - if (!e1000_phy_setup_autoneg(&adapter->Shared) && - !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, - &phy_ctrl)) { + if (!e1000_phy_setup_autoneg(hw) && + !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); - e1000_write_phy_reg(&adapter->Shared, - PHY_CTRL, phy_ctrl); + e1000_write_phy_reg(hw, + PHY_CONTROL, phy_ctrl); } } return; @@ -3103,7 +3081,7 @@ * you should reset the smartspeed counter once you obtain * link */ - } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { + } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { /* * Yes. Remember, we did at the start determine that * there's a master/slave configuration fault, so we're @@ -3115,22 +3093,18 @@ /* * If still no link, perhaps using 2/3 pair cable */ - e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, - &phy_ctrl); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); phy_ctrl |= CR_1000T_MS_ENABLE; - e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, - phy_ctrl); + e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); /* * Restart autoneg with phy enabled for manual * configuration of master/slave */ - if (!e1000_phy_setup_autoneg(&adapter->Shared) && - !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, - &phy_ctrl)) { + if (!e1000_phy_setup_autoneg(hw) && + !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); - e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, - phy_ctrl); + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); } /* * Hopefully, there are no more faults and we've obtained @@ -3141,8 +3115,8 @@ * Restart process after E1000_SMARTSPEED_MAX iterations (30 * seconds) */ - if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) - adapter->smartspeed = 0; + if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) + Adapter->smartspeed = 0; } static boolean_t @@ -3160,47 +3134,41 @@ } /* - * ********************************************************************** - * Name: * - * e1000g_stall_check * - * * - * Description: * - * This function checks if the adapter is stalled. (In transmit) * - * * - * It is called each time the timeout is invoked. * - * If the transmit descriptor reclaim continuously fails, * - * the watchdog value will increment by 1. If the watchdog * - * value exceeds the threshold, the adapter is assumed to * - * have stalled and need to be reset. * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * B_TRUE - The dapter is assumed to have stalled. * - * B_FALSE * - * * - * ********************************************************************** + * e1000g_stall_check - check for tx stall + * + * This function checks if the adapter is stalled (in transmit). + * + * It is called each time the watchdog timeout is invoked. + * If the transmit descriptor reclaim continuously fails, + * the watchdog value will increment by 1. If the watchdog + * value exceeds the threshold, the adapter is assumed to + * have stalled and need to be reset. */ static boolean_t e1000g_stall_check(struct e1000g *Adapter) { + e1000g_tx_ring_t *tx_ring; + + tx_ring = Adapter->tx_ring; + if (Adapter->link_state != LINK_STATE_UP) return (B_FALSE); - if (Adapter->tx_recycle_fail > 0) - Adapter->StallWatchdog++; + if (tx_ring->recycle_fail > 0) + tx_ring->stall_watchdog++; else - Adapter->StallWatchdog = 0; - - if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) + tx_ring->stall_watchdog = 0; + + if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) return (B_FALSE); + tx_ring->stall_watchdog = 0; + tx_ring->recycle_fail = 0; + return (B_TRUE); } - +#ifdef E1000G_DEBUG static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) { @@ -3221,7 +3189,7 @@ break; deault: - e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", iocp->ioc_cmd); return (IOC_INVAL); @@ -3243,7 +3211,7 @@ switch (ppd->pp_acc_space) { default: - e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, "e1000g_diag_ioctl: invalid access space 0x%X\n", ppd->pp_acc_space); return (IOC_INVAL); @@ -3295,10 +3263,9 @@ ddi_acc_handle_t handle; uint32_t *regaddr; - handle = - ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; + handle = e1000gp->osdep.reg_handle; regaddr = - (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); + (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); ppd->pp_acc_data = ddi_get32(handle, regaddr); } @@ -3310,10 +3277,9 @@ uint32_t *regaddr; uint32_t value; - handle = - ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; + handle = e1000gp->osdep.reg_handle; regaddr = - (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); + (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); value = (uint32_t)ppd->pp_acc_data; ddi_put32(handle, regaddr, value); @@ -3345,7 +3311,7 @@ break; } - e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", (void *)e1000gp, (void *)ppd, value, vaddr); @@ -3361,7 +3327,7 @@ vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; value = ppd->pp_acc_data; - e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", (void *)e1000gp, (void *)ppd, value, vaddr); @@ -3383,6 +3349,7 @@ break; } } +#endif /* * Loopback Support @@ -3410,7 +3377,7 @@ uint16_t phy_status; uint16_t phy_ext_status; - hw = &Adapter->Shared; + hw = &Adapter->shared; if (mp->b_cont == NULL) return (IOC_INVAL); @@ -3433,7 +3400,7 @@ (hw->media_type == e1000_media_type_fiber) || (hw->media_type == e1000_media_type_internal_serdes)) { value += sizeof (lb_phy); - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82571: case e1000_82572: value += sizeof (lb_external1000); @@ -3460,7 +3427,7 @@ (hw->media_type == e1000_media_type_fiber) || (hw->media_type == e1000_media_type_internal_serdes)) { value += sizeof (lb_phy); - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82571: case e1000_82572: value += sizeof (lb_external1000); @@ -3485,7 +3452,7 @@ (hw->media_type == e1000_media_type_fiber) || (hw->media_type == e1000_media_type_internal_serdes)) { lbpp[value++] = lb_phy; - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82571: case e1000_82572: lbpp[value++] = lb_external1000; @@ -3537,7 +3504,7 @@ if (mode == Adapter->loopback_mode) return (B_TRUE); - hw = &Adapter->Shared; + hw = &Adapter->shared; times = 0; again: @@ -3549,9 +3516,9 @@ /* Get original speed and duplex settings */ e1000g_force_speed_duplex(Adapter); /* Reset the chip */ - hw->wait_autoneg_complete = B_TRUE; + hw->phy.wait_for_link = B_TRUE; (void) e1000g_reset(Adapter); - hw->wait_autoneg_complete = B_FALSE; + hw->phy.wait_for_link = B_FALSE; break; case E1000G_LB_EXTERNAL_1000: @@ -3579,15 +3546,15 @@ case E1000G_LB_EXTERNAL_10: case E1000G_LB_INTERNAL_PHY: /* Wait for link up */ - for (i = (PHY_FORCE_TIME * 2); i > 0; i--) + for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) msec_delay(100); if (!e1000g_link_up(Adapter)) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "Failed to get the link up"); if (times < 2) { /* Reset the link */ - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "Reset the link ..."); (void) e1000g_reset(Adapter); goto again; @@ -3615,16 +3582,16 @@ uint32_t status; uint16_t phy_ctrl; - hw = &Adapter->Shared; + hw = &Adapter->shared; /* Disable Smart Power Down */ phy_spd_state(hw, B_FALSE); - e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); + e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82540: case e1000_82545: case e1000_82545_rev_3: @@ -3634,28 +3601,28 @@ /* Auto-MDI/MDIX off */ e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); /* Reset PHY to update Auto-MDI/MDIX */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); /* Reset PHY to auto-neg off and force 1000 */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_RESET); break; } /* Set loopback */ - e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); msec_delay(250); /* Now set up the MAC to the same speed/duplex as the PHY. */ - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ E1000_CTRL_FD); /* Force Duplex to FULL */ - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82540: case e1000_82545: case e1000_82545_rev_3: @@ -3666,9 +3633,9 @@ * so that the status is updated on link */ if (hw->media_type == e1000_media_type_internal_serdes) { - E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); msec_delay(100); - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); } if (hw->media_type == e1000_media_type_copper) { @@ -3676,7 +3643,7 @@ ctrl |= E1000_CTRL_ILOS; } else { /* Set ILOS on fiber nic if half duplex is detected */ - status = E1000_READ_REG(hw, STATUS); + status = E1000_READ_REG(hw, E1000_STATUS); if ((status & E1000_STATUS_FD) == 0) ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; } @@ -3686,7 +3653,7 @@ case e1000_82572: if (hw->media_type != e1000_media_type_copper) { /* Set ILOS on fiber nic if half duplex is detected */ - status = E1000_READ_REG(hw, STATUS); + status = E1000_READ_REG(hw, E1000_STATUS); if ((status & E1000_STATUS_FD) == 0) ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; } @@ -3697,13 +3664,13 @@ break; } - E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); /* * Disable PHY receiver for 82540/545/546 and 82573 Family. * For background, see comments above e1000g_set_internal_loopback(). */ - switch (hw->mac_type) { + switch (hw->mac.type) { case e1000_82540: case e1000_82545: case e1000_82545_rev_3: @@ -3728,7 +3695,7 @@ uint32_t status; uint32_t txcw; - hw = &Adapter->Shared; + hw = &Adapter->shared; /* Disable Smart Power Down */ phy_spd_state(hw, B_FALSE); @@ -3736,27 +3703,27 @@ switch (hw->media_type) { case e1000_media_type_copper: /* Force link up (Must be done before the PHY writes) */ - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl |= E1000_CTRL_SLU; /* Force Link Up */ - E1000_WRITE_REG(hw, CTRL, ctrl); - - rctl = E1000_READ_REG(hw, RCTL); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + rctl = E1000_READ_REG(hw, E1000_RCTL); rctl |= (E1000_RCTL_EN | E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE | E1000_RCTL_BAM); /* 0x803E */ - E1000_WRITE_REG(hw, RCTL, rctl); - - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + E1000_WRITE_REG(hw, E1000_RCTL, rctl); + + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | E1000_CTRL_EXT_SDP6_DATA | E1000_CTRL_EXT_SDP7_DATA | E1000_CTRL_EXT_SDP4_DIR | E1000_CTRL_EXT_SDP6_DIR | E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); /* * This sequence tunes the PHY's SDP and no customer @@ -3782,24 +3749,24 @@ break; case e1000_media_type_fiber: case e1000_media_type_internal_serdes: - status = E1000_READ_REG(hw, STATUS); + status = E1000_READ_REG(hw, E1000_STATUS); if (((status & E1000_STATUS_LU) == 0) || (hw->media_type == e1000_media_type_internal_serdes)) { - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; - E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); } /* Disable autoneg by setting bit 31 of TXCW to zero */ - txcw = E1000_READ_REG(hw, TXCW); + txcw = E1000_READ_REG(hw, E1000_TXCW); txcw &= ~((uint32_t)1 << 31); - E1000_WRITE_REG(hw, TXCW, txcw); + E1000_WRITE_REG(hw, E1000_TXCW, txcw); /* * Write 0x410 to Serdes Control register * to enable Serdes analog loopback */ - E1000_WRITE_REG(hw, SCTL, 0x0410); + E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); msec_delay(10); break; default: @@ -3814,7 +3781,7 @@ uint32_t ctrl; uint16_t phy_ctrl; - hw = &Adapter->Shared; + hw = &Adapter->shared; /* Disable Smart Power Down */ phy_spd_state(hw, B_FALSE); @@ -3823,17 +3790,17 @@ MII_CR_SPEED_100); /* Force 100/FD, reset PHY */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_RESET); /* 0xA100 */ msec_delay(10); /* Force 100/FD */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); /* 0x2100 */ msec_delay(10); /* Now setup the MAC to the same speed/duplex as the PHY. */ - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ @@ -3841,7 +3808,7 @@ E1000_CTRL_SPD_100 | /* Force Speed to 100 */ E1000_CTRL_FD); /* Force Duplex to FULL */ - E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); } static void @@ -3851,7 +3818,7 @@ uint32_t ctrl; uint16_t phy_ctrl; - hw = &Adapter->Shared; + hw = &Adapter->shared; /* Disable Smart Power Down */ phy_spd_state(hw, B_FALSE); @@ -3860,17 +3827,17 @@ MII_CR_SPEED_10); /* Force 10/FD, reset PHY */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_RESET); /* 0x8100 */ msec_delay(10); /* Force 10/FD */ - e1000_write_phy_reg(hw, PHY_CTRL, + e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); /* 0x0100 */ msec_delay(10); /* Now setup the MAC to the same speed/duplex as the PHY. */ - ctrl = E1000_READ_REG(hw, CTRL); + ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ @@ -3878,13 +3845,14 @@ E1000_CTRL_SPD_10 | /* Force Speed to 10 */ E1000_CTRL_FD); /* Force Duplex to FULL */ - E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); } #ifdef __sparc static boolean_t e1000g_find_mac_address(struct e1000g *Adapter) { + struct e1000_hw *hw = &Adapter->shared; uchar_t *bytes; struct ether_addr sysaddr; uint_t nelts; @@ -3905,7 +3873,7 @@ if (err == DDI_PROP_SUCCESS) { if (nelts == ETHERADDRL) { while (nelts--) - Adapter->Shared.mac_addr[nelts] = bytes[nelts]; + hw->mac.addr[nelts] = bytes[nelts]; found = B_TRUE; } ddi_prop_free(bytes); @@ -3919,8 +3887,7 @@ "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { if (localetheraddr(NULL, &sysaddr) != 0) { - bcopy(&sysaddr, Adapter->Shared.mac_addr, - ETHERADDRL); + bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); found = B_TRUE; } } @@ -3938,14 +3905,14 @@ if (err == DDI_PROP_SUCCESS) { if (nelts == ETHERADDRL) { while (nelts--) - Adapter->Shared.mac_addr[nelts] = bytes[nelts]; + hw->mac.addr[nelts] = bytes[nelts]; found = B_TRUE; } ddi_prop_free(bytes); } if (found) { - bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, + bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); } @@ -3966,7 +3933,7 @@ rc = ddi_intr_get_supported_types(devinfo, &intr_types); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Get supported interrupt types failed: %d\n", rc); return (DDI_FAILURE); } @@ -3978,14 +3945,14 @@ * So we should only enable MSI for PCI-E NICs and disable MSI for old * PCI/PCI-X NICs. */ - if (Adapter->Shared.mac_type < e1000_82571) + if (Adapter->shared.mac.type < e1000_82571) Adapter->msi_enabled = B_FALSE; if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Add MSI failed, trying Legacy interrupts\n"); } else { Adapter->intr_type = DDI_INTR_TYPE_MSI; @@ -3997,7 +3964,7 @@ rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "Add Legacy interrupts failed\n"); return (DDI_FAILURE); } @@ -4006,7 +3973,7 @@ } if (Adapter->intr_type == 0) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, "No interrupts registered\n"); return (DDI_FAILURE); } @@ -4031,7 +3998,7 @@ /* get number of interrupts */ rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); if ((rc != DDI_SUCCESS) || (count == 0)) { - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Get interrupt number failed. Return: %d, count: %d\n", rc, count); return (DDI_FAILURE); @@ -4040,14 +4007,14 @@ /* get number of available interrupts */ rc = ddi_intr_get_navail(devinfo, intr_type, &avail); if ((rc != DDI_SUCCESS) || (avail == 0)) { - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Get interrupt available number failed. " "Return: %d, available: %d\n", rc, avail); return (DDI_FAILURE); } if (avail < count) { - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Interrupts count: %d, available: %d\n", count, avail); } @@ -4064,7 +4031,7 @@ count, &actual, flag); if ((rc != DDI_SUCCESS) || (actual == 0)) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Allocate interrupts failed: %d\n", rc); kmem_free(Adapter->htable, Adapter->intr_size); @@ -4072,7 +4039,7 @@ } if (actual < count) { - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, "Interrupts requested: %d, received: %d\n", count, actual); } @@ -4083,7 +4050,7 @@ rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Get interrupt priority failed: %d\n", rc); /* Free already allocated intr */ @@ -4100,7 +4067,7 @@ * to avoid interrupt stealing when sharing interrupt with other * devices. */ - if (Adapter->Shared.mac_type < e1000_82571) + if (Adapter->shared.mac.type < e1000_82571) intr_handler = (ddi_intr_handler_t *)e1000g_intr; else intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; @@ -4111,7 +4078,7 @@ intr_handler, (caddr_t)Adapter, NULL); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Add interrupt handler failed: %d\n", rc); /* Remove already added handler */ @@ -4131,7 +4098,7 @@ rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Get interrupt cap failed: %d\n", rc); /* Free already allocated intr */ @@ -4156,14 +4123,14 @@ for (x = 0; x < Adapter->intr_cnt; x++) { rc = ddi_intr_remove_handler(Adapter->htable[x]); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Remove intr handler failed: %d\n", rc); return (DDI_FAILURE); } rc = ddi_intr_free(Adapter->htable[x]); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Free intr failed: %d\n", rc); return (DDI_FAILURE); } @@ -4186,7 +4153,7 @@ rc = ddi_intr_block_enable(Adapter->htable, Adapter->intr_cnt); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Enable block intr failed: %d\n", rc); return (DDI_FAILURE); } @@ -4195,7 +4162,7 @@ for (x = 0; x < Adapter->intr_cnt; x++) { rc = ddi_intr_enable(Adapter->htable[x]); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Enable intr failed: %d\n", rc); return (DDI_FAILURE); } @@ -4216,7 +4183,7 @@ rc = ddi_intr_block_disable(Adapter->htable, Adapter->intr_cnt); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Disable block intr failed: %d\n", rc); return (DDI_FAILURE); } @@ -4224,7 +4191,7 @@ for (x = 0; x < Adapter->intr_cnt; x++) { rc = ddi_intr_disable(Adapter->htable[x]); if (rc != DDI_SUCCESS) { - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Disable intr failed: %d\n", rc); return (DDI_FAILURE); } @@ -4233,79 +4200,3 @@ return (DDI_SUCCESS); } - -/* - * phy_spd_state - set smart-power-down (SPD) state - * - * This only acts on the 82541/47 family and the 82571/72 family. - * For any others, return without doing anything. - */ -void -phy_spd_state(struct e1000_hw *hw, boolean_t enable) -{ - int32_t offset; /* offset to register */ - uint16_t spd_bit; /* bit to be set */ - uint16_t reg; /* register contents */ - - switch (hw->mac_type) { - case e1000_82541: - case e1000_82547: - case e1000_82541_rev_2: - case e1000_82547_rev_2: - offset = IGP01E1000_GMII_FIFO; - spd_bit = IGP01E1000_GMII_SPD; - break; - case e1000_82571: - case e1000_82572: - offset = IGP02E1000_PHY_POWER_MGMT; - spd_bit = IGP02E1000_PM_SPD; - break; - default: - return; /* no action */ - } - - e1000_read_phy_reg(hw, offset, ®); - - if (enable) - reg |= spd_bit; /* enable: set the spd bit */ - else - reg &= ~spd_bit; /* disable: clear the spd bit */ - - e1000_write_phy_reg(hw, offset, reg); -} - -/* - * The real intent of this routine is to return the value from pci-e - * config space at offset reg into the capability space. - * ICH devices are "PCI Express"-ish. They have a configuration space, - * but do not contain PCI Express Capability registers, so this returns - * the equivalent of "not supported" - */ -int32_t -e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) -{ - *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, - PCI_EX_CONF_CAP + reg); - - return (0); -} - -/* - * Enables PCI-Express master access. - * - * hw: Struct containing variables accessed by shared code - * - * returns: - none. - */ -void -e1000_enable_pciex_master(struct e1000_hw *hw) -{ - uint32_t ctrl; - - if (hw->bus_type != e1000_bus_type_pci_express) - return; - - ctrl = E1000_READ_REG(hw, CTRL); - ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; - E1000_WRITE_REG(hw, CTRL, ctrl); -}
--- a/usr/src/uts/common/io/e1000g/e1000g_ndd.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_ndd.c Tue Aug 21 00:30:10 2007 -0700 @@ -109,55 +109,44 @@ { PARAM_LINK_DUPLEX, 0, 2, 0, NULL, "-link_duplex" }, { PARAM_LINK_AUTONEG, 0, 1, 0, NULL, "-link_autoneg" }, -/* Max Frame Size */ -{ PARAM_MAX_FRAME_SIZE, ETHERMAX, FRAME_SIZE_UPTO_16K, ETHERMAX, - NULL, "-max_frame_size" }, -/* Loopback mode */ -{ PARAM_LOOP_MODE, 0, 4, 0, NULL, "-loopback_mode" }, -/* Interrupt Type */ -{ PARAM_INTR_TYPE, 0, 4, 0, NULL, "-interrupt_type" }, - /* Tx Bcopy Threshold */ -{ PARAM_TX_BCOPY_THRESHOLD, MINTXBCOPYTHRESHOLD, - MAXTXBCOPYTHRESHOLD, - DEFAULTTXBCOPYTHRESHOLD, +{ PARAM_TX_BCOPY_THRESHOLD, MIN_TX_BCOPY_THRESHOLD, + MAX_TX_BCOPY_THRESHOLD, + DEFAULT_TX_BCOPY_THRESHOLD, NULL, "+tx_bcopy_threshold" }, -/* Tx Bcopy Fragments Limit */ -{ PARAM_TX_FRAGS_LIMIT, MINTXFRAGSLIMIT, - MAXTXFRAGSLIMIT, - DEFAULTTXFRAGSLIMIT, - NULL, "-tx_bcopy_frags_limit" }, -/* Tx Recycle Low-Water */ -{ PARAM_TX_RECYCLE_LOW_WATER, MINTXRECYCLELOWWATER, - MAXTXRECYCLELOWWATER, - DEFAULTTXRECYCLELOWWATER, - NULL, "+tx_recycle_low_water" }, -/* Tx Recycle Number */ -{ PARAM_TX_RECYCLE_NUM, MINTXRECYCLENUM, - MAXTXRECYCLENUM, - DEFAULTTXRECYCLENUM, - NULL, "+tx_recycle_num" }, /* Tx Interrupt Enable */ -{ PARAM_TX_INTR_ENABLE, 0, 1, 1, NULL, "+tx_interrupt_enable" }, +{ PARAM_TX_INTR_ENABLE, 0, 1, DEFAULT_TX_INTR_ENABLE, + NULL, "+tx_interrupt_enable" }, +/* Tx Interrupt Delay */ +{ PARAM_TX_TIDV, MIN_TX_INTR_DELAY, + MAX_TX_INTR_DELAY, + DEFAULT_TX_INTR_DELAY, + NULL, "+tx_intr_delay" }, /* Tx Interrupt Delay */ -{ PARAM_TX_INTR_DELAY, MINTXINTERRUPTDELAYVAL, - MAXTXINTERRUPTDELAYVAL, - DEFAULTTXINTERRUPTDELAYVAL, - NULL, "+tx_interrupt_delay" }, +{ PARAM_TX_TADV, MIN_TX_INTR_ABS_DELAY, + MAX_TX_INTR_ABS_DELAY, + DEFAULT_TX_INTR_ABS_DELAY, + NULL, "+tx_intr_abs_delay" }, /* Rx Bcopy Threshold */ -{ PARAM_RX_BCOPY_THRESHOLD, MINRXBCOPYTHRESHOLD, - MAXRXBCOPYTHRESHOLD, - DEFAULTRXBCOPYTHRESHOLD, +{ PARAM_RX_BCOPY_THRESHOLD, MIN_RX_BCOPY_THRESHOLD, + MAX_RX_BCOPY_THRESHOLD, + DEFAULT_RX_BCOPY_THRESHOLD, NULL, "+rx_bcopy_threshold" }, /* Rx Max Receive Packets Per Interrupt */ -{ PARAM_RX_PKT_ON_INTR, MINNUMRCVPKTONINTR, - MAXNUMRCVPKTONINTR, - DEFAULTMAXNUMRCVPKTONINTR, +{ PARAM_RX_PKT_ON_INTR, MIN_RX_LIMIT_ON_INTR, + MAX_RX_LIMIT_ON_INTR, + DEFAULT_RX_LIMIT_ON_INTR, NULL, "+max_num_rcv_packets" }, /* Receive Delay Timer Register */ -{ PARAM_RX_RDTR, 0, 65535, 0, NULL, "+rx_intr_delay" }, +{ PARAM_RX_RDTR, MIN_RX_INTR_DELAY, + MAX_RX_INTR_DELAY, + DEFAULT_RX_INTR_DELAY, + NULL, "+rx_intr_delay" }, /* Receive Interrupt Absolute Delay Register */ -{ PARAM_RX_RADV, 0, 65535, 0, NULL, "+rx_intr_abs_delay" }, +{ PARAM_RX_RADV, MIN_RX_INTR_ABS_DELAY, + MAX_RX_INTR_ABS_DELAY, + DEFAULT_RX_INTR_ABS_DELAY, + NULL, "+rx_intr_abs_delay" }, /* Terminator */ { PARAM_COUNT, 0, 0, 0, NULL, NULL } @@ -224,7 +213,7 @@ nm = &ndp->ndp_name[0]; setfn = e1000g_nd_set; - if (Adapter->Shared.media_type != e1000_media_type_copper) { + if (Adapter->shared.media_type != e1000_media_type_copper) { switch (*nm) { default: break; @@ -268,9 +257,9 @@ return (DDI_SUCCESS); nd_fail: - e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, - "e1000g_nd_param_load: FAILED at index %d [info %d]", - tmplp-nd_template, tmplp->ndp_info); + E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, + "e1000g_nd_param_load: FAILED at index %d [info %d]", + tmplp-nd_template, tmplp->ndp_info); nd_free(nddpp); return (DDI_FAILURE); } @@ -279,183 +268,156 @@ e1000g_nd_get_param_val(nd_param_t *ndp) { struct e1000g *Adapter; + struct e1000_hw *hw; uint16_t phy_reg; Adapter = ndp->ndp_instance; ASSERT(Adapter); + hw = &Adapter->shared; switch (ndp->ndp_info) { /* Hardware Capabilities */ case PARAM_AUTONEG_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & MII_SR_AUTONEG_CAPS) ? 1 : 0; break; case PARAM_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; break; case PARAM_ASYM_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; break; case PARAM_1000FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_EXT_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); ndp->ndp_val = ((phy_reg & IEEE_ESR_1000T_FD_CAPS) || (phy_reg & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; break; case PARAM_1000HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_EXT_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); ndp->ndp_val = ((phy_reg & IEEE_ESR_1000T_HD_CAPS) || (phy_reg & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; break; case PARAM_100T4_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & MII_SR_100T4_CAPS) ? 1 : 0; break; case PARAM_100FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = ((phy_reg & MII_SR_100X_FD_CAPS) || (phy_reg & MII_SR_100T2_FD_CAPS)) ? 1 : 0; break; case PARAM_100HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = ((phy_reg & MII_SR_100X_HD_CAPS) || (phy_reg & MII_SR_100T2_HD_CAPS)) ? 1 : 0; break; case PARAM_10FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & MII_SR_10T_FD_CAPS) ? 1 : 0; break; case PARAM_10HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & MII_SR_10T_HD_CAPS) ? 1 : 0; break; /* Auto-Negotiation Advertisement Capabilities */ case PARAM_ADV_AUTONEG_CAP: - ndp->ndp_val = Adapter->Shared.autoneg; + ndp->ndp_val = hw->mac.autoneg; break; case PARAM_ADV_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; break; case PARAM_ADV_ASYM_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; break; case PARAM_ADV_1000FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_CTRL, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); ndp->ndp_val = (phy_reg & CR_1000T_FD_CAPS) ? 1 : 0; break; case PARAM_ADV_1000HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_CTRL, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); ndp->ndp_val = (phy_reg & CR_1000T_HD_CAPS) ? 1 : 0; break; case PARAM_ADV_100T4_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_100T4_CAPS) ? 1 : 0; break; case PARAM_ADV_100FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; break; case PARAM_ADV_100HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; break; case PARAM_ADV_10FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_10T_FD_CAPS) ? 1 : 0; break; case PARAM_ADV_10HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_AR_10T_HD_CAPS) ? 1 : 0; break; /* Link-Partner's Advertisement Capabilities */ case PARAM_LP_AUTONEG_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_EXP, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; break; case PARAM_LP_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_PAUSE) ? 1 : 0; break; case PARAM_LP_ASYM_PAUSE_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_ASM_DIR) ? 1 : 0; break; case PARAM_LP_1000FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & SR_1000T_LP_FD_CAPS) ? 1 : 0; break; case PARAM_LP_1000HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); ndp->ndp_val = (phy_reg & SR_1000T_LP_HD_CAPS) ? 1 : 0; break; case PARAM_LP_100T4_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_100T4_CAPS) ? 1 : 0; break; case PARAM_LP_100FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; break; case PARAM_LP_100HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; break; case PARAM_LP_10FDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; break; case PARAM_LP_10HDX_CAP: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); ndp->ndp_val = (phy_reg & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; break; /* Force Speed and Duplex Parameter */ case PARAM_FORCE_SPEED_DUPLEX: - switch (Adapter->Shared.forced_speed_duplex) { - case e1000_10_half: + switch (hw->mac.forced_speed_duplex) { + case ADVERTISE_10_HALF: ndp->ndp_val = GDIAG_10_HALF; break; - case e1000_10_full: + case ADVERTISE_10_FULL: ndp->ndp_val = GDIAG_10_FULL; break; - case e1000_100_half: + case ADVERTISE_100_HALF: ndp->ndp_val = GDIAG_100_HALF; break; - case e1000_100_full: + case ADVERTISE_100_FULL: ndp->ndp_val = GDIAG_100_FULL; break; } @@ -471,12 +433,12 @@ ndp->ndp_val = Adapter->link_duplex; break; case PARAM_LINK_AUTONEG: - ndp->ndp_val = Adapter->Shared.autoneg; + ndp->ndp_val = hw->mac.autoneg; break; /* Driver Properties */ case PARAM_MAX_FRAME_SIZE: - ndp->ndp_val = Adapter->Shared.max_frame_size; + ndp->ndp_val = hw->mac.max_frame_size; break; case PARAM_LOOP_MODE: ndp->ndp_val = Adapter->loopback_mode; @@ -489,32 +451,26 @@ case PARAM_TX_BCOPY_THRESHOLD: ndp->ndp_val = Adapter->tx_bcopy_thresh; break; - case PARAM_TX_FRAGS_LIMIT: - ndp->ndp_val = Adapter->tx_frags_limit; - break; - case PARAM_TX_RECYCLE_LOW_WATER: - ndp->ndp_val = Adapter->tx_recycle_low_water; - break; - case PARAM_TX_RECYCLE_NUM: - ndp->ndp_val = Adapter->tx_recycle_num; - break; case PARAM_TX_INTR_ENABLE: ndp->ndp_val = Adapter->tx_intr_enable; break; - case PARAM_TX_INTR_DELAY: - ndp->ndp_val = Adapter->TxInterruptDelay; + case PARAM_TX_TIDV: + ndp->ndp_val = Adapter->tx_intr_delay; + break; + case PARAM_TX_TADV: + ndp->ndp_val = Adapter->tx_intr_abs_delay; break; case PARAM_RX_BCOPY_THRESHOLD: ndp->ndp_val = Adapter->rx_bcopy_thresh; break; case PARAM_RX_PKT_ON_INTR: - ndp->ndp_val = Adapter->MaxNumReceivePackets; + ndp->ndp_val = Adapter->rx_limit_onintr; break; case PARAM_RX_RDTR: - ndp->ndp_val = E1000_READ_REG(&Adapter->Shared, RDTR); + ndp->ndp_val = Adapter->rx_intr_delay; break; case PARAM_RX_RADV: - ndp->ndp_val = E1000_READ_REG(&Adapter->Shared, RADV); + ndp->ndp_val = Adapter->rx_intr_abs_delay; break; default: break; @@ -525,6 +481,8 @@ e1000g_nd_set_param_val(nd_param_t *ndp, uint32_t value) { struct e1000g *Adapter; + struct e1000_hw *hw; + e1000g_tx_ring_t *tx_ring; uint16_t autoneg_advertised; uint8_t forced_speed_duplex; boolean_t autoneg_enable; @@ -532,6 +490,8 @@ Adapter = ndp->ndp_instance; ASSERT(Adapter); + hw = &Adapter->shared; + tx_ring = Adapter->tx_ring; autoneg_advertised = 0; forced_speed_duplex = 0; @@ -544,53 +504,49 @@ case PARAM_TX_BCOPY_THRESHOLD: ndp->ndp_val = value; Adapter->tx_bcopy_thresh = value; - Adapter->tx_frags_limit = (Adapter->Shared.max_frame_size / + tx_ring->frags_limit = (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; - if (Adapter->tx_frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) - Adapter->tx_frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); - goto finished; - case PARAM_TX_RECYCLE_LOW_WATER: - ndp->ndp_val = value; - Adapter->tx_recycle_low_water = value; - goto finished; - case PARAM_TX_RECYCLE_NUM: - ndp->ndp_val = value; - Adapter->tx_recycle_num = value; + if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) + tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); goto finished; case PARAM_TX_INTR_ENABLE: ndp->ndp_val = value; Adapter->tx_intr_enable = (value == 1) ? B_TRUE : B_FALSE; if (Adapter->tx_intr_enable) - e1000g_EnableTxInterrupt(Adapter); + e1000g_mask_tx_interrupt(Adapter); else - e1000g_DisableTxInterrupt(Adapter); + e1000g_clear_tx_interrupt(Adapter); goto finished; - case PARAM_TX_INTR_DELAY: + case PARAM_TX_TIDV: ndp->ndp_val = value; - Adapter->TxInterruptDelay = value; - /* - * Setup Transmit Interrupt Delay Value - */ - if (Adapter->TxInterruptDelay) { - E1000_WRITE_REG(&Adapter->Shared, TIDV, - Adapter->TxInterruptDelay); + Adapter->tx_intr_delay = value; + /* A value of zero is not allowed for TIDV */ + if (Adapter->tx_intr_delay) { + E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); } goto finished; + case PARAM_TX_TADV: + ndp->ndp_val = value; + Adapter->tx_intr_abs_delay = value; + E1000_WRITE_REG(hw, E1000_TADV, Adapter->tx_intr_abs_delay); + goto finished; case PARAM_RX_BCOPY_THRESHOLD: ndp->ndp_val = value; Adapter->rx_bcopy_thresh = value; goto finished; case PARAM_RX_PKT_ON_INTR: ndp->ndp_val = value; - Adapter->MaxNumReceivePackets = value; + Adapter->rx_limit_onintr = value; goto finished; case PARAM_RX_RDTR: ndp->ndp_val = value; - E1000_WRITE_REG(&Adapter->Shared, RDTR, value); + Adapter->rx_intr_delay = value; + E1000_WRITE_REG(hw, E1000_RDTR, value); goto finished; case PARAM_RX_RADV: ndp->ndp_val = value; - E1000_WRITE_REG(&Adapter->Shared, RADV, value); + Adapter->rx_intr_abs_delay = value; + E1000_WRITE_REG(hw, E1000_RADV, value); goto finished; default: break; @@ -617,16 +573,16 @@ switch (Adapter->param_force_speed_duplex) { case GDIAG_10_HALF: - forced_speed_duplex = e1000_10_half; + forced_speed_duplex = ADVERTISE_10_HALF; break; case GDIAG_10_FULL: - forced_speed_duplex = e1000_10_full; + forced_speed_duplex = ADVERTISE_10_FULL; break; case GDIAG_100_HALF: - forced_speed_duplex = e1000_100_half; + forced_speed_duplex = ADVERTISE_100_HALF; break; case GDIAG_100_FULL: - forced_speed_duplex = e1000_100_full; + forced_speed_duplex = ADVERTISE_100_FULL; break; default: ASSERT(B_FALSE); @@ -738,16 +694,16 @@ link_change = B_TRUE; switch (value) { case GDIAG_10_HALF: - forced_speed_duplex = e1000_10_half; + forced_speed_duplex = ADVERTISE_10_HALF; break; case GDIAG_10_FULL: - forced_speed_duplex = e1000_10_full; + forced_speed_duplex = ADVERTISE_10_FULL; break; case GDIAG_100_HALF: - forced_speed_duplex = e1000_100_half; + forced_speed_duplex = ADVERTISE_100_HALF; break; case GDIAG_100_FULL: - forced_speed_duplex = e1000_100_full; + forced_speed_duplex = ADVERTISE_100_FULL; break; default: ASSERT(B_FALSE); @@ -768,20 +724,16 @@ goto finished; } - Adapter->Shared.autoneg = B_TRUE; - Adapter->Shared.autoneg_advertised = - autoneg_advertised; + hw->mac.autoneg = B_TRUE; + hw->phy.autoneg_advertised = autoneg_advertised; } else { - Adapter->Shared.autoneg = B_FALSE; - Adapter->Shared.forced_speed_duplex = - forced_speed_duplex; + hw->mac.autoneg = B_FALSE; + hw->mac.forced_speed_duplex = forced_speed_duplex; } ndp->ndp_val = value; - rw_exit(&Adapter->chip_lock); - (void) e1000g_reset(Adapter); - return; + e1000_setup_link(hw); } finished:
--- a/usr/src/uts/common/io/e1000g/e1000g_rx.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_rx.c Tue Aug 21 00:30:10 2007 -0700 @@ -32,18 +32,11 @@ * e1000g_rx.c * * * * Abstract: * - * This file contains some routines that takes care of Receive * - * interrupt and also for the received packet * - * it sends up to upper layer. * + * This file contains some routines that take care of Receive * + * interrupt and also for the received packets it sends up to * + * upper layer. * * It tries to do a zero copy if free buffers are available in * - * the pool. Also it implements shortcut to Ipq * - * * - * * - * This driver runs on the following hardware: * - * - Wisemane based PCI gigabit ethernet adapters * - * * - * Environment: * - * Kernel Mode - * + * the pool. * * * * ********************************************************************** */ @@ -51,37 +44,25 @@ #include "e1000g_sw.h" #include "e1000g_debug.h" -/* - * local prototypes - */ -static RX_SW_PACKET *e1000g_get_buf(e1000g_rx_ring_t *rx_ring); +static p_rx_sw_packet_t e1000g_get_buf(e1000g_rx_ring_t *rx_ring); #pragma inline(e1000g_get_buf) /* - * ********************************************************************** - * Name: e1000g_rxfree_func * - * * - * Description: * - * * - * This functionis called when a mp is freed by the user thru * - * freeb call (Only for mp constructed through desballoc call) * - * It returns back the freed buffer to the freelist * - * * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * * - * ********************************************************************** + * e1000g_rxfree_func - the call-back function to reclaim rx buffer + * + * This function is called when an mp is freed by the user thru + * freeb call (Only for mp constructed through desballoc call) + * It returns back the freed buffer to the freelist */ void -e1000g_rxfree_func(RX_SW_PACKET *packet) +e1000g_rxfree_func(p_rx_sw_packet_t packet) { struct e1000g *Adapter; e1000g_rx_ring_t *rx_ring; + rx_ring = (e1000g_rx_ring_t *)packet->rx_ring; + Adapter = rx_ring->adapter; + /* * Here the rx recycling processes different rx packets in different * threads, so we protect it with RW_READER to ensure it won't block @@ -89,12 +70,35 @@ */ rw_enter(&e1000g_rx_detach_lock, RW_READER); - if (!(packet->flag & E1000G_RX_SW_SENDUP)) { + if (packet->flag == E1000G_RX_SW_FREE) { rw_exit(&e1000g_rx_detach_lock); return; } - if (packet->flag & E1000G_RX_SW_DETACHED) { + if (packet->flag == E1000G_RX_SW_STOP) { + packet->flag = E1000G_RX_SW_FREE; + rw_exit(&e1000g_rx_detach_lock); + + rw_enter(&e1000g_rx_detach_lock, RW_WRITER); + rx_ring->pending_count--; + e1000g_mblks_pending--; + + if (rx_ring->pending_count == 0) { + while (rx_ring->pending_list != NULL) { + packet = rx_ring->pending_list; + rx_ring->pending_list = + rx_ring->pending_list->next; + + ASSERT(packet->mp == NULL); + e1000g_free_rx_sw_packet(packet); + } + } + rw_exit(&e1000g_rx_detach_lock); + return; + } + + if (packet->flag == E1000G_RX_SW_DETACH) { + packet->flag = E1000G_RX_SW_FREE; rw_exit(&e1000g_rx_detach_lock); ASSERT(packet->mp == NULL); @@ -111,10 +115,7 @@ return; } - packet->flag &= ~E1000G_RX_SW_SENDUP; - - rx_ring = (e1000g_rx_ring_t *)packet->rx_ring; - Adapter = rx_ring->adapter; + packet->flag = E1000G_RX_SW_FREE; if (packet->mp == NULL) { /* @@ -129,60 +130,40 @@ packet->mp->b_rptr += E1000G_IPALIGNROOM; packet->mp->b_wptr += E1000G_IPALIGNROOM; } else { - Adapter->rx_esballoc_fail++; + E1000G_STAT(rx_ring->stat_esballoc_fail); } } mutex_enter(&rx_ring->freelist_lock); QUEUE_PUSH_TAIL(&rx_ring->free_list, &packet->Link); - Adapter->rx_avail_freepkt++; + rx_ring->avail_freepkt++; mutex_exit(&rx_ring->freelist_lock); rw_exit(&e1000g_rx_detach_lock); } /* - * ********************************************************************** - * Name: SetupReceiveStructures * - * * - * Description: This routine initializes all of the receive related * - * structures. This includes the receive descriptors, the * - * actual receive buffers, and the RX_SW_PACKET software * - * structures. * - * * - * NOTE -- The device must have been reset before this * - * routine is called. * - * * - * Author: Hari Seshadri * - * Functions Called : get_32bit_value; * - * * - * * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * (none) * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** + * e1000g_rx_setup - setup rx data structures + * + * This routine initializes all of the receive related + * structures. This includes the receive descriptors, the + * actual receive buffers, and the rx_sw_packet software + * structures. */ void -SetupReceiveStructures(struct e1000g *Adapter) +e1000g_rx_setup(struct e1000g *Adapter) { - PRX_SW_PACKET packet; + struct e1000_hw *hw; + p_rx_sw_packet_t packet; struct e1000_rx_desc *descriptor; - uint32_t BufferLow; - uint32_t BufferHigh; + uint32_t buf_low; + uint32_t buf_high; uint32_t reg_val; int i; int size; e1000g_rx_ring_t *rx_ring; + hw = &Adapter->shared; rx_ring = Adapter->rx_ring; /* @@ -190,9 +171,9 @@ * assures any previous data or status is erased */ bzero(rx_ring->rbd_area, - sizeof (struct e1000_rx_desc) * Adapter->NumRxDescriptors); + sizeof (struct e1000_rx_desc) * Adapter->rx_desc_num); - if (Adapter->init_count == 0) { + if (!Adapter->rx_buffer_setup) { /* Init the list of "Receive Buffer" */ QUEUE_INIT_LIST(&rx_ring->recv_list); @@ -206,49 +187,42 @@ packet = rx_ring->packet_area; descriptor = rx_ring->rbd_first; - for (i = 0; i < Adapter->NumRxDescriptors; + for (i = 0; i < Adapter->rx_desc_num; i++, packet = packet->next, descriptor++) { - ASSERT(packet != NULL); ASSERT(descriptor != NULL); -#ifdef __sparc - descriptor->buffer_addr = - DWORD_SWAP(packet->rx_buf->dma_address); -#else descriptor->buffer_addr = packet->rx_buf->dma_address; -#endif - /* Add this RX_SW_PACKET to the receive list */ + + /* Add this rx_sw_packet to the receive list */ QUEUE_PUSH_TAIL(&rx_ring->recv_list, &packet->Link); } - for (i = 0; i < Adapter->NumRxFreeList; + for (i = 0; i < Adapter->rx_freelist_num; i++, packet = packet->next) { ASSERT(packet != NULL); - /* Add this RX_SW_PACKET to the free list */ + /* Add this rx_sw_packet to the free list */ QUEUE_PUSH_TAIL(&rx_ring->free_list, &packet->Link); } - Adapter->rx_avail_freepkt = Adapter->NumRxFreeList; + rx_ring->avail_freepkt = Adapter->rx_freelist_num; + + Adapter->rx_buffer_setup = B_TRUE; } else { /* Setup the initial pointer to the first rx descriptor */ - packet = (PRX_SW_PACKET) + packet = (p_rx_sw_packet_t) QUEUE_GET_HEAD(&rx_ring->recv_list); descriptor = rx_ring->rbd_first; - for (i = 0; i < Adapter->NumRxDescriptors; i++) { + for (i = 0; i < Adapter->rx_desc_num; i++) { ASSERT(packet != NULL); ASSERT(descriptor != NULL); -#ifdef __sparc - descriptor->buffer_addr = - DWORD_SWAP(packet->rx_buf->dma_address); -#else descriptor->buffer_addr = packet->rx_buf->dma_address; -#endif - /* Get next RX_SW_PACKET */ - packet = (PRX_SW_PACKET) + + /* Get next rx_sw_packet */ + packet = (p_rx_sw_packet_t) QUEUE_GET_NEXT(&rx_ring->recv_list, &packet->Link); descriptor++; } @@ -259,24 +233,24 @@ */ rx_ring->rbd_next = rx_ring->rbd_first; - size = Adapter->NumRxDescriptors * sizeof (struct e1000_rx_desc); - E1000_WRITE_REG(&Adapter->Shared, RDLEN, size); - size = E1000_READ_REG(&Adapter->Shared, RDLEN); + size = Adapter->rx_desc_num * sizeof (struct e1000_rx_desc); + E1000_WRITE_REG(hw, E1000_RDLEN, size); + size = E1000_READ_REG(hw, E1000_RDLEN); /* To get lower order bits */ - BufferLow = (uint32_t)rx_ring->rbd_dma_addr; + buf_low = (uint32_t)rx_ring->rbd_dma_addr; /* To get the higher order bits */ - BufferHigh = (uint32_t)(rx_ring->rbd_dma_addr >> 32); + buf_high = (uint32_t)(rx_ring->rbd_dma_addr >> 32); - E1000_WRITE_REG(&Adapter->Shared, RDBAH, BufferHigh); - E1000_WRITE_REG(&Adapter->Shared, RDBAL, BufferLow); + E1000_WRITE_REG(hw, E1000_RDBAH, buf_high); + E1000_WRITE_REG(hw, E1000_RDBAL, buf_low); /* * Setup our HW Rx Head & Tail descriptor pointers */ - E1000_WRITE_REG(&Adapter->Shared, RDT, + E1000_WRITE_REG(hw, E1000_RDT, (uint32_t)(rx_ring->rbd_last - rx_ring->rbd_first)); - E1000_WRITE_REG(&Adapter->Shared, RDH, 0); + E1000_WRITE_REG(hw, E1000_RDH, 0); /* * Setup the Receive Control Register (RCTL), and ENABLE the @@ -289,14 +263,14 @@ reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ E1000_RCTL_BAM | /* Accept Broadcast Packets */ E1000_RCTL_LPE | /* Large Packet Enable bit */ - (Adapter->Shared.mc_filter_type << E1000_RCTL_MO_SHIFT) | + (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | E1000_RCTL_RDMTS_HALF | E1000_RCTL_LBM_NO; /* Loopback Mode = none */ if (Adapter->strip_crc) - reg_val |= E1000_RCTL_SECRC; /* Strip Ethernet CRC */ + reg_val |= E1000_RCTL_SECRC; /* Strip Ethernet CRC */ - switch (Adapter->Shared.max_frame_size) { + switch (hw->mac.max_frame_size) { case ETHERMAX: reg_val |= E1000_RCTL_SZ_2048; break; @@ -306,7 +280,7 @@ case FRAME_SIZE_UPTO_8K: reg_val |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; break; - case FRAME_SIZE_UPTO_10K: + case FRAME_SIZE_UPTO_9K: case FRAME_SIZE_UPTO_16K: reg_val |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; break; @@ -315,244 +289,72 @@ break; } - if (Adapter->Shared.tbi_compatibility_on == 1) + if (e1000_tbi_sbp_enabled_82543(hw)) reg_val |= E1000_RCTL_SBP; - E1000_WRITE_REG(&Adapter->Shared, RCTL, reg_val); + /* + * Enable early receives on supported devices, only takes effect when + * packet size is equal or larger than the specified value (in 8 byte + * units), e.g. using jumbo frames when setting to E1000_ERT_2048 + */ + if ((hw->mac.type == e1000_82573) || (hw->mac.type == e1000_ich9lan)) + E1000_WRITE_REG(hw, E1000_ERT, E1000_ERT_2048); + + E1000_WRITE_REG(hw, E1000_RCTL, reg_val); reg_val = E1000_RXCSUM_TUOFL | /* TCP/UDP checksum offload Enable */ E1000_RXCSUM_IPOFL; /* IP checksum offload Enable */ - E1000_WRITE_REG(&Adapter->Shared, RXCSUM, reg_val); - - Adapter->Shared.autoneg_failed = 1; - - Adapter->rx_bcopy_thresh = DEFAULTRXBCOPYTHRESHOLD; + E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); } /* - * ********************************************************************** - * Name: SetupMulticastTable * - * * - * Description: This routine initializes all of the multicast related * - * structures. * - * NOTE -- The device must have been reset before this routine * - * is called. * - * * - * Author: Hari Seshadri * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * (none) * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** + * e1000g_get_buf - get an rx sw packet from the free_list */ -void -SetupMulticastTable(struct e1000g *Adapter) -{ - PUCHAR MulticastBuffer; - UINT32 MulticastAddressCount; - UINT32 TempRctlReg; - USHORT PciCommandWord; - int i; - - /* - * The e1000g has the ability to do perfect filtering of 16 - * addresses. The driver uses one of the e1000g's 16 receive - * address registers for its node/network/mac/individual address. - * So, we have room for up to 15 multicast addresses in the CAM, - * additional MC addresses are handled by the MTA (Multicast Table - * Array) - */ - - TempRctlReg = E1000_READ_REG(&Adapter->Shared, RCTL); - - MulticastBuffer = (PUCHAR) (Adapter->mcast_table); - - if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { - e1000g_log(Adapter, CE_WARN, - "Adapter requested more than %d MC Addresses.\n", - MAX_NUM_MULTICAST_ADDRESSES); - MulticastAddressCount = MAX_NUM_MULTICAST_ADDRESSES; - } else { - /* - * Set the number of MC addresses that we are being - * requested to use - */ - MulticastAddressCount = Adapter->mcast_count; - } - /* - * The Wiseman 2.0 silicon has an errata by which the receiver will - * hang while writing to the receive address registers if the receiver - * is not in reset before writing to the registers. Updating the RAR - * is done during the setting up of the multicast table, hence the - * receiver has to be put in reset before updating the multicast table - * and then taken out of reset at the end - */ - /* - * if WMI was enabled then dis able it before issueing the global - * reset to the hardware. - */ - /* - * Only required for WISEMAN_2_0 - */ - if (Adapter->Shared.mac_type == e1000_82542_rev2_0) { - e1000_pci_clear_mwi(&Adapter->Shared); - /* - * The e1000g must be in reset before changing any RA - * registers. Reset receive unit. The chip will remain in - * the reset state until software explicitly restarts it. - */ - E1000_WRITE_REG(&Adapter->Shared, RCTL, E1000_RCTL_RST); - /* Allow receiver time to go in to reset */ - DelayInMilliseconds(5); - } - - e1000_mc_addr_list_update(&Adapter->Shared, MulticastBuffer, - MulticastAddressCount, 0, Adapter->unicst_total); - - /* - * Only for Wiseman_2_0 - * If MWI was enabled then re-enable it after issueing (as we - * disabled it up there) the receive reset command. - * Wainwright does not have a receive reset command and only thing - * close to it is global reset which will require tx setup also - */ - if (Adapter->Shared.mac_type == e1000_82542_rev2_0) { - /* - * if WMI was enabled then reenable it after issueing the - * global or receive reset to the hardware. - */ - - /* - * Take receiver out of reset - * clear E1000_RCTL_RST bit (and all others) - */ - E1000_WRITE_REG(&Adapter->Shared, RCTL, 0); - DelayInMilliseconds(5); - if (Adapter->Shared.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) - e1000_pci_set_mwi(&Adapter->Shared); - } - - /* - * Restore original value - */ - E1000_WRITE_REG(&Adapter->Shared, RCTL, TempRctlReg); -} - -/* - * ********************************************************************** - * Name: e1000g_get_buf * - * * - * Description: This routine gets newpkt. * - * * - * Author: Hari Seshadri * - * * - * Arguments: * - * * - * Returns: * - * RX_SW_PACKET* * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** - */ -static RX_SW_PACKET * +static p_rx_sw_packet_t e1000g_get_buf(e1000g_rx_ring_t *rx_ring) { struct e1000g *Adapter; - RX_SW_PACKET *packet; + p_rx_sw_packet_t packet; Adapter = rx_ring->adapter; mutex_enter(&rx_ring->freelist_lock); - packet = (PRX_SW_PACKET) + packet = (p_rx_sw_packet_t) QUEUE_POP_HEAD(&rx_ring->free_list); if (packet != NULL) - Adapter->rx_avail_freepkt--; + rx_ring->avail_freepkt--; mutex_exit(&rx_ring->freelist_lock); return (packet); } /* - * ********************************************************************** - * Name: e1000g_receive * - * * - * Description: This routine will process packets spanning multiple * - * buffers * - * - Called from the e1000g_intr Handles interrupt for RX side * - * - Checks the interrupt cause and process it. At the time of * - * calling the interrupt cause register has been already * - * cleared. * - * * - * Author: Vinay K Awasthi * - * * - * Date : Feb 9, 2000 * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * Pointer to list of mblks to pass up to GLD * - * Functions Called: * - * (none) * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** + * e1000g_receive - main receive routine + * + * This routine will process packets received in an interrupt */ mblk_t * e1000g_receive(struct e1000g *Adapter) { - /* - * Need : - * This function addresses the need to process jumbo frames using - * standard 2048 byte buffers. In solaris, getting large aligned - * buffers in low memory systems is hard and often it comprises - * of multiple cookies rather than just one cookie which our HW - * wants. In low memory systems, it is hard to get lots of large - * chunks of memory i.e. you can get 256 2k buffers but it is hard - * to get 64 8k buffers. Pagesize is playing an important role here. - * If system administrator is willing to tune stream and system dma - * resources then we may not need this function. At the same time - * we may not have this option. - * This function will also make our driver do Jumbo frames on Wiseman - * hardware. - */ - + struct e1000_hw *hw; mblk_t *nmp; mblk_t *ret_mp; mblk_t *ret_nmp; struct e1000_rx_desc *current_desc; struct e1000_rx_desc *last_desc; - PRX_SW_PACKET packet; - PRX_SW_PACKET newpkt; + p_rx_sw_packet_t packet; + p_rx_sw_packet_t newpkt; USHORT length; uint32_t pkt_count; uint32_t desc_count; - unsigned char LastByte; - boolean_t AcceptFrame; + boolean_t accept_frame; boolean_t end_of_packet; boolean_t need_copy; e1000g_rx_ring_t *rx_ring; dma_buffer_t *rx_buf; uint16_t cksumflags; - uint32_t sync_offset; - uint32_t sync_len; ret_mp = NULL; ret_nmp = NULL; @@ -560,20 +362,19 @@ desc_count = 0; cksumflags = 0; + hw = &Adapter->shared; rx_ring = Adapter->rx_ring; - sync_offset = rx_ring->rbd_next - rx_ring->rbd_first; - /* Sync the Rx descriptor DMA buffers */ (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - 0, 0, DDI_DMA_SYNC_FORCPU); + 0, 0, DDI_DMA_SYNC_FORKERNEL); current_desc = rx_ring->rbd_next; if (!(current_desc->status & E1000_RXD_STAT_DD)) { /* * don't send anything up. just clear the RFD */ - Adapter->rx_none++; + E1000G_DEBUG_STAT(rx_ring->stat_none); return (ret_mp); } @@ -582,7 +383,7 @@ * descriptor owned by the hardware that begins a packet. */ while ((current_desc->status & E1000_RXD_STAT_DD) && - (pkt_count < Adapter->MaxNumReceivePackets)) { + (pkt_count < Adapter->rx_limit_onintr)) { desc_count++; /* @@ -607,79 +408,67 @@ * Buffer Address. */ packet = - (PRX_SW_PACKET)QUEUE_GET_HEAD(&rx_ring->recv_list); + (p_rx_sw_packet_t)QUEUE_GET_HEAD(&rx_ring->recv_list); ASSERT(packet != NULL); rx_buf = packet->rx_buf; length = current_desc->length; - switch (packet->dma_type) { #ifdef __sparc - case USE_DVMA: + if (packet->dma_type == USE_DVMA) dvma_sync(rx_buf->dma_handle, 0, DDI_DMA_SYNC_FORKERNEL); - break; -#endif - case USE_DMA: + else (void) ddi_dma_sync(rx_buf->dma_handle, E1000G_IPALIGNROOM, length, - DDI_DMA_SYNC_FORCPU); - break; - default: - ASSERT(B_FALSE); - break; + DDI_DMA_SYNC_FORKERNEL); +#else + (void) ddi_dma_sync(rx_buf->dma_handle, + E1000G_IPALIGNROOM, length, + DDI_DMA_SYNC_FORKERNEL); +#endif + + accept_frame = (current_desc->errors == 0) || + ((current_desc->errors & + (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) != 0); + + if (hw->mac.type == e1000_82543) { + unsigned char last_byte; + + last_byte = + *((unsigned char *)rx_buf->address + length - 1); + + if (TBI_ACCEPT(hw, + current_desc->status, current_desc->errors, + current_desc->length, last_byte)) { + + e1000_tbi_adjust_stats(Adapter, + length, hw->mac.addr); + + length--; + accept_frame = B_TRUE; + } else if (e1000_tbi_sbp_enabled_82543(hw) && + (current_desc->errors == E1000_RXD_ERR_CE)) { + accept_frame = B_TRUE; + } } - LastByte = - *((unsigned char *)rx_buf->address + length - 1); - - if (TBI_ACCEPT(&Adapter->Shared, - current_desc->status, - current_desc->errors, - current_desc->length, LastByte)) { - - AcceptFrame = B_TRUE; - mutex_enter(&Adapter->TbiCntrMutex); - AdjustTbiAcceptedStats(Adapter, length, - Adapter->Shared.mac_addr); - mutex_exit(&Adapter->TbiCntrMutex); - length--; - } else { - AcceptFrame = B_FALSE; - } /* * Indicate the packet to the NOS if it was good. * Normally, hardware will discard bad packets for us. * Check for the packet to be a valid Ethernet packet */ - - /* - * There can be few packets which are less than 2k but - * more than 1514 bytes length. They are really jumbo - * packets, but for our driver's buffer they can still - * fit in one buffer as minimum buffer size if 2K. In our - * above condition, we are taking all EOP packets as - * JumboPacket=False... JumboPacket=FALSE just tells us - * that now we can process this packet...as we have - * received complete packet. - */ - - if (!((current_desc->errors == 0) || - (current_desc->errors & - (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) || - ((Adapter->Shared.tbi_compatibility_on == 1) && - (current_desc->errors == E1000_RXD_ERR_CE)) || - AcceptFrame)) { + if (!accept_frame) { /* * error in incoming packet, either the packet is not a * ethernet size packet, or the packet has an error. In * either case, the packet will simply be discarded. */ - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "Process Receive Interrupts: Error in Packet\n"); - Adapter->rx_error++; + E1000G_STAT(rx_ring->stat_error); /* * Returning here as we are done here. There is * no point in waiting for while loop to elapse @@ -702,10 +491,10 @@ * drop this fragment, do the processing of * the end of the packet. */ - ASSERT(Adapter->rx_mblk_tail != NULL); - Adapter->rx_mblk_tail->b_wptr -= + ASSERT(rx_ring->rx_mblk_tail != NULL); + rx_ring->rx_mblk_tail->b_wptr -= CRC_LENGTH - length; - Adapter->rx_packet_len -= + rx_ring->rx_mblk_len -= CRC_LENGTH - length; QUEUE_POP_HEAD(&rx_ring->recv_list); @@ -733,7 +522,7 @@ packet->mp->b_rptr += E1000G_IPALIGNROOM; packet->mp->b_wptr += E1000G_IPALIGNROOM; } else { - Adapter->rx_esballoc_fail++; + E1000G_STAT(rx_ring->stat_esballoc_fail); } } @@ -761,7 +550,7 @@ */ nmp = packet->mp; packet->mp = NULL; - packet->flag |= E1000G_RX_SW_SENDUP; + packet->flag == E1000G_RX_SW_SENDUP; /* * Now replace old buffer with the new @@ -771,16 +560,13 @@ * point to this new packet. */ packet = newpkt; -#ifdef __sparc - current_desc->buffer_addr = - DWORD_SWAP(newpkt->rx_buf->dma_address); -#else + current_desc->buffer_addr = newpkt->rx_buf->dma_address; -#endif + need_copy = B_FALSE; } else { - Adapter->rx_no_freepkt++; + E1000G_DEBUG_STAT(rx_ring->stat_no_freepkt); } } @@ -792,8 +578,7 @@ * keep the original buffer. Dont want to * do this.. Yack but no other way */ - if ((nmp = - allocb(length + E1000G_IPALIGNROOM, + if ((nmp = allocb(length + E1000G_IPALIGNROOM, BPRI_MED)) == NULL) { /* * The system has no buffers available @@ -801,7 +586,7 @@ * the packet will have to be processed * when there're more buffers available. */ - Adapter->rx_allocb_fail++; + E1000G_STAT(rx_ring->stat_allocb_fail); goto rx_drop; } nmp->b_rptr += E1000G_IPALIGNROOM; @@ -813,32 +598,28 @@ * buffer will have to be retained for future * packet reception. */ - bcopy(rx_buf->address, - nmp->b_wptr, length); + bcopy(rx_buf->address, nmp->b_wptr, length); } /* - * The RX_SW_PACKET MUST be popped off the + * The rx_sw_packet MUST be popped off the * RxSwPacketList before either a putnext or freemsg * is done on the mp that has now been created by the * desballoc. If not, it is possible that the free * routine will get called from the interrupt context * and try to put this packet on the free list */ - (PRX_SW_PACKET)QUEUE_POP_HEAD(&rx_ring->recv_list); + (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); ASSERT(nmp != NULL); nmp->b_wptr += length; - if ((Adapter->rx_mblk == NULL) && - (GET_ETHER_TYPE((struct ether_header *)nmp->b_rptr) == - ETHERTYPE_IP)) { + if (rx_ring->rx_mblk == NULL) { /* * TCP/UDP checksum offload and * IP checksum offload */ - if (!(current_desc->status & - E1000_RXD_STAT_IXSM)) { + if (!(current_desc->status & E1000_RXD_STAT_IXSM)) { /* * Check TCP/UDP checksum */ @@ -864,20 +645,20 @@ * Adapter structure, for the Rx processing can end * with a fragment that has no EOP set. */ - if (Adapter->rx_mblk == NULL) { + if (rx_ring->rx_mblk == NULL) { /* Get the head of the message chain */ - Adapter->rx_mblk = nmp; - Adapter->rx_mblk_tail = nmp; - Adapter->rx_packet_len = length; + rx_ring->rx_mblk = nmp; + rx_ring->rx_mblk_tail = nmp; + rx_ring->rx_mblk_len = length; } else { /* Not the first packet */ /* Continue adding buffers */ - Adapter->rx_mblk_tail->b_cont = nmp; - Adapter->rx_mblk_tail = nmp; - Adapter->rx_packet_len += length; + rx_ring->rx_mblk_tail->b_cont = nmp; + rx_ring->rx_mblk_tail = nmp; + rx_ring->rx_mblk_len += length; } - ASSERT(Adapter->rx_mblk != NULL); - ASSERT(Adapter->rx_mblk_tail != NULL); - ASSERT(Adapter->rx_mblk_tail->b_cont == NULL); + ASSERT(rx_ring->rx_mblk != NULL); + ASSERT(rx_ring->rx_mblk_tail != NULL); + ASSERT(rx_ring->rx_mblk_tail->b_cont == NULL); /* * Now this MP is ready to travel upwards but some more @@ -899,47 +680,31 @@ * Process the last fragment. */ if (cksumflags != 0) { - (void) hcksum_assoc(Adapter->rx_mblk, + (void) hcksum_assoc(rx_ring->rx_mblk, NULL, NULL, 0, 0, 0, 0, cksumflags, 0); cksumflags = 0; } /* - * Jumbo Frame Counters - */ - if (Adapter->ProfileJumboTraffic) { - if ((Adapter->rx_packet_len > ETHERMAX) && - (Adapter->rx_packet_len <= FRAME_SIZE_UPTO_4K)) - Adapter->JumboRx_4K++; - - if ((Adapter->rx_packet_len > FRAME_SIZE_UPTO_4K) && - (Adapter->rx_packet_len <= FRAME_SIZE_UPTO_8K)) - Adapter->JumboRx_8K++; - - if ((Adapter->rx_packet_len > FRAME_SIZE_UPTO_8K) && - (Adapter->rx_packet_len <= FRAME_SIZE_UPTO_16K)) - Adapter->JumboRx_16K++; - } - /* * Count packets that span multi-descriptors */ - if (Adapter->rx_mblk->b_cont != NULL) - Adapter->rx_multi_desc++; + E1000G_DEBUG_STAT_COND(rx_ring->stat_multi_desc, + (rx_ring->rx_mblk->b_cont != NULL)); /* * Append to list to send upstream */ if (ret_mp == NULL) { - ret_mp = ret_nmp = Adapter->rx_mblk; + ret_mp = ret_nmp = rx_ring->rx_mblk; } else { - ret_nmp->b_next = Adapter->rx_mblk; - ret_nmp = Adapter->rx_mblk; + ret_nmp->b_next = rx_ring->rx_mblk; + ret_nmp = rx_ring->rx_mblk; } ret_nmp->b_next = NULL; - Adapter->rx_mblk = NULL; - Adapter->rx_mblk_tail = NULL; - Adapter->rx_packet_len = 0; + rx_ring->rx_mblk = NULL; + rx_ring->rx_mblk_tail = NULL; + rx_ring->rx_mblk_len = 0; pkt_count++; @@ -965,33 +730,17 @@ &packet->Link); } /* while loop */ - if (pkt_count >= Adapter->MaxNumReceivePackets) - Adapter->rx_exceed_pkt++; + if (pkt_count >= Adapter->rx_limit_onintr) + E1000G_STAT(rx_ring->stat_exceed_pkt); /* Sync the Rx descriptor DMA buffers */ - sync_len = desc_count; - /* Check the wrap-around case */ - if ((sync_offset + sync_len) <= Adapter->NumRxDescriptors) { - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - sync_offset * sizeof (struct e1000_rx_desc), - sync_len * sizeof (struct e1000_rx_desc), - DDI_DMA_SYNC_FORDEV); - } else { - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - sync_offset * sizeof (struct e1000_rx_desc), - 0, - DDI_DMA_SYNC_FORDEV); - sync_len = sync_offset + sync_len - Adapter->NumRxDescriptors; - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - 0, - sync_len * sizeof (struct e1000_rx_desc), - DDI_DMA_SYNC_FORDEV); - } + (void) ddi_dma_sync(rx_ring->rbd_dma_handle, + 0, 0, DDI_DMA_SYNC_FORDEV); /* * Advance the E1000's Receive Queue #0 "Tail Pointer". */ - E1000_WRITE_REG(&Adapter->Shared, RDT, + E1000_WRITE_REG(hw, E1000_RDT, (uint32_t)(last_desc - rx_ring->rbd_first)); return (ret_mp); @@ -1003,24 +752,8 @@ current_desc->status = 0; /* Sync the Rx descriptor DMA buffers */ - sync_len = desc_count; - /* Check the wrap-around case */ - if ((sync_offset + sync_len) <= Adapter->NumRxDescriptors) { - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - sync_offset * sizeof (struct e1000_rx_desc), - sync_len * sizeof (struct e1000_rx_desc), - DDI_DMA_SYNC_FORDEV); - } else { - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - sync_offset * sizeof (struct e1000_rx_desc), - 0, - DDI_DMA_SYNC_FORDEV); - sync_len = sync_offset + sync_len - Adapter->NumRxDescriptors; - (void) ddi_dma_sync(rx_ring->rbd_dma_handle, - 0, - sync_len * sizeof (struct e1000_rx_desc), - DDI_DMA_SYNC_FORDEV); - } + (void) ddi_dma_sync(rx_ring->rbd_dma_handle, + 0, 0, DDI_DMA_SYNC_FORDEV); if (current_desc == rx_ring->rbd_last) rx_ring->rbd_next = rx_ring->rbd_first; @@ -1029,23 +762,23 @@ last_desc = current_desc; - (PRX_SW_PACKET)QUEUE_POP_HEAD(&rx_ring->recv_list); + (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); QUEUE_PUSH_TAIL(&rx_ring->recv_list, &packet->Link); /* * Reclaim all old buffers already allocated during * Jumbo receives.....for incomplete reception */ - if (Adapter->rx_mblk != NULL) { - freemsg(Adapter->rx_mblk); - Adapter->rx_mblk = NULL; - Adapter->rx_mblk_tail = NULL; - Adapter->rx_packet_len = 0; + if (rx_ring->rx_mblk != NULL) { + freemsg(rx_ring->rx_mblk); + rx_ring->rx_mblk = NULL; + rx_ring->rx_mblk_tail = NULL; + rx_ring->rx_mblk_len = 0; } /* * Advance the E1000's Receive Queue #0 "Tail Pointer". */ - E1000_WRITE_REG(&Adapter->Shared, RDT, + E1000_WRITE_REG(hw, E1000_RDT, (uint32_t)(last_desc - rx_ring->rbd_first)); return (ret_mp);
--- a/usr/src/uts/common/io/e1000g/e1000g_stat.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_stat.c Tue Aug 21 00:30:10 2007 -0700 @@ -30,71 +30,50 @@ * * * Module Name: e1000g_stat.c * * * - * Abstract: Functions for displaying statistics * + * Abstract: Functions for processing statistics * * * * ********************************************************************** */ #include "e1000g_sw.h" #include "e1000g_debug.h" -static int UpdateStatsCounters(kstat_t *ksp, int rw); +static int e1000g_update_stats(kstat_t *ksp, int rw); /* - * ********************************************************************** - * * - * Name: AdjustTbiAcceptedStats * - * * - * Description: Adjusts statistic counters when a frame is accepted * - * under the TBI workaround. This function has been * - * adapted for Solaris from shared code. * - * * - * Author: Bill Campbell * - * * - * Born on Date: 4/12/2001 * - * * - * Arguments: * - * Adapter - Ptr to this card's adapter data structure. * - * FrameLength - Length as reported from Hardware * - * MacAddress - Pointer to MAC address field in frame. * - * * - * Returns: * - * VOID * - * * - * ********************************************************************** + * e1000_tbi_adjust_stats + * + * Adjusts statistic counters when a frame is accepted + * under the TBI workaround. This function has been + * adapted for Solaris from shared code. */ void -AdjustTbiAcceptedStats(struct e1000g *Adapter, - UINT32 FrameLength, PUCHAR MacAddress) +e1000_tbi_adjust_stats(struct e1000g *Adapter, + uint32_t frame_len, uint8_t *mac_addr) { - UINT32 CarryBit; - e1000gstat *e1000g_ksp; + struct e1000_hw *hw = &Adapter->shared; + uint32_t carry_bit; + p_e1000g_stat_t e1000g_ksp; - e1000g_ksp = (e1000gstat *)Adapter->e1000g_ksp->ks_data; + e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; - /* - * First adjust the frame length. - */ - FrameLength--; + /* First adjust the frame length */ + frame_len--; + /* * We need to adjust the statistics counters, since the hardware * counters overcount this packet as a CRC error and undercount * the packet as a good packet */ - - /* - * This packet should not be counted as a CRC error. - */ + /* This packet should not be counted as a CRC error */ e1000g_ksp->Crcerrs.value.ul--; - /* - * This packet does count as a Good Packet Received. - */ + /* This packet does count as a Good Packet Received */ e1000g_ksp->Gprc.value.ul++; /* * Adjust the Good Octets received counters */ - CarryBit = 0x80000000 & e1000g_ksp->Gorl.value.ul; - e1000g_ksp->Gorl.value.ul += FrameLength; + carry_bit = 0x80000000 & e1000g_ksp->Gorl.value.ul; + e1000g_ksp->Gorl.value.ul += frame_len; /* * If the high bit of Gorcl (the low 32 bits of the Good Octets * Received Count) was one before the addition, @@ -103,7 +82,7 @@ * This could be simplified if all environments supported * 64-bit integers. */ - if (CarryBit && ((e1000g_ksp->Gorl.value.ul & 0x80000000) == 0)) { + if (carry_bit && ((e1000g_ksp->Gorl.value.ul & 0x80000000) == 0)) { e1000g_ksp->Gorh.value.ul++; } /* @@ -111,19 +90,20 @@ * since the test for a multicast frame will test positive on * a broadcast frame. */ - if ((MacAddress[0] == (UCHAR) 0xff) && - (MacAddress[1] == (UCHAR) 0xff)) { + if ((mac_addr[0] == (uint8_t)0xff) && + (mac_addr[1] == (uint8_t)0xff)) { /* * Broadcast packet */ e1000g_ksp->Bprc.value.ul++; - } else if (*MacAddress & 0x01) { + } else if (*mac_addr & 0x01) { /* * Multicast packet */ e1000g_ksp->Mprc.value.ul++; } - if (FrameLength == Adapter->Shared.max_frame_size) { + + if (frame_len == hw->mac.max_frame_size) { /* * In this case, the hardware has overcounted the number of * oversize frames. @@ -134,63 +114,44 @@ /* * Adjust the bin counters when the extra byte put the frame in the - * wrong bin. Remember that the FrameLength was adjusted above. + * wrong bin. Remember that the frame_len was adjusted above. */ - if (FrameLength == 64) { + if (frame_len == 64) { e1000g_ksp->Prc64.value.ul++; e1000g_ksp->Prc127.value.ul--; - } else if (FrameLength == 127) { + } else if (frame_len == 127) { e1000g_ksp->Prc127.value.ul++; e1000g_ksp->Prc255.value.ul--; - } else if (FrameLength == 255) { + } else if (frame_len == 255) { e1000g_ksp->Prc255.value.ul++; e1000g_ksp->Prc511.value.ul--; - } else if (FrameLength == 511) { + } else if (frame_len == 511) { e1000g_ksp->Prc511.value.ul++; e1000g_ksp->Prc1023.value.ul--; - } else if (FrameLength == 1023) { + } else if (frame_len == 1023) { e1000g_ksp->Prc1023.value.ul++; e1000g_ksp->Prc1522.value.ul--; - } else if (FrameLength == 1522) { + } else if (frame_len == 1522) { e1000g_ksp->Prc1522.value.ul++; } } /* - * ********************************************************************** - * Name: UpdateStatsCounters * - * * - * Description: This routine will dump and reset the 1000's internal * - * Statistics counters. The current stats dump values will * - * be sent to the kernel status area. * - * * - * Author: Phil Cayton * - * * - * Born on Date: 7/13/98 * - * * - * Arguments: * - * *ksp - A kernel stat pointer * - * rw - Read/Write flag * - * * - * Returns: * - * (EACCES) If an attempt is made to write stats to the hw * - * (0) On successful read of statistics to kernel stats. * - * * - * File: e1000g_stat.c * - * * - * Modification log: * - * Date Who Description * - * -------- --- ------------------------------------------------------* - * Sept 10,99 Vinay New Counters for Livengood have been added. * - * ********************************************************************** + * e1000g_update_stats - update driver private kstat counters + * + * This routine will dump and reset the e1000's internal + * statistics counters. The current stats dump values will + * be sent to the kernel status area. */ static int -UpdateStatsCounters(IN kstat_t *ksp, int rw) +e1000g_update_stats(kstat_t *ksp, int rw) { - uint16_t LineSpeed, Duplex; struct e1000g *Adapter; - e1000gstat *e1000g_ksp; + struct e1000_hw *hw; + p_e1000g_stat_t e1000g_ksp; + e1000g_tx_ring_t *tx_ring; + e1000g_rx_ring_t *rx_ring; uint64_t val; uint32_t low_val, high_val; @@ -199,200 +160,147 @@ Adapter = (struct e1000g *)ksp->ks_private; ASSERT(Adapter != NULL); - e1000g_ksp = (e1000gstat *)ksp->ks_data; + e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; ASSERT(e1000g_ksp != NULL); + hw = &Adapter->shared; + + tx_ring = Adapter->tx_ring; + rx_ring = Adapter->rx_ring; + + rw_enter(&Adapter->chip_lock, RW_WRITER); e1000g_ksp->link_speed.value.ul = Adapter->link_speed; - e1000g_ksp->rx_none.value.ul = Adapter->rx_none; - e1000g_ksp->rx_error.value.ul = Adapter->rx_error; - e1000g_ksp->rx_no_freepkt.value.ul = Adapter->rx_no_freepkt; - e1000g_ksp->rx_esballoc_fail.value.ul = Adapter->rx_esballoc_fail; - e1000g_ksp->rx_exceed_pkt.value.ul = Adapter->rx_exceed_pkt; - e1000g_ksp->rx_multi_desc.value.ul = Adapter->rx_multi_desc; - e1000g_ksp->rx_allocb_fail.value.ul = Adapter->rx_allocb_fail; - e1000g_ksp->rx_avail_freepkt.value.ul = Adapter->rx_avail_freepkt; - e1000g_ksp->rx_seq_intr.value.ul = Adapter->rx_seq_intr; - e1000g_ksp->tx_no_desc.value.ul = Adapter->tx_no_desc; - e1000g_ksp->tx_no_swpkt.value.ul = Adapter->tx_no_swpkt; - e1000g_ksp->tx_lack_desc.value.ul = Adapter->tx_lack_desc; - e1000g_ksp->tx_send_fail.value.ul = Adapter->tx_send_fail; - e1000g_ksp->tx_multi_cookie.value.ul = Adapter->tx_multi_cookie; - e1000g_ksp->tx_over_size.value.ul = Adapter->tx_over_size; - e1000g_ksp->tx_under_size.value.ul = Adapter->tx_under_size; - e1000g_ksp->tx_copy.value.ul = Adapter->tx_copy; - e1000g_ksp->tx_bind.value.ul = Adapter->tx_bind; - e1000g_ksp->tx_multi_copy.value.ul = Adapter->tx_multi_copy; - e1000g_ksp->tx_reschedule.value.ul = Adapter->tx_reschedule; - e1000g_ksp->tx_empty_frags.value.ul = Adapter->tx_empty_frags; - e1000g_ksp->tx_exceed_frags.value.ul = Adapter->tx_exceed_frags; - e1000g_ksp->tx_recycle.value.ul = Adapter->tx_recycle; - e1000g_ksp->tx_recycle_retry.value.ul = Adapter->tx_recycle_retry; - e1000g_ksp->tx_recycle_intr.value.ul = Adapter->tx_recycle_intr; - e1000g_ksp->tx_recycle_none.value.ul = Adapter->tx_recycle_none; - e1000g_ksp->StallWatchdog.value.ul = Adapter->StallWatchdog; e1000g_ksp->reset_count.value.ul = Adapter->reset_count; - e1000g_ksp->JumboTx_4K.value.ul = Adapter->JumboTx_4K; - e1000g_ksp->JumboRx_4K.value.ul = Adapter->JumboRx_4K; - e1000g_ksp->JumboTx_8K.value.ul = Adapter->JumboTx_8K; - e1000g_ksp->JumboRx_8K.value.ul = Adapter->JumboRx_8K; - e1000g_ksp->JumboTx_16K.value.ul = Adapter->JumboTx_16K; - e1000g_ksp->JumboRx_16K.value.ul = Adapter->JumboRx_16K; - e1000g_ksp->intr_type.value.ul = Adapter->intr_type; + + e1000g_ksp->rx_error.value.ul = rx_ring->stat_error; + e1000g_ksp->rx_esballoc_fail.value.ul = rx_ring->stat_esballoc_fail; + e1000g_ksp->rx_allocb_fail.value.ul = rx_ring->stat_allocb_fail; + e1000g_ksp->rx_exceed_pkt.value.ul = rx_ring->stat_exceed_pkt; + + e1000g_ksp->tx_no_swpkt.value.ul = tx_ring->stat_no_swpkt; + e1000g_ksp->tx_no_desc.value.ul = tx_ring->stat_no_desc; + e1000g_ksp->tx_send_fail.value.ul = tx_ring->stat_send_fail; + e1000g_ksp->tx_reschedule.value.ul = tx_ring->stat_reschedule; + e1000g_ksp->tx_over_size.value.ul = tx_ring->stat_over_size; - /* - * Mutex required if in TBI mode - */ - if (Adapter->Shared.tbi_compatibility_on == 1) { - mutex_enter(&Adapter->TbiCntrMutex); - } +#ifdef E1000G_DEBUG + e1000g_ksp->rx_none.value.ul = rx_ring->stat_none; + e1000g_ksp->rx_multi_desc.value.ul = rx_ring->stat_multi_desc; + e1000g_ksp->rx_no_freepkt.value.ul = rx_ring->stat_no_freepkt; + e1000g_ksp->rx_avail_freepkt.value.ul = rx_ring->avail_freepkt; + + e1000g_ksp->tx_under_size.value.ul = tx_ring->stat_under_size; + e1000g_ksp->tx_exceed_frags.value.ul = tx_ring->stat_exceed_frags; + e1000g_ksp->tx_empty_frags.value.ul = tx_ring->stat_empty_frags; + e1000g_ksp->tx_recycle.value.ul = tx_ring->stat_recycle; + e1000g_ksp->tx_recycle_intr.value.ul = tx_ring->stat_recycle_intr; + e1000g_ksp->tx_recycle_retry.value.ul = tx_ring->stat_recycle_retry; + e1000g_ksp->tx_recycle_none.value.ul = tx_ring->stat_recycle_none; + e1000g_ksp->tx_copy.value.ul = tx_ring->stat_copy; + e1000g_ksp->tx_bind.value.ul = tx_ring->stat_bind; + e1000g_ksp->tx_multi_copy.value.ul = tx_ring->stat_multi_copy; + e1000g_ksp->tx_multi_cookie.value.ul = tx_ring->stat_multi_cookie; + e1000g_ksp->tx_lack_desc.value.ul = tx_ring->stat_lack_desc; +#endif /* * Standard Stats */ - e1000g_ksp->Mpc.value.ul += - E1000_READ_REG(&Adapter->Shared, MPC); - - e1000g_ksp->Symerrs.value.ul += - E1000_READ_REG(&Adapter->Shared, SYMERRS); + e1000g_ksp->Mpc.value.ul += E1000_READ_REG(hw, E1000_MPC); + e1000g_ksp->Rlec.value.ul += E1000_READ_REG(hw, E1000_RLEC); + e1000g_ksp->Xonrxc.value.ul += E1000_READ_REG(hw, E1000_XONRXC); + e1000g_ksp->Xontxc.value.ul += E1000_READ_REG(hw, E1000_XONTXC); + e1000g_ksp->Xoffrxc.value.ul += E1000_READ_REG(hw, E1000_XOFFRXC); + e1000g_ksp->Xofftxc.value.ul += E1000_READ_REG(hw, E1000_XOFFTXC); + e1000g_ksp->Fcruc.value.ul += E1000_READ_REG(hw, E1000_FCRUC); - e1000g_ksp->Rlec.value.ul += - E1000_READ_REG(&Adapter->Shared, RLEC); - - e1000g_ksp->Xonrxc.value.ul += - E1000_READ_REG(&Adapter->Shared, XONRXC); + if ((hw->mac.type != e1000_ich8lan) && + (hw->mac.type != e1000_ich9lan)) { + e1000g_ksp->Symerrs.value.ul += + E1000_READ_REG(hw, E1000_SYMERRS); - e1000g_ksp->Xontxc.value.ul += - E1000_READ_REG(&Adapter->Shared, XONTXC); - - e1000g_ksp->Xoffrxc.value.ul += - E1000_READ_REG(&Adapter->Shared, XOFFRXC); - - e1000g_ksp->Xofftxc.value.ul += - E1000_READ_REG(&Adapter->Shared, XOFFTXC); - - e1000g_ksp->Fcruc.value.ul += - E1000_READ_REG(&Adapter->Shared, FCRUC); + e1000g_ksp->Prc64.value.ul += + E1000_READ_REG(hw, E1000_PRC64); + e1000g_ksp->Prc127.value.ul += + E1000_READ_REG(hw, E1000_PRC127); + e1000g_ksp->Prc255.value.ul += + E1000_READ_REG(hw, E1000_PRC255); + e1000g_ksp->Prc511.value.ul += + E1000_READ_REG(hw, E1000_PRC511); + e1000g_ksp->Prc1023.value.ul += + E1000_READ_REG(hw, E1000_PRC1023); + e1000g_ksp->Prc1522.value.ul += + E1000_READ_REG(hw, E1000_PRC1522); - e1000g_ksp->Prc64.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC64); - - e1000g_ksp->Prc127.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC127); - - e1000g_ksp->Prc255.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC255); - - e1000g_ksp->Prc511.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC511); + e1000g_ksp->Ptc64.value.ul += + E1000_READ_REG(hw, E1000_PTC64); + e1000g_ksp->Ptc127.value.ul += + E1000_READ_REG(hw, E1000_PTC127); + e1000g_ksp->Ptc255.value.ul += + E1000_READ_REG(hw, E1000_PTC255); + e1000g_ksp->Ptc511.value.ul += + E1000_READ_REG(hw, E1000_PTC511); + e1000g_ksp->Ptc1023.value.ul += + E1000_READ_REG(hw, E1000_PTC1023); + e1000g_ksp->Ptc1522.value.ul += + E1000_READ_REG(hw, E1000_PTC1522); + } - e1000g_ksp->Prc1023.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC1023); - - e1000g_ksp->Prc1522.value.ul += - E1000_READ_REG(&Adapter->Shared, PRC1522); + e1000g_ksp->Gprc.value.ul += E1000_READ_REG(hw, E1000_GPRC); + e1000g_ksp->Gptc.value.ul += E1000_READ_REG(hw, E1000_GPTC); + e1000g_ksp->Ruc.value.ul += E1000_READ_REG(hw, E1000_RUC); + e1000g_ksp->Rfc.value.ul += E1000_READ_REG(hw, E1000_RFC); + e1000g_ksp->Roc.value.ul += E1000_READ_REG(hw, E1000_ROC); + e1000g_ksp->Rjc.value.ul += E1000_READ_REG(hw, E1000_RJC); + e1000g_ksp->Tpr.value.ul += E1000_READ_REG(hw, E1000_TPR); + e1000g_ksp->Tncrs.value.ul += E1000_READ_REG(hw, E1000_TNCRS); + e1000g_ksp->Tsctc.value.ul += E1000_READ_REG(hw, E1000_TSCTC); + e1000g_ksp->Tsctfc.value.ul += E1000_READ_REG(hw, E1000_TSCTFC); - e1000g_ksp->Gprc.value.ul += - E1000_READ_REG(&Adapter->Shared, GPRC); - - e1000g_ksp->Gptc.value.ul += - E1000_READ_REG(&Adapter->Shared, GPTC); + /* + * Adaptive Calculations + */ + hw->mac.tx_packet_delta = E1000_READ_REG(hw, E1000_TPT); + e1000g_ksp->Tpt.value.ul += hw->mac.tx_packet_delta; /* * The 64-bit register will reset whenever the upper * 32 bits are read. So we need to read the lower * 32 bits first, then read the upper 32 bits. */ - low_val = E1000_READ_REG(&Adapter->Shared, GORCL); - high_val = E1000_READ_REG(&Adapter->Shared, GORCH); + low_val = E1000_READ_REG(hw, E1000_GORCL); + high_val = E1000_READ_REG(hw, E1000_GORCH); val = (uint64_t)e1000g_ksp->Gorh.value.ul << 32 | (uint64_t)e1000g_ksp->Gorl.value.ul; val += (uint64_t)high_val << 32 | (uint64_t)low_val; e1000g_ksp->Gorl.value.ul = (uint32_t)val; e1000g_ksp->Gorh.value.ul = (uint32_t)(val >> 32); - low_val = E1000_READ_REG(&Adapter->Shared, GOTCL); - high_val = E1000_READ_REG(&Adapter->Shared, GOTCH); + low_val = E1000_READ_REG(hw, E1000_GOTCL); + high_val = E1000_READ_REG(hw, E1000_GOTCH); val = (uint64_t)e1000g_ksp->Goth.value.ul << 32 | (uint64_t)e1000g_ksp->Gotl.value.ul; val += (uint64_t)high_val << 32 | (uint64_t)low_val; e1000g_ksp->Gotl.value.ul = (uint32_t)val; e1000g_ksp->Goth.value.ul = (uint32_t)(val >> 32); - e1000g_ksp->Ruc.value.ul += - E1000_READ_REG(&Adapter->Shared, RUC); - - e1000g_ksp->Rfc.value.ul += - E1000_READ_REG(&Adapter->Shared, RFC); - - e1000g_ksp->Roc.value.ul += - E1000_READ_REG(&Adapter->Shared, ROC); - - e1000g_ksp->Rjc.value.ul += - E1000_READ_REG(&Adapter->Shared, RJC); - - low_val = E1000_READ_REG(&Adapter->Shared, TORL); - high_val = E1000_READ_REG(&Adapter->Shared, TORH); + low_val = E1000_READ_REG(hw, E1000_TORL); + high_val = E1000_READ_REG(hw, E1000_TORH); val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | (uint64_t)e1000g_ksp->Torl.value.ul; val += (uint64_t)high_val << 32 | (uint64_t)low_val; e1000g_ksp->Torl.value.ul = (uint32_t)val; e1000g_ksp->Torh.value.ul = (uint32_t)(val >> 32); - low_val = E1000_READ_REG(&Adapter->Shared, TOTL); - high_val = E1000_READ_REG(&Adapter->Shared, TOTH); + low_val = E1000_READ_REG(hw, E1000_TOTL); + high_val = E1000_READ_REG(hw, E1000_TOTH); val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | (uint64_t)e1000g_ksp->Totl.value.ul; val += (uint64_t)high_val << 32 | (uint64_t)low_val; e1000g_ksp->Totl.value.ul = (uint32_t)val; e1000g_ksp->Toth.value.ul = (uint32_t)(val >> 32); - e1000g_ksp->Tpr.value.ul += - E1000_READ_REG(&Adapter->Shared, TPR); - - /* - * Adaptive Calculations - */ - Adapter->Shared.tx_packet_delta = - E1000_READ_REG(&Adapter->Shared, TPT); - e1000g_ksp->Tpt.value.ul += - Adapter->Shared.tx_packet_delta; - - e1000g_ksp->Ptc64.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC64); - - e1000g_ksp->Ptc127.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC127); - - e1000g_ksp->Ptc255.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC255); - - e1000g_ksp->Ptc511.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC511); - - e1000g_ksp->Ptc1023.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC1023); - - e1000g_ksp->Ptc1522.value.ul += - E1000_READ_REG(&Adapter->Shared, PTC1522); - - /* - * Livengood Counters - */ - e1000g_ksp->Tncrs.value.ul += - E1000_READ_REG(&Adapter->Shared, TNCRS); - - e1000g_ksp->Tsctc.value.ul += - E1000_READ_REG(&Adapter->Shared, TSCTC); - - e1000g_ksp->Tsctfc.value.ul += - E1000_READ_REG(&Adapter->Shared, TSCTFC); - - /* - * Mutex required if in TBI mode - */ - if (Adapter->Shared.tbi_compatibility_on == 1) { - mutex_exit(&Adapter->TbiCntrMutex); - } + rw_exit(&Adapter->chip_lock); return (0); } @@ -401,11 +309,14 @@ e1000g_m_stat(void *arg, uint_t stat, uint64_t *val) { struct e1000g *Adapter = (struct e1000g *)arg; - e1000gstat *e1000g_ksp; + struct e1000_hw *hw = &Adapter->shared; + p_e1000g_stat_t e1000g_ksp; uint32_t low_val, high_val; uint16_t phy_reg, phy_reg_2; - e1000g_ksp = (e1000gstat *)Adapter->e1000g_ksp->ks_data; + e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; + + rw_enter(&Adapter->chip_lock, RW_WRITER); switch (stat) { case MAC_STAT_IFSPEED: @@ -414,45 +325,45 @@ case MAC_STAT_MULTIRCV: e1000g_ksp->Mprc.value.ul += - E1000_READ_REG(&Adapter->Shared, MPRC); + E1000_READ_REG(hw, E1000_MPRC); *val = e1000g_ksp->Mprc.value.ul; break; case MAC_STAT_BRDCSTRCV: e1000g_ksp->Bprc.value.ul += - E1000_READ_REG(&Adapter->Shared, BPRC); + E1000_READ_REG(hw, E1000_BPRC); *val = e1000g_ksp->Bprc.value.ul; break; case MAC_STAT_MULTIXMT: e1000g_ksp->Mptc.value.ul += - E1000_READ_REG(&Adapter->Shared, MPTC); + E1000_READ_REG(hw, E1000_MPTC); *val = e1000g_ksp->Mptc.value.ul; break; case MAC_STAT_BRDCSTXMT: e1000g_ksp->Bptc.value.ul += - E1000_READ_REG(&Adapter->Shared, BPTC); + E1000_READ_REG(hw, E1000_BPTC); *val = e1000g_ksp->Bptc.value.ul; break; case MAC_STAT_NORCVBUF: e1000g_ksp->Rnbc.value.ul += - E1000_READ_REG(&Adapter->Shared, RNBC); + E1000_READ_REG(hw, E1000_RNBC); *val = e1000g_ksp->Rnbc.value.ul; break; case MAC_STAT_IERRORS: e1000g_ksp->Rxerrc.value.ul += - E1000_READ_REG(&Adapter->Shared, RXERRC); + E1000_READ_REG(hw, E1000_RXERRC); e1000g_ksp->Algnerrc.value.ul += - E1000_READ_REG(&Adapter->Shared, ALGNERRC); + E1000_READ_REG(hw, E1000_ALGNERRC); e1000g_ksp->Rlec.value.ul += - E1000_READ_REG(&Adapter->Shared, RLEC); + E1000_READ_REG(hw, E1000_RLEC); e1000g_ksp->Crcerrs.value.ul += - E1000_READ_REG(&Adapter->Shared, CRCERRS); + E1000_READ_REG(hw, E1000_CRCERRS); e1000g_ksp->Cexterr.value.ul += - E1000_READ_REG(&Adapter->Shared, CEXTERR); + E1000_READ_REG(hw, E1000_CEXTERR); *val = e1000g_ksp->Rxerrc.value.ul + e1000g_ksp->Algnerrc.value.ul + e1000g_ksp->Rlec.value.ul + @@ -461,18 +372,18 @@ break; case MAC_STAT_NOXMTBUF: - *val = Adapter->tx_no_desc; + *val = Adapter->tx_ring->stat_no_desc; break; case MAC_STAT_OERRORS: e1000g_ksp->Ecol.value.ul += - E1000_READ_REG(&Adapter->Shared, ECOL); + E1000_READ_REG(hw, E1000_ECOL); *val = e1000g_ksp->Ecol.value.ul; break; case MAC_STAT_COLLISIONS: e1000g_ksp->Colc.value.ul += - E1000_READ_REG(&Adapter->Shared, COLC); + E1000_READ_REG(hw, E1000_COLC); *val = e1000g_ksp->Colc.value.ul; break; @@ -482,8 +393,8 @@ * 32 bits are read. So we need to read the lower * 32 bits first, then read the upper 32 bits. */ - low_val = E1000_READ_REG(&Adapter->Shared, TORL); - high_val = E1000_READ_REG(&Adapter->Shared, TORH); + low_val = E1000_READ_REG(hw, E1000_TORL); + high_val = E1000_READ_REG(hw, E1000_TORH); *val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | (uint64_t)e1000g_ksp->Torl.value.ul; *val += (uint64_t)high_val << 32 | (uint64_t)low_val; @@ -494,7 +405,7 @@ case MAC_STAT_IPACKETS: e1000g_ksp->Tpr.value.ul += - E1000_READ_REG(&Adapter->Shared, TPR); + E1000_READ_REG(hw, E1000_TPR); *val = e1000g_ksp->Tpr.value.ul; break; @@ -504,8 +415,8 @@ * 32 bits are read. So we need to read the lower * 32 bits first, then read the upper 32 bits. */ - low_val = E1000_READ_REG(&Adapter->Shared, TOTL); - high_val = E1000_READ_REG(&Adapter->Shared, TOTH); + low_val = E1000_READ_REG(hw, E1000_TOTL); + high_val = E1000_READ_REG(hw, E1000_TOTH); *val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | (uint64_t)e1000g_ksp->Totl.value.ul; *val += (uint64_t)high_val << 32 | (uint64_t)low_val; @@ -516,79 +427,79 @@ case MAC_STAT_OPACKETS: e1000g_ksp->Tpt.value.ul += - E1000_READ_REG(&Adapter->Shared, TPT); + E1000_READ_REG(hw, E1000_TPT); *val = e1000g_ksp->Tpt.value.ul; break; case ETHER_STAT_ALIGN_ERRORS: e1000g_ksp->Algnerrc.value.ul += - E1000_READ_REG(&Adapter->Shared, ALGNERRC); + E1000_READ_REG(hw, E1000_ALGNERRC); *val = e1000g_ksp->Algnerrc.value.ul; break; case ETHER_STAT_FCS_ERRORS: e1000g_ksp->Crcerrs.value.ul += - E1000_READ_REG(&Adapter->Shared, CRCERRS); + E1000_READ_REG(hw, E1000_CRCERRS); *val = e1000g_ksp->Crcerrs.value.ul; break; case ETHER_STAT_SQE_ERRORS: e1000g_ksp->Sec.value.ul += - E1000_READ_REG(&Adapter->Shared, SEC); + E1000_READ_REG(hw, E1000_SEC); *val = e1000g_ksp->Sec.value.ul; break; case ETHER_STAT_CARRIER_ERRORS: e1000g_ksp->Cexterr.value.ul += - E1000_READ_REG(&Adapter->Shared, CEXTERR); + E1000_READ_REG(hw, E1000_CEXTERR); *val = e1000g_ksp->Cexterr.value.ul; break; case ETHER_STAT_EX_COLLISIONS: e1000g_ksp->Ecol.value.ul += - E1000_READ_REG(&Adapter->Shared, ECOL); + E1000_READ_REG(hw, E1000_ECOL); *val = e1000g_ksp->Ecol.value.ul; break; case ETHER_STAT_TX_LATE_COLLISIONS: e1000g_ksp->Latecol.value.ul += - E1000_READ_REG(&Adapter->Shared, LATECOL); + E1000_READ_REG(hw, E1000_LATECOL); *val = e1000g_ksp->Latecol.value.ul; break; case ETHER_STAT_DEFER_XMTS: e1000g_ksp->Dc.value.ul += - E1000_READ_REG(&Adapter->Shared, DC); + E1000_READ_REG(hw, E1000_DC); *val = e1000g_ksp->Dc.value.ul; break; case ETHER_STAT_FIRST_COLLISIONS: e1000g_ksp->Scc.value.ul += - E1000_READ_REG(&Adapter->Shared, SCC); + E1000_READ_REG(hw, E1000_SCC); *val = e1000g_ksp->Scc.value.ul; break; case ETHER_STAT_MULTI_COLLISIONS: e1000g_ksp->Mcc.value.ul += - E1000_READ_REG(&Adapter->Shared, MCC); + E1000_READ_REG(hw, E1000_MCC); *val = e1000g_ksp->Mcc.value.ul; break; case ETHER_STAT_MACRCV_ERRORS: e1000g_ksp->Rxerrc.value.ul += - E1000_READ_REG(&Adapter->Shared, RXERRC); + E1000_READ_REG(hw, E1000_RXERRC); *val = e1000g_ksp->Rxerrc.value.ul; break; case ETHER_STAT_MACXMT_ERRORS: e1000g_ksp->Ecol.value.ul += - E1000_READ_REG(&Adapter->Shared, ECOL); + E1000_READ_REG(hw, E1000_ECOL); *val = e1000g_ksp->Ecol.value.ul; break; case ETHER_STAT_TOOLONG_ERRORS: e1000g_ksp->Roc.value.ul += - E1000_READ_REG(&Adapter->Shared, ROC); + E1000_READ_REG(hw, E1000_ROC); *val = e1000g_ksp->Roc.value.ul; break; @@ -598,26 +509,24 @@ break; case ETHER_STAT_XCVR_ID: - e1000_read_phy_reg(&Adapter->Shared, PHY_ID1, &phy_reg); - e1000_read_phy_reg(&Adapter->Shared, PHY_ID2, &phy_reg_2); + e1000_read_phy_reg(hw, PHY_ID1, &phy_reg); + e1000_read_phy_reg(hw, PHY_ID2, &phy_reg_2); *val = (uint32_t)((phy_reg << 16) | phy_reg_2); break; case ETHER_STAT_XCVR_INUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); switch (Adapter->link_speed) { case SPEED_1000: *val = - (Adapter->Shared.media_type == - e1000_media_type_copper) ? XCVR_1000T : - XCVR_1000X; + (hw->media_type == e1000_media_type_copper) ? + XCVR_1000T : XCVR_1000X; break; case SPEED_100: *val = - (Adapter->Shared.media_type == - e1000_media_type_copper) ? (phy_reg & - MII_SR_100T4_CAPS) ? XCVR_100T4 : XCVR_100T2 : - XCVR_100X; + (hw->media_type == e1000_media_type_copper) ? + (phy_reg & MII_SR_100T4_CAPS) ? + XCVR_100T4 : XCVR_100T2 : XCVR_100X; break; case SPEED_10: *val = XCVR_10; @@ -629,178 +538,155 @@ break; case ETHER_STAT_CAP_1000FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_EXT_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); *val = ((phy_reg & IEEE_ESR_1000T_FD_CAPS) || (phy_reg & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; break; case ETHER_STAT_CAP_1000HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_EXT_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); *val = ((phy_reg & IEEE_ESR_1000T_HD_CAPS) || (phy_reg & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; break; case ETHER_STAT_CAP_100FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); *val = ((phy_reg & MII_SR_100X_FD_CAPS) || (phy_reg & MII_SR_100T2_FD_CAPS)) ? 1 : 0; break; case ETHER_STAT_CAP_100HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); *val = ((phy_reg & MII_SR_100X_HD_CAPS) || (phy_reg & MII_SR_100T2_HD_CAPS)) ? 1 : 0; break; case ETHER_STAT_CAP_10FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); *val = (phy_reg & MII_SR_10T_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_CAP_10HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); *val = (phy_reg & MII_SR_10T_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_CAP_ASMPAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; break; case ETHER_STAT_CAP_PAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; break; case ETHER_STAT_CAP_AUTONEG: - e1000_read_phy_reg(&Adapter->Shared, PHY_STATUS, &phy_reg); + e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); *val = (phy_reg & MII_SR_AUTONEG_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_1000FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_CTRL, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); *val = (phy_reg & CR_1000T_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_1000HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_CTRL, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); *val = (phy_reg & CR_1000T_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_100FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_100HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_10FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_10T_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_10HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_10T_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_ASMPAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_PAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; break; case ETHER_STAT_ADV_CAP_AUTONEG: - *val = Adapter->Shared.autoneg; + *val = hw->mac.autoneg; break; case ETHER_STAT_LP_CAP_1000FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); *val = (phy_reg & SR_1000T_LP_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_1000HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_1000T_STATUS, - &phy_reg); + e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); *val = (phy_reg & SR_1000T_LP_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_100FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_100HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_10FDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_10HDX: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; break; case ETHER_STAT_LP_CAP_ASMPAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_ASM_DIR) ? 1 : 0; break; case ETHER_STAT_LP_CAP_PAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_LP_ABILITY, - &phy_reg); + e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); *val = (phy_reg & NWAY_LPAR_PAUSE) ? 1 : 0; break; case ETHER_STAT_LP_CAP_AUTONEG: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_EXP, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_reg); *val = (phy_reg & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; break; case ETHER_STAT_LINK_ASMPAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; break; case ETHER_STAT_LINK_PAUSE: - e1000_read_phy_reg(&Adapter->Shared, PHY_AUTONEG_ADV, - &phy_reg); + e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; break; case ETHER_STAT_LINK_AUTONEG: - e1000_read_phy_reg(&Adapter->Shared, PHY_CTRL, &phy_reg); + e1000_read_phy_reg(hw, PHY_CONTROL, &phy_reg); *val = (phy_reg & MII_CR_AUTO_NEG_EN) ? 1 : 0; break; @@ -810,51 +696,33 @@ break; default: + rw_exit(&Adapter->chip_lock); return (ENOTSUP); } + rw_exit(&Adapter->chip_lock); + return (0); } /* - * ********************************************************************** - * Name: InitStatsCounters * - * * - * Description: This routine will create and initialize the kernel * - * statistics counters. * - * * - * Author: Phil Cayton * - * * - * Born on Date: 7/13/98 * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * '0' if unable to create kernel statistics structure. * - * '1' if creation and initialization successful * - * * - * File: e1000g_stat.c * - * * - * Modification log: * - * Date Who Description * - * -------- --- ------------------------------------------------------* - * * - * ********************************************************************** + * e1000g_init_stats - initialize kstat data structures + * + * This routine will create and initialize the driver private + * statistics counters. */ int -InitStatsCounters(IN struct e1000g *Adapter) +e1000g_init_stats(struct e1000g *Adapter) { kstat_t *ksp; - e1000gstat *e1000g_ksp; + p_e1000g_stat_t e1000g_ksp; /* * Create and init kstat */ ksp = kstat_create(WSNAME, ddi_get_instance(Adapter->dip), "statistics", "net", KSTAT_TYPE_NAMED, - sizeof (e1000gstat) / sizeof (kstat_named_t), 0); + sizeof (e1000g_stat_t) / sizeof (kstat_named_t), 0); if (ksp == NULL) { e1000g_log(Adapter, CE_WARN, @@ -864,246 +732,155 @@ Adapter->e1000g_ksp = ksp; /* Fill in the Adapters ksp */ - e1000g_ksp = (e1000gstat *) ksp->ks_data; + e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; /* * Initialize all the statistics */ kstat_named_init(&e1000g_ksp->link_speed, "link_speed", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->rx_none, "Rx No Data", + kstat_named_init(&e1000g_ksp->reset_count, "Reset Count", KSTAT_DATA_ULONG); kstat_named_init(&e1000g_ksp->rx_error, "Rx Error", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->rx_no_freepkt, "Rx Freelist Empty", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->rx_avail_freepkt, "Rx Freelist Avail", - KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->rx_esballoc_fail, "Rx Desballoc Failure", KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->rx_exceed_pkt, "Rx Exceed Max Pkt Count", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->rx_multi_desc, "Rx Span Multi Desc", - KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->rx_allocb_fail, "Rx Allocb Failure", KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->rx_seq_intr, "Rx Seq Err Intr", - KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->tx_no_desc, "Tx No Desc", KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->tx_no_swpkt, "Tx No Buffer", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_lack_desc, "Tx Desc Insufficient", + kstat_named_init(&e1000g_ksp->tx_send_fail, "Tx Send Failure", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->tx_over_size, "Tx Pkt Over Size", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->tx_reschedule, "Tx Reschedule", KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->tx_send_fail, - "Tx Send Failure", KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Mpc, "Recv_Missed_Packets", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Symerrs, "Recv_Symbol_Errors", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Rlec, "Recv_Length_Errors", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Xonrxc, "XONs_Recvd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Xontxc, "XONs_Xmitd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Xoffrxc, "XOFFs_Recvd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Xofftxc, "XOFFs_Xmitd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Fcruc, "Recv_Unsupport_FC_Pkts", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc64, "Pkts_Recvd_( 64b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc127, "Pkts_Recvd_( 65- 127b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc255, "Pkts_Recvd_( 127- 255b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc511, "Pkts_Recvd_( 256- 511b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc1023, "Pkts_Recvd_( 511-1023b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Prc1522, "Pkts_Recvd_(1024-1522b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Gprc, "Good_Pkts_Recvd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Gptc, "Good_Pkts_Xmitd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Gorl, "Good_Octets_Recvd_Lo", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Gorh, "Good_Octets_Recvd_Hi", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Gotl, "Good_Octets_Xmitd_Lo", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Goth, "Good_Octets_Xmitd_Hi", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ruc, "Recv_Undersize", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Rfc, "Recv_Frag", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Roc, "Recv_Oversize", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Rjc, "Recv_Jabber", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Torl, "Total_Octets_Recvd_Lo", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Torh, "Total_Octets_Recvd_Hi", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Totl, "Total_Octets_Xmitd_Lo", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Toth, "Total_Octets_Xmitd_Hi", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Tpr, "Total_Packets_Recvd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Tpt, "Total_Packets_Xmitd", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc64, "Pkts_Xmitd_( 64b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc127, "Pkts_Xmitd_( 65- 127b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc255, "Pkts_Xmitd_( 128- 255b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc511, "Pkts_Xmitd_( 255- 511b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc1023, "Pkts_Xmitd_( 512-1023b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Ptc1522, "Pkts_Xmitd_(1024-1522b)", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Tncrs, "Xmit_with_No_CRS", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Tsctc, "Xmit_TCP_Seg_Contexts", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->Tsctfc, "Xmit_TCP_Seg_Contexts_Fail", + KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->tx_multi_cookie, - "Tx Bind Multi Cookies", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_over_size, "Tx Pkt Over Size", +#ifdef E1000G_DEBUG + kstat_named_init(&e1000g_ksp->rx_none, "Rx No Data", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->rx_multi_desc, "Rx Span Multi Desc", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->rx_no_freepkt, "Rx Freelist Empty", + KSTAT_DATA_ULONG); + kstat_named_init(&e1000g_ksp->rx_avail_freepkt, "Rx Freelist Avail", KSTAT_DATA_ULONG); kstat_named_init(&e1000g_ksp->tx_under_size, "Tx Pkt Under Size", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_copy, "Tx Send Copy", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_bind, "Tx Send Bind", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_multi_copy, "Tx Copy Multi Frags", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_reschedule, "Tx Reschedule", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_empty_frags, "Tx Empty Frags", - KSTAT_DATA_ULONG); - kstat_named_init(&e1000g_ksp->tx_exceed_frags, "Tx Exceed Max Frags", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_recycle, - "Tx Desc Recycle", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_recycle_retry, - "Tx Desc Recycle Retry", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_recycle_intr, - "Tx Desc Recycle Intr", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->tx_recycle_none, - "Tx Desc Recycled None", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->StallWatchdog, - "Tx Stall Watchdog", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->reset_count, - "Reset Count", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->intr_type, - "Interrupt Type", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Mpc, "Recv_Missed_Packets", + kstat_named_init(&e1000g_ksp->tx_empty_frags, "Tx Empty Frags", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Symerrs, "Recv_Symbol_Errors", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Rlec, "Recv_Length_Errors", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Xonrxc, "XONs_Recvd", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Xontxc, "XONs_Xmitd", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Xoffrxc, "XOFFs_Recvd", + kstat_named_init(&e1000g_ksp->tx_recycle, "Tx Recycle", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Xofftxc, "XOFFs_Xmitd", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Fcruc, "Recv_Unsupport_FC_Pkts", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc64, "Pkts_Recvd_( 64b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc127, "Pkts_Recvd_( 65- 127b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc255, "Pkts_Recvd_( 127- 255b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc511, "Pkts_Recvd_( 256- 511b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc1023, "Pkts_Recvd_( 511-1023b)", + kstat_named_init(&e1000g_ksp->tx_recycle_intr, "Tx Recycle Intr", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Prc1522, "Pkts_Recvd_(1024-1522b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Gprc, "Good_Pkts_Recvd", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Gptc, "Good_Pkts_Xmitd", + kstat_named_init(&e1000g_ksp->tx_recycle_retry, "Tx Recycle Retry", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Gorl, "Good_Octets_Recvd_Lo", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Gorh, "Good_Octets_Recvd_Hi", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Gotl, "Good_Octets_Xmitd_Lo", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Goth, "Good_Octets_Xmitd_Hi", + kstat_named_init(&e1000g_ksp->tx_recycle_none, "Tx Recycled None", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ruc, "Recv_Undersize", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Rfc, "Recv_Frag", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Roc, "Recv_Oversize", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Rjc, "Recv_Jabber", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Torl, "Total_Octets_Recvd_Lo", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Torh, "Total_Octets_Recvd_Hi", + kstat_named_init(&e1000g_ksp->tx_copy, "Tx Send Copy", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Totl, "Total_Octets_Xmitd_Lo", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Toth, "Total_Octets_Xmitd_Hi", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Tpr, "Total_Packets_Recvd", + kstat_named_init(&e1000g_ksp->tx_bind, "Tx Send Bind", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Tpt, "Total_Packets_Xmitd", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc64, "Pkts_Xmitd_( 64b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc127, "Pkts_Xmitd_( 65- 127b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc255, "Pkts_Xmitd_( 128- 255b)", + kstat_named_init(&e1000g_ksp->tx_multi_copy, "Tx Copy Multi Frags", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc511, "Pkts_Xmitd_( 255- 511b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc1023, "Pkts_Xmitd_( 512-1023b)", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Ptc1522, "Pkts_Xmitd_(1024-1522b)", - KSTAT_DATA_ULONG); - - /* - * Livengood Initializations - */ - kstat_named_init(&e1000g_ksp->Tncrs, "Xmit_with_No_CRS", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Tsctc, "Xmit_TCP_Seg_Contexts", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->Tsctfc, "Xmit_TCP_Seg_Contexts_Fail", + kstat_named_init(&e1000g_ksp->tx_multi_cookie, "Tx Bind Multi Cookies", KSTAT_DATA_ULONG); - - /* - * Jumbo Frame Counters - */ - kstat_named_init(&e1000g_ksp->JumboTx_4K, "Jumbo Tx Frame 4K", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->JumboRx_4K, "Jumbo Rx Frame 4K", + kstat_named_init(&e1000g_ksp->tx_lack_desc, "Tx Desc Insufficient", KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->JumboTx_8K, "Jumbo Tx Frame 8K", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->JumboRx_8K, "Jumbo Rx Frame 8K", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->JumboTx_16K, "Jumbo Tx Frame 16K", - KSTAT_DATA_ULONG); - - kstat_named_init(&e1000g_ksp->JumboRx_16K, "Jumbo Rx Frame 16K", - KSTAT_DATA_ULONG); +#endif /* * Function to provide kernel stat update on demand */ - ksp->ks_update = UpdateStatsCounters; + ksp->ks_update = e1000g_update_stats; /* * Pointer into provider's raw statistics
--- a/usr/src/uts/common/io/e1000g/e1000g_sw.h Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_sw.h Tue Aug 21 00:30:10 2007 -0700 @@ -41,23 +41,9 @@ * This header file contains Software-related data structures * * definitions. * * * - * This driver runs on the following hardware: * - * - Wisemane based PCI gigabit ethernet adapters * - * * - * Environment: * - * Kernel Mode - * - * * * ********************************************************************** */ -#ifdef DEBUG -#define e1000g_DEBUG -#endif - -/* - * Solaris Multithreaded GLD wiseman PCI Ethernet Driver - */ - #include <sys/types.h> #include <sys/conf.h> #include <sys/debug.h> @@ -85,36 +71,8 @@ #include <inet/ip.h> #include <inet/mi.h> #include <inet/nd.h> -#include "e1000_hw.h" - -/* - * PCI Command Register Bit Definitions - * Configuration Space Header - */ -#define CMD_IO_SPACE 0x0001 /* BIT_0 */ -#define CMD_MEMORY_SPACE 0x0002 /* BIT_1 */ -#define CMD_BUS_MASTER 0x0004 /* BIT_2 */ -#define CMD_SPECIAL_CYCLES 0x0008 /* BIT_3 */ +#include "e1000_api.h" -#define CMD_VGA_PALLETTE_SNOOP 0x0020 /* BIT_5 */ -#define CMD_PARITY_RESPONSE 0x0040 /* BIT_6 */ -#define CMD_WAIT_CYCLE_CONTROL 0x0080 /* BIT_7 */ -#define CMD_SERR_ENABLE 0x0100 /* BIT_8 */ -#define CMD_BACK_TO_BACK 0x0200 /* BIT_9 */ - -#define WSDRAINTIME (200) /* # milliseconds xmit drain */ - -#ifdef __sparc -#ifdef _LP64 -#define DWORD_SWAP(value) (value) -#else -#define DWORD_SWAP(value) \ - (uint64_t)((((uint64_t)value & 0x00000000FFFFFFFF) << 32) | \ - (((uint64_t)value & 0xFFFFFFFF00000000) >> 32)) -#endif -#else -#define DWORD_SWAP(value) (value) -#endif #define JUMBO_FRAG_LENGTH 4096 @@ -133,55 +91,55 @@ #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ -#define MAXNUMTXDESCRIPTOR 4096 -#define MAXNUMRXDESCRIPTOR 4096 -#define MAXNUMRXFREELIST 4096 -#define MAXNUMTXSWPACKET 4096 -#define MAXNUMRCVPKTONINTR 4096 -#define MAXTXFRAGSLIMIT 1024 -#define MAXTXINTERRUPTDELAYVAL 65535 -#define MAXINTERRUPTTHROTTLINGVAL 65535 -#define MAXRXBCOPYTHRESHOLD E1000_RX_BUFFER_SIZE_2K -#define MAXTXBCOPYTHRESHOLD E1000_TX_BUFFER_SIZE_2K -#define MAXTXRECYCLELOWWATER \ - (DEFAULTNUMTXDESCRIPTOR - MAX_TX_DESC_PER_PACKET) -#define MAXTXRECYCLENUM DEFAULTNUMTXDESCRIPTOR +#define MAX_NUM_TX_DESCRIPTOR 4096 +#define MAX_NUM_RX_DESCRIPTOR 4096 +#define MAX_NUM_RX_FREELIST 4096 +#define MAX_NUM_TX_FREELIST 4096 +#define MAX_RX_LIMIT_ON_INTR 4096 +#define MAX_RX_INTR_DELAY 65535 +#define MAX_RX_INTR_ABS_DELAY 65535 +#define MAX_TX_INTR_DELAY 65535 +#define MAX_TX_INTR_ABS_DELAY 65535 +#define MAX_INTR_THROTTLING 65535 +#define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K +#define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K -#define MINNUMTXDESCRIPTOR 80 -#define MINNUMRXDESCRIPTOR 80 -#define MINNUMRXFREELIST 64 -#define MINNUMTXSWPACKET 80 -#define MINNUMRCVPKTONINTR 16 -#define MINTXFRAGSLIMIT 2 -#define MINTXINTERRUPTDELAYVAL 0 -#define MININTERRUPTTHROTTLINGVAL 0 -#define MINRXBCOPYTHRESHOLD 0 -#define MINTXBCOPYTHRESHOLD MINIMUM_ETHERNET_PACKET_SIZE -#define MINTXRECYCLELOWWATER MAX_TX_DESC_PER_PACKET -#define MINTXRECYCLENUM MAX_TX_DESC_PER_PACKET +#define MIN_NUM_TX_DESCRIPTOR 80 +#define MIN_NUM_RX_DESCRIPTOR 80 +#define MIN_NUM_RX_FREELIST 64 +#define MIN_NUM_TX_FREELIST 80 +#define MIN_RX_LIMIT_ON_INTR 16 +#define MIN_RX_INTR_DELAY 0 +#define MIN_RX_INTR_ABS_DELAY 0 +#define MIN_TX_INTR_DELAY 0 +#define MIN_TX_INTR_ABS_DELAY 0 +#define MIN_INTR_THROTTLING 0 +#define MIN_RX_BCOPY_THRESHOLD 0 +#define MIN_TX_BCOPY_THRESHOLD MINIMUM_ETHERNET_PACKET_SIZE -#define DEFAULTNUMTXDESCRIPTOR 2048 -#define DEFAULTNUMRXDESCRIPTOR 2048 -#define DEFAULTNUMRXFREELIST 4096 -#define DEFAULTNUMTXSWPACKET 2048 -#define DEFAULTMAXNUMRCVPKTONINTR 256 -#define DEFAULTTXFRAGSLIMIT 4 -#define DEFAULTFLOWCONTROLVAL 3 -#define DEFAULTTXINTERRUPTDELAYVAL 300 -#define DEFAULTINTERRUPTTHROTTLINGVAL 0x225 -#define DEFAULTMWIENABLEVAL 1 /* Only PCI 450NX chipset */ - /* needs this value to be 0 */ -#define DEFAULTMASTERLATENCYTIMERVAL 0 /* BIOS should decide */ +#define DEFAULT_NUM_RX_DESCRIPTOR 2048 +#define DEFAULT_NUM_TX_DESCRIPTOR 2048 +#define DEFAULT_NUM_RX_FREELIST 4096 +#define DEFAULT_NUM_TX_FREELIST 2048 +#define DEFAULT_RX_LIMIT_ON_INTR 256 +#define DEFAULT_RX_INTR_DELAY 0 +#define DEFAULT_RX_INTR_ABS_DELAY 0 +#define DEFAULT_TX_INTR_DELAY 300 +#define DEFAULT_TX_INTR_ABS_DELAY 0 +#define DEFAULT_INTR_THROTTLING 0x225 +#define DEFAULT_RX_BCOPY_THRESHOLD 0 +#define DEFAULT_TX_BCOPY_THRESHOLD 512 + +#define DEFAULT_TX_RECYCLE_LOW_WATER 64 +#define DEFAULT_TX_RECYCLE_NUM 128 +#define DEFAULT_TX_INTR_ENABLE 1 +#define DEFAULT_FLOW_CONTROL 3 +#define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ /* which is normally 0x040 */ -#define DEFAULTRXPCIPRIORITYVAL 1 /* Boolean value */ -#define DEFAULTPROFILEJUMBOTRAFFIC 1 /* Profile Jumbo Traffic */ -#define DEFAULTTBICOMPATIBILITYENABLE 1 /* Enable SBP workaround */ -#define DEFAULTMSIENABLE 1 /* MSI Enable */ +#define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ +#define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ -#define DEFAULTRXBCOPYTHRESHOLD 0 -#define DEFAULTTXBCOPYTHRESHOLD 512 -#define DEFAULTTXRECYCLELOWWATER 64 -#define DEFAULTTXRECYCLENUM 128 +#define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ /* * The size of the receive/transmite buffers @@ -201,14 +159,8 @@ #define E1000G_RX_SW_FREE 0x0 #define E1000G_RX_SW_SENDUP 0x1 -#define E1000G_RX_SW_DETACHED 0x2 - -/* - * By default it will print only to log - */ -#define DEFAULTDEBUGLEVEL 0x004 -#define DEFAULTDISPLAYONLY 0 -#define DEFAULTPRINTONLY 1 +#define E1000G_RX_SW_STOP 0x2 +#define E1000G_RX_SW_DETACH 0x3 /* * definitions for smartspeed workaround @@ -231,24 +183,23 @@ #define E1000G_IPALIGNPRESERVEROOM 64 #define E1000G_IMS_TX_INTR (E1000_IMS_TXDW | E1000_IMS_TXQE) -#define E1000G_IMC_TX_INTR (E1000_IMC_TXDW | E1000_IMC_TXQE) #define E1000G_ICR_TX_INTR (E1000_ICR_TXDW | E1000_ICR_TXQE) /* * bit flags for 'attach_progress' which is a member variable in struct e1000g */ -#define ATTACH_PROGRESS_SOFTINTR 0x0001 /* Soft interrupt added */ -#define ATTACH_PROGRESS_REGSMAPPED 0x0002 /* registers mapped */ -#define ATTACH_PROGRESS_LOCKS 0x0004 /* locks initialized */ -#define ATTACH_PROGRESS_PCICONFIG 0x0008 /* PCI config set up */ -#define ATTACH_PROGRESS_KSTATS 0x0010 /* kstats created */ -#define ATTACH_PROGRESS_INIT 0x0020 /* reset */ -#define ATTACH_PROGRESS_INTRADDED 0x0040 /* interrupts added */ -#define ATTACH_PROGRESS_MACREGISTERED 0x0080 /* MAC registered */ -#define ATTACH_PROGRESS_PROP 0x0100 /* properties initialized */ +#define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ +#define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ +#define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ +#define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ +#define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ +#define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ +#define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ +#define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ +#define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ #define ATTACH_PROGRESS_NDD 0x0200 /* NDD initialized */ -#define ATTACH_PROGRESS_INTRENABLED 0x0400 /* DDI interrupts enabled */ -#define ATTACH_PROGRESS_ALLOC 0x0800 /* DMA resources allocated */ +#define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ +#define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ /* * Speed and Duplex Settings @@ -259,7 +210,6 @@ #define GDIAG_100_FULL 4 #define GDIAG_1000_FULL 6 #define GDIAG_ANY 7 -#define MAX_DEVICES 256 /* * Coexist Workaround RP: 07/04/03 @@ -276,12 +226,17 @@ #define FRAME_SIZE_UPTO_4K 4096 #define FRAME_SIZE_UPTO_8K 8192 #define FRAME_SIZE_UPTO_16K 16384 -#define FRAME_SIZE_UPTO_10K 10500 +#define FRAME_SIZE_UPTO_9K 9234 -/* - * Max microsecond for ITR (Interrupt Throttling Register) - */ -#define E1000_ITR_MAX_MICROSECOND 0x3fff +/* The sizes (in bytes) of a ethernet packet */ +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ +#define ETHERNET_FCS_SIZE 4 +#define MAXIMUM_ETHERNET_PACKET_SIZE \ + (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define MINIMUM_ETHERNET_PACKET_SIZE \ + (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define CRC_LENGTH ETHERNET_FCS_SIZE /* Defines for Tx stall check */ #define E1000G_STALL_WATCHDOG_COUNT 8 @@ -303,10 +258,6 @@ #define E1000G_LB_INTERNAL_PHY 4 -#define GET_ETHER_TYPE(ptr) (\ - (((uint8_t *)&((struct ether_header *)ptr)->ether_type)[0] << 8) | \ - (((uint8_t *)&((struct ether_header *)ptr)->ether_type)[1])) - /* * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. */ @@ -430,14 +381,9 @@ #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val - #define param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val -#define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val -#define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val -#define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val -#define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val - +#ifdef E1000G_DEBUG /* * E1000G-specific ioctls ... */ @@ -461,6 +407,7 @@ uint64_t pp_acc_data; /* output for peek */ /* input for poke */ } e1000g_peekpoke_t; +#endif /* E1000G_DEBUG */ /* * (Internal) return values from ioctl subroutines @@ -541,11 +488,9 @@ PARAM_INTR_TYPE, PARAM_TX_BCOPY_THRESHOLD, - PARAM_TX_FRAGS_LIMIT, - PARAM_TX_RECYCLE_LOW_WATER, - PARAM_TX_RECYCLE_NUM, PARAM_TX_INTR_ENABLE, - PARAM_TX_INTR_DELAY, + PARAM_TX_TIDV, + PARAM_TX_TADV, PARAM_RX_BCOPY_THRESHOLD, PARAM_RX_PKT_ON_INTR, PARAM_RX_RDTR, @@ -554,36 +499,6 @@ PARAM_COUNT }; -static struct ether_addr etherbroadcastaddr = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; - -/* - * DMA access attributes <Little Endian Card> - */ -static ddi_device_acc_attr_t accattr = { - DDI_DEVICE_ATTR_V0, - DDI_STRUCTURE_LE_ACC, - DDI_STRICTORDER_ACC, -}; - -/* - * DMA access attributes for receive buffer <Big Endian> for Sparc - */ -#ifdef __sparc -static ddi_device_acc_attr_t accattr2 = { - DDI_DEVICE_ATTR_V0, - DDI_STRUCTURE_BE_ACC, - DDI_STRICTORDER_ACC, -}; -#else -static ddi_device_acc_attr_t accattr2 = { - DDI_DEVICE_ATTR_V0, - DDI_STRUCTURE_LE_ACC, - DDI_STRICTORDER_ACC, -}; -#endif - typedef struct _private_devi_list { dev_info_t *dip; dev_info_t *priv_dip; @@ -608,15 +523,15 @@ /* * Address-Length pair structure that stores descriptor info */ -typedef struct _ADDRESS_LENGTH_PAIR { - uint64_t Address; - uint32_t Length; -} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; +typedef struct _sw_desc { + uint64_t address; + uint32_t length; +} sw_desc_t, *p_sw_desc_t; -typedef struct _DESCRIPTOR_PAIR { - ADDRESS_LENGTH_PAIR Descriptor[4]; - uint32_t Elements; -} DESC_ARRAY, *PDESC_ARRAY; +typedef struct _desc_array { + sw_desc_t descriptor[4]; + uint32_t elements; +} desc_array_t, *p_desc_array_t; typedef enum { USE_NONE, @@ -632,7 +547,7 @@ ddi_dma_handle_t dma_handle; size_t size; size_t len; -} dma_buffer_t, *pdma_buffer_t; +} dma_buffer_t, *p_dma_buffer_t; /* * Transmit Control Block (TCB), Ndis equiv of SWPacket This @@ -641,43 +556,42 @@ * message block pointer and the TBD addresses associated with * the m_blk and also the link to the next tcb in the chain */ -typedef struct _TX_SW_PACKET_ { - /* Link to the next TX_SW_PACKET in the list */ +typedef struct _tx_sw_packet { + /* Link to the next tx_sw_packet in the list */ SINGLE_LIST_LINK Link; mblk_t *mp; - UINT num_desc; - UINT num_mblk_frag; + uint32_t num_desc; + uint32_t num_mblk_frag; dma_type_t dma_type; dma_type_t data_transfer_type; ddi_dma_handle_t tx_dma_handle; dma_buffer_t tx_buf[1]; - ADDRESS_LENGTH_PAIR desc[MAX_TX_DESC_PER_PACKET + 1]; -} TX_SW_PACKET, *PTX_SW_PACKET; + sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; +} tx_sw_packet_t, *p_tx_sw_packet_t; /* - * This structure is similar to the RX_SW_PACKET structure used + * This structure is similar to the rx_sw_packet structure used * for Ndis. This structure stores information about the 2k * aligned receive buffer into which the FX1000 DMA's frames. * This structure is maintained as a linked list of many * receiver buffer pointers. */ -typedef struct _RX_SW_PACKET { - /* Link to the next RX_SW_PACKET in the list */ +typedef struct _rx_sw_apcket { + /* Link to the next rx_sw_packet_t in the list */ SINGLE_LIST_LINK Link; - struct _RX_SW_PACKET *next; + struct _rx_sw_apcket *next; uint16_t flag; mblk_t *mp; caddr_t rx_ring; dma_type_t dma_type; frtn_t free_rtn; dma_buffer_t rx_buf[1]; -} RX_SW_PACKET, *PRX_SW_PACKET; +} rx_sw_packet_t, *p_rx_sw_packet_t; -typedef struct _e1000g_msg_chain { +typedef struct _mblk_list { mblk_t *head; mblk_t *tail; - kmutex_t lock; -} e1000g_msg_chain_t; +} mblk_list_t, *p_mblk_list_t; typedef struct _cksum_data { uint32_t ether_header_size; @@ -686,17 +600,6 @@ uint32_t cksum_stuff; } cksum_data_t; -/* - * MultiCast Command Block (MULTICAST_CB) The multicast - * structure contains an array of multicast addresses and - * also a count of the total number of addresses. - */ -typedef struct _multicast_cb_t { - ushort_t mc_count; /* Number of multicast addresses */ - uchar_t MulticastBuffer[(ETH_LENGTH_OF_ADDRESS * - MAX_NUM_MULTICAST_ADDRESSES)]; -} mltcst_cb_t, *pmltcst_cb_t; - typedef union _e1000g_ether_addr { struct { uint32_t high; @@ -705,42 +608,46 @@ struct { uint8_t set; uint8_t redundant; - uint8_t addr[NODE_ADDRESS_SIZE]; + uint8_t addr[ETHERADDRL]; } mac; } e1000g_ether_addr_t; -typedef struct _e1000gstat { +typedef struct _e1000g_stat { kstat_named_t link_speed; /* Link Speed */ - kstat_named_t rx_none; /* Rx No Incoming Data */ + kstat_named_t reset_count; /* Reset Count */ + kstat_named_t rx_error; /* Rx Error in Packet */ kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ + kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ + kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ + + kstat_named_t tx_no_desc; /* Tx No Desc */ + kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ + kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ + kstat_named_t tx_over_size; /* Tx Pkt Too Long */ + kstat_named_t tx_reschedule; /* Tx Reschedule */ + +#ifdef E1000G_DEBUG + kstat_named_t rx_none; /* Rx No Incoming Data */ kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ - kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ - kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ - kstat_named_t rx_seq_intr; /* Rx Sequencing Errors Intr */ - kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ - kstat_named_t tx_no_desc; /* Tx No Desc */ - kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ - kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ - kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ - kstat_named_t tx_over_size; /* Tx Pkt Too Long */ - kstat_named_t tx_under_size; /* Tx Allocb Failure */ - kstat_named_t tx_reschedule; /* Tx Reschedule */ + + kstat_named_t tx_under_size; /* Tx Packet Under Size */ kstat_named_t tx_empty_frags; /* Tx Empty Frags */ kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ kstat_named_t tx_recycle; /* Tx Recycle */ + kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ - kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ kstat_named_t tx_copy; /* Tx Send Copy */ kstat_named_t tx_bind; /* Tx Send Bind */ kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ - kstat_named_t StallWatchdog; /* Tx Stall Watchdog */ - kstat_named_t reset_count; /* Reset Count */ - kstat_named_t intr_type; /* Interrupt Type */ + kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ + kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ +#endif + kstat_named_t Crcerrs; /* CRC Error Count */ kstat_named_t Symerrs; /* Symbol Error Count */ kstat_named_t Mpc; /* Missed Packet Count */ @@ -790,9 +697,6 @@ kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ kstat_named_t Mptc; /* Multicast Packets Xmited Count */ kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ - /* - * New Livengood Stat Counters - */ kstat_named_t Algnerrc; /* Alignment Error count */ kstat_named_t Tuc; /* Transmit Underrun count */ kstat_named_t Rxerrc; /* Rx Error Count */ @@ -801,22 +705,13 @@ kstat_named_t Rutec; /* Receive DMA too Early count */ kstat_named_t Tsctc; /* TCP seg contexts xmit count */ kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ - /* - * Jumbo Frame Counters - */ - kstat_named_t JumboTx_4K; /* 4k Jumbo Frames Transmitted */ - kstat_named_t JumboRx_4K; /* 4k Jumbo Frames Received */ - kstat_named_t JumboTx_8K; /* 8k Jumbo Frames Transmitted */ - kstat_named_t JumboRx_8K; /* 8k Jumbo Frames Received */ - kstat_named_t JumboTx_16K; /* 16k Jumbo Frames Transmitted */ - kstat_named_t JumboRx_16K; /* 16k Jumbo Frames Received */ - -} e1000gstat, *e1000gstatp; +} e1000g_stat_t, *p_e1000g_stat_t; typedef struct _e1000g_tx_ring { kmutex_t tx_lock; kmutex_t freelist_lock; kmutex_t usedlist_lock; + kmutex_t mblks_lock; /* * Descriptor queue definitions */ @@ -828,10 +723,11 @@ struct e1000_tx_desc *tbd_last; struct e1000_tx_desc *tbd_oldest; struct e1000_tx_desc *tbd_next; + uint32_t tbd_avail; /* * Software packet structures definitions */ - PTX_SW_PACKET packet_area; + p_tx_sw_packet_t packet_area; LIST_DESCRIBER used_list; LIST_DESCRIBER free_list; /* @@ -844,6 +740,38 @@ timeout_id_t timer_id_82547; boolean_t timer_enable_82547; /* + * reschedule when tx resource is available + */ + boolean_t resched_needed; + uint32_t recycle_low_water; + uint32_t recycle_num; + uint32_t frags_limit; + uint32_t stall_watchdog; + uint32_t recycle_fail; + mblk_list_t mblks; + /* + * Statistics + */ + uint32_t stat_no_swpkt; + uint32_t stat_no_desc; + uint32_t stat_send_fail; + uint32_t stat_reschedule; + uint32_t stat_over_size; +#ifdef E1000G_DEBUG + uint32_t stat_under_size; + uint32_t stat_exceed_frags; + uint32_t stat_empty_frags; + uint32_t stat_recycle; + uint32_t stat_recycle_intr; + uint32_t stat_recycle_retry; + uint32_t stat_recycle_none; + uint32_t stat_copy; + uint32_t stat_bind; + uint32_t stat_multi_copy; + uint32_t stat_multi_cookie; + uint32_t stat_lack_desc; +#endif + /* * Pointer to the adapter */ struct e1000g *adapter; @@ -865,9 +793,28 @@ /* * Software packet structures definitions */ - PRX_SW_PACKET packet_area; + p_rx_sw_packet_t packet_area; LIST_DESCRIBER recv_list; LIST_DESCRIBER free_list; + + p_rx_sw_packet_t pending_list; + uint32_t pending_count; + uint32_t avail_freepkt; + uint32_t rx_mblk_len; + mblk_t *rx_mblk; + mblk_t *rx_mblk_tail; + /* + * Statistics + */ + uint32_t stat_error; + uint32_t stat_esballoc_fail; + uint32_t stat_allocb_fail; + uint32_t stat_exceed_pkt; +#ifdef E1000G_DEBUG + uint32_t stat_none; + uint32_t stat_multi_desc; + uint32_t stat_no_freepkt; +#endif /* * Pointer to the adapter */ @@ -875,56 +822,72 @@ } e1000g_rx_ring_t, *pe1000g_rx_ring_t; typedef struct e1000g { - mac_handle_t mh; + int instance; dev_info_t *dip; dev_info_t *priv_dip; - ddi_acc_handle_t handle; - ddi_acc_handle_t E1000_handle; /* Ws-PCI handle to regs */ - int AdapterInstance; - struct e1000_hw Shared; + mac_handle_t mh; + mac_resource_handle_t mrh; + struct e1000_hw shared; struct e1000g_osdep osdep; + boolean_t started; + boolean_t e1000g_promisc; + boolean_t strip_crc; + boolean_t rx_buffer_setup; link_state_t link_state; - UINT link_speed; - UINT link_duplex; - UINT NumRxDescriptors; - UINT NumRxFreeList; - UINT NumTxDescriptors; - UINT NumTxSwPacket; - UINT MaxNumReceivePackets; - UINT bar64; - USHORT TxInterruptDelay; - USHORT MWIEnable; - UINT MasterLatencyTimer; -#ifdef e1000g_DEBUG - UINT DebugLevel; - UINT DisplayOnly; - UINT PrintOnly; + uint32_t link_speed; + uint32_t link_duplex; + uint32_t master_latency_timer; + uint32_t smartspeed; /* smartspeed w/a counter */ + uint32_t init_count; + uint32_t reset_count; + uint32_t attach_progress; /* attach tracking */ + uint32_t loopback_mode; + + uint32_t tx_desc_num; + uint32_t tx_freelist_num; + uint32_t rx_desc_num; + uint32_t rx_freelist_num; + uint32_t tx_buffer_size; + uint32_t rx_buffer_size; + + uint32_t tx_link_down_timeout; + uint32_t tx_bcopy_thresh; + uint32_t rx_limit_onintr; + uint32_t rx_bcopy_thresh; +#ifndef NO_82542_SUPPORT + uint32_t rx_buf_align; #endif - UINT smartspeed; /* smartspeed w/a counter */ - uint32_t init_count; - size_t TxBufferSize; - size_t RxBufferSize; + boolean_t intr_adaptive; + boolean_t tx_intr_enable; + uint32_t tx_intr_delay; + uint32_t tx_intr_abs_delay; + uint32_t rx_intr_delay; + uint32_t rx_intr_abs_delay; uint32_t intr_throttling_rate; - timeout_id_t WatchDogTimer_id; + + boolean_t watchdog_timer_enabled; + boolean_t watchdog_timer_started; + timeout_id_t watchdog_tid; + boolean_t link_complete; timeout_id_t link_tid; - boolean_t link_complete; - boolean_t strip_crc; + + e1000g_rx_ring_t rx_ring[1]; + e1000g_tx_ring_t tx_ring[1]; /* - * The e1000g_timeout_lock must be held when updateing the + * The watchdog_lock must be held when updateing the * timeout fields in struct e1000g, that is, - * WatchDogTimer_id, timeout_enabled, timeout_started. + * watchdog_tid, watchdog_timer_started. */ - kmutex_t e1000g_timeout_lock; + kmutex_t watchdog_lock; /* - * The e1000g_linklock protects the link fields in struct e1000g, + * The link_lock protects the link fields in struct e1000g, * such as link_state, link_speed, link_duplex, link_complete, and * link_tid. */ - kmutex_t e1000g_linklock; - kmutex_t TbiCntrMutex; + kmutex_t link_lock; /* * The chip_lock assures that the Rx/Tx process must be * stopped while other functions change the hardware @@ -933,68 +896,6 @@ */ krwlock_t chip_lock; - e1000g_rx_ring_t rx_ring[1]; - e1000g_tx_ring_t tx_ring[1]; - - uint32_t rx_bcopy_thresh; - uint32_t tx_bcopy_thresh; - uint32_t tx_recycle_low_water; - uint32_t tx_recycle_num; - uint32_t tx_frags_limit; - uint32_t tx_link_down_timeout; - - boolean_t tx_intr_enable; - ddi_softint_handle_t tx_softint_handle; - int tx_softint_pri; - /* - * Message chain that needs to be freed - */ - e1000g_msg_chain_t tx_msg_chain[1]; - - mblk_t *rx_mblk; - mblk_t *rx_mblk_tail; - USHORT rx_packet_len; - - kstat_t *e1000g_ksp; - - uint32_t rx_none; - uint32_t rx_error; - uint32_t rx_exceed_pkt; - uint32_t rx_multi_desc; - uint32_t rx_no_freepkt; - uint32_t rx_esballoc_fail; - uint32_t rx_avail_freepkt; - uint32_t rx_allocb_fail; - uint32_t rx_seq_intr; - uint32_t tx_lack_desc; - uint32_t tx_no_desc; - uint32_t tx_no_swpkt; - uint32_t tx_send_fail; - uint32_t tx_multi_cookie; - uint32_t tx_over_size; - uint32_t tx_under_size; - uint32_t tx_reschedule; - uint32_t tx_empty_frags; - uint32_t tx_exceed_frags; - uint32_t tx_recycle; - uint32_t tx_recycle_retry; - uint32_t tx_recycle_intr; - uint32_t tx_recycle_none; - uint32_t tx_copy; - uint32_t tx_bind; - uint32_t tx_multi_copy; - - uint32_t JumboTx_4K; - uint32_t JumboRx_4K; - uint32_t JumboTx_8K; - uint32_t JumboRx_8K; - uint32_t JumboTx_16K; - uint32_t JumboRx_16K; - - uint32_t StallWatchdog; - uint32_t tx_recycle_fail; - uint32_t reset_count; - uint32_t unicst_avail; uint32_t unicst_total; e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; @@ -1002,24 +903,6 @@ uint32_t mcast_count; struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; - uint32_t loopback_mode; - - UINT ProfileJumboTraffic; - UINT RcvBufferAlignment; - - boolean_t timeout_enabled; - boolean_t timeout_started; - - boolean_t e1000g_promisc; - boolean_t started; - mac_resource_handle_t mrh; - - uint32_t attach_progress; /* attach tracking */ - /* - * reschedule when tx resource is available - */ - boolean_t resched_needed; - #ifdef __sparc ulong_t sys_page_sz; uint_t dvma_page_num; @@ -1033,95 +916,58 @@ uint_t intr_pri; ddi_intr_handle_t *htable; + int tx_softint_pri; + ddi_softint_handle_t tx_softint_handle; + + kstat_t *e1000g_ksp; + /* * NDD parameters */ caddr_t nd_data; nd_param_t nd_params[PARAM_COUNT]; -} e1000g, *Pe1000g, ADAPTER_STRUCT, *PADAPTER_STRUCT; - - -static ddi_dma_attr_t tx_dma_attr = { - DMA_ATTR_V0, /* version of this structure */ - 0, /* lowest usable address */ - 0xffffffffffffffffULL, /* highest usable address */ - 0x7fffffff, /* maximum DMAable byte count */ - 1, /* alignment in bytes */ - 0x7ff, /* burst sizes (any?) */ - 1, /* minimum transfer */ - 0xffffffffU, /* maximum transfer */ - 0xffffffffffffffffULL, /* maximum segment length */ - 16, /* maximum number of segments */ - 1, /* granularity */ - 0, /* flags (reserved) */ -}; +} e1000g_t; -static ddi_dma_attr_t buf_dma_attr = { - DMA_ATTR_V0, /* version of this structure */ - 0, /* lowest usable address */ - 0xffffffffffffffffULL, /* highest usable address */ - 0x7fffffff, /* maximum DMAable byte count */ - 1, /* alignment in bytes */ - 0x7ff, /* burst sizes (any?) */ - 1, /* minimum transfer */ - 0xffffffffU, /* maximum transfer */ - 0xffffffffffffffffULL, /* maximum segment length */ - 1, /* maximum number of segments */ - 1, /* granularity */ - 0, /* flags (reserved) */ -}; - -static ddi_dma_attr_t tbd_dma_attr = { - DMA_ATTR_V0, /* version of this structure */ - 0, /* lowest usable address */ - 0xffffffffffffffffULL, /* highest usable address */ - 0x7fffffff, /* maximum DMAable byte count */ - E1000_MDALIGN, /* alignment in bytes 4K! */ - 0x7ff, /* burst sizes (any?) */ - 1, /* minimum transfer */ - 0xffffffffU, /* maximum transfer */ - 0xffffffffffffffffULL, /* maximum segment length */ - 1, /* maximum number of segments */ - 1, /* granularity */ - 0, /* flags (reserved) */ -}; /* * Function prototypes */ int e1000g_alloc_dma_resources(struct e1000g *Adapter); void e1000g_release_dma_resources(struct e1000g *Adapter); -void e1000g_free_rx_sw_packet(PRX_SW_PACKET packet); -void SetupTransmitStructures(struct e1000g *Adapter); -void SetupReceiveStructures(struct e1000g *Adapter); -void SetupMulticastTable(struct e1000g *Adapter); +void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); +void e1000g_tx_setup(struct e1000g *Adapter); +void e1000g_rx_setup(struct e1000g *Adapter); +void e1000g_setup_multicast(struct e1000g *Adapter); boolean_t e1000g_reset(struct e1000g *Adapter); int e1000g_recycle(e1000g_tx_ring_t *tx_ring); -void FreeTxSwPacket(PTX_SW_PACKET packet); -uint_t e1000g_tx_freemsg(caddr_t arg1, caddr_t arg2); +void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); +void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); +uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); mblk_t *e1000g_receive(struct e1000g *Adapter); -void e1000g_rxfree_func(PRX_SW_PACKET packet); +void e1000g_rxfree_func(p_rx_sw_packet_t packet); int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); -int InitStatsCounters(struct e1000g *Adapter); -void AdjustTbiAcceptedStats(struct e1000g *Adapter, UINT32 FrameLength, - PUCHAR MacAddress); +int e1000g_init_stats(struct e1000g *Adapter); +void e1000_tbi_adjust_stats(struct e1000g *Adapter, + uint32_t frame_len, uint8_t *mac_addr); enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter, queue_t *wq, mblk_t *mp, struct iocblk *iocp); void e1000g_nd_cleanup(struct e1000g *Adapter); int e1000g_nd_init(struct e1000g *Adapter); -void e1000g_DisableInterrupt(struct e1000g *Adapter); -void e1000g_EnableInterrupt(struct e1000g *Adapter); -void e1000g_DisableAllInterrupts(struct e1000g *Adapter); -void e1000g_DisableTxInterrupt(struct e1000g *Adapter); -void e1000g_EnableTxInterrupt(struct e1000g *Adapter); +void e1000g_clear_interrupt(struct e1000g *Adapter); +void e1000g_mask_interrupt(struct e1000g *Adapter); +void e1000g_clear_all_interrupts(struct e1000g *Adapter); +void e1000g_clear_tx_interrupt(struct e1000g *Adapter); +void e1000g_mask_tx_interrupt(struct e1000g *Adapter); void phy_spd_state(struct e1000_hw *hw, boolean_t enable); void e1000_enable_pciex_master(struct e1000_hw *hw); +#pragma inline(e1000_rar_set) + /* * Global variables */
--- a/usr/src/uts/common/io/e1000g/e1000g_tx.c Mon Aug 20 23:01:08 2007 -0700 +++ b/usr/src/uts/common/io/e1000g/e1000g_tx.c Tue Aug 21 00:30:10 2007 -0700 @@ -32,22 +32,9 @@ * e1000g_tx.c * * * * Abstract: * - * This file contains some routines that takes care of Transmit * - * interrupt and also makes the hardware to send the data pointed * - * by the packet out on to the physical medium. * - * * - * * - * Environment: * - * Kernel Mode - * - * * - * Source History: * - * The code in this file is based somewhat on the "send" code * - * developed for the Intel Pro/100 family(Speedo1 and Speedo3) by * - * Steve Lindsay, and partly on some sample DDK code * - * of solaris. * - * * - * March 12, 1997 Steve Lindsay * - * 1st created - Ported from E100B send.c file * + * This file contains some routines that take care of Transmit, * + * make the hardware to send the data pointed by the packet out * + * on to the physical medium. * * * * ********************************************************************** */ @@ -56,27 +43,26 @@ #include "e1000g_debug.h" static boolean_t e1000g_send(struct e1000g *, mblk_t *); -static int e1000g_tx_copy(struct e1000g *, PTX_SW_PACKET, mblk_t *, uint32_t); -static int e1000g_tx_bind(struct e1000g *, PTX_SW_PACKET, mblk_t *); +static int e1000g_tx_copy(e1000g_tx_ring_t *, + p_tx_sw_packet_t, mblk_t *, uint32_t); +static int e1000g_tx_bind(e1000g_tx_ring_t *, + p_tx_sw_packet_t, mblk_t *); static boolean_t check_cksum_context(e1000g_tx_ring_t *, cksum_data_t *); static int e1000g_fill_tx_ring(e1000g_tx_ring_t *, LIST_DESCRIBER *, cksum_data_t *); static void e1000g_fill_context_descriptor(cksum_data_t *, struct e1000_context_desc *); -static int e1000g_fill_tx_desc(struct e1000g *, - PTX_SW_PACKET, uint64_t, size_t); +static int e1000g_fill_tx_desc(e1000g_tx_ring_t *, + p_tx_sw_packet_t, uint64_t, size_t); static uint32_t e1000g_fill_82544_desc(uint64_t Address, size_t Length, - PDESC_ARRAY desc_array); -static int e1000g_tx_workaround_PCIX_82544(struct e1000g *, - PTX_SW_PACKET, uint64_t, size_t); -static int e1000g_tx_workaround_jumbo_82544(struct e1000g *, - PTX_SW_PACKET, uint64_t, size_t); -static uint32_t e1000g_tx_free_desc_num(e1000g_tx_ring_t *); + p_desc_array_t desc_array); +static int e1000g_tx_workaround_PCIX_82544(p_tx_sw_packet_t, uint64_t, size_t); +static int e1000g_tx_workaround_jumbo_82544(p_tx_sw_packet_t, uint64_t, size_t); static void e1000g_82547_timeout(void *); static void e1000g_82547_tx_move_tail(e1000g_tx_ring_t *); static void e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *); -#ifndef e1000g_DEBUG +#ifndef E1000G_DEBUG #pragma inline(e1000g_tx_copy) #pragma inline(e1000g_tx_bind) #pragma inline(check_cksum_context) @@ -86,28 +72,17 @@ #pragma inline(e1000g_fill_82544_desc) #pragma inline(e1000g_tx_workaround_PCIX_82544) #pragma inline(e1000g_tx_workaround_jumbo_82544) -#pragma inline(FreeTxSwPacket) -#pragma inline(e1000g_tx_free_desc_num) +#pragma inline(e1000g_free_tx_swpkt) #endif /* - * ********************************************************************** - * Name: FreeTxSwPacket * - * * - * Description: * - * Frees up the previusly allocated Dma handle for given * - * transmit sw packet. * - * * - * Parameter Passed: * - * * - * Return Value: * - * * - * Functions called: * - * * - * ********************************************************************** + * e1000g_free_tx_swpkt - free up the tx sw packet + * + * Unbind the previously bound DMA handle for a given + * transmit sw packet. And reset the sw packet data. */ void -FreeTxSwPacket(register PTX_SW_PACKET packet) +e1000g_free_tx_swpkt(register p_tx_sw_packet_t packet) { switch (packet->data_transfer_type) { case USE_BCOPY: @@ -136,46 +111,43 @@ packet->num_desc = 0; } +#pragma inline(e1000g_tx_freemsg) + +void +e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring) +{ + mblk_t *mp; + + if (mutex_tryenter(&tx_ring->mblks_lock) == 0) + return; + + mp = tx_ring->mblks.head; + + tx_ring->mblks.head = NULL; + tx_ring->mblks.tail = NULL; + + mutex_exit(&tx_ring->mblks_lock); + + if (mp != NULL) + freemsgchain(mp); +} + uint_t -e1000g_tx_freemsg(caddr_t arg1, caddr_t arg2) +e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2) { struct e1000g *Adapter; mblk_t *mp; Adapter = (struct e1000g *)arg1; - if ((Adapter == NULL) || (arg2 != NULL)) + if (Adapter == NULL) return (DDI_INTR_UNCLAIMED); - if (!mutex_tryenter(&Adapter->tx_msg_chain->lock)) - return (DDI_INTR_CLAIMED); - - mp = Adapter->tx_msg_chain->head; - Adapter->tx_msg_chain->head = NULL; - Adapter->tx_msg_chain->tail = NULL; - - mutex_exit(&Adapter->tx_msg_chain->lock); - - freemsgchain(mp); + e1000g_tx_freemsg(Adapter->tx_ring); return (DDI_INTR_CLAIMED); } -static uint32_t -e1000g_tx_free_desc_num(e1000g_tx_ring_t *tx_ring) -{ - struct e1000g *Adapter; - int num; - - Adapter = tx_ring->adapter; - - num = tx_ring->tbd_oldest - tx_ring->tbd_next; - if (num <= 0) - num += Adapter->NumTxDescriptors; - - return (num); -} - mblk_t * e1000g_m_tx(void *arg, mblk_t *mp) { @@ -206,30 +178,18 @@ } /* - * ********************************************************************** - * Name: e1000g_send * - * * - * Description: * - * Called from e1000g_m_tx with an mp ready to send. this * - * routine sets up the transmit descriptors and sends to * - * the wire. It also pushes the just transmitted packet to * - * the used tx sw packet list * - * * - * Arguments: * - * Pointer to the mblk to be sent, pointer to this adapter * - * * - * Returns: * - * B_TRUE, B_FALSE * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * ********************************************************************** + * e1000g_send - send packets onto the wire + * + * Called from e1000g_m_tx with an mblk ready to send. this + * routine sets up the transmit descriptors and sends data to + * the wire. It also pushes the just transmitted packet to + * the used tx sw packet list. */ static boolean_t e1000g_send(struct e1000g *Adapter, mblk_t *mp) { - PTX_SW_PACKET packet; + struct e1000_hw *hw; + p_tx_sw_packet_t packet; LIST_DESCRIBER pending_list; size_t len; size_t msg_size; @@ -242,6 +202,9 @@ e1000g_tx_ring_t *tx_ring; cksum_data_t cksum; + hw = &Adapter->shared; + tx_ring = Adapter->tx_ring; + /* Get the total size and frags number of the message */ force_bcopy = 0; frag_count = 0; @@ -258,20 +221,18 @@ } /* Make sure packet is less than the max frame size */ - if (msg_size > Adapter->Shared.max_frame_size + VLAN_TAGSZ) { + if (msg_size > hw->mac.max_frame_size + VLAN_TAGSZ) { /* * For the over size packet, we'll just drop it. * So we return B_TRUE here. */ - e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, "Tx packet out of bound. length = %d \n", msg_size); + E1000G_STAT(tx_ring->stat_over_size); freemsg(mp); - Adapter->tx_over_size++; return (B_TRUE); } - tx_ring = Adapter->tx_ring; - /* * Check and reclaim tx descriptors. * This low water mark check should be done all the time as @@ -280,19 +241,14 @@ * Descriptors... As you may run short of them before getting any * transmit interrupt... */ - if ((Adapter->NumTxDescriptors - e1000g_tx_free_desc_num(tx_ring)) > - Adapter->tx_recycle_low_water) { - if (Adapter->Shared.mac_type == e1000_82547) { - mutex_enter(&tx_ring->tx_lock); - e1000g_82547_tx_move_tail(tx_ring); - mutex_exit(&tx_ring->tx_lock); - } - Adapter->tx_recycle++; + if ((Adapter->tx_desc_num - tx_ring->tbd_avail) > + tx_ring->recycle_low_water) { + E1000G_DEBUG_STAT(tx_ring->stat_recycle); (void) e1000g_recycle(tx_ring); } - if (e1000g_tx_free_desc_num(tx_ring) < MAX_TX_DESC_PER_PACKET) { - Adapter->tx_lack_desc++; + if (tx_ring->tbd_avail < MAX_TX_DESC_PER_PACKET) { + E1000G_DEBUG_STAT(tx_ring->stat_lack_desc); goto tx_no_resource; } @@ -300,9 +256,9 @@ * If there are many frags of the message, then bcopy them * into one tx descriptor buffer will get better performance. */ - if ((frag_count >= Adapter->tx_frags_limit) && - (msg_size <= Adapter->TxBufferSize)) { - Adapter->tx_exceed_frags++; + if ((frag_count >= tx_ring->frags_limit) && + (msg_size <= Adapter->tx_buffer_size)) { + E1000G_DEBUG_STAT(tx_ring->stat_exceed_frags); force_bcopy |= FORCE_BCOPY_EXCEED_FRAGS; } @@ -311,7 +267,7 @@ * we'll use bcopy to send it, and padd it to 60 bytes later. */ if (msg_size < MINIMUM_ETHERNET_PACKET_SIZE) { - Adapter->tx_under_size++; + E1000G_DEBUG_STAT(tx_ring->stat_under_size); force_bcopy |= FORCE_BCOPY_UNDER_SIZE; } @@ -339,7 +295,7 @@ len = MBLKL(nmp); /* Check zero length mblks */ if (len == 0) { - Adapter->tx_empty_frags++; + E1000G_DEBUG_STAT(tx_ring->stat_empty_frags); /* * If there're no packet buffers have been used, * or we just completed processing a buffer, then @@ -359,14 +315,14 @@ if (desc_count > 0) { mutex_enter(&tx_ring->freelist_lock); - packet = (PTX_SW_PACKET) + packet = (p_tx_sw_packet_t) QUEUE_POP_HEAD(&tx_ring->free_list); mutex_exit(&tx_ring->freelist_lock); if (packet == NULL) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "No Tx SwPacket available\n"); - Adapter->tx_no_swpkt++; + E1000G_STAT(tx_ring->stat_no_swpkt); goto tx_send_failed; } QUEUE_PUSH_TAIL(&pending_list, &packet->Link); @@ -379,19 +335,18 @@ */ if ((len <= Adapter->tx_bcopy_thresh) || force_bcopy) { desc_count = - e1000g_tx_copy(Adapter, packet, nmp, force_bcopy); - Adapter->tx_copy++; + e1000g_tx_copy(tx_ring, packet, nmp, force_bcopy); + E1000G_DEBUG_STAT(tx_ring->stat_copy); } else { desc_count = - e1000g_tx_bind(Adapter, packet, nmp); - Adapter->tx_bind++; + e1000g_tx_bind(tx_ring, packet, nmp); + E1000G_DEBUG_STAT(tx_ring->stat_bind); } - if (desc_count < 0) - goto tx_send_failed; - if (desc_count > 0) desc_total += desc_count; + else if (desc_count < 0) + goto tx_send_failed; nmp = tmp; } @@ -402,8 +357,8 @@ packet->mp = mp; /* Try to recycle the tx descriptors again */ - if (e1000g_tx_free_desc_num(tx_ring) < MAX_TX_DESC_PER_PACKET) { - Adapter->tx_recycle_retry++; + if (tx_ring->tbd_avail < (desc_total + 2)) { + E1000G_DEBUG_STAT(tx_ring->stat_recycle_retry); (void) e1000g_recycle(tx_ring); } @@ -414,10 +369,10 @@ * (one redundant descriptor and one hw checksum context descriptor are * included), then return failure. */ - if (e1000g_tx_free_desc_num(tx_ring) < (desc_total + 2)) { - e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, + if (tx_ring->tbd_avail < (desc_total + 2)) { + E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, "No Enough Tx descriptors\n"); - Adapter->tx_no_desc++; + E1000G_STAT(tx_ring->stat_no_desc); mutex_exit(&tx_ring->tx_lock); goto tx_send_failed; } @@ -428,31 +383,16 @@ ASSERT(desc_count > 0); - /* Update statistic counters */ - if (Adapter->ProfileJumboTraffic) { - if ((msg_size > ETHERMAX) && - (msg_size <= FRAME_SIZE_UPTO_4K)) - Adapter->JumboTx_4K++; - - if ((msg_size > FRAME_SIZE_UPTO_4K) && - (msg_size <= FRAME_SIZE_UPTO_8K)) - Adapter->JumboTx_8K++; - - if ((msg_size > FRAME_SIZE_UPTO_8K) && - (msg_size <= FRAME_SIZE_UPTO_16K)) - Adapter->JumboTx_16K++; - } - /* Send successful */ return (B_TRUE); tx_send_failed: /* Free pending TxSwPackets */ - packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&pending_list); + packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&pending_list); while (packet) { packet->mp = NULL; - FreeTxSwPacket(packet); - packet = (PTX_SW_PACKET) + e1000g_free_tx_swpkt(packet); + packet = (p_tx_sw_packet_t) QUEUE_GET_NEXT(&pending_list, &packet->Link); } @@ -461,7 +401,7 @@ QUEUE_APPEND(&tx_ring->free_list, &pending_list); mutex_exit(&tx_ring->freelist_lock); - Adapter->tx_send_fail++; + E1000G_STAT(tx_ring->stat_send_fail); freemsg(mp); @@ -473,9 +413,9 @@ * Enable Transmit interrupts, so that the interrupt routine can * call mac_tx_update() when transmit descriptors become available. */ - Adapter->resched_needed = B_TRUE; + tx_ring->resched_needed = B_TRUE; if (!Adapter->tx_intr_enable) - e1000g_EnableTxInterrupt(Adapter); + e1000g_mask_tx_interrupt(Adapter); /* Message will be scheduled for re-transmit */ return (B_FALSE); @@ -508,18 +448,18 @@ cksum_data_t *cksum) { struct e1000g *Adapter; - PTX_SW_PACKET first_packet; - PTX_SW_PACKET packet; + struct e1000_hw *hw; + p_tx_sw_packet_t first_packet; + p_tx_sw_packet_t packet; boolean_t cksum_load; struct e1000_tx_desc *first_data_desc; struct e1000_tx_desc *next_desc; struct e1000_tx_desc *descriptor; - uint32_t sync_offset; - int sync_len; int desc_count; int i; Adapter = tx_ring->adapter; + hw = &Adapter->shared; desc_count = 0; first_packet = NULL; @@ -532,7 +472,7 @@ cksum_load = check_cksum_context(tx_ring, cksum); if (cksum_load) { - first_packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(pending_list); + first_packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(pending_list); descriptor = next_desc; @@ -550,23 +490,18 @@ first_data_desc = next_desc; - packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(pending_list); + packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(pending_list); while (packet) { ASSERT(packet->num_desc); for (i = 0; i < packet->num_desc; i++) { - ASSERT(e1000g_tx_free_desc_num(tx_ring) > 0); + ASSERT(tx_ring->tbd_avail > 0); descriptor = next_desc; -#ifdef __sparc descriptor->buffer_addr = - DWORD_SWAP(packet->desc[i].Address); -#else - descriptor->buffer_addr = - packet->desc[i].Address; -#endif + packet->desc[i].address; descriptor->lower.data = - packet->desc[i].Length; + packet->desc[i].length; /* Zero out status */ descriptor->upper.data = 0; @@ -595,7 +530,7 @@ first_packet = NULL; } - packet = (PTX_SW_PACKET) + packet = (p_tx_sw_packet_t) QUEUE_GET_NEXT(pending_list, &packet->Link); } @@ -614,7 +549,7 @@ * Last Descriptor of Packet needs End Of Packet (EOP), Report * Status (RS) and append Ethernet CRC (IFCS) bits set. */ - if (Adapter->TxInterruptDelay) { + if (Adapter->tx_intr_delay) { descriptor->lower.data |= E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; } else { @@ -625,25 +560,8 @@ /* * Sync the Tx descriptors DMA buffer */ - sync_offset = tx_ring->tbd_next - tx_ring->tbd_first; - sync_len = descriptor - tx_ring->tbd_next + 1; - /* Check the wrap-around case */ - if (sync_len > 0) { - (void) ddi_dma_sync(tx_ring->tbd_dma_handle, - sync_offset * sizeof (struct e1000_tx_desc), - sync_len * sizeof (struct e1000_tx_desc), - DDI_DMA_SYNC_FORDEV); - } else { - (void) ddi_dma_sync(tx_ring->tbd_dma_handle, - sync_offset * sizeof (struct e1000_tx_desc), - 0, - DDI_DMA_SYNC_FORDEV); - sync_len = descriptor - tx_ring->tbd_first + 1; - (void) ddi_dma_sync(tx_ring->tbd_dma_handle, - 0, - sync_len * sizeof (struct e1000_tx_desc), - DDI_DMA_SYNC_FORDEV); - } + (void) ddi_dma_sync(tx_ring->tbd_dma_handle, + 0, 0, DDI_DMA_SYNC_FORDEV); tx_ring->tbd_next = next_desc; @@ -651,15 +569,16 @@ * Advance the Transmit Descriptor Tail (Tdt), this tells the * FX1000 that this frame is available to transmit. */ - if (Adapter->Shared.mac_type == e1000_82547) + if (hw->mac.type == e1000_82547) e1000g_82547_tx_move_tail(tx_ring); else - E1000_WRITE_REG(&Adapter->Shared, TDT, + E1000_WRITE_REG(hw, E1000_TDT, (uint32_t)(next_desc - tx_ring->tbd_first)); /* Put the pending SwPackets to the "Used" list */ mutex_enter(&tx_ring->usedlist_lock); QUEUE_APPEND(&tx_ring->used_list, pending_list); + tx_ring->tbd_avail -= desc_count; mutex_exit(&tx_ring->usedlist_lock); /* Store the cksum data */ @@ -671,39 +590,17 @@ /* - * ********************************************************************** - * Name: SetupTransmitStructures * - * * - * Description: This routine initializes all of the transmit related * - * structures. This includes the Transmit descriptors, the * - * coalesce buffers, and the TX_SW_PACKETs structures. * - * * - * NOTE -- The device must have been reset before this * - * routine is called. * - * * - * Author: Hari Seshadri * - * Functions Called : get_32bit_value * - * * - * * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * (none) * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** + * e1000g_tx_setup - setup tx data structures + * + * This routine initializes all of the transmit related + * structures. This includes the Transmit descriptors, + * and the tx_sw_packet structures. */ void -SetupTransmitStructures(struct e1000g *Adapter) +e1000g_tx_setup(struct e1000g *Adapter) { struct e1000_hw *hw; - PTX_SW_PACKET packet; + p_tx_sw_packet_t packet; UINT i; uint32_t buf_high; uint32_t buf_low; @@ -714,13 +611,13 @@ int size; e1000g_tx_ring_t *tx_ring; - hw = &Adapter->Shared; + hw = &Adapter->shared; tx_ring = Adapter->tx_ring; /* init the lists */ /* * Here we don't need to protect the lists using the - * tx_usedlist_lock and tx_freelist_lock, for they have + * usedlist_lock and freelist_lock, for they have * been protected by the chip_lock. */ QUEUE_INIT_LIST(&tx_ring->used_list); @@ -728,10 +625,10 @@ /* Go through and set up each SW_Packet */ packet = tx_ring->packet_area; - for (i = 0; i < Adapter->NumTxSwPacket; i++, packet++) { - /* Initialize this TX_SW_PACKET area */ - FreeTxSwPacket(packet); - /* Add this TX_SW_PACKET to the free list */ + for (i = 0; i < Adapter->tx_freelist_num; i++, packet++) { + /* Initialize this tx_sw_apcket area */ + e1000g_free_tx_swpkt(packet); + /* Add this tx_sw_packet to the free list */ QUEUE_PUSH_TAIL(&tx_ring->free_list, &packet->Link); } @@ -746,69 +643,69 @@ /* Setup the Transmit Control Register (TCTL). */ reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | - (E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT); + (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | + E1000_TCTL_RTLC; /* Enable the MULR bit */ - if (hw->bus_type == e1000_bus_type_pci_express) + if (hw->bus.type == e1000_bus_type_pci_express) reg_tctl |= E1000_TCTL_MULR; - E1000_WRITE_REG(hw, TCTL, reg_tctl); + E1000_WRITE_REG(hw, E1000_TCTL, reg_tctl); - if ((hw->mac_type == e1000_82571) || (hw->mac_type == e1000_82572)) { + if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { e1000_get_speed_and_duplex(hw, &speed, &duplex); - reg_tarc = E1000_READ_REG(hw, TARC0); + reg_tarc = E1000_READ_REG(hw, E1000_TARC0); reg_tarc |= (1 << 25); if (speed == SPEED_1000) reg_tarc |= (1 << 21); - E1000_WRITE_REG(hw, TARC0, reg_tarc); + E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); - reg_tarc = E1000_READ_REG(hw, TARC1); + reg_tarc = E1000_READ_REG(hw, E1000_TARC1); reg_tarc |= (1 << 25); if (reg_tctl & E1000_TCTL_MULR) reg_tarc &= ~(1 << 28); else reg_tarc |= (1 << 28); - E1000_WRITE_REG(hw, TARC1, reg_tarc); + E1000_WRITE_REG(hw, E1000_TARC1, reg_tarc); - } else if (hw->mac_type == e1000_80003es2lan) { - reg_tarc = E1000_READ_REG(hw, TARC0); + } else if (hw->mac.type == e1000_80003es2lan) { + reg_tarc = E1000_READ_REG(hw, E1000_TARC0); reg_tarc |= 1; if (hw->media_type == e1000_media_type_internal_serdes) reg_tarc |= (1 << 20); - E1000_WRITE_REG(hw, TARC0, reg_tarc); + E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); - reg_tarc = E1000_READ_REG(hw, TARC1); + reg_tarc = E1000_READ_REG(hw, E1000_TARC1); reg_tarc |= 1; - E1000_WRITE_REG(hw, TARC1, reg_tarc); + E1000_WRITE_REG(hw, E1000_TARC1, reg_tarc); } /* Setup HW Base and Length of Tx descriptor area */ - size = (Adapter->NumTxDescriptors * sizeof (struct e1000_tx_desc)); - E1000_WRITE_REG(hw, TDLEN, size); - size = E1000_READ_REG(hw, TDLEN); + size = (Adapter->tx_desc_num * sizeof (struct e1000_tx_desc)); + E1000_WRITE_REG(hw, E1000_TDLEN, size); + size = E1000_READ_REG(hw, E1000_TDLEN); buf_low = (uint32_t)tx_ring->tbd_dma_addr; buf_high = (uint32_t)(tx_ring->tbd_dma_addr >> 32); - E1000_WRITE_REG(hw, TDBAL, buf_low); - E1000_WRITE_REG(hw, TDBAH, buf_high); + E1000_WRITE_REG(hw, E1000_TDBAL, buf_low); + E1000_WRITE_REG(hw, E1000_TDBAH, buf_high); /* Setup our HW Tx Head & Tail descriptor pointers */ - E1000_WRITE_REG(hw, TDH, 0); - E1000_WRITE_REG(hw, TDT, 0); + E1000_WRITE_REG(hw, E1000_TDH, 0); + E1000_WRITE_REG(hw, E1000_TDT, 0); /* Set the default values for the Tx Inter Packet Gap timer */ - switch (hw->mac_type) { - case e1000_82542_rev2_0: - case e1000_82542_rev2_1: + if ((hw->mac.type == e1000_82542) && + ((hw->revision_id == E1000_REVISION_2) || + (hw->revision_id == E1000_REVISION_3))) { reg_tipg = DEFAULT_82542_TIPG_IPGT; reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; - break; - default: + } else { if (hw->media_type == e1000_media_type_fiber) reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; else @@ -817,62 +714,32 @@ DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; - break; } - E1000_WRITE_REG(hw, TIPG, reg_tipg); + E1000_WRITE_REG(hw, E1000_TIPG, reg_tipg); /* Setup Transmit Interrupt Delay Value */ - if (Adapter->TxInterruptDelay) { - E1000_WRITE_REG(hw, TIDV, Adapter->TxInterruptDelay); + if (Adapter->tx_intr_delay) { + E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); } + tx_ring->tbd_avail = Adapter->tx_desc_num; + /* For TCP/UDP checksum offload */ tx_ring->cksum_data.cksum_stuff = 0; tx_ring->cksum_data.cksum_start = 0; tx_ring->cksum_data.cksum_flags = 0; tx_ring->cksum_data.ether_header_size = 0; - - /* Initialize tx parameters */ - Adapter->tx_bcopy_thresh = DEFAULTTXBCOPYTHRESHOLD; - Adapter->tx_recycle_low_water = DEFAULTTXRECYCLELOWWATER; - Adapter->tx_recycle_num = DEFAULTTXRECYCLENUM; - Adapter->tx_intr_enable = B_TRUE; - Adapter->tx_frags_limit = - (Adapter->Shared.max_frame_size / Adapter->tx_bcopy_thresh) + 2; - if (Adapter->tx_frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) - Adapter->tx_frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); } /* - * ********************************************************************** - * Name: e1000g_recycle * - * * - * Description: This routine cleans transmit packets. * - * * - * * - * * - * Arguments: * - * Adapter - A pointer to our context sensitive "Adapter" * - * structure. * - * * - * Returns: * - * (none) * - * Functions Called: * - * None * - * * - * Modification log: * - * Date Who Description * - * -------- --- ----------------------------------------------------- * - * * - * ********************************************************************** + * e1000g_recycle - recycle the tx descriptors and tx sw packets */ int e1000g_recycle(e1000g_tx_ring_t *tx_ring) { struct e1000g *Adapter; LIST_DESCRIBER pending_list; - PTX_SW_PACKET packet; - e1000g_msg_chain_t *msg_chain; + p_tx_sw_packet_t packet; mblk_t *mp; mblk_t *nmp; struct e1000_tx_desc *descriptor; @@ -891,42 +758,38 @@ mutex_enter(&tx_ring->usedlist_lock); - packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); + packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); if (packet == NULL) { mutex_exit(&tx_ring->usedlist_lock); - Adapter->tx_recycle_fail = 0; - Adapter->StallWatchdog = 0; + tx_ring->recycle_fail = 0; + tx_ring->stall_watchdog = 0; return (0); } + /* Sync the Tx descriptor DMA buffer */ + (void) ddi_dma_sync(tx_ring->tbd_dma_handle, + 0, 0, DDI_DMA_SYNC_FORKERNEL); + /* * While there are still TxSwPackets in the used queue check them */ while (packet = - (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list)) { + (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list)) { /* * Get hold of the next descriptor that the e1000g will * report status back to (this will be the last descriptor - * of a given TxSwPacket). We only want to free the - * TxSwPacket (and it resources) if the e1000g is done + * of a given sw packet). We only want to free the + * sw packet (and it resources) if the e1000g is done * with ALL of the descriptors. If the e1000g is done * with the last one then it is done with all of them. */ ASSERT(packet->num_desc); - descriptor = tx_ring->tbd_oldest + - (packet->num_desc - 1); + descriptor = tx_ring->tbd_oldest + (packet->num_desc - 1); /* Check for wrap case */ if (descriptor > tx_ring->tbd_last) - descriptor -= Adapter->NumTxDescriptors; - - /* Sync the Tx descriptor DMA buffer */ - (void) ddi_dma_sync(tx_ring->tbd_dma_handle, - (descriptor - tx_ring->tbd_first) * - sizeof (struct e1000_tx_desc), - sizeof (struct e1000_tx_desc), - DDI_DMA_SYNC_FORCPU); + descriptor -= Adapter->tx_desc_num; /* * If the descriptor done bit is set free TxSwPacket and @@ -945,11 +808,11 @@ desc_count += packet->num_desc; - if (desc_count >= Adapter->tx_recycle_num) + if (desc_count >= tx_ring->recycle_num) break; } else { /* - * Found a TxSwPacket that the e1000g is not done + * Found a sw packet that the e1000g is not done * with then there is no reason to check the rest * of the queue. */ @@ -957,20 +820,22 @@ } } + tx_ring->tbd_avail += desc_count; + mutex_exit(&tx_ring->usedlist_lock); if (desc_count == 0) { - Adapter->tx_recycle_fail++; - Adapter->tx_recycle_none++; + tx_ring->recycle_fail++; + E1000G_DEBUG_STAT(tx_ring->stat_recycle_none); return (0); } - Adapter->tx_recycle_fail = 0; - Adapter->StallWatchdog = 0; + tx_ring->recycle_fail = 0; + tx_ring->stall_watchdog = 0; mp = NULL; nmp = NULL; - packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&pending_list); + packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&pending_list); ASSERT(packet != NULL); while (packet != NULL) { if (packet->mp != NULL) { @@ -988,24 +853,23 @@ } /* Free the TxSwPackets */ - FreeTxSwPacket(packet); + e1000g_free_tx_swpkt(packet); - packet = (PTX_SW_PACKET) + packet = (p_tx_sw_packet_t) QUEUE_GET_NEXT(&pending_list, &packet->Link); } /* Save the message chain */ if (mp != NULL) { - msg_chain = Adapter->tx_msg_chain; - mutex_enter(&msg_chain->lock); - if (msg_chain->head == NULL) { - msg_chain->head = mp; - msg_chain->tail = nmp; + mutex_enter(&tx_ring->mblks_lock); + if (tx_ring->mblks.head == NULL) { + tx_ring->mblks.head = mp; + tx_ring->mblks.tail = nmp; } else { - msg_chain->tail->b_next = mp; - msg_chain->tail = nmp; + tx_ring->mblks.tail->b_next = mp; + tx_ring->mblks.tail = nmp; } - mutex_exit(&msg_chain->lock); + mutex_exit(&tx_ring->mblks_lock); /* * If the tx interrupt is enabled, the messages will be freed @@ -1078,8 +942,8 @@ * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c(DAC) */ static uint32_t -e1000g_fill_82544_desc(uint64_t Address, - size_t Length, PDESC_ARRAY desc_array) +e1000g_fill_82544_desc(uint64_t address, + size_t length, p_desc_array_t desc_array) { /* * Since issue is sensitive to length and address. @@ -1087,39 +951,38 @@ */ uint32_t safe_terminator; - if (Length <= 4) { - desc_array->Descriptor[0].Address = Address; - desc_array->Descriptor[0].Length = Length; - desc_array->Elements = 1; - return (desc_array->Elements); + if (length <= 4) { + desc_array->descriptor[0].address = address; + desc_array->descriptor[0].length = length; + desc_array->elements = 1; + return (desc_array->elements); } safe_terminator = - (uint32_t)((((uint32_t)Address & 0x7) + - (Length & 0xF)) & 0xF); + (uint32_t)((((uint32_t)address & 0x7) + + (length & 0xF)) & 0xF); /* * if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then * return */ if (safe_terminator == 0 || - (safe_terminator > 4 && - safe_terminator < 9) || + (safe_terminator > 4 && safe_terminator < 9) || (safe_terminator > 0xC && safe_terminator <= 0xF)) { - desc_array->Descriptor[0].Address = Address; - desc_array->Descriptor[0].Length = Length; - desc_array->Elements = 1; - return (desc_array->Elements); + desc_array->descriptor[0].address = address; + desc_array->descriptor[0].length = length; + desc_array->elements = 1; + return (desc_array->elements); } - desc_array->Descriptor[0].Address = Address; - desc_array->Descriptor[0].Length = Length - 4; - desc_array->Descriptor[1].Address = Address + (Length - 4); - desc_array->Descriptor[1].Length = 4; - desc_array->Elements = 2; - return (desc_array->Elements); + desc_array->descriptor[0].address = address; + desc_array->descriptor[0].length = length - 4; + desc_array->descriptor[1].address = address + (length - 4); + desc_array->descriptor[1].length = 4; + desc_array->elements = 2; + return (desc_array->elements); } static int -e1000g_tx_copy(struct e1000g *Adapter, PTX_SW_PACKET packet, +e1000g_tx_copy(e1000g_tx_ring_t *tx_ring, p_tx_sw_packet_t packet, mblk_t *mp, uint32_t force_bcopy) { size_t len; @@ -1153,15 +1016,15 @@ finished = B_TRUE; else if (force_bcopy) finished = B_FALSE; - else if (len1 > Adapter->tx_bcopy_thresh) + else if (len1 > tx_ring->adapter->tx_bcopy_thresh) finished = B_TRUE; else finished = B_FALSE; } if (finished) { - if (tx_buf->len > len) - Adapter->tx_multi_copy++; + E1000G_DEBUG_STAT_COND(tx_ring->stat_multi_copy, + (tx_buf->len > len)); /* * If the packet is smaller than 64 bytes, which is the @@ -1177,24 +1040,20 @@ tx_buf->len = MINIMUM_ETHERNET_PACKET_SIZE; } - switch (packet->dma_type) { #ifdef __sparc - case USE_DVMA: + if (packet->dma_type == USE_DVMA) dvma_sync(tx_buf->dma_handle, 0, DDI_DMA_SYNC_FORDEV); - break; -#endif - case USE_DMA: + else (void) ddi_dma_sync(tx_buf->dma_handle, 0, tx_buf->len, DDI_DMA_SYNC_FORDEV); - break; - default: - ASSERT(B_FALSE); - break; - } +#else + (void) ddi_dma_sync(tx_buf->dma_handle, 0, + tx_buf->len, DDI_DMA_SYNC_FORDEV); +#endif packet->data_transfer_type = USE_BCOPY; - desc_count = e1000g_fill_tx_desc(Adapter, + desc_count = e1000g_fill_tx_desc(tx_ring, packet, tx_buf->dma_address, tx_buf->len); @@ -1207,7 +1066,7 @@ } static int -e1000g_tx_bind(struct e1000g *Adapter, PTX_SW_PACKET packet, mblk_t *mp) +e1000g_tx_bind(e1000g_tx_ring_t *tx_ring, p_tx_sw_packet_t packet, mblk_t *mp) { int j; int mystat; @@ -1255,7 +1114,7 @@ DDI_DMA_DONTWAIT, 0, &dma_cookie, &ncookies)) != DDI_DMA_MAPPED) { - e1000g_log(Adapter, CE_WARN, + e1000g_log(tx_ring->adapter, CE_WARN, "Couldn't bind mblk buffer to Tx DMA handle: " "return: %X, Pkt: %X\n", mystat, packet); @@ -1269,12 +1128,12 @@ * here any more. */ ASSERT(ncookies); - if (ncookies > 1) - Adapter->tx_multi_cookie++; + E1000G_DEBUG_STAT_COND(tx_ring->stat_multi_cookie, + (ncookies > 1)); /* * The data_transfer_type value must be set after the handle - * has been bound, for it will be used in FreeTxSwPacket() + * has been bound, for it will be used in e1000g_free_tx_swpkt() * to decide whether we need to unbind the handle. */ packet->data_transfer_type = USE_DMA; @@ -1292,7 +1151,7 @@ */ for (j = ncookies; j != 0; j--) { - desc_count = e1000g_fill_tx_desc(Adapter, + desc_count = e1000g_fill_tx_desc(tx_ring, packet, dma_cookie.dmac_laddress, dma_cookie.dmac_size); @@ -1372,52 +1231,44 @@ } static int -e1000g_fill_tx_desc(struct e1000g *Adapter, - PTX_SW_PACKET packet, uint64_t address, size_t size) +e1000g_fill_tx_desc(e1000g_tx_ring_t *tx_ring, + p_tx_sw_packet_t packet, uint64_t address, size_t size) { - PADDRESS_LENGTH_PAIR desc; - int desc_count; - - desc_count = 0; - - if ((Adapter->Shared.bus_type == e1000_bus_type_pcix) && - (Adapter->Shared.mac_type == e1000_82544)) { - - desc_count = e1000g_tx_workaround_PCIX_82544(Adapter, - packet, address, size); + struct e1000_hw *hw = &tx_ring->adapter->shared; + p_sw_desc_t desc; - } else if ((Adapter->Shared.mac_type == e1000_82544) && - (size > JUMBO_FRAG_LENGTH)) { - - desc_count = e1000g_tx_workaround_jumbo_82544(Adapter, - packet, address, size); + if (hw->mac.type == e1000_82544) { + if (hw->bus.type == e1000_bus_type_pcix) + return (e1000g_tx_workaround_PCIX_82544(packet, + address, size)); - } else { - ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); - - desc = &packet->desc[packet->num_desc]; - - desc->Address = address; - desc->Length = size; - - packet->num_desc++; - desc_count++; + if (size > JUMBO_FRAG_LENGTH) + return (e1000g_tx_workaround_jumbo_82544(packet, + address, size)); } - return (desc_count); + ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); + + desc = &packet->desc[packet->num_desc]; + desc->address = address; + desc->length = size; + + packet->num_desc++; + + return (1); } static int -e1000g_tx_workaround_PCIX_82544(struct e1000g *Adapter, - PTX_SW_PACKET packet, uint64_t address, size_t size) +e1000g_tx_workaround_PCIX_82544(p_tx_sw_packet_t packet, + uint64_t address, size_t size) { - PADDRESS_LENGTH_PAIR desc; + p_sw_desc_t desc; int desc_count; long size_left; size_t len; uint32_t counter; uint32_t array_elements; - DESC_ARRAY desc_array; + desc_array_t desc_array; /* * Coexist Workaround for cordova: RP: 07/04/03 @@ -1441,20 +1292,15 @@ for (counter = 0; counter < array_elements; counter++) { ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); - if (packet->num_desc >= MAX_TX_DESC_PER_PACKET) { - e1000g_log(Adapter, CE_WARN, - "No enough preparing tx descriptors"); - return (-1); - } /* * Put in the buffer address */ desc = &packet->desc[packet->num_desc]; - desc->Address = - desc_array.Descriptor[counter].Address; - desc->Length = - desc_array.Descriptor[counter].Length; + desc->address = + desc_array.descriptor[counter].address; + desc->length = + desc_array.descriptor[counter].length; packet->num_desc++; desc_count++; @@ -1471,10 +1317,10 @@ } static int -e1000g_tx_workaround_jumbo_82544(struct e1000g *Adapter, - PTX_SW_PACKET packet, uint64_t address, size_t size) +e1000g_tx_workaround_jumbo_82544(p_tx_sw_packet_t packet, + uint64_t address, size_t size) { - PADDRESS_LENGTH_PAIR desc; + p_sw_desc_t desc; int desc_count; long size_left; uint32_t offset; @@ -1488,34 +1334,32 @@ offset = 0; while (size_left > 0) { ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); - if (packet->num_desc >= MAX_TX_DESC_PER_PACKET) { - e1000g_log(Adapter, CE_WARN, - "No enough preparing tx descriptors"); - return (-1); - } desc = &packet->desc[packet->num_desc]; - desc->Address = address + offset; + desc->address = address + offset; if (size_left > JUMBO_FRAG_LENGTH) - desc->Length = JUMBO_FRAG_LENGTH; + desc->length = JUMBO_FRAG_LENGTH; else - desc->Length = size_left; + desc->length = size_left; packet->num_desc++; desc_count++; - offset += desc->Length; + offset += desc->length; size_left -= JUMBO_FRAG_LENGTH; } return (desc_count); } +#pragma inline(e1000g_82547_tx_move_tail_work) + static void e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *tx_ring) { + struct e1000_hw *hw; uint16_t hw_tdt; uint16_t sw_tdt; struct e1000_tx_desc *tx_desc; @@ -1524,21 +1368,22 @@ struct e1000g *Adapter; Adapter = tx_ring->adapter; + hw = &Adapter->shared; - hw_tdt = E1000_READ_REG(&Adapter->Shared, TDT); + hw_tdt = E1000_READ_REG(hw, E1000_TDT); sw_tdt = tx_ring->tbd_next - tx_ring->tbd_first; while (hw_tdt != sw_tdt) { tx_desc = &(tx_ring->tbd_first[hw_tdt]); length += tx_desc->lower.flags.length; eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; - if (++hw_tdt == Adapter->NumTxDescriptors) + if (++hw_tdt == Adapter->tx_desc_num) hw_tdt = 0; if (eop) { if ((Adapter->link_duplex == HALF_DUPLEX) && - e1000_82547_fifo_workaround(&Adapter->Shared, - length) != E1000_SUCCESS) { + (e1000_fifo_workaround_82547(hw, length) + != E1000_SUCCESS)) { if (tx_ring->timer_enable_82547) { ASSERT(tx_ring->timer_id_82547 == 0); tx_ring->timer_id_82547 = @@ -1549,10 +1394,8 @@ return; } else { - E1000_WRITE_REG(&Adapter->Shared, TDT, - hw_tdt); - e1000_update_tx_fifo_head(&Adapter->Shared, - length); + E1000_WRITE_REG(hw, E1000_TDT, hw_tdt); + e1000_update_tx_fifo_head_82547(hw, length); length = 0; } }