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changeset 3309:c7009276e9da

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6464647 OPL needs to reprogram dTLB for large kernel pages
author jimand
date Thu, 21 Dec 2006 10:11:40 -0800
parents 78c915eacfcd
children c2a9fea2455d
files usr/src/uts/sun4u/cpu/opl_olympus.c usr/src/uts/sun4u/cpu/opl_olympus_asm.s usr/src/uts/sun4u/cpu/us3_common_mmu.c
diffstat 3 files changed, 25 insertions(+), 5 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/sun4u/cpu/opl_olympus.c	Thu Dec 21 04:02:02 2006 -0800
+++ b/usr/src/uts/sun4u/cpu/opl_olympus.c	Thu Dec 21 10:11:40 2006 -0800
@@ -40,6 +40,7 @@
 #include <vm/vm_dep.h>
 #include <vm/hat_sfmmu.h>
 #include <vm/seg_kpm.h>
+#include <vm/seg_kmem.h>
 #include <sys/cpuvar.h>
 #include <sys/opl_olympus_regs.h>
 #include <sys/opl_module.h>
@@ -2115,10 +2116,25 @@
 	mutex_exit(&cpu_lock);
 }
 
-/*ARGSUSED*/
+int heaplp_use_stlb = -1;
+
 void
 mmu_init_kernel_pgsz(struct hat *hat)
 {
+	uint_t tte = page_szc(segkmem_lpsize);
+	uchar_t new_cext_primary, new_cext_nucleus;
+
+	if (heaplp_use_stlb == 0) {
+		/* do not reprogram stlb */
+		tte = TTE8K;
+	}
+
+	new_cext_nucleus = TAGACCEXT_MKSZPAIR(tte, TTE8K);
+	new_cext_primary = TAGACCEXT_MKSZPAIR(TTE8K, tte);
+
+	hat->sfmmu_cext = new_cext_primary;
+	kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) |
+		((uint64_t)new_cext_primary << CTXREG_EXT_SHIFT);
 }
 
 size_t
--- a/usr/src/uts/sun4u/cpu/opl_olympus_asm.s	Thu Dec 21 04:02:02 2006 -0800
+++ b/usr/src/uts/sun4u/cpu/opl_olympus_asm.s	Thu Dec 21 10:11:40 2006 -0800
@@ -989,15 +989,20 @@
  * corrupted, so we set here some reasonable values for
  * them. Note that resetting MMU registers also reset the context
  * info, we will need to reset the window registers to prevent
- * spill/fill that depends on context info for correct behaviour
+ * spill/fill that depends on context info for correct behaviour.
+ * Note that the TLBs must be flushed before programming the context
+ * registers.
  */
 
 #if !defined(lint)
 #define	RESET_MMU_REGS(tmp1, tmp2, tmp3)			\
+	FLUSH_ALL_TLB(tmp1)					;\
 	set	MMU_PCONTEXT, tmp1				;\
-	stxa	%g0, [tmp1]ASI_DMMU				;\
+	sethi	%hi(kcontextreg), tmp2				;\
+	ldx	[tmp2 + %lo(kcontextreg)], tmp2			;\
+	stxa	tmp2, [tmp1]ASI_DMMU				;\
 	set	MMU_SCONTEXT, tmp1				;\
-	stxa	%g0, [tmp1]ASI_DMMU				;\
+	stxa	tmp2, [tmp1]ASI_DMMU				;\
 	sethi	%hi(ktsb_base), tmp1				;\
 	ldx	[tmp1 + %lo(ktsb_base)], tmp2			;\
 	mov	MMU_TSB, tmp3					;\
--- a/usr/src/uts/sun4u/cpu/us3_common_mmu.c	Thu Dec 21 04:02:02 2006 -0800
+++ b/usr/src/uts/sun4u/cpu/us3_common_mmu.c	Thu Dec 21 10:11:40 2006 -0800
@@ -570,7 +570,6 @@
 	hat->sfmmu_cext = new_cext_primary;
 	kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) |
 		((uint64_t)new_cext_primary << CTXREG_EXT_SHIFT);
-	mmu_init_kcontext();
 }
 
 size_t