Mercurial > illumos > illumos-gate
changeset 10893:cc98a2de6736
PSARC/2009/520 Intel WiFi Link 6000 Series Device Driver
6850605 Solaris needs to support Intel Puma Peak and Kilmer Peak
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--- a/usr/src/pkgdefs/Makefile Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/pkgdefs/Makefile Wed Oct 28 11:45:14 2009 +0800 @@ -133,6 +133,7 @@ SUNWiwh \ SUNWiwi \ SUNWiwk \ + SUNWiwp \ SUNWkvm.i \ SUNWlxr \ SUNWlxu \
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/Makefile Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,38 @@ +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +include ../Makefile.com + +DATAFILES += depend +LICENSEFILES += \ + ../../uts/common/io/iwp/THIRDPARTYLICENSE \ + ../../uts/common/io/iwp/fw-iw/LICENSE +CDDL= + +.KEEP_STATE: + +all: $(FILES) postinstall postremove +install: all pkg + +include ../Makefile.targ
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/pkginfo.tmpl Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,44 @@ +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +PKG="SUNWiwp" +NAME="Intel(R) WiFi Link 6000 series driver" +ARCH="ISA" +VERSION="ONVERS,REV=0.0.0" +SUNW_PRODNAME="SunOS" +SUNW_PRODVERS="RELEASE/VERSION" +SUNW_PKGVERS="1.0" +SUNW_PKGTYPE="root" +MAXINST="1000" +CATEGORY="system" +VENDOR="Sun Microsystems, Inc." +DESC="Intel(R) WiFi Link 6000 series driver" +CLASSES="none" +HOTLINE="Please contact your local service provider" +EMAIL="" +BASEDIR=/ +SUNW_PKG_ALLZONES="true" +SUNW_PKG_HOLLOW="true" +SUNW_PKG_THISZONE="false"
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/postinstall Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,92 @@ +#! /usr/bin/sh +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# + +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +# Driver info +DRV=iwp +DRVALIAS='"pciex8086,422b" "pciex8086,422c" "pciex8086,4238" +"pciex8086,4239" "pciex8086,008d" "pciex8086,008e"' + +BASEDIR=${BASEDIR:-/} + +# Function: check_add_drv() +# +# This function will check if add_drv has been executed. +# If not simply calls add_drv. Otherwise adds entries to +# driver_aliases, driver_classes and minor_perm if necessary. +# The syntax of this function is the same as add_drv. + +check_add_drv() +{ + CMD="add_drv" + + ALIAS="" + ALIASDIR="${BASEDIR}"/etc/driver_aliases + while getopts i:b: opt 2>/dev/null; do + case "$opt" in + i) CMD="${CMD} -i ${OPTARG}" + ALIAS=`echo ${OPTARG} | /usr/bin/sed -e "s/'//g"` + ;; + b) if [ "${OPTARG}" != "/" ]; then + # On a client + # modify the sytem files and touch + # /reconfigure for reconfigure reboot + CMD="${CMD} -b \"${OPTARG}\"" + fi + ;; + \?) echo "check_add_drv(): Unknown option $opt" + return + ;; + esac + done + shift `/usr/bin/expr ${OPTIND} - 1` + DRIVER=$1 + CMD="${CMD} ${DRIVER}" + + # Make sure add_drv has not been previously executed + # before attempting to add the driver + /usr/bin/egrep -s "^${DRIVER}[ ]" "$BASEDIR"/etc/name_to_major + + if [ $? -ne 0 ]; then + eval ${CMD} + if [ $? -ne 0 ]; then + echo "Failed add_drv ${DRIVER}!\n" >&2 + exit 1 + fi + else + # Add driver entry if necessary + if [ -n "${ALIAS}" ]; then + for i in ${ALIAS}; do + /usr/bin/egrep -s "^${DRIVER}[ ]+$i" ${ALIASDIR} + if [ $? -ne 0 ]; then + echo "${DRIVER} $i" >> ${ALIASDIR} + fi + done + fi + fi +} + +check_add_drv -b "${BASEDIR}" -i "'${DRVALIAS}'" ${DRV}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/postremove Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,38 @@ +#! /usr/bin/sh +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +DRV=iwp +BD=${BASEDIR:-/} +if grep -w $DRV $BD/etc/name_to_major > /dev/null 2>&1 +then + rem_drv -b ${BD} $DRV + if [ $? -ne 0 ] + then + exit 1 + fi +fi + +exit 0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/prototype_com Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,45 @@ +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +# +# This required package information file contains a list of package contents. +# The 'pkgmk' command uses this file to identify the contents of a package +# and their location on the development machine when building the package. +# Can be created via a text editor or through use of the 'pkgproto' command. + +#!search <pathname pathname ...> # where to find pkg objects +#!include <filename> # include another 'prototype' file +#!default <mode> <owner> <group> # default used if not specified on entry +#!<param>=<value> # puts parameter in pkg environment + +# +# SUNWiwp +# + +i pkginfo +i copyright +i depend +i postinstall +i postremove
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/pkgdefs/SUNWiwp/prototype_i386 Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,50 @@ +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +# +# This required package information file contains a list of package contents. +# The 'pkgmk' command uses this file to identify the contents of a package +# and their location on the development machine when building the package. +# Can be created via a text editor or through use of the 'pkgproto' command. + +#!search <pathname pathname ...> # where to find pkg objects +#!include <filename> # include another 'prototype' file +#!default <mode> <owner> <group> # default used if not specified on entry +#!<param>=<value> # puts parameter in pkg environment + +# +# SUNWiwp +# + +# Include ISA independent files (prototype_com) +# +!include prototype_com + +# iwp IEEE80211a/b/g wifi driver +d none kernel 0755 root sys +d none kernel/drv 0755 root sys +f none kernel/drv/iwp 0755 root sys +d none kernel/drv/amd64 0755 root sys +f none kernel/drv/amd64/iwp 0755 root sys
--- a/usr/src/pkgdefs/common_files/i.minorperm_i386 Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/pkgdefs/common_files/i.minorperm_i386 Wed Oct 28 11:45:14 2009 +0800 @@ -117,6 +117,7 @@ clone:iwh 0600 root sys 0666 root sys /dev/iwh clone:iwi 0600 root sys 0666 root sys /dev/iwi clone:iwk 0600 root sys 0666 root sys /dev/iwk +clone:iwp 0600 root sys 0666 root sys /dev/iwp clone:mwl 0600 root sys 0666 root sys /dev/mwl clone:pcwl 0600 root sys 0666 root sys /dev/pcwl clone:pcan 0600 root sys 0666 root sys /dev/pcan @@ -151,6 +152,7 @@ iwh:* 0600 root sys 0666 root sys /dev/iwh* iwi:* 0600 root sys 0666 root sys /dev/iwi* iwk:* 0600 root sys 0666 root sys /dev/iwk* +iwp:* 0600 root sys 0666 root sys /dev/iwp* mwl:* 0600 root sys 0666 root sys /dev/mwl* pcwl:* 0600 root sys 0666 root sys /dev/pcwl* pcan:* 0600 root sys 0666 root sys /dev/pcan* @@ -312,6 +314,7 @@ clone:iwh clone:iwi clone:iwk +clone:iwp clone:mwl clone:pcwl clone:pcan @@ -346,6 +349,7 @@ iwh:* iwi:* iwk:* +iwp:* mwl:* pcwl:* pcan:*
--- a/usr/src/tools/opensolaris/license-list Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/tools/opensolaris/license-list Wed Oct 28 11:45:14 2009 +0800 @@ -156,6 +156,8 @@ usr/src/uts/common/io/iwi/fw-ipw2200/LICENSE usr/src/uts/common/io/iwk/THIRDPARTYLICENSE usr/src/uts/common/io/iwk/fw-iw/LICENSE +usr/src/uts/common/io/iwp/THIRDPARTYLICENSE +usr/src/uts/common/io/iwp/fw-iw/LICENSE usr/src/uts/common/io/ixgbe/THIRDPARTYLICENSE usr/src/uts/common/io/mega_sas/THIRDPARTYLICENSE usr/src/uts/common/io/mr_sas/THIRDPARTYLICENSE
--- a/usr/src/uts/common/Makefile.files Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/uts/common/Makefile.files Wed Oct 28 11:45:14 2009 +0800 @@ -1742,6 +1742,8 @@ IWK_OBJS += iwk2.o +IWP_OBJS += iwp.o + MWL_OBJS += mwl.o MWLFW_OBJS += mwlfw_mode.o
--- a/usr/src/uts/common/Makefile.rules Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/uts/common/Makefile.rules Wed Oct 28 11:45:14 2009 +0800 @@ -800,6 +800,10 @@ $(COMPILE.c) -o $@ $< $(CTFCONVERT_O) +$(OBJS_DIR)/%.o: $(UTSBASE)/common/io/iwp/%.c + $(COMPILE.c) -o $@ $< + $(CTFCONVERT_O) + $(OBJS_DIR)/%.o: $(UTSBASE)/common/io/kb8042/%.c $(COMPILE.c) -o $@ $< $(CTFCONVERT_O) @@ -2048,6 +2052,9 @@ $(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/iwk/%.c @($(LHEAD) $(LINT.c) $< $(LTAIL)) +$(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/iwp/%.c + @($(LHEAD) $(LINT.c) $< $(LTAIL)) + $(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/kb8042/%.c @($(LHEAD) $(LINT.c) $< $(LTAIL))
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/THIRDPARTYLICENSE Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,57 @@ +/* + * Sun elects to have this file available under and governed by the BSD license + * (see below for full license text). However, the following notice + * accompanied the original version of this file: + */ + +/* + * Copyright (c) 2006 + * Copyright (c) 2007 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * BSD LICENSE + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/THIRDPARTYLICENSE.descrip Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,1 @@ +INTEL WiFi Link 6000 Series Device Driver
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/fw-iw/LICENSE Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,39 @@ +Copyright (c) 2006-2009, Intel Corporation. +All rights reserved. + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +* Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. +* Neither the name of Intel Corporation nor the names of its suppliers + may be used to endorse or promote products derived from this software + without specific prior written permission. +* No reverse engineering, decompilation, or disassembly of this software + is permitted. + +Limited patent license. Intel Corporation grants a world-wide, +royalty-free, non-exclusive license under patents it now or hereafter +owns or controls to make, have made, use, import, offer to sell and +sell ("Utilize") this software, but solely to the extent that any +such patent is necessary to Utilize the software alone, or in +combination with an operating system licensed under an approved Open +Source license as listed by the Open Source Initiative at +http://opensource.org/licenses. The patent license shall not apply to +any other combinations which include this software. No hardware per +se is licensed hereunder. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND +FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +DAMAGE.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/fw-iw/LICENSE.descrip Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,1 @@ +INTEL WIFI LINK 6000 SERIES FIRMWARE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/fw-iw/iwp.ucode Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,57500 @@ +0x01, 0x04, 0xb0, 0x09, 0xdb, 0x3d, 0x00, 0x00, +0x14, 0x43, 0x02, 0x00, 0x00, 0x40, 0x01, 0x00, +0xa8, 0x41, 0x02, 0x00, 0x00, 0x40, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x80, 0x0f, +0x00, 0x00, 0x40, 0x00, 0x69, 0x20, 0x00, 0x00, +0x69, 0x20, 0x40, 0x00, 0x69, 0x20, 0x00, 0x00, +0x69, 0x20, 0x40, 0x00, 0x20, 0x20, 0x80, 0x0f, +0x00, 0x00, 0xe8, 0x00, 0x69, 0x20, 0x00, 0x00, +0x69, 0x20, 0x40, 0x00, 0x69, 0x20, 0x00, 0x00, +0x69, 0x20, 0x40, 0x00, 0x20, 0x20, 0x80, 0x0f, +0x00, 0x00, 0x78, 0x06, 0x69, 0x20, 0x00, 0x00, +0x69, 0x20, 0x40, 0x00, 0x69, 0x20, 0x00, 0x00, +0x4a, 0x20, 0x00, 0x00, 0x4a, 0x21, 0x00, 0x00, +0x4a, 0x22, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, +0x4a, 0x24, 0x00, 0x00, 0x4a, 0x25, 0x00, 0x00, +0x4a, 0x26, 0x00, 0x00, 0x4a, 0x27, 0x00, 0x00, +0x4a, 0x20, 0x00, 0x10, 0x4a, 0x21, 0x00, 0x10, +0x4a, 0x22, 0x00, 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/iwp.c Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,5410 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +/* + * Copyright (c) 2009, Intel Corporation + * All rights reserved. + */ + +/* + * Copyright (c) 2006 + * Copyright (c) 2007 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Intel(R) WiFi Link 6000 Driver + */ + +#include <sys/types.h> +#include <sys/byteorder.h> +#include <sys/conf.h> +#include <sys/cmn_err.h> +#include <sys/stat.h> +#include <sys/ddi.h> +#include <sys/sunddi.h> +#include <sys/strsubr.h> +#include <sys/ethernet.h> +#include <inet/common.h> +#include <inet/nd.h> +#include <inet/mi.h> +#include <sys/note.h> +#include <sys/stream.h> +#include <sys/strsun.h> +#include <sys/modctl.h> +#include <sys/devops.h> +#include <sys/dlpi.h> +#include <sys/mac_provider.h> +#include <sys/mac_wifi.h> +#include <sys/net80211.h> +#include <sys/net80211_proto.h> +#include <sys/varargs.h> +#include <sys/policy.h> +#include <sys/pci.h> + +#include "iwp_calibration.h" +#include "iwp_hw.h" +#include "iwp_eeprom.h" +#include "iwp_var.h" +#include <inet/wifi_ioctl.h> + +#ifdef DEBUG +#define IWP_DEBUG_80211 (1 << 0) +#define IWP_DEBUG_CMD (1 << 1) +#define IWP_DEBUG_DMA (1 << 2) +#define IWP_DEBUG_EEPROM (1 << 3) +#define IWP_DEBUG_FW (1 << 4) +#define IWP_DEBUG_HW (1 << 5) +#define IWP_DEBUG_INTR (1 << 6) +#define IWP_DEBUG_MRR (1 << 7) +#define IWP_DEBUG_PIO (1 << 8) +#define IWP_DEBUG_RX (1 << 9) +#define IWP_DEBUG_SCAN (1 << 10) +#define IWP_DEBUG_TX (1 << 11) +#define IWP_DEBUG_RATECTL (1 << 12) +#define IWP_DEBUG_RADIO (1 << 13) +#define IWP_DEBUG_RESUME (1 << 14) +#define IWP_DEBUG_CALIBRATION (1 << 15) +/* + * if want to see debug message of a given section, + * please set this flag to one of above values + */ +uint32_t iwp_dbg_flags = 0; +#define IWP_DBG(x) \ + iwp_dbg x +#else +#define IWP_DBG(x) +#endif + +static void *iwp_soft_state_p = NULL; + +/* + * ucode will be compiled into driver image + */ +static uint8_t iwp_fw_bin [] = { +#include "fw-iw/iwp.ucode" +}; + +/* + * DMA attributes for a shared page + */ +static ddi_dma_attr_t sh_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 0x1000, /* alignment in bytes */ + 0x1000, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for a keep warm DRAM descriptor + */ +static ddi_dma_attr_t kw_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 0x1000, /* alignment in bytes */ + 0x1000, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for a ring descriptor + */ +static ddi_dma_attr_t ring_desc_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 0x100, /* alignment in bytes */ + 0x100, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for a cmd + */ +static ddi_dma_attr_t cmd_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 4, /* alignment in bytes */ + 0x100, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for a rx buffer + */ +static ddi_dma_attr_t rx_buffer_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 0x100, /* alignment in bytes */ + 0x100, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for a tx buffer. + * the maximum number of segments is 4 for the hardware. + * now all the wifi drivers put the whole frame in a single + * descriptor, so we define the maximum number of segments 1, + * just the same as the rx_buffer. we consider leverage the HW + * ability in the future, that is why we don't define rx and tx + * buffer_dma_attr as the same. + */ +static ddi_dma_attr_t tx_buffer_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0xffffffffU, /* maximum DMAable byte count */ + 4, /* alignment in bytes */ + 0x100, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * DMA attributes for text and data part in the firmware + */ +static ddi_dma_attr_t fw_dma_attr = { + DMA_ATTR_V0, /* version of this structure */ + 0, /* lowest usable address */ + 0xffffffffU, /* highest usable address */ + 0x7fffffff, /* maximum DMAable byte count */ + 0x10, /* alignment in bytes */ + 0x100, /* burst sizes (any?) */ + 1, /* minimum transfer */ + 0xffffffffU, /* maximum transfer */ + 0xffffffffU, /* maximum segment length */ + 1, /* maximum number of segments */ + 1, /* granularity */ + 0, /* flags (reserved) */ +}; + +/* + * regs access attributes + */ +static ddi_device_acc_attr_t iwp_reg_accattr = { + DDI_DEVICE_ATTR_V0, + DDI_STRUCTURE_LE_ACC, + DDI_STRICTORDER_ACC, + DDI_DEFAULT_ACC +}; + +/* + * DMA access attributes for descriptor + */ +static ddi_device_acc_attr_t iwp_dma_descattr = { + DDI_DEVICE_ATTR_V0, + DDI_STRUCTURE_LE_ACC, + DDI_STRICTORDER_ACC, + DDI_DEFAULT_ACC +}; + +/* + * DMA access attributes + */ +static ddi_device_acc_attr_t iwp_dma_accattr = { + DDI_DEVICE_ATTR_V0, + DDI_NEVERSWAP_ACC, + DDI_STRICTORDER_ACC, + DDI_DEFAULT_ACC +}; + +static int iwp_ring_init(iwp_sc_t *); +static void iwp_ring_free(iwp_sc_t *); +static int iwp_alloc_shared(iwp_sc_t *); +static void iwp_free_shared(iwp_sc_t *); +static int iwp_alloc_kw(iwp_sc_t *); +static void iwp_free_kw(iwp_sc_t *); +static int iwp_alloc_fw_dma(iwp_sc_t *); +static void iwp_free_fw_dma(iwp_sc_t *); +static int iwp_alloc_rx_ring(iwp_sc_t *); +static void iwp_reset_rx_ring(iwp_sc_t *); +static void iwp_free_rx_ring(iwp_sc_t *); +static int iwp_alloc_tx_ring(iwp_sc_t *, iwp_tx_ring_t *, + int, int); +static void iwp_reset_tx_ring(iwp_sc_t *, iwp_tx_ring_t *); +static void iwp_free_tx_ring(iwp_tx_ring_t *); +static ieee80211_node_t *iwp_node_alloc(ieee80211com_t *); +static void iwp_node_free(ieee80211_node_t *); +static int iwp_newstate(ieee80211com_t *, enum ieee80211_state, int); +static void iwp_mac_access_enter(iwp_sc_t *); +static void iwp_mac_access_exit(iwp_sc_t *); +static uint32_t iwp_reg_read(iwp_sc_t *, uint32_t); +static void iwp_reg_write(iwp_sc_t *, uint32_t, uint32_t); +static int iwp_load_init_firmware(iwp_sc_t *); +static int iwp_load_run_firmware(iwp_sc_t *); +static void iwp_tx_intr(iwp_sc_t *, iwp_rx_desc_t *); +static void iwp_cmd_intr(iwp_sc_t *, iwp_rx_desc_t *); +static uint_t iwp_intr(caddr_t, caddr_t); +static int iwp_eep_load(iwp_sc_t *); +static void iwp_get_mac_from_eep(iwp_sc_t *); +static int iwp_eep_sem_down(iwp_sc_t *); +static void iwp_eep_sem_up(iwp_sc_t *); +static uint_t iwp_rx_softintr(caddr_t, caddr_t); +static uint8_t iwp_rate_to_plcp(int); +static int iwp_cmd(iwp_sc_t *, int, const void *, int, int); +static void iwp_set_led(iwp_sc_t *, uint8_t, uint8_t, uint8_t); +static int iwp_hw_set_before_auth(iwp_sc_t *); +static int iwp_scan(iwp_sc_t *); +static int iwp_config(iwp_sc_t *); +static void iwp_stop_master(iwp_sc_t *); +static int iwp_power_up(iwp_sc_t *); +static int iwp_preinit(iwp_sc_t *); +static int iwp_init(iwp_sc_t *); +static void iwp_stop(iwp_sc_t *); +static int iwp_quiesce(dev_info_t *t); +static void iwp_amrr_init(iwp_amrr_t *); +static void iwp_amrr_timeout(iwp_sc_t *); +static void iwp_amrr_ratectl(void *, ieee80211_node_t *); +static void iwp_ucode_alive(iwp_sc_t *, iwp_rx_desc_t *); +static void iwp_rx_phy_intr(iwp_sc_t *, iwp_rx_desc_t *); +static void iwp_rx_mpdu_intr(iwp_sc_t *, iwp_rx_desc_t *); +static void iwp_release_calib_buffer(iwp_sc_t *); +static int iwp_init_common(iwp_sc_t *); +static uint8_t *iwp_eep_addr_trans(iwp_sc_t *, uint32_t); +static int iwp_put_seg_fw(iwp_sc_t *, uint32_t, uint32_t, uint32_t); +static int iwp_alive_common(iwp_sc_t *); +static void iwp_save_calib_result(iwp_sc_t *, iwp_rx_desc_t *); +static int iwp_attach(dev_info_t *, ddi_attach_cmd_t); +static int iwp_detach(dev_info_t *, ddi_detach_cmd_t); +static void iwp_destroy_locks(iwp_sc_t *); +static int iwp_send(ieee80211com_t *, mblk_t *, uint8_t); +static void iwp_thread(iwp_sc_t *); +static int iwp_run_state_config(iwp_sc_t *); +static int iwp_fast_recover(iwp_sc_t *); +static void iwp_overwrite_ic_default(iwp_sc_t *); +static int iwp_add_ap_sta(iwp_sc_t *); +static int iwp_alloc_dma_mem(iwp_sc_t *, size_t, + ddi_dma_attr_t *, ddi_device_acc_attr_t *, + uint_t, iwp_dma_t *); +static void iwp_free_dma_mem(iwp_dma_t *); +static int iwp_eep_ver_chk(iwp_sc_t *); +static void iwp_set_chip_param(iwp_sc_t *); + +/* + * GLD specific operations + */ +static int iwp_m_stat(void *, uint_t, uint64_t *); +static int iwp_m_start(void *); +static void iwp_m_stop(void *); +static int iwp_m_unicst(void *, const uint8_t *); +static int iwp_m_multicst(void *, boolean_t, const uint8_t *); +static int iwp_m_promisc(void *, boolean_t); +static mblk_t *iwp_m_tx(void *, mblk_t *); +static void iwp_m_ioctl(void *, queue_t *, mblk_t *); +static int iwp_m_setprop(void *arg, const char *pr_name, + mac_prop_id_t wldp_pr_num, uint_t wldp_length, const void *wldp_buf); +static int iwp_m_getprop(void *arg, const char *pr_name, + mac_prop_id_t wldp_pr_num, uint_t pr_flags, uint_t wldp_length, + void *wldp_buf, uint_t *perm); + +/* + * Supported rates for 802.11b/g modes (in 500Kbps unit). + */ +static const struct ieee80211_rateset iwp_rateset_11b = + { 4, { 2, 4, 11, 22 } }; + +static const struct ieee80211_rateset iwp_rateset_11g = + { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; + +/* + * For mfthread only + */ +extern pri_t minclsyspri; + +#define DRV_NAME_SP "iwp" + +/* + * Module Loading Data & Entry Points + */ +DDI_DEFINE_STREAM_OPS(iwp_devops, nulldev, nulldev, iwp_attach, + iwp_detach, nodev, NULL, D_MP, NULL, iwp_quiesce); + +static struct modldrv iwp_modldrv = { + &mod_driverops, + "Intel(R) PumaPeak driver(N)", + &iwp_devops +}; + +static struct modlinkage iwp_modlinkage = { + MODREV_1, + &iwp_modldrv, + NULL +}; + +int +_init(void) +{ + int status; + + status = ddi_soft_state_init(&iwp_soft_state_p, + sizeof (iwp_sc_t), 1); + if (status != DDI_SUCCESS) { + return (status); + } + + mac_init_ops(&iwp_devops, DRV_NAME_SP); + status = mod_install(&iwp_modlinkage); + if (status != DDI_SUCCESS) { + mac_fini_ops(&iwp_devops); + ddi_soft_state_fini(&iwp_soft_state_p); + } + + return (status); +} + +int +_fini(void) +{ + int status; + + status = mod_remove(&iwp_modlinkage); + if (DDI_SUCCESS == status) { + mac_fini_ops(&iwp_devops); + ddi_soft_state_fini(&iwp_soft_state_p); + } + + return (status); +} + +int +_info(struct modinfo *mip) +{ + return (mod_info(&iwp_modlinkage, mip)); +} + +/* + * Mac Call Back entries + */ +mac_callbacks_t iwp_m_callbacks = { + MC_IOCTL | MC_SETPROP | MC_GETPROP, + iwp_m_stat, + iwp_m_start, + iwp_m_stop, + iwp_m_promisc, + iwp_m_multicst, + iwp_m_unicst, + iwp_m_tx, + iwp_m_ioctl, + NULL, + NULL, + NULL, + iwp_m_setprop, + iwp_m_getprop +}; + +#ifdef DEBUG +void +iwp_dbg(uint32_t flags, const char *fmt, ...) +{ + va_list ap; + + if (flags & iwp_dbg_flags) { + va_start(ap, fmt); + vcmn_err(CE_NOTE, fmt, ap); + va_end(ap); + } +} +#endif /* DEBUG */ + +/* + * device operations + */ +int +iwp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int instance, i; + char strbuf[32]; + wifi_data_t wd = { 0 }; + mac_register_t *macp; + int intr_type; + int intr_count; + int intr_actual; + int err = DDI_FAILURE; + + switch (cmd) { + case DDI_ATTACH: + break; + case DDI_RESUME: + instance = ddi_get_instance(dip); + sc = ddi_get_soft_state(iwp_soft_state_p, + instance); + ASSERT(sc != NULL); + + if (sc->sc_flags & IWP_F_RUNNING) { + (void) iwp_init(sc); + } + + atomic_and_32(&sc->sc_flags, ~IWP_F_SUSPEND); + + IWP_DBG((IWP_DEBUG_RESUME, "iwp_attach(): " + "resume\n")); + return (DDI_SUCCESS); + default: + goto attach_fail1; + } + + instance = ddi_get_instance(dip); + err = ddi_soft_state_zalloc(iwp_soft_state_p, instance); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to allocate soft state\n"); + goto attach_fail1; + } + + sc = ddi_get_soft_state(iwp_soft_state_p, instance); + ASSERT(sc != NULL); + + sc->sc_dip = dip; + + /* + * map configure space + */ + err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, + &iwp_reg_accattr, &sc->sc_cfg_handle); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to map config spaces regs\n"); + goto attach_fail2; + } + + sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle, + (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); + if ((sc->sc_dev_id != 0x422B) && + (sc->sc_dev_id != 0x422C) && + (sc->sc_dev_id != 0x4238) && + (sc->sc_dev_id != 0x4239) && + (sc->sc_dev_id != 0x008d) && + (sc->sc_dev_id != 0x008e)) { + cmn_err(CE_WARN, "iwp_attach(): " + "Do not support this device\n"); + goto attach_fail3; + } + + iwp_set_chip_param(sc); + + sc->sc_rev = ddi_get8(sc->sc_cfg_handle, + (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); + + /* + * keep from disturbing C3 state of CPU + */ + ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + + PCI_CFG_RETRY_TIMEOUT), 0); + + /* + * determine the size of buffer for frame and command to ucode + */ + sc->sc_clsz = ddi_get16(sc->sc_cfg_handle, + (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); + if (!sc->sc_clsz) { + sc->sc_clsz = 16; + } + sc->sc_clsz = (sc->sc_clsz << 2); + + sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) + + IEEE80211_MTU + IEEE80211_CRC_LEN + + (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + + IEEE80211_WEP_CRCLEN), sc->sc_clsz); + + /* + * Map operating registers + */ + err = ddi_regs_map_setup(dip, 1, &sc->sc_base, + 0, 0, &iwp_reg_accattr, &sc->sc_handle); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to map device regs\n"); + goto attach_fail3; + } + + /* + * this is used to differentiate type of hardware + */ + sc->sc_hw_rev = IWP_READ(sc, CSR_HW_REV); + + err = ddi_intr_get_supported_types(dip, &intr_type); + if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) { + cmn_err(CE_WARN, "iwp_attach(): " + "fixed type interrupt is not supported\n"); + goto attach_fail4; + } + + err = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &intr_count); + if ((err != DDI_SUCCESS) || (intr_count != 1)) { + cmn_err(CE_WARN, "iwp_attach(): " + "no fixed interrupts\n"); + goto attach_fail4; + } + + sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP); + + err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0, + intr_count, &intr_actual, 0); + if ((err != DDI_SUCCESS) || (intr_actual != 1)) { + cmn_err(CE_WARN, "iwp_attach(): " + "ddi_intr_alloc() failed 0x%x\n", err); + goto attach_fail5; + } + + err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "ddi_intr_get_pri() failed 0x%x\n", err); + goto attach_fail6; + } + + mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(sc->sc_intr_pri)); + mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(sc->sc_intr_pri)); + mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(sc->sc_intr_pri)); + + cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL); + cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL); + cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL); + + /* + * initialize the mfthread + */ + cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL); + sc->sc_mf_thread = NULL; + sc->sc_mf_thread_switch = 0; + + /* + * Allocate shared buffer for communication between driver and ucode. + */ + err = iwp_alloc_shared(sc); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to allocate shared page\n"); + goto attach_fail7; + } + + (void) memset(sc->sc_shared, 0, sizeof (iwp_shared_t)); + + /* + * Allocate keep warm page. + */ + err = iwp_alloc_kw(sc); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to allocate keep warm page\n"); + goto attach_fail8; + } + + /* + * Do some necessary hardware initializations. + */ + err = iwp_preinit(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to initialize hardware\n"); + goto attach_fail9; + } + + /* + * get hardware configurations from eeprom + */ + err = iwp_eep_load(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to load eeprom\n"); + goto attach_fail9; + } + + /* + * calibration information from EEPROM + */ + sc->sc_eep_calib = (struct iwp_eep_calibration *) + iwp_eep_addr_trans(sc, EEP_CALIBRATION); + + err = iwp_eep_ver_chk(sc); + if (err != IWP_SUCCESS) { + goto attach_fail9; + } + + /* + * get MAC address of this chipset + */ + iwp_get_mac_from_eep(sc); + + + /* + * initialize TX and RX ring buffers + */ + err = iwp_ring_init(sc); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to allocate and initialize ring\n"); + goto attach_fail9; + } + + sc->sc_hdr = (iwp_firmware_hdr_t *)iwp_fw_bin; + + /* + * copy ucode to dma buffer + */ + err = iwp_alloc_fw_dma(sc); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to allocate firmware dma\n"); + goto attach_fail10; + } + + /* + * Initialize the wifi part, which will be used by + * 802.11 module + */ + ic = &sc->sc_ic; + ic->ic_phytype = IEEE80211_T_OFDM; + ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ + ic->ic_state = IEEE80211_S_INIT; + ic->ic_maxrssi = 100; /* experimental number */ + ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | + IEEE80211_C_PMGT | IEEE80211_C_SHSLOT; + + /* + * Support WPA/WPA2 + */ + ic->ic_caps |= IEEE80211_C_WPA; + + /* + * set supported .11b and .11g rates + */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = iwp_rateset_11b; + ic->ic_sup_rates[IEEE80211_MODE_11G] = iwp_rateset_11g; + + /* + * set supported .11b and .11g channels (1 through 11) + */ + for (i = 1; i <= 11; i++) { + ic->ic_sup_channels[i].ich_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); + ic->ic_sup_channels[i].ich_flags = + IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | + IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ | + IEEE80211_CHAN_PASSIVE; + } + + ic->ic_ibss_chan = &ic->ic_sup_channels[0]; + ic->ic_xmit = iwp_send; + + /* + * attach to 802.11 module + */ + ieee80211_attach(ic); + + /* + * different instance has different WPA door + */ + (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR, + ddi_driver_name(dip), + ddi_get_instance(dip)); + + /* + * Overwrite 80211 default configurations. + */ + iwp_overwrite_ic_default(sc); + + /* + * initialize 802.11 module + */ + ieee80211_media_init(ic); + + /* + * initialize default tx key + */ + ic->ic_def_txkey = 0; + + err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX, + iwp_rx_softintr, (caddr_t)sc); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "add soft interrupt failed\n"); + goto attach_fail12; + } + + err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwp_intr, + (caddr_t)sc, NULL); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "ddi_intr_add_handle() failed\n"); + goto attach_fail13; + } + + err = ddi_intr_enable(sc->sc_intr_htable[0]); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "ddi_intr_enable() failed\n"); + goto attach_fail14; + } + + /* + * Initialize pointer to device specific functions + */ + wd.wd_secalloc = WIFI_SEC_NONE; + wd.wd_opmode = ic->ic_opmode; + IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_macaddr); + + /* + * create relation to GLD + */ + macp = mac_alloc(MAC_VERSION); + if (NULL == macp) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to do mac_alloc()\n"); + goto attach_fail15; + } + + macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; + macp->m_driver = sc; + macp->m_dip = dip; + macp->m_src_addr = ic->ic_macaddr; + macp->m_callbacks = &iwp_m_callbacks; + macp->m_min_sdu = 0; + macp->m_max_sdu = IEEE80211_MTU; + macp->m_pdata = &wd; + macp->m_pdata_size = sizeof (wd); + + /* + * Register the macp to mac + */ + err = mac_register(macp, &ic->ic_mach); + mac_free(macp); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to do mac_register()\n"); + goto attach_fail15; + } + + /* + * Create minor node of type DDI_NT_NET_WIFI + */ + (void) snprintf(strbuf, sizeof (strbuf), DRV_NAME_SP"%d", instance); + err = ddi_create_minor_node(dip, strbuf, S_IFCHR, + instance + 1, DDI_NT_NET_WIFI, 0); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_attach(): " + "failed to do ddi_create_minor_node()\n"); + } + + /* + * Notify link is down now + */ + mac_link_update(ic->ic_mach, LINK_STATE_DOWN); + + /* + * create the mf thread to handle the link status, + * recovery fatal error, etc. + */ + sc->sc_mf_thread_switch = 1; + if (NULL == sc->sc_mf_thread) { + sc->sc_mf_thread = thread_create((caddr_t)NULL, 0, + iwp_thread, sc, 0, &p0, TS_RUN, minclsyspri); + } + + atomic_or_32(&sc->sc_flags, IWP_F_ATTACHED); + + return (DDI_SUCCESS); + +attach_fail15: + (void) ddi_intr_disable(sc->sc_intr_htable[0]); +attach_fail14: + (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); +attach_fail13: + (void) ddi_intr_remove_softint(sc->sc_soft_hdl); + sc->sc_soft_hdl = NULL; +attach_fail12: + ieee80211_detach(ic); +attach_fail11: + iwp_free_fw_dma(sc); +attach_fail10: + iwp_ring_free(sc); +attach_fail9: + iwp_free_kw(sc); +attach_fail8: + iwp_free_shared(sc); +attach_fail7: + iwp_destroy_locks(sc); +attach_fail6: + (void) ddi_intr_free(sc->sc_intr_htable[0]); +attach_fail5: + kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); +attach_fail4: + ddi_regs_map_free(&sc->sc_handle); +attach_fail3: + ddi_regs_map_free(&sc->sc_cfg_handle); +attach_fail2: + ddi_soft_state_free(iwp_soft_state_p, instance); +attach_fail1: + return (DDI_FAILURE); +} + +int +iwp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int err; + + sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); + ASSERT(sc != NULL); + ic = &sc->sc_ic; + + switch (cmd) { + case DDI_DETACH: + break; + case DDI_SUSPEND: + atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); + atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); + + atomic_or_32(&sc->sc_flags, IWP_F_SUSPEND); + + if (sc->sc_flags & IWP_F_RUNNING) { + iwp_stop(sc); + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + + } + + IWP_DBG((IWP_DEBUG_RESUME, "iwp_detach(): " + "suspend\n")); + return (DDI_SUCCESS); + default: + return (DDI_FAILURE); + } + + if (!(sc->sc_flags & IWP_F_ATTACHED)) { + return (DDI_FAILURE); + } + + /* + * Destroy the mf_thread + */ + sc->sc_mf_thread_switch = 0; + + mutex_enter(&sc->sc_mt_lock); + while (sc->sc_mf_thread != NULL) { + if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) { + break; + } + } + mutex_exit(&sc->sc_mt_lock); + + err = mac_disable(sc->sc_ic.ic_mach); + if (err != DDI_SUCCESS) { + return (err); + } + + /* + * stop chipset + */ + iwp_stop(sc); + + DELAY(500000); + + /* + * release buffer for calibration + */ + iwp_release_calib_buffer(sc); + + /* + * Unregiste from GLD + */ + (void) mac_unregister(sc->sc_ic.ic_mach); + + mutex_enter(&sc->sc_glock); + iwp_free_fw_dma(sc); + iwp_ring_free(sc); + iwp_free_kw(sc); + iwp_free_shared(sc); + mutex_exit(&sc->sc_glock); + + (void) ddi_intr_disable(sc->sc_intr_htable[0]); + (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); + (void) ddi_intr_free(sc->sc_intr_htable[0]); + kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); + + (void) ddi_intr_remove_softint(sc->sc_soft_hdl); + sc->sc_soft_hdl = NULL; + + /* + * detach from 80211 module + */ + ieee80211_detach(&sc->sc_ic); + + iwp_destroy_locks(sc); + + ddi_regs_map_free(&sc->sc_handle); + ddi_regs_map_free(&sc->sc_cfg_handle); + ddi_remove_minor_node(dip, NULL); + ddi_soft_state_free(iwp_soft_state_p, ddi_get_instance(dip)); + + return (DDI_SUCCESS); +} + +/* + * destroy all locks + */ +static void +iwp_destroy_locks(iwp_sc_t *sc) +{ + cv_destroy(&sc->sc_mt_cv); + cv_destroy(&sc->sc_cmd_cv); + cv_destroy(&sc->sc_put_seg_cv); + cv_destroy(&sc->sc_ucode_cv); + mutex_destroy(&sc->sc_mt_lock); + mutex_destroy(&sc->sc_tx_lock); + mutex_destroy(&sc->sc_glock); +} + +/* + * Allocate an area of memory and a DMA handle for accessing it + */ +static int +iwp_alloc_dma_mem(iwp_sc_t *sc, size_t memsize, + ddi_dma_attr_t *dma_attr_p, ddi_device_acc_attr_t *acc_attr_p, + uint_t dma_flags, iwp_dma_t *dma_p) +{ + caddr_t vaddr; + int err = DDI_FAILURE; + + /* + * Allocate handle + */ + err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p, + DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); + if (err != DDI_SUCCESS) { + dma_p->dma_hdl = NULL; + return (DDI_FAILURE); + } + + /* + * Allocate memory + */ + err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p, + dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), + DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); + if (err != DDI_SUCCESS) { + ddi_dma_free_handle(&dma_p->dma_hdl); + dma_p->dma_hdl = NULL; + dma_p->acc_hdl = NULL; + return (DDI_FAILURE); + } + + /* + * Bind the two together + */ + dma_p->mem_va = vaddr; + err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, + vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, + &dma_p->cookie, &dma_p->ncookies); + if (err != DDI_DMA_MAPPED) { + ddi_dma_mem_free(&dma_p->acc_hdl); + ddi_dma_free_handle(&dma_p->dma_hdl); + dma_p->acc_hdl = NULL; + dma_p->dma_hdl = NULL; + return (DDI_FAILURE); + } + + dma_p->nslots = ~0U; + dma_p->size = ~0U; + dma_p->token = ~0U; + dma_p->offset = 0; + return (DDI_SUCCESS); +} + +/* + * Free one allocated area of DMAable memory + */ +static void +iwp_free_dma_mem(iwp_dma_t *dma_p) +{ + if (dma_p->dma_hdl != NULL) { + if (dma_p->ncookies) { + (void) ddi_dma_unbind_handle(dma_p->dma_hdl); + dma_p->ncookies = 0; + } + ddi_dma_free_handle(&dma_p->dma_hdl); + dma_p->dma_hdl = NULL; + } + + if (dma_p->acc_hdl != NULL) { + ddi_dma_mem_free(&dma_p->acc_hdl); + dma_p->acc_hdl = NULL; + } +} + +/* + * copy ucode into dma buffers + */ +static int +iwp_alloc_fw_dma(iwp_sc_t *sc) +{ + int err = DDI_FAILURE; + iwp_dma_t *dma_p; + char *t; + + /* + * firmware image layout: + * |HDR|<-TEXT->|<-DATA->|<-INIT_TEXT->|<-INIT_DATA->|<-BOOT->| + */ + + /* + * Check firmware image size. + */ + if (LE_32(sc->sc_hdr->init_textsz) > RTC_INST_SIZE) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "firmware init text size 0x%x is too large\n", + LE_32(sc->sc_hdr->init_textsz)); + + goto fail; + } + + if (LE_32(sc->sc_hdr->init_datasz) > RTC_DATA_SIZE) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "firmware init data size 0x%x is too large\n", + LE_32(sc->sc_hdr->init_datasz)); + + goto fail; + } + + if (LE_32(sc->sc_hdr->textsz) > RTC_INST_SIZE) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "firmware text size 0x%x is too large\n", + LE_32(sc->sc_hdr->textsz)); + + goto fail; + } + + if (LE_32(sc->sc_hdr->datasz) > RTC_DATA_SIZE) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "firmware data size 0x%x is too large\n", + LE_32(sc->sc_hdr->datasz)); + + goto fail; + } + + /* + * copy text of runtime ucode + */ + t = (char *)(sc->sc_hdr + 1); + err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz), + &fw_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_fw_text); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "failed to allocate text dma memory.\n"); + goto fail; + } + + dma_p = &sc->sc_dma_fw_text; + + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_fw_dma(): " + "text[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz)); + + /* + * copy data and bak-data of runtime ucode + */ + t += LE_32(sc->sc_hdr->textsz); + err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), + &fw_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_fw_data); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "failed to allocate data dma memory\n"); + goto fail; + } + + dma_p = &sc->sc_dma_fw_data; + + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_fw_dma(): " + "data[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); + + err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), + &fw_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_fw_data_bak); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "failed to allocate data bakup dma memory\n"); + goto fail; + } + + dma_p = &sc->sc_dma_fw_data_bak; + + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_fw_dma(): " + "data_bak[ncookies:%d addr:%lx " + "size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); + + /* + * copy text of init ucode + */ + t += LE_32(sc->sc_hdr->datasz); + err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz), + &fw_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_fw_init_text); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "failed to allocate init text dma memory\n"); + goto fail; + } + + dma_p = &sc->sc_dma_fw_init_text; + + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_fw_dma(): " + "init_text[ncookies:%d addr:%lx " + "size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz)); + + /* + * copy data of init ucode + */ + t += LE_32(sc->sc_hdr->init_textsz); + err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz), + &fw_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_fw_init_data); + if (err != DDI_SUCCESS) { + cmn_err(CE_WARN, "iwp_alloc_fw_dma(): " + "failed to allocate init data dma memory\n"); + goto fail; + } + + dma_p = &sc->sc_dma_fw_init_data; + + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_fw_dma(): " + "init_data[ncookies:%d addr:%lx " + "size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz)); + + sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz); +fail: + return (err); +} + +static void +iwp_free_fw_dma(iwp_sc_t *sc) +{ + iwp_free_dma_mem(&sc->sc_dma_fw_text); + iwp_free_dma_mem(&sc->sc_dma_fw_data); + iwp_free_dma_mem(&sc->sc_dma_fw_data_bak); + iwp_free_dma_mem(&sc->sc_dma_fw_init_text); + iwp_free_dma_mem(&sc->sc_dma_fw_init_data); +} + +/* + * Allocate a shared buffer between host and NIC. + */ +static int +iwp_alloc_shared(iwp_sc_t *sc) +{ +#ifdef DEBUG + iwp_dma_t *dma_p; +#endif + int err = DDI_FAILURE; + + /* + * must be aligned on a 4K-page boundary + */ + err = iwp_alloc_dma_mem(sc, sizeof (iwp_shared_t), + &sh_dma_attr, &iwp_dma_descattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_sh); + if (err != DDI_SUCCESS) { + goto fail; + } + + sc->sc_shared = (iwp_shared_t *)sc->sc_dma_sh.mem_va; + +#ifdef DEBUG + dma_p = &sc->sc_dma_sh; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_shared(): " + "sh[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + return (err); +fail: + iwp_free_shared(sc); + return (err); +} + +static void +iwp_free_shared(iwp_sc_t *sc) +{ + iwp_free_dma_mem(&sc->sc_dma_sh); +} + +/* + * Allocate a keep warm page. + */ +static int +iwp_alloc_kw(iwp_sc_t *sc) +{ +#ifdef DEBUG + iwp_dma_t *dma_p; +#endif + int err = DDI_FAILURE; + + /* + * must be aligned on a 4K-page boundary + */ + err = iwp_alloc_dma_mem(sc, IWP_KW_SIZE, + &kw_dma_attr, &iwp_dma_descattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &sc->sc_dma_kw); + if (err != DDI_SUCCESS) { + goto fail; + } + +#ifdef DEBUG + dma_p = &sc->sc_dma_kw; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_kw(): " + "kw[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + return (err); +fail: + iwp_free_kw(sc); + return (err); +} + +static void +iwp_free_kw(iwp_sc_t *sc) +{ + iwp_free_dma_mem(&sc->sc_dma_kw); +} + +/* + * initialize RX ring buffers + */ +static int +iwp_alloc_rx_ring(iwp_sc_t *sc) +{ + iwp_rx_ring_t *ring; + iwp_rx_data_t *data; +#ifdef DEBUG + iwp_dma_t *dma_p; +#endif + int i, err = DDI_FAILURE; + + ring = &sc->sc_rxq; + ring->cur = 0; + + /* + * allocate RX description ring buffer + */ + err = iwp_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t), + &ring_desc_dma_attr, &iwp_dma_descattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &ring->dma_desc); + if (err != DDI_SUCCESS) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_rx_ring(): " + "dma alloc rx ring desc " + "failed\n")); + goto fail; + } + + ring->desc = (uint32_t *)ring->dma_desc.mem_va; +#ifdef DEBUG + dma_p = &ring->dma_desc; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_rx_ring(): " + "rx bd[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + /* + * Allocate Rx frame buffers. + */ + for (i = 0; i < RX_QUEUE_SIZE; i++) { + data = &ring->data[i]; + err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, + &rx_buffer_dma_attr, &iwp_dma_accattr, + DDI_DMA_READ | DDI_DMA_STREAMING, + &data->dma_data); + if (err != DDI_SUCCESS) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_rx_ring(): " + "dma alloc rx ring " + "buf[%d] failed\n", i)); + goto fail; + } + /* + * the physical address bit [8-36] are used, + * instead of bit [0-31] in 3945. + */ + ring->desc[i] = (uint32_t) + (data->dma_data.cookie.dmac_address >> 8); + } + +#ifdef DEBUG + dma_p = &ring->data[0].dma_data; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_rx_ring(): " + "rx buffer[0][ncookies:%d addr:%lx " + "size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + IWP_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); + + return (err); + +fail: + iwp_free_rx_ring(sc); + return (err); +} + +/* + * disable RX ring + */ +static void +iwp_reset_rx_ring(iwp_sc_t *sc) +{ + int n; + + iwp_mac_access_enter(sc); + IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); + for (n = 0; n < 2000; n++) { + if (IWP_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) { + break; + } + DELAY(1000); + } +#ifdef DEBUG + if (2000 == n) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_reset_rx_ring(): " + "timeout resetting Rx ring\n")); + } +#endif + iwp_mac_access_exit(sc); + + sc->sc_rxq.cur = 0; +} + +static void +iwp_free_rx_ring(iwp_sc_t *sc) +{ + int i; + + for (i = 0; i < RX_QUEUE_SIZE; i++) { + if (sc->sc_rxq.data[i].dma_data.dma_hdl) { + IWP_DMA_SYNC(sc->sc_rxq.data[i].dma_data, + DDI_DMA_SYNC_FORCPU); + } + + iwp_free_dma_mem(&sc->sc_rxq.data[i].dma_data); + } + + if (sc->sc_rxq.dma_desc.dma_hdl) { + IWP_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV); + } + + iwp_free_dma_mem(&sc->sc_rxq.dma_desc); +} + +/* + * initialize TX ring buffers + */ +static int +iwp_alloc_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring, + int slots, int qid) +{ + iwp_tx_data_t *data; + iwp_tx_desc_t *desc_h; + uint32_t paddr_desc_h; + iwp_cmd_t *cmd_h; + uint32_t paddr_cmd_h; +#ifdef DEBUG + iwp_dma_t *dma_p; +#endif + int i, err = DDI_FAILURE; + ring->qid = qid; + ring->count = TFD_QUEUE_SIZE_MAX; + ring->window = slots; + ring->queued = 0; + ring->cur = 0; + ring->desc_cur = 0; + + /* + * allocate buffer for TX descriptor ring + */ + err = iwp_alloc_dma_mem(sc, + TFD_QUEUE_SIZE_MAX * sizeof (iwp_tx_desc_t), + &ring_desc_dma_attr, &iwp_dma_descattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &ring->dma_desc); + if (err != DDI_SUCCESS) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "dma alloc tx ring desc[%d] " + "failed\n", qid)); + goto fail; + } + +#ifdef DEBUG + dma_p = &ring->dma_desc; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "tx bd[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + desc_h = (iwp_tx_desc_t *)ring->dma_desc.mem_va; + paddr_desc_h = ring->dma_desc.cookie.dmac_address; + + /* + * allocate buffer for ucode command + */ + err = iwp_alloc_dma_mem(sc, + TFD_QUEUE_SIZE_MAX * sizeof (iwp_cmd_t), + &cmd_dma_attr, &iwp_dma_accattr, + DDI_DMA_RDWR | DDI_DMA_CONSISTENT, + &ring->dma_cmd); + if (err != DDI_SUCCESS) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "dma alloc tx ring cmd[%d]" + " failed\n", qid)); + goto fail; + } + +#ifdef DEBUG + dma_p = &ring->dma_cmd; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "tx cmd[ncookies:%d addr:%lx size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + cmd_h = (iwp_cmd_t *)ring->dma_cmd.mem_va; + paddr_cmd_h = ring->dma_cmd.cookie.dmac_address; + + /* + * Allocate Tx frame buffers. + */ + ring->data = kmem_zalloc(sizeof (iwp_tx_data_t) * TFD_QUEUE_SIZE_MAX, + KM_NOSLEEP); + if (NULL == ring->data) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "could not allocate " + "tx data slots\n")); + goto fail; + } + + for (i = 0; i < TFD_QUEUE_SIZE_MAX; i++) { + data = &ring->data[i]; + err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, + &tx_buffer_dma_attr, &iwp_dma_accattr, + DDI_DMA_WRITE | DDI_DMA_STREAMING, + &data->dma_data); + if (err != DDI_SUCCESS) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "dma alloc tx " + "ring buf[%d] failed\n", i)); + goto fail; + } + + data->desc = desc_h + i; + data->paddr_desc = paddr_desc_h + + _PTRDIFF(data->desc, desc_h); + data->cmd = cmd_h + i; + data->paddr_cmd = paddr_cmd_h + + _PTRDIFF(data->cmd, cmd_h); + } +#ifdef DEBUG + dma_p = &ring->data[0].dma_data; +#endif + IWP_DBG((IWP_DEBUG_DMA, "iwp_alloc_tx_ring(): " + "tx buffer[0][ncookies:%d addr:%lx " + "size:%lx]\n", + dma_p->ncookies, dma_p->cookie.dmac_address, + dma_p->cookie.dmac_size)); + + return (err); + +fail: + iwp_free_tx_ring(ring); + + return (err); +} + +/* + * disable TX ring + */ +static void +iwp_reset_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring) +{ + iwp_tx_data_t *data; + int i, n; + + iwp_mac_access_enter(sc); + + IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0); + for (n = 0; n < 200; n++) { + if (IWP_READ(sc, IWP_FH_TSSR_TX_STATUS_REG) & + IWP_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ring->qid)) { + break; + } + DELAY(10); + } + +#ifdef DEBUG + if (200 == n) { + IWP_DBG((IWP_DEBUG_DMA, "iwp_reset_tx_ring(): " + "timeout reset tx ring %d\n", + ring->qid)); + } +#endif + + iwp_mac_access_exit(sc); + + /* by pass, if it's quiesce */ + if (!(sc->sc_flags & IWP_F_QUIESCED)) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + IWP_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV); + } + } + + ring->queued = 0; + ring->cur = 0; + ring->desc_cur = 0; +} + +static void +iwp_free_tx_ring(iwp_tx_ring_t *ring) +{ + int i; + + if (ring->dma_desc.dma_hdl != NULL) { + IWP_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); + } + iwp_free_dma_mem(&ring->dma_desc); + + if (ring->dma_cmd.dma_hdl != NULL) { + IWP_DMA_SYNC(ring->dma_cmd, DDI_DMA_SYNC_FORDEV); + } + iwp_free_dma_mem(&ring->dma_cmd); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + if (ring->data[i].dma_data.dma_hdl) { + IWP_DMA_SYNC(ring->data[i].dma_data, + DDI_DMA_SYNC_FORDEV); + } + iwp_free_dma_mem(&ring->data[i].dma_data); + } + kmem_free(ring->data, ring->count * sizeof (iwp_tx_data_t)); + } +} + +/* + * initialize TX and RX ring + */ +static int +iwp_ring_init(iwp_sc_t *sc) +{ + int i, err = DDI_FAILURE; + + for (i = 0; i < IWP_NUM_QUEUES; i++) { + if (IWP_CMD_QUEUE_NUM == i) { + continue; + } + + err = iwp_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS, + i); + if (err != DDI_SUCCESS) { + goto fail; + } + } + + /* + * initialize command queue + */ + err = iwp_alloc_tx_ring(sc, &sc->sc_txq[IWP_CMD_QUEUE_NUM], + TFD_CMD_SLOTS, IWP_CMD_QUEUE_NUM); + if (err != DDI_SUCCESS) { + goto fail; + } + + err = iwp_alloc_rx_ring(sc); + if (err != DDI_SUCCESS) { + goto fail; + } + +fail: + return (err); +} + +static void +iwp_ring_free(iwp_sc_t *sc) +{ + int i = IWP_NUM_QUEUES; + + iwp_free_rx_ring(sc); + while (--i >= 0) { + iwp_free_tx_ring(&sc->sc_txq[i]); + } +} + +/* ARGSUSED */ +static ieee80211_node_t * +iwp_node_alloc(ieee80211com_t *ic) +{ + iwp_amrr_t *amrr; + + amrr = kmem_zalloc(sizeof (iwp_amrr_t), KM_SLEEP); + if (NULL == amrr) { + cmn_err(CE_WARN, "iwp_node_alloc(): " + "failed to allocate memory for amrr structure\n"); + return (NULL); + } + + iwp_amrr_init(amrr); + + return (&amrr->in); +} + +static void +iwp_node_free(ieee80211_node_t *in) +{ + ieee80211com_t *ic; + + if ((NULL == in) || + (NULL == in->in_ic)) { + cmn_err(CE_WARN, "iwp_node_free() " + "Got a NULL point from Net80211 module\n"); + return; + } + ic = in->in_ic; + + if (ic->ic_node_cleanup != NULL) { + ic->ic_node_cleanup(in); + } + + if (in->in_wpa_ie != NULL) { + ieee80211_free(in->in_wpa_ie); + } + + if (in->in_wme_ie != NULL) { + ieee80211_free(in->in_wme_ie); + } + + if (in->in_htcap_ie != NULL) { + ieee80211_free(in->in_htcap_ie); + } + + kmem_free(in, sizeof (iwp_amrr_t)); +} + + +/* + * change station's state. this function will be invoked by 80211 module + * when need to change staton's state. + */ +static int +iwp_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) +{ + iwp_sc_t *sc; + ieee80211_node_t *in; + enum ieee80211_state ostate; + iwp_add_sta_t node; + int i, err = IWP_FAIL; + + if (NULL == ic) { + return (err); + } + sc = (iwp_sc_t *)ic; + in = ic->ic_bss; + ostate = ic->ic_state; + + mutex_enter(&sc->sc_glock); + + switch (nstate) { + case IEEE80211_S_SCAN: + switch (ostate) { + case IEEE80211_S_INIT: + atomic_or_32(&sc->sc_flags, IWP_F_SCANNING); + iwp_set_led(sc, 2, 10, 2); + + /* + * clear association to receive beacons from + * all BSS'es + */ + sc->sc_config.assoc_id = 0; + sc->sc_config.filter_flags &= + ~LE_32(RXON_FILTER_ASSOC_MSK); + + IWP_DBG((IWP_DEBUG_80211, "iwp_newstate(): " + "config chan %d " + "flags %x filter_flags %x\n", + LE_16(sc->sc_config.chan), + LE_32(sc->sc_config.flags), + LE_32(sc->sc_config.filter_flags))); + + err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, + sizeof (iwp_rxon_cmd_t), 1); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_newstate(): " + "could not clear association\n"); + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + mutex_exit(&sc->sc_glock); + return (err); + } + + /* add broadcast node to send probe request */ + (void) memset(&node, 0, sizeof (node)); + (void) memset(&node.sta.addr, 0xff, IEEE80211_ADDR_LEN); + node.sta.sta_id = IWP_BROADCAST_ID; + err = iwp_cmd(sc, REPLY_ADD_STA, &node, + sizeof (node), 1); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_newstate(): " + "could not add broadcast node\n"); + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + mutex_exit(&sc->sc_glock); + return (err); + } + break; + case IEEE80211_S_SCAN: + mutex_exit(&sc->sc_glock); + /* step to next channel before actual FW scan */ + err = sc->sc_newstate(ic, nstate, arg); + mutex_enter(&sc->sc_glock); + if ((err != 0) || ((err = iwp_scan(sc)) != 0)) { + cmn_err(CE_WARN, "iwp_newstate(): " + "could not initiate scan\n"); + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + ieee80211_cancel_scan(ic); + } + mutex_exit(&sc->sc_glock); + return (err); + default: + break; + } + sc->sc_clk = 0; + break; + + case IEEE80211_S_AUTH: + if (ostate == IEEE80211_S_SCAN) { + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + } + + /* + * reset state to handle reassociations correctly + */ + sc->sc_config.assoc_id = 0; + sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); + + /* + * before sending authentication and association request frame, + * we need do something in the hardware, such as setting the + * channel same to the target AP... + */ + if ((err = iwp_hw_set_before_auth(sc)) != 0) { + IWP_DBG((IWP_DEBUG_80211, "iwp_newstate(): " + "could not send authentication request\n")); + mutex_exit(&sc->sc_glock); + return (err); + } + break; + + case IEEE80211_S_RUN: + if (ostate == IEEE80211_S_SCAN) { + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + } + + if (IEEE80211_M_MONITOR == ic->ic_opmode) { + /* let LED blink when monitoring */ + iwp_set_led(sc, 2, 10, 10); + break; + } + + IWP_DBG((IWP_DEBUG_80211, "iwp_newstate(): " + "associated.\n")); + + err = iwp_run_state_config(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_newstate(): " + "failed to set up association\n"); + mutex_exit(&sc->sc_glock); + return (err); + } + + /* + * start automatic rate control + */ + if (IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) { + atomic_or_32(&sc->sc_flags, IWP_F_RATE_AUTO_CTL); + + /* + * set rate to some reasonable initial value + */ + i = in->in_rates.ir_nrates - 1; + while (i > 0 && IEEE80211_RATE(i) > 72) { + i--; + } + in->in_txrate = i; + + } else { + atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); + } + + /* + * set LED on after associated + */ + iwp_set_led(sc, 2, 0, 1); + break; + + case IEEE80211_S_INIT: + if (ostate == IEEE80211_S_SCAN) { + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + } + /* + * set LED off after init + */ + iwp_set_led(sc, 2, 1, 0); + break; + + case IEEE80211_S_ASSOC: + if (ostate == IEEE80211_S_SCAN) { + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); + } + break; + } + + mutex_exit(&sc->sc_glock); + + return (sc->sc_newstate(ic, nstate, arg)); +} + +/* + * exclusive access to mac begin. + */ +static void +iwp_mac_access_enter(iwp_sc_t *sc) +{ + uint32_t tmp; + int n; + + tmp = IWP_READ(sc, CSR_GP_CNTRL); + IWP_WRITE(sc, CSR_GP_CNTRL, + tmp | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + + /* wait until we succeed */ + for (n = 0; n < 1000; n++) { + if ((IWP_READ(sc, CSR_GP_CNTRL) & + (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | + CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP)) == + CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN) { + break; + } + DELAY(10); + } + +#ifdef DEBUG + if (1000 == n) { + IWP_DBG((IWP_DEBUG_PIO, "iwp_mac_access_enter(): " + "could not lock memory\n")); + } +#endif +} + +/* + * exclusive access to mac end. + */ +static void +iwp_mac_access_exit(iwp_sc_t *sc) +{ + uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); + IWP_WRITE(sc, CSR_GP_CNTRL, + tmp & ~CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); +} + +/* + * this function defined here for future use. + * static uint32_t + * iwp_mem_read(iwp_sc_t *sc, uint32_t addr) + * { + * IWP_WRITE(sc, HBUS_TARG_MEM_RADDR, addr); + * return (IWP_READ(sc, HBUS_TARG_MEM_RDAT)); + * } + */ + +/* + * write mac memory + */ +static void +iwp_mem_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) +{ + IWP_WRITE(sc, HBUS_TARG_MEM_WADDR, addr); + IWP_WRITE(sc, HBUS_TARG_MEM_WDAT, data); +} + +/* + * read mac register + */ +static uint32_t +iwp_reg_read(iwp_sc_t *sc, uint32_t addr) +{ + IWP_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24)); + return (IWP_READ(sc, HBUS_TARG_PRPH_RDAT)); +} + +/* + * write mac register + */ +static void +iwp_reg_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) +{ + IWP_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24)); + IWP_WRITE(sc, HBUS_TARG_PRPH_WDAT, data); +} + + +/* + * steps of loading ucode: + * load init ucode=>init alive=>calibrate=> + * receive calibration result=>reinitialize NIC=> + * load runtime ucode=>runtime alive=> + * send calibration result=>running. + */ +static int +iwp_load_init_firmware(iwp_sc_t *sc) +{ + int err = IWP_FAIL; + clock_t clk; + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + /* + * load init_text section of uCode to hardware + */ + err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address, + RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_load_init_firmware(): " + "failed to write init uCode.\n"); + return (err); + } + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + + /* wait loading init_text until completed or timeout */ + while (!(sc->sc_flags & IWP_F_PUT_SEG)) { + if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_PUT_SEG)) { + cmn_err(CE_WARN, "iwp_load_init_firmware(): " + "timeout waiting for init uCode load.\n"); + return (IWP_FAIL); + } + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + /* + * load init_data section of uCode to hardware + */ + err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address, + RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_load_init_firmware(): " + "failed to write init_data uCode.\n"); + return (err); + } + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + + /* + * wait loading init_data until completed or timeout + */ + while (!(sc->sc_flags & IWP_F_PUT_SEG)) { + if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_PUT_SEG)) { + cmn_err(CE_WARN, "iwp_load_init_firmware(): " + "timeout waiting for init_data uCode load.\n"); + return (IWP_FAIL); + } + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + return (err); +} + +static int +iwp_load_run_firmware(iwp_sc_t *sc) +{ + int err = IWP_FAIL; + clock_t clk; + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + /* + * load init_text section of uCode to hardware + */ + err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address, + RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_load_run_firmware(): " + "failed to write run uCode.\n"); + return (err); + } + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + + /* wait loading run_text until completed or timeout */ + while (!(sc->sc_flags & IWP_F_PUT_SEG)) { + if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_PUT_SEG)) { + cmn_err(CE_WARN, "iwp_load_run_firmware(): " + "timeout waiting for run uCode load.\n"); + return (IWP_FAIL); + } + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + /* + * load run_data section of uCode to hardware + */ + err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address, + RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_load_run_firmware(): " + "failed to write run_data uCode.\n"); + return (err); + } + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + + /* + * wait loading run_data until completed or timeout + */ + while (!(sc->sc_flags & IWP_F_PUT_SEG)) { + if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_PUT_SEG)) { + cmn_err(CE_WARN, "iwp_load_run_firmware(): " + "timeout waiting for run_data uCode load.\n"); + return (IWP_FAIL); + } + + atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); + + return (err); +} + +/* + * this function will be invoked to receive phy information + * when a frame is received. + */ +static void +iwp_rx_phy_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + + sc->sc_rx_phy_res.flag = 1; + + (void) memcpy(sc->sc_rx_phy_res.buf, (uint8_t *)(desc + 1), + sizeof (iwp_rx_phy_res_t)); +} + +/* + * this function will be invoked to receive body of frame when + * a frame is received. + */ +static void +iwp_rx_mpdu_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + ieee80211com_t *ic = &sc->sc_ic; +#ifdef DEBUG + iwp_rx_ring_t *ring = &sc->sc_rxq; +#endif + struct ieee80211_frame *wh; + struct iwp_rx_non_cfg_phy *phyinfo; + struct iwp_rx_mpdu_body_size *mpdu_size; + + mblk_t *mp; + int16_t t; + uint16_t len, rssi, agc; + uint32_t temp, crc, *tail; + uint32_t arssi, brssi, crssi, mrssi; + iwp_rx_phy_res_t *stat; + ieee80211_node_t *in; + + /* + * assuming not 11n here. cope with 11n in phase-II + */ + mpdu_size = (struct iwp_rx_mpdu_body_size *)(desc + 1); + stat = (iwp_rx_phy_res_t *)sc->sc_rx_phy_res.buf; + if (stat->cfg_phy_cnt > 20) { + return; + } + + phyinfo = (struct iwp_rx_non_cfg_phy *)stat->non_cfg_phy; + temp = LE_32(phyinfo->non_cfg_phy[IWP_RX_RES_AGC_IDX]); + agc = (temp & IWP_OFDM_AGC_MSK) >> IWP_OFDM_AGC_BIT_POS; + + temp = LE_32(phyinfo->non_cfg_phy[IWP_RX_RES_RSSI_AB_IDX]); + arssi = (temp & IWP_OFDM_RSSI_A_MSK) >> IWP_OFDM_RSSI_A_BIT_POS; + brssi = (temp & IWP_OFDM_RSSI_B_MSK) >> IWP_OFDM_RSSI_B_BIT_POS; + + temp = LE_32(phyinfo->non_cfg_phy[IWP_RX_RES_RSSI_C_IDX]); + crssi = (temp & IWP_OFDM_RSSI_C_MSK) >> IWP_OFDM_RSSI_C_BIT_POS; + + mrssi = MAX(arssi, brssi); + mrssi = MAX(mrssi, crssi); + + t = mrssi - agc - IWP_RSSI_OFFSET; + /* + * convert dBm to percentage + */ + rssi = (100 * 75 * 75 - (-20 - t) * (15 * 75 + 62 * (-20 - t))) + / (75 * 75); + if (rssi > 100) { + rssi = 100; + } + if (rssi < 1) { + rssi = 1; + } + + /* + * size of frame, not include FCS + */ + len = LE_16(mpdu_size->byte_count); + tail = (uint32_t *)((uint8_t *)(desc + 1) + + sizeof (struct iwp_rx_mpdu_body_size) + len); + bcopy(tail, &crc, 4); + + IWP_DBG((IWP_DEBUG_RX, "iwp_rx_mpdu_intr(): " + "rx intr: idx=%d phy_len=%x len=%d " + "rate=%x chan=%d tstamp=%x non_cfg_phy_count=%x " + "cfg_phy_count=%x tail=%x", ring->cur, sizeof (*stat), + len, stat->rate.r.s.rate, stat->channel, + LE_32(stat->timestampl), stat->non_cfg_phy_cnt, + stat->cfg_phy_cnt, LE_32(crc))); + + if ((len < 16) || (len > sc->sc_dmabuf_sz)) { + IWP_DBG((IWP_DEBUG_RX, "iwp_rx_mpdu_intr(): " + "rx frame oversize\n")); + return; + } + + /* + * discard Rx frames with bad CRC + */ + if ((LE_32(crc) & + (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) != + (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) { + IWP_DBG((IWP_DEBUG_RX, "iwp_rx_mpdu_intr(): " + "rx crc error tail: %x\n", + LE_32(crc))); + sc->sc_rx_err++; + return; + } + + wh = (struct ieee80211_frame *) + ((uint8_t *)(desc + 1)+ sizeof (struct iwp_rx_mpdu_body_size)); + + if (IEEE80211_FC0_SUBTYPE_ASSOC_RESP == *(uint8_t *)wh) { + sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2); + IWP_DBG((IWP_DEBUG_RX, "iwp_rx_mpdu_intr(): " + "rx : association id = %x\n", + sc->sc_assoc_id)); + } + +#ifdef DEBUG + if (iwp_dbg_flags & IWP_DEBUG_RX) { + ieee80211_dump_pkt((uint8_t *)wh, len, 0, 0); + } +#endif + + in = ieee80211_find_rxnode(ic, wh); + mp = allocb(len, BPRI_MED); + if (mp) { + (void) memcpy(mp->b_wptr, wh, len); + mp->b_wptr += len; + + /* + * send the frame to the 802.11 layer + */ + (void) ieee80211_input(ic, mp, in, rssi, 0); + } else { + sc->sc_rx_nobuf++; + IWP_DBG((IWP_DEBUG_RX, "iwp_rx_mpdu_intr(): " + "alloc rx buf failed\n")); + } + + /* + * release node reference + */ + ieee80211_free_node(in); +} + +/* + * process correlative affairs after a frame is sent. + */ +static void +iwp_tx_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + ieee80211com_t *ic = &sc->sc_ic; + iwp_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3]; + iwp_tx_stat_t *stat = (iwp_tx_stat_t *)(desc + 1); + iwp_amrr_t *amrr; + + if (NULL == ic->ic_bss) { + return; + } + + amrr = (iwp_amrr_t *)ic->ic_bss; + + amrr->txcnt++; + IWP_DBG((IWP_DEBUG_RATECTL, "iwp_tx_intr(): " + "tx: %d cnt\n", amrr->txcnt)); + + if (stat->ntries > 0) { + amrr->retrycnt++; + sc->sc_tx_retries++; + IWP_DBG((IWP_DEBUG_TX, "iwp_tx_intr(): " + "tx: %d retries\n", + sc->sc_tx_retries)); + } + + mutex_enter(&sc->sc_mt_lock); + sc->sc_tx_timer = 0; + mutex_exit(&sc->sc_mt_lock); + + mutex_enter(&sc->sc_tx_lock); + + ring->queued--; + if (ring->queued < 0) { + ring->queued = 0; + } + + if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) { + sc->sc_need_reschedule = 0; + mutex_exit(&sc->sc_tx_lock); + mac_tx_update(ic->ic_mach); + mutex_enter(&sc->sc_tx_lock); + } + + mutex_exit(&sc->sc_tx_lock); +} + +/* + * inform a given command has been executed + */ +static void +iwp_cmd_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + if ((desc->hdr.qid & 7) != 4) { + return; + } + + if (sc->sc_cmd_accum > 0) { + sc->sc_cmd_accum--; + return; + } + + mutex_enter(&sc->sc_glock); + + sc->sc_cmd_flag = SC_CMD_FLG_DONE; + + cv_signal(&sc->sc_cmd_cv); + + mutex_exit(&sc->sc_glock); + + IWP_DBG((IWP_DEBUG_CMD, "iwp_cmd_intr(): " + "qid=%x idx=%d flags=%x type=0x%x\n", + desc->hdr.qid, desc->hdr.idx, desc->hdr.flags, + desc->hdr.type)); +} + +/* + * this function will be invoked when alive notification occur. + */ +static void +iwp_ucode_alive(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + uint32_t rv; + struct iwp_calib_cfg_cmd cmd; + struct iwp_alive_resp *ar = + (struct iwp_alive_resp *)(desc + 1); + struct iwp_calib_results *res_p = &sc->sc_calib_results; + + /* + * the microcontroller is ready + */ + IWP_DBG((IWP_DEBUG_FW, "iwp_ucode_alive(): " + "microcode alive notification minor: %x major: %x type: " + "%x subtype: %x\n", + ar->ucode_minor, ar->ucode_minor, ar->ver_type, ar->ver_subtype)); + +#ifdef DEBUG + if (LE_32(ar->is_valid) != UCODE_VALID_OK) { + IWP_DBG((IWP_DEBUG_FW, "iwp_ucode_alive(): " + "microcontroller initialization failed\n")); + } +#endif + + /* + * determine if init alive or runtime alive. + */ + if (INITIALIZE_SUBTYPE == ar->ver_subtype) { + IWP_DBG((IWP_DEBUG_FW, "iwp_ucode_alive(): " + "initialization alive received.\n")); + + (void) memcpy(&sc->sc_card_alive_init, ar, + sizeof (struct iwp_init_alive_resp)); + + /* + * necessary configuration to NIC + */ + mutex_enter(&sc->sc_glock); + + rv = iwp_alive_common(sc); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "common alive process failed in init alive.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + (void) memset(&cmd, 0, sizeof (cmd)); + + cmd.ucd_calib_cfg.once.is_enable = IWP_CALIB_INIT_CFG_ALL; + cmd.ucd_calib_cfg.once.start = IWP_CALIB_INIT_CFG_ALL; + cmd.ucd_calib_cfg.once.send_res = IWP_CALIB_INIT_CFG_ALL; + cmd.ucd_calib_cfg.flags = IWP_CALIB_INIT_CFG_ALL; + + /* + * require ucode execute calibration + */ + rv = iwp_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "failed to send calibration configure command.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + mutex_exit(&sc->sc_glock); + + } else { /* runtime alive */ + + IWP_DBG((IWP_DEBUG_FW, "iwp_ucode_alive(): " + "runtime alive received.\n")); + + (void) memcpy(&sc->sc_card_alive_run, ar, + sizeof (struct iwp_alive_resp)); + + mutex_enter(&sc->sc_glock); + + /* + * necessary configuration to NIC + */ + rv = iwp_alive_common(sc); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "common alive process failed in run alive.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + /* + * send the result of local oscilator calibration to uCode. + */ + if (res_p->lo_res != NULL) { + rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, + res_p->lo_res, res_p->lo_res_len, 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "failed to send local" + "oscilator calibration command.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + DELAY(1000); + } + + /* + * send the result of TX IQ calibration to uCode. + */ + if (res_p->tx_iq_res != NULL) { + rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, + res_p->tx_iq_res, res_p->tx_iq_res_len, 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "failed to send TX IQ" + "calibration command.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + DELAY(1000); + } + + /* + * send the result of TX IQ perd calibration to uCode. + */ + if (res_p->tx_iq_perd_res != NULL) { + rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, + res_p->tx_iq_perd_res, + res_p->tx_iq_perd_res_len, 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "failed to send TX IQ perd" + "calibration command.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + DELAY(1000); + } + + /* + * send the result of Base Band calibration to uCode. + */ + if (res_p->base_band_res != NULL) { + rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, + res_p->base_band_res, + res_p->base_band_res_len, 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_ucode_alive(): " + "failed to send Base Band" + "calibration command.\n"); + mutex_exit(&sc->sc_glock); + return; + } + + DELAY(1000); + } + + atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); + cv_signal(&sc->sc_ucode_cv); + + mutex_exit(&sc->sc_glock); + } + +} + +/* + * deal with receiving frames, command response + * and all notifications from ucode. + */ +/* ARGSUSED */ +static uint_t +iwp_rx_softintr(caddr_t arg, caddr_t unused) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + iwp_rx_desc_t *desc; + iwp_rx_data_t *data; + uint32_t index; + + if (NULL == arg) { + return (DDI_INTR_UNCLAIMED); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + /* + * firmware has moved the index of the rx queue, driver get it, + * and deal with it. + */ + index = (sc->sc_shared->val0) & 0xfff; + + while (sc->sc_rxq.cur != index) { + data = &sc->sc_rxq.data[sc->sc_rxq.cur]; + desc = (iwp_rx_desc_t *)data->dma_data.mem_va; + + IWP_DBG((IWP_DEBUG_INTR, "iwp_rx_softintr(): " + "rx notification index = %d" + " cur = %d qid=%x idx=%d flags=%x type=%x len=%d\n", + index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx, + desc->hdr.flags, desc->hdr.type, LE_32(desc->len))); + + /* + * a command other than a tx need to be replied + */ + if (!(desc->hdr.qid & 0x80) && + (desc->hdr.type != REPLY_SCAN_CMD) && + (desc->hdr.type != REPLY_TX)) { + iwp_cmd_intr(sc, desc); + } + + switch (desc->hdr.type) { + case REPLY_RX_PHY_CMD: + iwp_rx_phy_intr(sc, desc); + break; + + case REPLY_RX_MPDU_CMD: + iwp_rx_mpdu_intr(sc, desc); + break; + + case REPLY_TX: + iwp_tx_intr(sc, desc); + break; + + case REPLY_ALIVE: + iwp_ucode_alive(sc, desc); + break; + + case CARD_STATE_NOTIFICATION: + { + uint32_t *status = (uint32_t *)(desc + 1); + + IWP_DBG((IWP_DEBUG_RADIO, "iwp_rx_softintr(): " + "state changed to %x\n", + LE_32(*status))); + + if (LE_32(*status) & 1) { + /* + * the radio button has to be pushed(OFF). It + * is considered as a hw error, the + * iwp_thread() tries to recover it after the + * button is pushed again(ON) + */ + cmn_err(CE_NOTE, "iwp_rx_softintr(): " + "radio transmitter is off\n"); + sc->sc_ostate = sc->sc_ic.ic_state; + ieee80211_new_state(&sc->sc_ic, + IEEE80211_S_INIT, -1); + atomic_or_32(&sc->sc_flags, + IWP_F_HW_ERR_RECOVER | IWP_F_RADIO_OFF); + } + + break; + } + + case SCAN_START_NOTIFICATION: + { + iwp_start_scan_t *scan = + (iwp_start_scan_t *)(desc + 1); + + IWP_DBG((IWP_DEBUG_SCAN, "iwp_rx_softintr(): " + "scanning channel %d status %x\n", + scan->chan, LE_32(scan->status))); + + ic->ic_curchan = &ic->ic_sup_channels[scan->chan]; + break; + } + + case SCAN_COMPLETE_NOTIFICATION: + { +#ifdef DEBUG + iwp_stop_scan_t *scan = + (iwp_stop_scan_t *)(desc + 1); + + IWP_DBG((IWP_DEBUG_SCAN, "iwp_rx_softintr(): " + "completed channel %d (burst of %d) status %02x\n", + scan->chan, scan->nchan, scan->status)); +#endif + + sc->sc_scan_pending++; + break; + } + + case STATISTICS_NOTIFICATION: + { + /* + * handle statistics notification + */ + break; + } + + case CALIBRATION_RES_NOTIFICATION: + iwp_save_calib_result(sc, desc); + break; + + case CALIBRATION_COMPLETE_NOTIFICATION: + mutex_enter(&sc->sc_glock); + atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); + cv_signal(&sc->sc_ucode_cv); + mutex_exit(&sc->sc_glock); + break; + + case MISSED_BEACONS_NOTIFICATION: + { + struct iwp_beacon_missed *miss = + (struct iwp_beacon_missed *)(desc + 1); + + if ((ic->ic_state == IEEE80211_S_RUN) && + (LE_32(miss->consecutive) > 50)) { + cmn_err(CE_NOTE, "iwp: iwp_rx_softintr(): " + "beacon missed %d/%d\n", + LE_32(miss->consecutive), + LE_32(miss->total)); + (void) ieee80211_new_state(ic, + IEEE80211_S_INIT, -1); + } + break; + } + } + + sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE; + } + + /* + * driver dealt with what received in rx queue and tell the information + * to the firmware. + */ + index = (0 == index) ? RX_QUEUE_SIZE - 1 : index - 1; + IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7)); + + /* + * re-enable interrupts + */ + IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); + + return (DDI_INTR_CLAIMED); +} + +/* + * the handle of interrupt + */ +/* ARGSUSED */ +static uint_t +iwp_intr(caddr_t arg, caddr_t unused) +{ + iwp_sc_t *sc; + uint32_t r, rfh; + + if (NULL == arg) { + return (DDI_INTR_UNCLAIMED); + } + sc = (iwp_sc_t *)arg; + + r = IWP_READ(sc, CSR_INT); + if (0 == r || 0xffffffff == r) { + return (DDI_INTR_UNCLAIMED); + } + + IWP_DBG((IWP_DEBUG_INTR, "iwp_intr(): " + "interrupt reg %x\n", r)); + + rfh = IWP_READ(sc, CSR_FH_INT_STATUS); + + IWP_DBG((IWP_DEBUG_INTR, "iwp_intr(): " + "FH interrupt reg %x\n", rfh)); + + /* + * disable interrupts + */ + IWP_WRITE(sc, CSR_INT_MASK, 0); + + /* + * ack interrupts + */ + IWP_WRITE(sc, CSR_INT, r); + IWP_WRITE(sc, CSR_FH_INT_STATUS, rfh); + + if (r & (BIT_INT_SWERROR | BIT_INT_ERR)) { + IWP_DBG((IWP_DEBUG_FW, "iwp_intr(): " + "fatal firmware error\n")); + iwp_stop(sc); + sc->sc_ostate = sc->sc_ic.ic_state; + + /* notify upper layer */ + if (!IWP_CHK_FAST_RECOVER(sc)) { + ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1); + } + + atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); + return (DDI_INTR_CLAIMED); + } + + if (r & BIT_INT_RF_KILL) { + uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); + if (tmp & (1 << 27)) { + cmn_err(CE_NOTE, "RF switch: radio on\n"); + } + } + + if ((r & (BIT_INT_FH_RX | BIT_INT_SW_RX)) || + (rfh & FH_INT_RX_MASK)) { + (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL); + return (DDI_INTR_CLAIMED); + } + + if (r & BIT_INT_FH_TX) { + mutex_enter(&sc->sc_glock); + atomic_or_32(&sc->sc_flags, IWP_F_PUT_SEG); + cv_signal(&sc->sc_put_seg_cv); + mutex_exit(&sc->sc_glock); + } + +#ifdef DEBUG + if (r & BIT_INT_ALIVE) { + IWP_DBG((IWP_DEBUG_FW, "iwp_intr(): " + "firmware initialized.\n")); + } +#endif + + /* + * re-enable interrupts + */ + IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); + + return (DDI_INTR_CLAIMED); +} + +static uint8_t +iwp_rate_to_plcp(int rate) +{ + uint8_t ret; + + switch (rate) { + /* + * CCK rates + */ + case 2: + ret = 0xa; + break; + + case 4: + ret = 0x14; + break; + + case 11: + ret = 0x37; + break; + + case 22: + ret = 0x6e; + break; + + /* + * OFDM rates + */ + case 12: + ret = 0xd; + break; + + case 18: + ret = 0xf; + break; + + case 24: + ret = 0x5; + break; + + case 36: + ret = 0x7; + break; + + case 48: + ret = 0x9; + break; + + case 72: + ret = 0xb; + break; + + case 96: + ret = 0x1; + break; + + case 108: + ret = 0x3; + break; + + default: + ret = 0; + break; + } + + return (ret); +} + +/* + * invoked by GLD send frames + */ +static mblk_t * +iwp_m_tx(void *arg, mblk_t *mp) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + mblk_t *next; + + if (NULL == arg) { + return (NULL); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + if (sc->sc_flags & IWP_F_SUSPEND) { + freemsgchain(mp); + return (NULL); + } + + if (ic->ic_state != IEEE80211_S_RUN) { + freemsgchain(mp); + return (NULL); + } + + if ((sc->sc_flags & IWP_F_HW_ERR_RECOVER) && + IWP_CHK_FAST_RECOVER(sc)) { + IWP_DBG((IWP_DEBUG_FW, "iwp_m_tx(): " + "hold queue\n")); + return (mp); + } + + + while (mp != NULL) { + next = mp->b_next; + mp->b_next = NULL; + if (iwp_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != 0) { + mp->b_next = next; + break; + } + mp = next; + } + + return (mp); +} + +/* + * send frames + */ +static int +iwp_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) +{ + iwp_sc_t *sc; + iwp_tx_ring_t *ring; + iwp_tx_desc_t *desc; + iwp_tx_data_t *data; + iwp_tx_data_t *desc_data; + iwp_cmd_t *cmd; + iwp_tx_cmd_t *tx; + ieee80211_node_t *in; + struct ieee80211_frame *wh; + struct ieee80211_key *k = NULL; + mblk_t *m, *m0; + int hdrlen, len, len0, mblen, off, err = IWP_SUCCESS; + uint16_t masks = 0; + uint32_t rate, s_id = 0; + + if (NULL == ic) { + return (IWP_FAIL); + } + sc = (iwp_sc_t *)ic; + + if (sc->sc_flags & IWP_F_SUSPEND) { + if ((type & IEEE80211_FC0_TYPE_MASK) != + IEEE80211_FC0_TYPE_DATA) { + freemsg(mp); + } + err = IWP_FAIL; + goto exit; + } + + mutex_enter(&sc->sc_tx_lock); + ring = &sc->sc_txq[0]; + data = &ring->data[ring->cur]; + cmd = data->cmd; + bzero(cmd, sizeof (*cmd)); + + ring->cur = (ring->cur + 1) % ring->count; + + /* + * Need reschedule TX if TX buffer is full. + */ + if (ring->queued > ring->count - IWP_MAX_WIN_SIZE) { + IWP_DBG((IWP_DEBUG_TX, "iwp_send(): " + "no txbuf\n")); + + sc->sc_need_reschedule = 1; + mutex_exit(&sc->sc_tx_lock); + + if ((type & IEEE80211_FC0_TYPE_MASK) != + IEEE80211_FC0_TYPE_DATA) { + freemsg(mp); + } + sc->sc_tx_nobuf++; + err = IWP_FAIL; + goto exit; + } + + ring->queued++; + + mutex_exit(&sc->sc_tx_lock); + + hdrlen = ieee80211_hdrspace(ic, mp->b_rptr); + + m = allocb(msgdsize(mp) + 32, BPRI_MED); + if (NULL == m) { /* can not alloc buf, drop this package */ + cmn_err(CE_WARN, "iwp_send(): " + "failed to allocate msgbuf\n"); + freemsg(mp); + + mutex_enter(&sc->sc_tx_lock); + ring->queued--; + if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { + sc->sc_need_reschedule = 0; + mutex_exit(&sc->sc_tx_lock); + mac_tx_update(ic->ic_mach); + mutex_enter(&sc->sc_tx_lock); + } + mutex_exit(&sc->sc_tx_lock); + + err = IWP_SUCCESS; + goto exit; + } + + for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { + mblen = MBLKL(m0); + (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); + off += mblen; + } + + m->b_wptr += off; + + wh = (struct ieee80211_frame *)m->b_rptr; + + /* + * determine send which AP or station in IBSS + */ + in = ieee80211_find_txnode(ic, wh->i_addr1); + if (NULL == in) { + cmn_err(CE_WARN, "iwp_send(): " + "failed to find tx node\n"); + freemsg(mp); + freemsg(m); + sc->sc_tx_err++; + + mutex_enter(&sc->sc_tx_lock); + ring->queued--; + if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { + sc->sc_need_reschedule = 0; + mutex_exit(&sc->sc_tx_lock); + mac_tx_update(ic->ic_mach); + mutex_enter(&sc->sc_tx_lock); + } + mutex_exit(&sc->sc_tx_lock); + + err = IWP_SUCCESS; + goto exit; + } + + /* + * Net80211 module encapsulate outbound data frames. + * Add some feilds of 80211 frame. + */ + if ((type & IEEE80211_FC0_TYPE_MASK) == + IEEE80211_FC0_TYPE_DATA) { + (void) ieee80211_encap(ic, m, in); + } + + freemsg(mp); + + cmd->hdr.type = REPLY_TX; + cmd->hdr.flags = 0; + cmd->hdr.qid = ring->qid; + + tx = (iwp_tx_cmd_t *)cmd->data; + tx->tx_flags = 0; + + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { + tx->tx_flags &= ~(LE_32(TX_CMD_FLG_ACK_MSK)); + } else { + tx->tx_flags |= LE_32(TX_CMD_FLG_ACK_MSK); + } + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ic, m); + if (NULL == k) { + freemsg(m); + sc->sc_tx_err++; + + mutex_enter(&sc->sc_tx_lock); + ring->queued--; + if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { + sc->sc_need_reschedule = 0; + mutex_exit(&sc->sc_tx_lock); + mac_tx_update(ic->ic_mach); + mutex_enter(&sc->sc_tx_lock); + } + mutex_exit(&sc->sc_tx_lock); + + err = IWP_SUCCESS; + goto exit; + } + + /* packet header may have moved, reset our local pointer */ + wh = (struct ieee80211_frame *)m->b_rptr; + } + + len = msgdsize(m); + +#ifdef DEBUG + if (iwp_dbg_flags & IWP_DEBUG_TX) { + ieee80211_dump_pkt((uint8_t *)wh, hdrlen, 0, 0); + } +#endif + + tx->rts_retry_limit = IWP_TX_RTS_RETRY_LIMIT; + tx->data_retry_limit = IWP_TX_DATA_RETRY_LIMIT; + + /* + * specific TX parameters for management frames + */ + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == + IEEE80211_FC0_TYPE_MGT) { + /* + * mgmt frames are sent at 1M + */ + if ((in->in_rates.ir_rates[0] & + IEEE80211_RATE_VAL) != 0) { + rate = in->in_rates.ir_rates[0] & IEEE80211_RATE_VAL; + } else { + rate = 2; + } + + tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK); + + /* + * tell h/w to set timestamp in probe responses + */ + if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_PROBE_RESP) { + tx->tx_flags |= LE_32(TX_CMD_FLG_TSF_MSK); + + tx->data_retry_limit = 3; + if (tx->data_retry_limit < tx->rts_retry_limit) { + tx->rts_retry_limit = tx->data_retry_limit; + } + } + + if (((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_ASSOC_REQ) || + ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_REASSOC_REQ)) { + tx->timeout.pm_frame_timeout = LE_16(3); + } else { + tx->timeout.pm_frame_timeout = LE_16(2); + } + + } else { + /* + * do it here for the software way rate scaling. + * later for rate scaling in hardware. + * + * now the txrate is determined in tx cmd flags, set to the + * max value 54M for 11g and 11M for 11b originally. + */ + if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { + rate = ic->ic_fixed_rate; + } else { + if ((in->in_rates.ir_rates[in->in_txrate] & + IEEE80211_RATE_VAL) != 0) { + rate = in->in_rates. + ir_rates[in->in_txrate] & + IEEE80211_RATE_VAL; + } + } + + tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK); + + tx->timeout.pm_frame_timeout = 0; + } + + IWP_DBG((IWP_DEBUG_TX, "iwp_send(): " + "tx rate[%d of %d] = %x", + in->in_txrate, in->in_rates.ir_nrates, rate)); + + len0 = roundup(4 + sizeof (iwp_tx_cmd_t) + hdrlen, 4); + if (len0 != (4 + sizeof (iwp_tx_cmd_t) + hdrlen)) { + tx->tx_flags |= LE_32(TX_CMD_FLG_MH_PAD_MSK); + } + + /* + * retrieve destination node's id + */ + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { + tx->sta_id = IWP_BROADCAST_ID; + } else { + tx->sta_id = IWP_AP_ID; + } + + if (2 == rate || 4 == rate || 11 == rate || 22 == rate) { + masks |= RATE_MCS_CCK_MSK; + } + + masks |= RATE_MCS_ANT_B_MSK; + tx->rate.r.rate_n_flags = LE_32(iwp_rate_to_plcp(rate) | masks); + + IWP_DBG((IWP_DEBUG_TX, "iwp_send(): " + "tx flag = %x", + tx->tx_flags)); + + tx->stop_time.life_time = LE_32(0xffffffff); + + tx->len = LE_16(len); + + tx->dram_lsb_ptr = + LE_32(data->paddr_cmd + 4 + offsetof(iwp_tx_cmd_t, scratch)); + tx->dram_msb_ptr = 0; + tx->driver_txop = 0; + tx->next_frame_len = 0; + + (void) memcpy(tx + 1, m->b_rptr, hdrlen); + m->b_rptr += hdrlen; + (void) memcpy(data->dma_data.mem_va, m->b_rptr, len - hdrlen); + + IWP_DBG((IWP_DEBUG_TX, "iwp_send(): " + "sending data: qid=%d idx=%d len=%d", + ring->qid, ring->cur, len)); + + /* + * first segment includes the tx cmd plus the 802.11 header, + * the second includes the remaining of the 802.11 frame. + */ + mutex_enter(&sc->sc_tx_lock); + + cmd->hdr.idx = ring->desc_cur; + + desc_data = &ring->data[ring->desc_cur]; + desc = desc_data->desc; + bzero(desc, sizeof (*desc)); + desc->val0 = 2 << 24; + desc->pa[0].tb1_addr = data->paddr_cmd; + desc->pa[0].val1 = ((len0 << 4) & 0xfff0) | + ((data->dma_data.cookie.dmac_address & 0xffff) << 16); + desc->pa[0].val2 = + ((data->dma_data.cookie.dmac_address & 0xffff0000) >> 16) | + ((len - hdrlen) << 20); + IWP_DBG((IWP_DEBUG_TX, "iwp_send(): " + "phy addr1 = 0x%x phy addr2 = 0x%x " + "len1 = 0x%x, len2 = 0x%x val1 = 0x%x val2 = 0x%x", + data->paddr_cmd, data->dma_data.cookie.dmac_address, + len0, len - hdrlen, desc->pa[0].val1, desc->pa[0].val2)); + + /* + * kick ring + */ + s_id = tx->sta_id; + + sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. + tfd_offset[ring->desc_cur].val = + (8 + len) | (s_id << 12); + if (ring->desc_cur < IWP_MAX_WIN_SIZE) { + sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. + tfd_offset[IWP_QUEUE_SIZE + ring->desc_cur].val = + (8 + len) | (s_id << 12); + } + + IWP_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV); + IWP_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); + + ring->desc_cur = (ring->desc_cur + 1) % ring->count; + IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur); + + mutex_exit(&sc->sc_tx_lock); + freemsg(m); + + /* + * release node reference + */ + ieee80211_free_node(in); + + ic->ic_stats.is_tx_bytes += len; + ic->ic_stats.is_tx_frags++; + + mutex_enter(&sc->sc_mt_lock); + if (0 == sc->sc_tx_timer) { + sc->sc_tx_timer = 4; + } + mutex_exit(&sc->sc_mt_lock); + +exit: + return (err); +} + +/* + * invoked by GLD to deal with IOCTL affaires + */ +static void +iwp_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int err = EINVAL; + + if (NULL == arg) { + return; + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + err = ieee80211_ioctl(ic, wq, mp); + if (ENETRESET == err) { + /* + * This is special for the hidden AP connection. + * In any case, we should make sure only one 'scan' + * in the driver for a 'connect' CLI command. So + * when connecting to a hidden AP, the scan is just + * sent out to the air when we know the desired + * essid of the AP we want to connect. + */ + if (ic->ic_des_esslen) { + if (sc->sc_flags & IWP_F_RUNNING) { + iwp_m_stop(sc); + (void) iwp_m_start(sc); + (void) ieee80211_new_state(ic, + IEEE80211_S_SCAN, -1); + } + } + } +} + +/* + * Call back functions for get/set proporty + */ +static int +iwp_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, + uint_t pr_flags, uint_t wldp_length, void *wldp_buf, uint_t *perm) +{ + iwp_sc_t *sc; + int err = EINVAL; + + if (NULL == arg) { + return (EINVAL); + } + sc = (iwp_sc_t *)arg; + + err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num, + pr_flags, wldp_length, wldp_buf, perm); + + return (err); +} + +static int +iwp_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, + uint_t wldp_length, const void *wldp_buf) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int err = EINVAL; + + if (NULL == arg) { + return (EINVAL); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length, + wldp_buf); + + if (err == ENETRESET) { + if (ic->ic_des_esslen) { + if (sc->sc_flags & IWP_F_RUNNING) { + iwp_m_stop(sc); + (void) iwp_m_start(sc); + (void) ieee80211_new_state(ic, + IEEE80211_S_SCAN, -1); + } + } + err = 0; + } + return (err); +} + +/* + * invoked by GLD supply statistics NIC and driver + */ +static int +iwp_m_stat(void *arg, uint_t stat, uint64_t *val) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + ieee80211_node_t *in; + + if (NULL == arg) { + return (EINVAL); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + mutex_enter(&sc->sc_glock); + + switch (stat) { + case MAC_STAT_IFSPEED: + in = ic->ic_bss; + *val = ((IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) ? + IEEE80211_RATE(in->in_txrate) : + ic->ic_fixed_rate) / 2 * 1000000; + break; + case MAC_STAT_NOXMTBUF: + *val = sc->sc_tx_nobuf; + break; + case MAC_STAT_NORCVBUF: + *val = sc->sc_rx_nobuf; + break; + case MAC_STAT_IERRORS: + *val = sc->sc_rx_err; + break; + case MAC_STAT_RBYTES: + *val = ic->ic_stats.is_rx_bytes; + break; + case MAC_STAT_IPACKETS: + *val = ic->ic_stats.is_rx_frags; + break; + case MAC_STAT_OBYTES: + *val = ic->ic_stats.is_tx_bytes; + break; + case MAC_STAT_OPACKETS: + *val = ic->ic_stats.is_tx_frags; + break; + case MAC_STAT_OERRORS: + case WIFI_STAT_TX_FAILED: + *val = sc->sc_tx_err; + break; + case WIFI_STAT_TX_RETRANS: + *val = sc->sc_tx_retries; + break; + case WIFI_STAT_FCS_ERRORS: + case WIFI_STAT_WEP_ERRORS: + case WIFI_STAT_TX_FRAGS: + case WIFI_STAT_MCAST_TX: + case WIFI_STAT_RTS_SUCCESS: + case WIFI_STAT_RTS_FAILURE: + case WIFI_STAT_ACK_FAILURE: + case WIFI_STAT_RX_FRAGS: + case WIFI_STAT_MCAST_RX: + case WIFI_STAT_RX_DUPS: + mutex_exit(&sc->sc_glock); + return (ieee80211_stat(ic, stat, val)); + default: + mutex_exit(&sc->sc_glock); + return (ENOTSUP); + } + + mutex_exit(&sc->sc_glock); + + return (IWP_SUCCESS); + +} + +/* + * invoked by GLD to start or open NIC + */ +static int +iwp_m_start(void *arg) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int err = IWP_FAIL; + + if (NULL == arg) { + return (EINVAL); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + err = iwp_init(sc); + if (err != IWP_SUCCESS) { + /* + * The hw init err(eg. RF is OFF). Return Success to make + * the 'plumb' succeed. The iwp_thread() tries to re-init + * background. + */ + atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); + return (IWP_SUCCESS); + } + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + + atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); + + return (IWP_SUCCESS); +} + +/* + * invoked by GLD to stop or down NIC + */ +static void +iwp_m_stop(void *arg) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + + if (NULL == arg) { + return; + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + iwp_stop(sc); + + /* + * release buffer for calibration + */ + iwp_release_calib_buffer(sc); + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + + atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); + atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); + + atomic_and_32(&sc->sc_flags, ~IWP_F_RUNNING); + atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); +} + +/* + * invoked by GLD to configure NIC + */ +static int +iwp_m_unicst(void *arg, const uint8_t *macaddr) +{ + iwp_sc_t *sc; + ieee80211com_t *ic; + int err = IWP_SUCCESS; + + if (NULL == arg) { + return (EINVAL); + } + sc = (iwp_sc_t *)arg; + ic = &sc->sc_ic; + + if (!IEEE80211_ADDR_EQ(ic->ic_macaddr, macaddr)) { + IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); + mutex_enter(&sc->sc_glock); + err = iwp_config(sc); + mutex_exit(&sc->sc_glock); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_m_unicst(): " + "failed to configure device\n"); + goto fail; + } + } + + return (err); + +fail: + return (err); +} + +/* ARGSUSED */ +static int +iwp_m_multicst(void *arg, boolean_t add, const uint8_t *m) +{ + return (IWP_SUCCESS); +} + +/* ARGSUSED */ +static int +iwp_m_promisc(void *arg, boolean_t on) +{ + return (IWP_SUCCESS); +} + +/* + * kernel thread to deal with exceptional situation + */ +static void +iwp_thread(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + clock_t clk; + int err, n = 0, timeout = 0; + uint32_t tmp; +#ifdef DEBUG + int times = 0; +#endif + + while (sc->sc_mf_thread_switch) { + tmp = IWP_READ(sc, CSR_GP_CNTRL); + if (tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) { + atomic_and_32(&sc->sc_flags, ~IWP_F_RADIO_OFF); + } else { + atomic_or_32(&sc->sc_flags, IWP_F_RADIO_OFF); + } + + /* + * If in SUSPEND or the RF is OFF, do nothing. + */ + if (sc->sc_flags & IWP_F_RADIO_OFF) { + delay(drv_usectohz(100000)); + continue; + } + + /* + * recovery fatal error + */ + if (ic->ic_mach && + (sc->sc_flags & IWP_F_HW_ERR_RECOVER)) { + + IWP_DBG((IWP_DEBUG_FW, "iwp_thread(): " + "try to recover fatal hw error: %d\n", times++)); + + iwp_stop(sc); + + if (IWP_CHK_FAST_RECOVER(sc)) { + /* save runtime configuration */ + bcopy(&sc->sc_config, &sc->sc_config_save, + sizeof (sc->sc_config)); + } else { + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + delay(drv_usectohz(2000000 + n*500000)); + } + + err = iwp_init(sc); + if (err != IWP_SUCCESS) { + n++; + if (n < 20) { + continue; + } + } + + n = 0; + if (!err) { + atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); + } + + + if (!IWP_CHK_FAST_RECOVER(sc) || + iwp_fast_recover(sc) != IWP_SUCCESS) { + atomic_and_32(&sc->sc_flags, + ~IWP_F_HW_ERR_RECOVER); + + delay(drv_usectohz(2000000)); + if (sc->sc_ostate != IEEE80211_S_INIT) { + ieee80211_new_state(ic, + IEEE80211_S_SCAN, 0); + } + } + } + + if (ic->ic_mach && + (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) { + IWP_DBG((IWP_DEBUG_SCAN, "iwp_thread(): " + "wait for probe response\n")); + + sc->sc_scan_pending--; + delay(drv_usectohz(200000)); + ieee80211_next_scan(ic); + } + + /* + * rate ctl + */ + if (ic->ic_mach && + (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) { + clk = ddi_get_lbolt(); + if (clk > sc->sc_clk + drv_usectohz(1000000)) { + iwp_amrr_timeout(sc); + } + } + + delay(drv_usectohz(100000)); + + mutex_enter(&sc->sc_mt_lock); + if (sc->sc_tx_timer) { + timeout++; + if (10 == timeout) { + sc->sc_tx_timer--; + if (0 == sc->sc_tx_timer) { + atomic_or_32(&sc->sc_flags, + IWP_F_HW_ERR_RECOVER); + sc->sc_ostate = IEEE80211_S_RUN; + IWP_DBG((IWP_DEBUG_FW, "iwp_thread(): " + "try to recover from " + "send fail\n")); + } + timeout = 0; + } + } + mutex_exit(&sc->sc_mt_lock); + } + + mutex_enter(&sc->sc_mt_lock); + sc->sc_mf_thread = NULL; + cv_signal(&sc->sc_mt_cv); + mutex_exit(&sc->sc_mt_lock); +} + + +/* + * Send a command to the ucode. + */ +static int +iwp_cmd(iwp_sc_t *sc, int code, const void *buf, int size, int async) +{ + iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; + iwp_tx_desc_t *desc; + iwp_cmd_t *cmd; + + ASSERT(size <= sizeof (cmd->data)); + ASSERT(mutex_owned(&sc->sc_glock)); + + IWP_DBG((IWP_DEBUG_CMD, "iwp_cmd() " + "code[%d]", code)); + desc = ring->data[ring->cur].desc; + cmd = ring->data[ring->cur].cmd; + + cmd->hdr.type = (uint8_t)code; + cmd->hdr.flags = 0; + cmd->hdr.qid = ring->qid; + cmd->hdr.idx = ring->cur; + (void) memcpy(cmd->data, buf, size); + (void) memset(desc, 0, sizeof (*desc)); + + desc->val0 = 1 << 24; + desc->pa[0].tb1_addr = + (uint32_t)(ring->data[ring->cur].paddr_cmd & 0xffffffff); + desc->pa[0].val1 = ((4 + size) << 4) & 0xfff0; + + if (async) { + sc->sc_cmd_accum++; + } + + /* + * kick cmd ring XXX + */ + sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. + tfd_offset[ring->cur].val = 8; + if (ring->cur < IWP_MAX_WIN_SIZE) { + sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. + tfd_offset[IWP_QUEUE_SIZE + ring->cur].val = 8; + } + ring->cur = (ring->cur + 1) % ring->count; + IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); + + if (async) { + return (IWP_SUCCESS); + } else { + clock_t clk; + + clk = ddi_get_lbolt() + drv_usectohz(2000000); + while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) { + if (cv_timedwait(&sc->sc_cmd_cv, + &sc->sc_glock, clk) < 0) { + break; + } + } + + if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) { + sc->sc_cmd_flag = SC_CMD_FLG_NONE; + return (IWP_SUCCESS); + } else { + sc->sc_cmd_flag = SC_CMD_FLG_NONE; + return (IWP_FAIL); + } + } +} + +/* + * require ucode seting led of NIC + */ +static void +iwp_set_led(iwp_sc_t *sc, uint8_t id, uint8_t off, uint8_t on) +{ + iwp_led_cmd_t led; + + led.interval = LE_32(100000); /* unit: 100ms */ + led.id = id; + led.off = off; + led.on = on; + + (void) iwp_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1); +} + +/* + * necessary setting to NIC before authentication + */ +static int +iwp_hw_set_before_auth(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + ieee80211_node_t *in = ic->ic_bss; + int err = IWP_FAIL; + + /* + * update adapter's configuration according + * the info of target AP + */ + IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid); + sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan)); + + sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0; + sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0; + sc->sc_config.ofdm_ht_single_stream_basic_rates = 0; + + if (IEEE80211_MODE_11B == ic->ic_curmode) { + sc->sc_config.cck_basic_rates = 0x03; + sc->sc_config.ofdm_basic_rates = 0; + } else if ((in->in_chan != IEEE80211_CHAN_ANYC) && + (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) { + sc->sc_config.cck_basic_rates = 0; + sc->sc_config.ofdm_basic_rates = 0x15; + } else { /* assume 802.11b/g */ + sc->sc_config.cck_basic_rates = 0x0f; + sc->sc_config.ofdm_basic_rates = 0xff; + } + + sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK | + RXON_FLG_SHORT_SLOT_MSK); + + if (ic->ic_flags & IEEE80211_F_SHSLOT) { + sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK); + } else { + sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK); + } + + if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) { + sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); + } else { + sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK); + } + + IWP_DBG((IWP_DEBUG_80211, "iwp_hw_set_before_auth(): " + "config chan %d flags %x " + "filter_flags %x cck %x ofdm %x" + " bssid:%02x:%02x:%02x:%02x:%02x:%2x\n", + LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags), + LE_32(sc->sc_config.filter_flags), + sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates, + sc->sc_config.bssid[0], sc->sc_config.bssid[1], + sc->sc_config.bssid[2], sc->sc_config.bssid[3], + sc->sc_config.bssid[4], sc->sc_config.bssid[5])); + + err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, + sizeof (iwp_rxon_cmd_t), 1); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_hw_set_before_auth(): " + "failed to config chan%d\n", sc->sc_config.chan); + return (err); + } + + /* + * add default AP node + */ + err = iwp_add_ap_sta(sc); + if (err != IWP_SUCCESS) { + return (err); + } + + + return (err); +} + +/* + * Send a scan request(assembly scan cmd) to the firmware. + */ +static int +iwp_scan(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; + iwp_tx_desc_t *desc; + iwp_tx_data_t *data; + iwp_cmd_t *cmd; + iwp_scan_hdr_t *hdr; + iwp_scan_chan_t chan; + struct ieee80211_frame *wh; + ieee80211_node_t *in = ic->ic_bss; + uint8_t essid[IEEE80211_NWID_LEN+1]; + struct ieee80211_rateset *rs; + enum ieee80211_phymode mode; + uint8_t *frm; + int i, pktlen, nrates; + + data = &ring->data[ring->cur]; + desc = data->desc; + cmd = (iwp_cmd_t *)data->dma_data.mem_va; + + cmd->hdr.type = REPLY_SCAN_CMD; + cmd->hdr.flags = 0; + cmd->hdr.qid = ring->qid; + cmd->hdr.idx = ring->cur | 0x40; + + hdr = (iwp_scan_hdr_t *)cmd->data; + (void) memset(hdr, 0, sizeof (iwp_scan_hdr_t)); + hdr->nchan = 1; + hdr->quiet_time = LE_16(50); + hdr->quiet_plcp_th = LE_16(1); + + hdr->flags = LE_32(RXON_FLG_BAND_24G_MSK); + hdr->rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK | + (0x7 << RXON_RX_CHAIN_VALID_POS) | + (0x2 << RXON_RX_CHAIN_FORCE_SEL_POS) | + (0x2 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS)); + + hdr->tx_cmd.tx_flags = LE_32(TX_CMD_FLG_SEQ_CTL_MSK); + hdr->tx_cmd.sta_id = IWP_BROADCAST_ID; + hdr->tx_cmd.stop_time.life_time = LE_32(0xffffffff); + hdr->tx_cmd.rate.r.rate_n_flags = LE_32(iwp_rate_to_plcp(2)); + hdr->tx_cmd.rate.r.rate_n_flags |= + LE_32(RATE_MCS_ANT_B_MSK |RATE_MCS_CCK_MSK); + hdr->direct_scan[0].len = ic->ic_des_esslen; + hdr->direct_scan[0].id = IEEE80211_ELEMID_SSID; + + hdr->filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK | + RXON_FILTER_BCON_AWARE_MSK); + + if (ic->ic_des_esslen) { + bcopy(ic->ic_des_essid, essid, ic->ic_des_esslen); + essid[ic->ic_des_esslen] = '\0'; + IWP_DBG((IWP_DEBUG_SCAN, "iwp_scan(): " + "directed scan %s\n", essid)); + + bcopy(ic->ic_des_essid, hdr->direct_scan[0].ssid, + ic->ic_des_esslen); + } else { + bzero(hdr->direct_scan[0].ssid, + sizeof (hdr->direct_scan[0].ssid)); + } + + /* + * a probe request frame is required after the REPLY_SCAN_CMD + */ + wh = (struct ieee80211_frame *)(hdr + 1); + wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | + IEEE80211_FC0_SUBTYPE_PROBE_REQ; + wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; + (void) memset(wh->i_addr1, 0xff, 6); + IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_macaddr); + (void) memset(wh->i_addr3, 0xff, 6); + *(uint16_t *)&wh->i_dur[0] = 0; + *(uint16_t *)&wh->i_seq[0] = 0; + + frm = (uint8_t *)(wh + 1); + + /* + * essid IE + */ + if (in->in_esslen) { + bcopy(in->in_essid, essid, in->in_esslen); + essid[in->in_esslen] = '\0'; + IWP_DBG((IWP_DEBUG_SCAN, "iwp_scan(): " + "probe with ESSID %s\n", + essid)); + } + *frm++ = IEEE80211_ELEMID_SSID; + *frm++ = in->in_esslen; + (void) memcpy(frm, in->in_essid, in->in_esslen); + frm += in->in_esslen; + + mode = ieee80211_chan2mode(ic, ic->ic_curchan); + rs = &ic->ic_sup_rates[mode]; + + /* + * supported rates IE + */ + *frm++ = IEEE80211_ELEMID_RATES; + nrates = rs->ir_nrates; + if (nrates > IEEE80211_RATE_SIZE) { + nrates = IEEE80211_RATE_SIZE; + } + + *frm++ = (uint8_t)nrates; + (void) memcpy(frm, rs->ir_rates, nrates); + frm += nrates; + + /* + * supported xrates IE + */ + if (rs->ir_nrates > IEEE80211_RATE_SIZE) { + nrates = rs->ir_nrates - IEEE80211_RATE_SIZE; + *frm++ = IEEE80211_ELEMID_XRATES; + *frm++ = (uint8_t)nrates; + (void) memcpy(frm, rs->ir_rates + IEEE80211_RATE_SIZE, nrates); + frm += nrates; + } + + /* + * optionnal IE (usually for wpa) + */ + if (ic->ic_opt_ie != NULL) { + (void) memcpy(frm, ic->ic_opt_ie, ic->ic_opt_ie_len); + frm += ic->ic_opt_ie_len; + } + + /* setup length of probe request */ + hdr->tx_cmd.len = LE_16(_PTRDIFF(frm, wh)); + hdr->len = LE_16(hdr->nchan * sizeof (iwp_scan_chan_t) + + LE_16(hdr->tx_cmd.len) + sizeof (iwp_scan_hdr_t)); + + /* + * the attribute of the scan channels are required after the probe + * request frame. + */ + for (i = 1; i <= hdr->nchan; i++) { + if (ic->ic_des_esslen) { + chan.type = LE_32(3); + } else { + chan.type = LE_32(1); + } + + chan.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan)); + chan.tpc.tx_gain = 0x28; + chan.tpc.dsp_atten = 110; + chan.active_dwell = LE_16(50); + chan.passive_dwell = LE_16(120); + + bcopy(&chan, frm, sizeof (iwp_scan_chan_t)); + frm += sizeof (iwp_scan_chan_t); + } + + pktlen = _PTRDIFF(frm, cmd); + + (void) memset(desc, 0, sizeof (*desc)); + desc->val0 = 1 << 24; + desc->pa[0].tb1_addr = + (uint32_t)(data->dma_data.cookie.dmac_address & 0xffffffff); + desc->pa[0].val1 = (pktlen << 4) & 0xfff0; + + /* + * maybe for cmd, filling the byte cnt table is not necessary. + * anyway, we fill it here. + */ + sc->sc_shared->queues_byte_cnt_tbls[ring->qid] + .tfd_offset[ring->cur].val = 8; + if (ring->cur < IWP_MAX_WIN_SIZE) { + sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. + tfd_offset[IWP_QUEUE_SIZE + ring->cur].val = 8; + } + + /* + * kick cmd ring + */ + ring->cur = (ring->cur + 1) % ring->count; + IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); + + return (IWP_SUCCESS); +} + +/* + * configure NIC by using ucode commands after loading ucode. + */ +static int +iwp_config(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + iwp_powertable_cmd_t powertable; + iwp_bt_cmd_t bt; + iwp_add_sta_t node; + iwp_rem_sta_t rm_sta; + const uint8_t bcast[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + int err = IWP_FAIL; + + /* + * set power mode. Disable power management at present, do it later + */ + (void) memset(&powertable, 0, sizeof (powertable)); + powertable.flags = LE_16(0x8); + err = iwp_cmd(sc, POWER_TABLE_CMD, &powertable, + sizeof (powertable), 0); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_config(): " + "failed to set power mode\n"); + return (err); + } + + /* + * configure bt coexistence + */ + (void) memset(&bt, 0, sizeof (bt)); + bt.flags = 3; + bt.lead_time = 0xaa; + bt.max_kill = 1; + err = iwp_cmd(sc, REPLY_BT_CONFIG, &bt, + sizeof (bt), 0); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_config(): " + "failed to configurate bt coexistence\n"); + return (err); + } + + /* + * configure rxon + */ + (void) memset(&sc->sc_config, 0, sizeof (iwp_rxon_cmd_t)); + IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr); + IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr); + sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan)); + sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK); + sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | + RXON_FLG_CHANNEL_MODE_PURE_40_MSK)); + + switch (ic->ic_opmode) { + case IEEE80211_M_STA: + sc->sc_config.dev_type = RXON_DEV_TYPE_ESS; + sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | + RXON_FILTER_DIS_DECRYPT_MSK | + RXON_FILTER_DIS_GRP_DECRYPT_MSK); + break; + case IEEE80211_M_IBSS: + case IEEE80211_M_AHDEMO: + sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS; + + sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); + sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK | + RXON_FILTER_DIS_DECRYPT_MSK | + RXON_FILTER_DIS_GRP_DECRYPT_MSK); + break; + case IEEE80211_M_HOSTAP: + sc->sc_config.dev_type = RXON_DEV_TYPE_AP; + break; + case IEEE80211_M_MONITOR: + sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER; + sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | + RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); + break; + } + + /* + * Support all CCK rates. + */ + sc->sc_config.cck_basic_rates = 0x0f; + + /* + * Support all OFDM rates. + */ + sc->sc_config.ofdm_basic_rates = 0xff; + + sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK | + (0x7 << RXON_RX_CHAIN_VALID_POS) | + (0x2 << RXON_RX_CHAIN_FORCE_SEL_POS) | + (0x2 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS)); + + err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, + sizeof (iwp_rxon_cmd_t), 0); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_config(): " + "failed to set configure command\n"); + return (err); + } + + /* + * remove all nodes in NIC + */ + (void) memset(&rm_sta, 0, sizeof (rm_sta)); + rm_sta.num_sta = 1; + (void) memcpy(rm_sta.addr, bcast, 6); + + err = iwp_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwp_rem_sta_t), 0); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_config(): " + "failed to remove broadcast node in hardware.\n"); + return (err); + } + + /* + * add broadcast node so that we can send broadcast frame + */ + (void) memset(&node, 0, sizeof (node)); + (void) memset(node.sta.addr, 0xff, 6); + node.mode = 0; + node.sta.sta_id = IWP_BROADCAST_ID; + node.station_flags = 0; + + err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_config(): " + "failed to add broadcast node\n"); + return (err); + } + + return (err); +} + +/* + * quiesce(9E) entry point. + * This function is called when the system is single-threaded at high + * PIL with preemption disabled. Therefore, this function must not be + * blocked. + * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. + * DDI_FAILURE indicates an error condition and should almost never happen. + */ +static int +iwp_quiesce(dev_info_t *dip) +{ + iwp_sc_t *sc; + + sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); + if (NULL == sc) { + return (DDI_FAILURE); + } + +#ifdef DEBUG + /* by pass any messages, if it's quiesce */ + iwp_dbg_flags = 0; +#endif + + /* + * No more blocking is allowed while we are in the + * quiesce(9E) entry point. + */ + atomic_or_32(&sc->sc_flags, IWP_F_QUIESCED); + + /* + * Disable and mask all interrupts. + */ + iwp_stop(sc); + + return (DDI_SUCCESS); +} + +static void +iwp_stop_master(iwp_sc_t *sc) +{ + uint32_t tmp; + int n; + + tmp = IWP_READ(sc, CSR_RESET); + IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER); + + tmp = IWP_READ(sc, CSR_GP_CNTRL); + if ((tmp & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE) == + CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE) { + return; + } + + for (n = 0; n < 2000; n++) { + if (IWP_READ(sc, CSR_RESET) & + CSR_RESET_REG_FLAG_MASTER_DISABLED) { + break; + } + DELAY(1000); + } + +#ifdef DEBUG + if (2000 == n) { + IWP_DBG((IWP_DEBUG_HW, "iwp_stop_master(): " + "timeout waiting for master stop\n")); + } +#endif +} + +static int +iwp_power_up(iwp_sc_t *sc) +{ + uint32_t tmp; + + iwp_mac_access_enter(sc); + tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); + tmp &= ~APMG_PS_CTRL_REG_MSK_POWER_SRC; + tmp |= APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN; + iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); + iwp_mac_access_exit(sc); + + DELAY(5000); + return (IWP_SUCCESS); +} + +/* + * hardware initialization + */ +static int +iwp_preinit(iwp_sc_t *sc) +{ + int n; + uint8_t vlink; + uint16_t radio_cfg; + uint32_t tmp; + + /* + * clear any pending interrupts + */ + IWP_WRITE(sc, CSR_INT, 0xffffffff); + + tmp = IWP_READ(sc, CSR_GIO_CHICKEN_BITS); + IWP_WRITE(sc, CSR_GIO_CHICKEN_BITS, + tmp | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); + + tmp = IWP_READ(sc, CSR_GP_CNTRL); + IWP_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + + /* + * wait for clock ready + */ + for (n = 0; n < 1000; n++) { + if (IWP_READ(sc, CSR_GP_CNTRL) & + CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) { + break; + } + DELAY(10); + } + + if (1000 == n) { + return (ETIMEDOUT); + } + + iwp_mac_access_enter(sc); + + iwp_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT); + + DELAY(20); + tmp = iwp_reg_read(sc, ALM_APMG_PCIDEV_STT); + iwp_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp | + APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE); + iwp_mac_access_exit(sc); + + radio_cfg = IWP_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION); + if (SP_RADIO_TYPE_MSK(radio_cfg) < SP_RADIO_TYPE_MAX) { + tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); + IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, + tmp | SP_RADIO_TYPE_MSK(radio_cfg) | + SP_RADIO_STEP_MSK(radio_cfg) | + SP_RADIO_DASH_MSK(radio_cfg)); + } else { + cmn_err(CE_WARN, "iwp_preinit(): " + "radio configuration information in eeprom is wrong\n"); + return (IWP_FAIL); + } + + + IWP_WRITE(sc, CSR_INT_COALESCING, 512 / 32); + + (void) iwp_power_up(sc); + + if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) { + tmp = ddi_get32(sc->sc_cfg_handle, + (uint32_t *)(sc->sc_cfg_base + 0xe8)); + ddi_put32(sc->sc_cfg_handle, + (uint32_t *)(sc->sc_cfg_base + 0xe8), + tmp & ~(1 << 11)); + } + + vlink = ddi_get8(sc->sc_cfg_handle, + (uint8_t *)(sc->sc_cfg_base + 0xf0)); + ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), + vlink & ~2); + + tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); + tmp |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | + CSR_HW_IF_CONFIG_REG_BIT_MAC_SI; + IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, tmp); + + /* + * make sure power supply on each part of the hardware + */ + iwp_mac_access_enter(sc); + tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); + tmp |= APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ; + iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); + DELAY(5); + + tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); + tmp &= ~APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ; + iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); + iwp_mac_access_exit(sc); + + if (PA_TYPE_MIX == sc->sc_chip_param.pa_type) { + IWP_WRITE(sc, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_MIX); + } + + if (PA_TYPE_INTER == sc->sc_chip_param.pa_type) { + + IWP_WRITE(sc, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); + } + + return (IWP_SUCCESS); +} + +/* + * set up semphore flag to own EEPROM + */ +static int +iwp_eep_sem_down(iwp_sc_t *sc) +{ + int count1, count2; + uint32_t tmp; + + for (count1 = 0; count1 < 1000; count1++) { + tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); + IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, + tmp | CSR_HW_IF_CONFIG_REG_EEP_SEM); + + for (count2 = 0; count2 < 2; count2++) { + if (IWP_READ(sc, CSR_HW_IF_CONFIG_REG) & + CSR_HW_IF_CONFIG_REG_EEP_SEM) { + return (IWP_SUCCESS); + } + DELAY(10000); + } + } + return (IWP_FAIL); +} + +/* + * reset semphore flag to release EEPROM + */ +static void +iwp_eep_sem_up(iwp_sc_t *sc) +{ + uint32_t tmp; + + tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); + IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, + tmp & (~CSR_HW_IF_CONFIG_REG_EEP_SEM)); +} + +/* + * This function read all infomation from eeprom + */ +static int +iwp_eep_load(iwp_sc_t *sc) +{ + int i, rr; + uint32_t rv, tmp, eep_gp; + uint16_t addr, eep_sz = sizeof (sc->sc_eep_map); + uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map; + + /* + * read eeprom gp register in CSR + */ + eep_gp = IWP_READ(sc, CSR_EEPROM_GP); + if ((eep_gp & CSR_EEPROM_GP_VALID_MSK) == + CSR_EEPROM_GP_BAD_SIGNATURE) { + IWP_DBG((IWP_DEBUG_EEPROM, "iwp_eep_load(): " + "not find eeprom\n")); + return (IWP_FAIL); + } + + rr = iwp_eep_sem_down(sc); + if (rr != 0) { + IWP_DBG((IWP_DEBUG_EEPROM, "iwp_eep_load(): " + "driver failed to own EEPROM\n")); + return (IWP_FAIL); + } + + for (addr = 0; addr < eep_sz; addr += 2) { + IWP_WRITE(sc, CSR_EEPROM_REG, addr<<1); + tmp = IWP_READ(sc, CSR_EEPROM_REG); + IWP_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2)); + + for (i = 0; i < 10; i++) { + rv = IWP_READ(sc, CSR_EEPROM_REG); + if (rv & 1) { + break; + } + DELAY(10); + } + + if (!(rv & 1)) { + IWP_DBG((IWP_DEBUG_EEPROM, "iwp_eep_load(): " + "time out when read eeprome\n")); + iwp_eep_sem_up(sc); + return (IWP_FAIL); + } + + eep_p[addr/2] = LE_16(rv >> 16); + } + + iwp_eep_sem_up(sc); + return (IWP_SUCCESS); +} + +/* + * initialize mac address in ieee80211com_t struct + */ +static void +iwp_get_mac_from_eep(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + + IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]); + + IWP_DBG((IWP_DEBUG_EEPROM, "iwp_get_mac_from_eep(): " + "mac:%2x:%2x:%2x:%2x:%2x:%2x\n", + ic->ic_macaddr[0], ic->ic_macaddr[1], ic->ic_macaddr[2], + ic->ic_macaddr[3], ic->ic_macaddr[4], ic->ic_macaddr[5])); +} + +/* + * main initialization function + */ +static int +iwp_init(iwp_sc_t *sc) +{ + int err = IWP_FAIL; + clock_t clk; + + /* + * release buffer for calibration + */ + iwp_release_calib_buffer(sc); + + mutex_enter(&sc->sc_glock); + atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); + + err = iwp_init_common(sc); + if (err != IWP_SUCCESS) { + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + /* + * backup ucode data part for future use. + */ + (void) memcpy(sc->sc_dma_fw_data_bak.mem_va, + sc->sc_dma_fw_data.mem_va, + sc->sc_dma_fw_data.alength); + + /* load firmware init segment into NIC */ + err = iwp_load_init_firmware(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_init(): " + "failed to setup init firmware\n"); + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + /* + * now press "execute" start running + */ + IWP_WRITE(sc, CSR_RESET, 0); + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + while (!(sc->sc_flags & IWP_F_FW_INIT)) { + if (cv_timedwait(&sc->sc_ucode_cv, + &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_FW_INIT)) { + cmn_err(CE_WARN, "iwp_init(): " + "failed to process init alive.\n"); + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + mutex_exit(&sc->sc_glock); + + /* + * stop chipset for initializing chipset again + */ + iwp_stop(sc); + + mutex_enter(&sc->sc_glock); + atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); + + err = iwp_init_common(sc); + if (err != IWP_SUCCESS) { + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + /* + * load firmware run segment into NIC + */ + err = iwp_load_run_firmware(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_init(): " + "failed to setup run firmware\n"); + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + /* + * now press "execute" start running + */ + IWP_WRITE(sc, CSR_RESET, 0); + + clk = ddi_get_lbolt() + drv_usectohz(1000000); + while (!(sc->sc_flags & IWP_F_FW_INIT)) { + if (cv_timedwait(&sc->sc_ucode_cv, + &sc->sc_glock, clk) < 0) { + break; + } + } + + if (!(sc->sc_flags & IWP_F_FW_INIT)) { + cmn_err(CE_WARN, "iwp_init(): " + "failed to process runtime alive.\n"); + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + mutex_exit(&sc->sc_glock); + + DELAY(1000); + + mutex_enter(&sc->sc_glock); + atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); + + /* + * at this point, the firmware is loaded OK, then config the hardware + * with the ucode API, including rxon, txpower, etc. + */ + err = iwp_config(sc); + if (err) { + cmn_err(CE_WARN, "iwp_init(): " + "failed to configure device\n"); + mutex_exit(&sc->sc_glock); + return (IWP_FAIL); + } + + /* + * at this point, hardware may receive beacons :) + */ + mutex_exit(&sc->sc_glock); + return (IWP_SUCCESS); +} + +/* + * stop or disable NIC + */ +static void +iwp_stop(iwp_sc_t *sc) +{ + uint32_t tmp; + int i; + + /* by pass if it's quiesced */ + if (!(sc->sc_flags & IWP_F_QUIESCED)) { + mutex_enter(&sc->sc_glock); + } + + IWP_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); + /* + * disable interrupts + */ + IWP_WRITE(sc, CSR_INT_MASK, 0); + IWP_WRITE(sc, CSR_INT, CSR_INI_SET_MASK); + IWP_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff); + + /* + * reset all Tx rings + */ + for (i = 0; i < IWP_NUM_QUEUES; i++) { + iwp_reset_tx_ring(sc, &sc->sc_txq[i]); + } + + /* + * reset Rx ring + */ + iwp_reset_rx_ring(sc); + + iwp_mac_access_enter(sc); + iwp_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT); + iwp_mac_access_exit(sc); + + DELAY(5); + + iwp_stop_master(sc); + + mutex_enter(&sc->sc_mt_lock); + sc->sc_tx_timer = 0; + mutex_exit(&sc->sc_mt_lock); + + tmp = IWP_READ(sc, CSR_RESET); + IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET); + + /* by pass if it's quiesced */ + if (!(sc->sc_flags & IWP_F_QUIESCED)) { + mutex_exit(&sc->sc_glock); + } +} + +/* + * Naive implementation of the Adaptive Multi Rate Retry algorithm: + * "IEEE 802.11 Rate Adaptation: A Practical Approach" + * Mathieu Lacage, Hossein Manshaei, Thierry Turletti + * INRIA Sophia - Projet Planete + * http://www-sop.inria.fr/rapports/sophia/RR-5208.html + */ +#define is_success(amrr) \ + ((amrr)->retrycnt < (amrr)->txcnt / 10) +#define is_failure(amrr) \ + ((amrr)->retrycnt > (amrr)->txcnt / 3) +#define is_enough(amrr) \ + ((amrr)->txcnt > 200) +#define not_very_few(amrr) \ + ((amrr)->txcnt > 40) +#define is_min_rate(in) \ + (0 == (in)->in_txrate) +#define is_max_rate(in) \ + ((in)->in_rates.ir_nrates - 1 == (in)->in_txrate) +#define increase_rate(in) \ + ((in)->in_txrate++) +#define decrease_rate(in) \ + ((in)->in_txrate--) +#define reset_cnt(amrr) \ + { (amrr)->txcnt = (amrr)->retrycnt = 0; } + +#define IWP_AMRR_MIN_SUCCESS_THRESHOLD 1 +#define IWP_AMRR_MAX_SUCCESS_THRESHOLD 15 + +static void +iwp_amrr_init(iwp_amrr_t *amrr) +{ + amrr->success = 0; + amrr->recovery = 0; + amrr->txcnt = amrr->retrycnt = 0; + amrr->success_threshold = IWP_AMRR_MIN_SUCCESS_THRESHOLD; +} + +static void +iwp_amrr_timeout(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + + IWP_DBG((IWP_DEBUG_RATECTL, "iwp_amrr_timeout(): " + "enter\n")); + + if (IEEE80211_M_STA == ic->ic_opmode) { + iwp_amrr_ratectl(NULL, ic->ic_bss); + } else { + ieee80211_iterate_nodes(&ic->ic_sta, iwp_amrr_ratectl, NULL); + } + + sc->sc_clk = ddi_get_lbolt(); +} + +/* ARGSUSED */ +static void +iwp_amrr_ratectl(void *arg, ieee80211_node_t *in) +{ + iwp_amrr_t *amrr = (iwp_amrr_t *)in; + int need_change = 0; + + if (is_success(amrr) && is_enough(amrr)) { + amrr->success++; + if (amrr->success >= amrr->success_threshold && + !is_max_rate(in)) { + amrr->recovery = 1; + amrr->success = 0; + increase_rate(in); + IWP_DBG((IWP_DEBUG_RATECTL, "iwp_amrr_ratectl(): " + "AMRR increasing rate %d " + "(txcnt=%d retrycnt=%d)\n", + in->in_txrate, amrr->txcnt, + amrr->retrycnt)); + need_change = 1; + } else { + amrr->recovery = 0; + } + } else if (not_very_few(amrr) && is_failure(amrr)) { + amrr->success = 0; + if (!is_min_rate(in)) { + if (amrr->recovery) { + amrr->success_threshold++; + if (amrr->success_threshold > + IWP_AMRR_MAX_SUCCESS_THRESHOLD) { + amrr->success_threshold = + IWP_AMRR_MAX_SUCCESS_THRESHOLD; + } + } else { + amrr->success_threshold = + IWP_AMRR_MIN_SUCCESS_THRESHOLD; + } + decrease_rate(in); + IWP_DBG((IWP_DEBUG_RATECTL, "iwp_amrr_ratectl(): " + "AMRR decreasing rate %d " + "(txcnt=%d retrycnt=%d)\n", + in->in_txrate, amrr->txcnt, + amrr->retrycnt)); + need_change = 1; + } + amrr->recovery = 0; /* paper is incorrect */ + } + + if (is_enough(amrr) || need_change) { + reset_cnt(amrr); + } +} + +/* + * translate indirect address in eeprom to direct address + * in eeprom and return address of entry whos indirect address + * is indi_addr + */ +static uint8_t * +iwp_eep_addr_trans(iwp_sc_t *sc, uint32_t indi_addr) +{ + uint32_t di_addr; + uint16_t temp; + + if (!(indi_addr & INDIRECT_ADDRESS)) { + di_addr = indi_addr; + return (&sc->sc_eep_map[di_addr]); + } + + switch (indi_addr & INDIRECT_TYPE_MSK) { + case INDIRECT_GENERAL: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_GENERAL); + break; + case INDIRECT_HOST: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_HOST); + break; + case INDIRECT_REGULATORY: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY); + break; + case INDIRECT_CALIBRATION: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION); + break; + case INDIRECT_PROCESS_ADJST: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST); + break; + case INDIRECT_OTHERS: + temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_OTHERS); + break; + default: + temp = 0; + cmn_err(CE_WARN, "iwp_eep_addr_trans(): " + "incorrect indirect eeprom address.\n"); + break; + } + + di_addr = (indi_addr & ADDRESS_MSK) + (temp << 1); + + return (&sc->sc_eep_map[di_addr]); +} + +/* + * loade a section of ucode into NIC + */ +static int +iwp_put_seg_fw(iwp_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len) +{ + + iwp_mac_access_enter(sc); + + IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), + IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); + + IWP_WRITE(sc, IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(IWP_FH_SRVC_CHNL), addr_d); + + IWP_WRITE(sc, IWP_FH_TFDIB_CTRL0_REG(IWP_FH_SRVC_CHNL), + (addr_s & FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK)); + + IWP_WRITE(sc, IWP_FH_TFDIB_CTRL1_REG(IWP_FH_SRVC_CHNL), len); + + IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(IWP_FH_SRVC_CHNL), + (1 << IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | + (1 << IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | + IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); + + IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), + IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | + IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | + IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); + + iwp_mac_access_exit(sc); + + return (IWP_SUCCESS); +} + +/* + * necessary setting during alive notification + */ +static int +iwp_alive_common(iwp_sc_t *sc) +{ + uint32_t base; + uint32_t i; + iwp_wimax_coex_cmd_t w_cmd; + iwp_calibration_crystal_cmd_t c_cmd; + uint32_t rv = IWP_FAIL; + + /* + * initialize SCD related registers to make TX work. + */ + iwp_mac_access_enter(sc); + + /* + * read sram address of data base. + */ + sc->sc_scd_base = iwp_reg_read(sc, IWP_SCD_SRAM_BASE_ADDR); + + for (base = sc->sc_scd_base + IWP_SCD_CONTEXT_DATA_OFFSET; + base < sc->sc_scd_base + IWP_SCD_TX_STTS_BITMAP_OFFSET; + base += 4) { + iwp_mem_write(sc, base, 0); + } + + for (; base < sc->sc_scd_base + IWP_SCD_TRANSLATE_TBL_OFFSET; + base += 4) { + iwp_mem_write(sc, base, 0); + } + + for (i = 0; i < sizeof (uint16_t) * IWP_NUM_QUEUES; i += 4) { + iwp_mem_write(sc, base + i, 0); + } + + iwp_reg_write(sc, IWP_SCD_DRAM_BASE_ADDR, + sc->sc_dma_sh.cookie.dmac_address >> 10); + + iwp_reg_write(sc, IWP_SCD_QUEUECHAIN_SEL, + IWP_SCD_QUEUECHAIN_SEL_ALL(IWP_NUM_QUEUES)); + + iwp_reg_write(sc, IWP_SCD_AGGR_SEL, 0); + + for (i = 0; i < IWP_NUM_QUEUES; i++) { + iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(i), 0); + IWP_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8)); + iwp_mem_write(sc, sc->sc_scd_base + + IWP_SCD_CONTEXT_QUEUE_OFFSET(i), 0); + iwp_mem_write(sc, sc->sc_scd_base + + IWP_SCD_CONTEXT_QUEUE_OFFSET(i) + + sizeof (uint32_t), + ((SCD_WIN_SIZE << IWP_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & + IWP_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | + ((SCD_FRAME_LIMIT << + IWP_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & + IWP_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); + } + + iwp_reg_write(sc, IWP_SCD_INTERRUPT_MASK, (1 << IWP_NUM_QUEUES) - 1); + + iwp_reg_write(sc, (IWP_SCD_BASE + 0x10), + SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); + + IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8)); + iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0); + + /* + * queue 0-7 map to FIFO 0-7 and + * all queues work under FIFO mode(none-scheduler_ack) + */ + for (i = 0; i < 4; i++) { + iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), + (1 << IWP_SCD_QUEUE_STTS_REG_POS_ACTIVE) | + ((3-i) << IWP_SCD_QUEUE_STTS_REG_POS_TXF) | + (1 << IWP_SCD_QUEUE_STTS_REG_POS_WSL) | + IWP_SCD_QUEUE_STTS_REG_MSK); + } + + iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM), + (1 << IWP_SCD_QUEUE_STTS_REG_POS_ACTIVE) | + (IWP_CMD_FIFO_NUM << IWP_SCD_QUEUE_STTS_REG_POS_TXF) | + (1 << IWP_SCD_QUEUE_STTS_REG_POS_WSL) | + IWP_SCD_QUEUE_STTS_REG_MSK); + + for (i = 5; i < 7; i++) { + iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), + (1 << IWP_SCD_QUEUE_STTS_REG_POS_ACTIVE) | + (i << IWP_SCD_QUEUE_STTS_REG_POS_TXF) | + (1 << IWP_SCD_QUEUE_STTS_REG_POS_WSL) | + IWP_SCD_QUEUE_STTS_REG_MSK); + } + + iwp_mac_access_exit(sc); + + (void) memset(&w_cmd, 0, sizeof (w_cmd)); + + rv = iwp_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_alive_common(): " + "failed to send wimax coexist command.\n"); + return (rv); + } + + (void) memset(&c_cmd, 0, sizeof (c_cmd)); + + c_cmd.opCode = PHY_CALIBRATE_CRYSTAL_FRQ_CMD; + c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]); + c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]); + + rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &c_cmd, sizeof (c_cmd), 1); + if (rv != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_alive_common(): " + "failed to send crystal frq calibration command.\n"); + return (rv); + } + + /* + * make sure crystal frequency calibration ready + * before next operations. + */ + DELAY(1000); + + return (IWP_SUCCESS); +} + +/* + * save results of calibration from ucode + */ +static void +iwp_save_calib_result(iwp_sc_t *sc, iwp_rx_desc_t *desc) +{ + struct iwp_calib_results *res_p = &sc->sc_calib_results; + struct iwp_calib_hdr *calib_hdr = (struct iwp_calib_hdr *)(desc + 1); + int len = LE_32(desc->len); + + /* + * ensure the size of buffer is not too big + */ + len = (len & FH_RSCSR_FRAME_SIZE_MASK) - 4; + + switch (calib_hdr->op_code) { + case PHY_CALIBRATE_LO_CMD: + if (NULL == res_p->lo_res) { + res_p->lo_res = kmem_alloc(len, KM_NOSLEEP); + } + + if (NULL == res_p->lo_res) { + cmn_err(CE_WARN, "iwp_save_calib_result(): " + "failed to allocate memory.\n"); + return; + } + + res_p->lo_res_len = len; + (void) memcpy(res_p->lo_res, calib_hdr, len); + break; + case PHY_CALIBRATE_TX_IQ_CMD: + if (NULL == res_p->tx_iq_res) { + res_p->tx_iq_res = kmem_alloc(len, KM_NOSLEEP); + } + + if (NULL == res_p->tx_iq_res) { + cmn_err(CE_WARN, "iwp_save_calib_result(): " + "failed to allocate memory.\n"); + return; + } + + res_p->tx_iq_res_len = len; + (void) memcpy(res_p->tx_iq_res, calib_hdr, len); + break; + case PHY_CALIBRATE_TX_IQ_PERD_CMD: + if (NULL == res_p->tx_iq_perd_res) { + res_p->tx_iq_perd_res = kmem_alloc(len, KM_NOSLEEP); + } + + if (NULL == res_p->tx_iq_perd_res) { + cmn_err(CE_WARN, "iwp_save_calib_result(): " + "failed to allocate memory.\n"); + } + + res_p->tx_iq_perd_res_len = len; + (void) memcpy(res_p->tx_iq_perd_res, calib_hdr, len); + break; + case PHY_CALIBRATE_BASE_BAND_CMD: + if (NULL == res_p->base_band_res) { + res_p->base_band_res = kmem_alloc(len, KM_NOSLEEP); + } + + if (NULL == res_p->base_band_res) { + cmn_err(CE_WARN, "iwp_save_calib_result(): " + "failed to allocate memory.\n"); + } + + res_p->base_band_res_len = len; + (void) memcpy(res_p->base_band_res, calib_hdr, len); + break; + default: + cmn_err(CE_WARN, "iwp_save_calib_result(): " + "incorrect calibration type(%d).\n", calib_hdr->op_code); + break; + } + +} + +static void +iwp_release_calib_buffer(iwp_sc_t *sc) +{ + if (sc->sc_calib_results.lo_res != NULL) { + kmem_free(sc->sc_calib_results.lo_res, + sc->sc_calib_results.lo_res_len); + sc->sc_calib_results.lo_res = NULL; + } + + if (sc->sc_calib_results.tx_iq_res != NULL) { + kmem_free(sc->sc_calib_results.tx_iq_res, + sc->sc_calib_results.tx_iq_res_len); + sc->sc_calib_results.tx_iq_res = NULL; + } + + if (sc->sc_calib_results.tx_iq_perd_res != NULL) { + kmem_free(sc->sc_calib_results.tx_iq_perd_res, + sc->sc_calib_results.tx_iq_perd_res_len); + sc->sc_calib_results.tx_iq_perd_res = NULL; + } + + if (sc->sc_calib_results.base_band_res != NULL) { + kmem_free(sc->sc_calib_results.base_band_res, + sc->sc_calib_results.base_band_res_len); + sc->sc_calib_results.base_band_res = NULL; + } + +} + +/* + * common section of intialization + */ +static int +iwp_init_common(iwp_sc_t *sc) +{ + int32_t qid; + uint32_t tmp; + + (void) iwp_preinit(sc); + + tmp = IWP_READ(sc, CSR_GP_CNTRL); + if (!(tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) { + cmn_err(CE_NOTE, "iwp_init_common(): " + "radio transmitter is off\n"); + return (IWP_FAIL); + } + + /* + * init Rx ring + */ + iwp_mac_access_enter(sc); + IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); + + IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); + IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG, + sc->sc_rxq.dma_desc.cookie.dmac_address >> 8); + + IWP_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG, + ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address + + offsetof(struct iwp_shared, val0)) >> 4)); + + IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, + FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | + FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | + IWP_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | + (RX_QUEUE_SIZE_LOG << + FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT)); + iwp_mac_access_exit(sc); + IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, + (RX_QUEUE_SIZE - 1) & ~0x7); + + /* + * init Tx rings + */ + iwp_mac_access_enter(sc); + iwp_reg_write(sc, IWP_SCD_TXFACT, 0); + + /* + * keep warm page + */ + IWP_WRITE(sc, IWP_FH_KW_MEM_ADDR_REG, + sc->sc_dma_kw.cookie.dmac_address >> 4); + + for (qid = 0; qid < IWP_NUM_QUEUES; qid++) { + IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid), + sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8); + IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid), + IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | + IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); + } + + iwp_mac_access_exit(sc); + + /* + * clear "radio off" and "disable command" bits + */ + IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); + + /* + * clear any pending interrupts + */ + IWP_WRITE(sc, CSR_INT, 0xffffffff); + + /* + * enable interrupts + */ + IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); + + IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + + return (IWP_SUCCESS); +} + +static int +iwp_fast_recover(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + int err = IWP_FAIL; + + mutex_enter(&sc->sc_glock); + + /* restore runtime configuration */ + bcopy(&sc->sc_config_save, &sc->sc_config, + sizeof (sc->sc_config)); + + sc->sc_config.assoc_id = 0; + sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); + + if ((err = iwp_hw_set_before_auth(sc)) != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_fast_recover(): " + "could not setup authentication\n"); + mutex_exit(&sc->sc_glock); + return (err); + } + + bcopy(&sc->sc_config_save, &sc->sc_config, + sizeof (sc->sc_config)); + + /* update adapter's configuration */ + err = iwp_run_state_config(sc); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_fast_recover(): " + "failed to setup association\n"); + mutex_exit(&sc->sc_glock); + return (err); + } + /* set LED on */ + iwp_set_led(sc, 2, 0, 1); + + mutex_exit(&sc->sc_glock); + + atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); + + /* start queue */ + IWP_DBG((IWP_DEBUG_FW, "iwp_fast_recover(): " + "resume xmit\n")); + mac_tx_update(ic->ic_mach); + + return (IWP_SUCCESS); +} + +static int +iwp_run_state_config(iwp_sc_t *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + ieee80211_node_t *in = ic->ic_bss; + int err = IWP_FAIL; + + /* + * update adapter's configuration + */ + sc->sc_config.assoc_id = in->in_associd & 0x3fff; + + /* + * short preamble/slot time are + * negotiated when associating + */ + sc->sc_config.flags &= + ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK | + RXON_FLG_SHORT_SLOT_MSK); + + if (ic->ic_flags & IEEE80211_F_SHSLOT) { + sc->sc_config.flags |= + LE_32(RXON_FLG_SHORT_SLOT_MSK); + } + + if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) { + sc->sc_config.flags |= + LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); + } + + sc->sc_config.filter_flags |= + LE_32(RXON_FILTER_ASSOC_MSK); + + if (ic->ic_opmode != IEEE80211_M_STA) { + sc->sc_config.filter_flags |= + LE_32(RXON_FILTER_BCON_AWARE_MSK); + } + + IWP_DBG((IWP_DEBUG_80211, "iwp_run_state_config(): " + "config chan %d flags %x" + " filter_flags %x\n", + sc->sc_config.chan, sc->sc_config.flags, + sc->sc_config.filter_flags)); + + err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, + sizeof (iwp_rxon_cmd_t), 1); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_run_state_config(): " + "could not update configuration\n"); + return (err); + } + + return (err); +} + +/* + * This function overwrites default configurations of + * ieee80211com structure in Net80211 module. + */ +static void +iwp_overwrite_ic_default(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = iwp_newstate; + ic->ic_node_alloc = iwp_node_alloc; + ic->ic_node_free = iwp_node_free; +} + + +/* + * This function adds AP station into hardware. + */ +static int +iwp_add_ap_sta(iwp_sc_t *sc) +{ + ieee80211com_t *ic = &sc->sc_ic; + ieee80211_node_t *in = ic->ic_bss; + iwp_add_sta_t node; + int err = IWP_FAIL; + + /* + * Add AP node into hardware. + */ + (void) memset(&node, 0, sizeof (node)); + IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid); + node.mode = STA_MODE_ADD_MSK; + node.sta.sta_id = IWP_AP_ID; + + err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1); + if (err != IWP_SUCCESS) { + cmn_err(CE_WARN, "iwp_add_ap_sta(): " + "failed to add AP node\n"); + return (err); + } + + return (err); +} + +/* + * Check EEPROM version and Calibration version. + */ +static int +iwp_eep_ver_chk(iwp_sc_t *sc) +{ + if ((IWP_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) || + (sc->sc_eep_calib->tx_pow_calib_hdr.calib_version < 4)) { + cmn_err(CE_WARN, "iwp_eep_ver_chk(): " + "unsupported eeprom detected\n"); + return (IWP_FAIL); + } + + return (IWP_SUCCESS); +} + +/* + * Determine parameters for all supported chips. + */ +static void +iwp_set_chip_param(iwp_sc_t *sc) +{ + if ((0x008d == sc->sc_dev_id) || + (0x008e == sc->sc_dev_id)) { + sc->sc_chip_param.phy_mode = PHY_MODE_G | + PHY_MODE_A | PHY_MODE_N; + + sc->sc_chip_param.tx_ant = ANT_A | ANT_B; + sc->sc_chip_param.rx_ant = ANT_A | ANT_B; + + sc->sc_chip_param.pa_type = PA_TYPE_MIX; + } + + if ((0x422c == sc->sc_dev_id) || + (0x4239 == sc->sc_dev_id)) { + sc->sc_chip_param.phy_mode = PHY_MODE_G | + PHY_MODE_A | PHY_MODE_N; + + sc->sc_chip_param.tx_ant = ANT_B | ANT_C; + sc->sc_chip_param.rx_ant = ANT_B | ANT_C; + + sc->sc_chip_param.pa_type = PA_TYPE_INTER; + } + + if ((0x422b == sc->sc_dev_id) || + (0x4238 == sc->sc_dev_id)) { + sc->sc_chip_param.phy_mode = PHY_MODE_G | + PHY_MODE_A | PHY_MODE_N; + + sc->sc_chip_param.tx_ant = ANT_A | ANT_B | ANT_C; + sc->sc_chip_param.rx_ant = ANT_A | ANT_B | ANT_C; + + sc->sc_chip_param.pa_type = PA_TYPE_SYSTEM; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/iwp_calibration.h Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,126 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +/* + * Copyright (c) 2009, Intel Corporation + * All rights reserved. + */ + +/* + * Sun elects to use this software under the BSD license. + */ + +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, + * USA + * + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * James P. Ketrenos <ipw2100-admin@linux.intel.com> + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + * + * BSD LICENSE + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _IWP_CALIBRATION_H +#define _IWP_CALIBRATION_H + +#define EEP_TX_POWER_TX_CHAINS (3) +#define EEP_RXIQ_CAL_CHANNELS (7) +#define EEP_CAL_CHANNEL_GROUP (7) +#define EEP_RXIQ_DRIVER_MODES (12) + +struct tx_pow_calib_hdr { + uint8_t calib_version; + uint8_t pa_type; + uint16_t voltage_reading; +}; + +struct iwp_eep_txpower_sample { + uint8_t gain_index; /* index to power setup table */ + int8_t power; /* power level for this channel group */ + uint8_t v_det; /* PA output voltage */ + uint8_t temp_reading; +}; + +struct iwp_eep_txpower_cal { + struct iwp_eep_txpower_sample samples[6]; /* 6 power level */ + /* highest power possible by hardware in this band */ + uint8_t saturation_power; + /* "representative" channel number in this band */ + uint8_t group_channel; + int8_t t_pa_det; + int8_t t_actual_power; +}; + +struct rx_iq_cal { + int16_t ars; + int16_t arc; +}; + +struct iwp_eep_calibration { + struct tx_pow_calib_hdr tx_pow_calib_hdr; + struct iwp_eep_txpower_cal txpow_group + [EEP_TX_POWER_TX_CHAINS][EEP_CAL_CHANNEL_GROUP]; + uint16_t xtal_calib[2]; + int16_t temp_calib_temp; + int16_t temp_calib_volt; + uint8_t rx_iBB_filter; + uint8_t reserved; + struct rx_iq_cal rx_iq_cal + [EEP_RXIQ_CAL_CHANNELS][EEP_RXIQ_DRIVER_MODES]; +}; + +#endif /* _IWP_CALIBRATION_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/iwp_eeprom.h Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,246 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +/* + * Copyright (c) 2009, Intel Corporation + * All rights reserved. + */ + +/* + * Sun elects to use this software under the BSD license. + */ + +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, + * USA + * + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * James P. Ketrenos <ipw2100-admin@linux.intel.com> + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + * + * BSD LICENSE + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IWP_EEPROM_H_ +#define _IWP_EEPROM_H_ + +/* + * This file defines EEPROM related constants, enums, and inline functions. + */ + +/* + * EEPROM field values + */ +#define ANTENNA_SWITCH_NORMAL 0 +#define ANTENNA_SWITCH_INVERSE 1 + +enum { + EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ + EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ + /* Bit 2 Reserved */ + EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ + EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ + EEPROM_CHANNEL_WIDE = (1 << 5), + EEPROM_CHANNEL_NARROW = (1 << 6), + EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ +}; + +/* + * EEPROM field lengths + */ +#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 + +/* + * EEPROM field lengths + */ +#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 +#define EEPROM_REGULATORY_SKU_ID_LENGTH 4 +#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14 +#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13 +#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12 +#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11 +#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6 + + +#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5 + +/* + * SKU Capabilities + */ +#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) +#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) +#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) + +/* + * *regulatory* channel data from eeprom, one for each channel + */ +struct iwl_eeprom_channel { + uint8_t flags; /* flags copied from EEPROM */ + int8_t max_power_avg; /* max power (dBm) on this chnl, limit 31 */ +}; + +/* + * Mapping of a Tx power level, at factory calibration temperature, + * to a radio/DSP gain table index. + * One for each of 5 "sample" power levels in each band. + * v_det is measured at the factory, using the 3945's built-in power amplifier + * (PA) output voltage detector. This same detector is used during Tx of + * long packets in normal operation to provide feedback as to proper output + * level. + * Data copied from EEPROM. + */ +struct iwl_eeprom_txpower_sample { + uint8_t gain_index; /* index into power (gain) setup table ... */ + int8_t power; /* ... for this pwr level for this chnl group */ + uint16_t v_det; /* PA output voltage */ +}; + +/* + * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. + * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). + * Tx power setup code interpolates between the 5 "sample" power levels + * to determine the nominal setup for a requested power level. + * Data copied from EEPROM. + * DO NOT ALTER THIS STRUCTURE!!! + */ +struct iwl_eeprom_txpower_group { + /* 5 power levels */ + struct iwl_eeprom_txpower_sample samples[5]; + /* coefficients for voltage->power formula (signed) */ + uint32_t a, b, c, d, e; + /* these modify coeffs based on frequency (signed) */ + uint32_t Fa, Fb, Fc, Fd, Fe; + /* highest power possible by h/w in this * band */ + int8_t saturation_power; + /* "representative" channel # in this band */ + uint8_t group_channel; + /* h/w temperature at factory calib this band (signed) */ + uint16_t temperature; +}; + +/* + * Temperature-based Tx-power compensation data, not band-specific. + * These coefficients are use to modify a/b/c/d/e coeffs based on + * difference between current temperature and factory calib temperature. + * Data copied from EEPROM. + */ +struct iwl_eeprom_temperature_corr { + uint32_t Ta; + uint32_t Tb; + uint32_t Tc; + uint32_t Td; + uint32_t Te; +}; + + +/* + * eeprom map + */ +#define EEP_MAC_ADDRESS 42 /* chipset's MAC address 6 bytes */ +#define EEP_VERSION 136 /* eeprom version 2 bytes */ +#define EEP_SP_RADIO_CONFIGURATION 144 /* SP's radio configuration */ + + + +#define CSR_EEPROM_REG (CSR_BASE+0x02c) +#define CSR_EEPROM_GP (CSR_BASE+0x030) +#define CSR_EEPROM_GP_VALID_MSK 0x00000007 +#define CSR_EEPROM_GP_BAD_SIGNATURE 0x00000000 +#define IWP_SP_EEPROM_SIZE 2048 + +#define IWP_READ_EEP_SHORT(sc, addr) ((((uint16_t)sc->sc_eep_map[addr + 1])\ + << 8) |\ + ((uint16_t)sc->sc_eep_map[addr])) + +#define SP_RADIO_TYPE_3x3 (0) +#define SP_RADIO_TYPE_2x2 (1) +#define SP_RADIO_TYPE_1x2 (2) +#define SP_RADIO_TYPE_MAX (3) + +#define SP_RADIO_TYPE_MSK(x) (x & 3) +#define SP_RADIO_STEP_MSK(x) ((x>>2) & 3) +#define SP_RADIO_DASH_MSK(x) ((x>>4) & 3) +#define SP_RADIO_PNUM_MSK(x) ((x>>6) & 3) +#define SP_RADIO_TX_CHAIN_MSK(x) ((x>>8) & 0xf) +#define SP_RADIO_RX_CHAIN_MSK(x) ((x>>12) & 0xf) + +#define ADDRESS_MSK 0x0000ffff +#define INDIRECT_TYPE_MSK 0x000f0000 +#define INDIRECT_HOST 0x00010000 +#define INDIRECT_GENERAL 0x00020000 +#define INDIRECT_REGULATORY 0x00030000 +#define INDIRECT_CALIBRATION 0x00040000 +#define INDIRECT_PROCESS_ADJST 0x00050000 +#define INDIRECT_OTHERS 0x00060000 +#define INDIRECT_ADDRESS 0x00100000 + +#define EEP_LINK_HOST (200) +#define EEP_LINK_GENERAL (202) +#define EEP_LINK_REGULATORY (204) +#define EEP_LINK_CALIBRATION (206) +#define EEP_LINK_PROCESS_ADJST (208) +#define EEP_LINK_OTHERS (210) + +#define EEP_CALIBRATION ((0x00) | INDIRECT_ADDRESS |\ + INDIRECT_CALIBRATION) + +#define EEP_TX_POWER_TX_CHAINS (3) +#define EEP_RXIQ_CAL_CHANNELS (7) +#define EEP_CAL_CHANNEL_GROUP (7) +#define EEP_RXIQ_DRIVER_MODES (12) + + + +#endif /* _IWP_EEPROM_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/iwp_hw.h Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,2633 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +/* + * Copyright (c) 2009, Intel Corporation + * All rights reserved. + */ + +/* + * Sun elects to use this software under the BSD license. + */ + +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, + * USA + * + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * James P. Ketrenos <ipw2100-admin@linux.intel.com> + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + * + * BSD LICENSE + * + * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IWP_HW_H_ +#define _IWP_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * maximum scatter/gather + */ +#define IWP_MAX_SCATTER (10) + +/* + * Flow Handler Definitions + */ +#define FH_MEM_LOWER_BOUND (0x1000) +#define FH_MEM_UPPER_BOUND (0x1EF0) + +#define IWP_FH_REGS_LOWER_BOUND (0x1000) +#define IWP_FH_REGS_UPPER_BOUND (0x2000) + +/* + * TFDB Area - TFDs buffer table + */ +#define FH_MEM_TFDB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x000) +#define FH_MEM_TFDB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x900) + +/* + * channels 0 - 8 + */ +#define FH_MEM_TFDB_CHNL_BUF0(x) (FH_MEM_TFDB_LOWER_BOUND + (x) * 0x100) +#define FH_MEM_TFDB_CHNL_BUF1(x) (FH_MEM_TFDB_LOWER_BOUND + 0x80 + (x) * 0x100) + +/* + * TFDIB Area - TFD Immediate Buffer + */ +#define FH_MEM_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) +#define FH_MEM_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) + +/* + * channels 0 - 10 + */ +#define FH_MEM_TFDIB_CHNL(x) (FH_MEM_TFDIB_LOWER_BOUND + (x) * 0x8) + +/* + * TFDIB registers used in Service Mode + */ +#define FH_MEM_TFDIB_CHNL9_REG0 (FH_MEM_TFDIB_CHNL(9)) +#define FH_MEM_TFDIB_CHNL9_REG1 (FH_MEM_TFDIB_CHNL(9) + 4) +#define FH_MEM_TFDIB_CHNL10_REG0 (FH_MEM_TFDIB_CHNL(10)) +#define FH_MEM_TFDIB_CHNL10_REG1 (FH_MEM_TFDIB_CHNL(10) + 4) + +/* + * Tx service channels + */ +#define FH_MEM_TFDIB_DRAM_ADDR_MSB_MASK (0xF00000000) +#define FH_MEM_TFDIB_TB_LENGTH_MASK (0x0001FFFF) /* bits 16:0 */ + +#define FH_MEM_TFDIB_DRAM_ADDR_LSB_BITSHIFT (0) +#define FH_MEM_TFDIB_DRAM_ADDR_MSB_BITSHIFT (32) +#define FH_MEM_TFDIB_TB_LENGTH_BITSHIFT (0) + +#define FH_MEM_TFDIB_REG0_ADDR_MASK (0xFFFFFFFF) +#define FH_MEM_TFDIB_REG1_ADDR_MASK (0xF0000000) +#define FH_MEM_TFDIB_REG1_LENGTH_MASK (0x0001FFFF) + +#define FH_MEM_TFDIB_REG0_ADDR_BITSHIFT (0) +#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT (28) +#define FH_MEM_TFDIB_REG1_LENGTH_BITSHIFT (0) +#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK (0xFFFFFFFF) + +/* + * TRB Area - Transmit Request Buffers + */ +#define FH_MEM_TRB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0958) +#define FH_MEM_TRB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0980) + +/* + * channels 0 - 8 + */ +#define FH_MEM_TRB_CHNL(x) (FH_MEM_TRB_LOWER_BOUND + (x) * 0x4) + +/* + * Keep-Warm (KW) buffer base address. + * + * Driver must allocate a 4KByte buffer that is used by Shirely Peak(SP) for + * keeping the + * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency + * DRAM access when SP is Txing or Rxing. The dummy accesses prevent host + * from going into a power-savings mode that would cause higher DRAM latency, + * and possible data over/under-runs, before all Tx/Rx is complete. + * + * Driver loads IWP_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) + * of the buffer, which must be 4K aligned. Once this is set up, the SP + * automatically invokes keep-warm accesses when normal accesses might not + * be sufficient to maintain fast DRAM response. + * + * Bit fields: + * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned + */ +#define IWP_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) + +/* + * STAGB Area - Scheduler TAG Buffer + */ +#define FH_MEM_STAGB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x980) +#define FH_MEM_STAGB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) + +/* + * channels 0 - 8 + */ +#define FH_MEM_STAGB_0(x) (FH_MEM_STAGB_LOWER_BOUND + (x) * 0x8) +#define FH_MEM_STAGB_1(x) (FH_MEM_STAGB_LOWER_BOUND + 0x4 + (x) * 0x8) + +/* + * Tx service channels + */ +#define FH_MEM_SRAM_ADDR_9 (FH_MEM_STAGB_LOWER_BOUND + 0x048) +#define FH_MEM_SRAM_ADDR_10 (FH_MEM_STAGB_LOWER_BOUND + 0x04C) + +#define FH_MEM_STAGB_SRAM_ADDR_MASK (0x00FFFFFF) + +/* + * TFD Circular Buffers Base (CBBC) addresses + * + * SP has 16 base pointer registers, one for each of 16 host-DRAM-resident + * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) + * (see struct iwp_tfd_frame). These 16 pointer registers are offset by 0x04 + * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte + * aligned (address bits 0-7 must be 0). + * + * Bit fields in each pointer register: + * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned + */ +#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) +#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) + +/* + * queues 0 - 15 + */ +#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) + +/* + * TAGR Area - TAG reconstruct table + */ +#define FH_MEM_TAGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) +#define FH_MEM_TAGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA70) + +/* + * TDBGR Area - Tx Debug Registers + */ +#define FH_MEM_TDBGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0A70) +#define FH_MEM_TDBGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0B20) + +/* + * channels 0 - 10 + */ +#define FH_MEM_TDBGR_CHNL(x) (FH_MEM_TDBGR_LOWER_BOUND + (x) * 0x10) + +#define FH_MEM_TDBGR_CHNL_REG_0(x) (FH_MEM_TDBGR_CHNL(x)) +#define FH_MEM_TDBGR_CHNL_REG_1(x) (FH_MEM_TDBGR_CHNL_REG_0(x) + 0x4) + +#define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_MASK (0x000FFFFF) +#define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_BITSHIFT (0) + +/* + * RDBUF Area + */ +#define FH_MEM_RDBUF_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) +#define FH_MEM_RDBUF_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) +#define FH_MEM_RDBUF_CHNL0 (FH_MEM_RDBUF_LOWER_BOUND) + +/* + * Rx SRAM Control and Status Registers (RSCSR) + * + * These registers provide handshake between driver and Shirley Peak for + * the Rx queue + * (this queue handles *all* command responses, notifications, Rx data, etc. + * sent from SP uCode to host driver). Unlike Tx, there is only one Rx + * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can + * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer + * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 + * mapping between RBDs and RBs. + * + * Driver must allocate host DRAM memory for the following, and set the + * physical address of each into SP registers: + * + * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 + * entries (although any power of 2, up to 4096, is selectable by driver). + * Each entry (1 dword) points to a receive buffer (RB) of consistent size + * (typically 4K, although 8K or 16K are also selectable by driver). + * Driver sets up RB size and number of RBDs in the CB via Rx config + * register FH_MEM_RCSR_CHNL0_CONFIG_REG. + * + * Bit fields within one RBD: + * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned. + * + * Driver sets physical address [35:8] of base of RBD circular buffer + * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. + * + * 2) Rx status buffer, 8 bytes, in which SP indicates which Rx Buffers + * (RBs) have been filled, via a "write pointer", actually the index of + * the RB's corresponding RBD within the circular buffer. Driver sets + * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. + * + * Bit fields in lower dword of Rx status buffer (upper dword not used + * by driver; see struct iwp_shared, val0): + * 31-12: Not used by driver + * 11- 0: Index of last filled Rx buffer descriptor + * (SP writes, driver reads this value) + * + * As the driver prepares Receive Buffers (RBs) for SP to fill, driver must + * enter pointers to these RBs into contiguous RBD circular buffer entries, + * and update the SP's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. + * + * This "write" index corresponds to the *next* RBD that the driver will make + * available, i.e. one RBD past the the tail of the ready-to-fill RBDs within + * the circular buffer. This value should initially be 0 (before preparing any + * RBs), should be 8 after preparing the first 8 RBs (for example), and must + * wrap back to 0 at the end of the circular buffer (but don't wrap before + * "read" index has advanced past 1! See below). + * NOTE: SP EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. + * + * As the SP fills RBs (referenced from contiguous RBDs within the circular + * buffer), it updates the Rx status buffer in DRAM, 2) described above, + * to tell the driver the index of the latest filled RBD. The driver must + * read this "read" index from DRAM after receiving an Rx interrupt from SP. + * + * The driver must also internally keep track of a third index, which is the + * next RBD to process. When receiving an Rx interrupt, driver should process + * all filled but unprocessed RBs up to, but not including, the RB + * corresponding to the "read" index. For example, if "read" index becomes "1", + * driver may process the RB pointed to by RBD 0. Depending on volume of + * traffic, there may be many RBs to process. + * + * If read index == write index, SP thinks there is no room to put new data. + * Due to this, the maximum number of filled RBs is 255, instead of 256. To + * be safe, make sure that there is a gap of at least 2 RBDs between "write" + * and "read" indexes; that is, make sure that there are no more than 254 + * buffers waiting to be filled. + */ +#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) +#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) +#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) +#define FH_MEM_RSCSR_CHNL1 (FH_MEM_RSCSR_LOWER_BOUND + 0x020) + +/* + * Physical base address of 8-byte Rx Status buffer. + * Bit fields: + * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. + */ + +#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) + +/* + * Physical base address of Rx Buffer Descriptor Circular Buffer. + * Bit fields: + * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. + */ +#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) + +/* + * Rx write pointer (index, really!). + * Bit fields: + * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. + * NOTE: For 256-entry circular buffer, use only bits [7:0]. + */ +#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) +#define FH_RSCSR_CHNL0_RBDCB_RPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) + + +/* + * RSCSR registers used in Service mode + */ +#define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1) +#define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004) +#define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008) +#define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C) + +/* + * Rx Config/Status Registers (RCSR) + * Rx Config Reg for channel 0 (only channel used) + * + * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for + * normal operation (see bit fields). + * + * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. + * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for + * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. + * + * Bit fields: + * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, + * '10' operate normally + * 29-24: reserved + * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), + * min "5" for 32 RBDs, max "12" for 4096 RBDs. + * 19-18: reserved + * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, + * '10' 12K, '11' 16K. + * 15-14: reserved + * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) + * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) + * typical value 0x10 (about 1/2 msec) + * 3- 0: reserved + */ +#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) +#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) +#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) +#define FH_MEM_RCSR_CHNL1 (FH_MEM_RCSR_LOWER_BOUND + 0x020) + +#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) +#define FH_MEM_RCSR_CHNL0_CREDIT_REG (FH_MEM_RCSR_CHNL0 + 0x004) +#define FH_MEM_RCSR_CHNL0_RBD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x008) +#define FH_MEM_RCSR_CHNL0_RB_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x00C) +#define FH_MEM_RCSR_CHNL0_RXPD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x010) + +#define FH_MEM_RCSR_CHNL0_RBD_STTS_FRAME_RB_CNT_MASK (0x7FFFFFF0) + +/* + * RCSR registers used in Service mode + */ +#define FH_MEM_RCSR_CHNL1_CONFIG_REG (FH_MEM_RCSR_CHNL1) +#define FH_MEM_RCSR_CHNL1_RB_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x00C) +#define FH_MEM_RCSR_CHNL1_RX_PD_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x010) + +/* + * Rx Shared Status Registers (RSSR) + * + * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), + * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. + * + * Bit fields: + * 24: 1 = Channel 0 is idle + * + * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain + * default values that should not be altered by the driver. + */ +#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) +#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) +#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) +#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) +#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) + +/* + * Transmit DMA Channel Control/Status Registers (TCSR) + * + * SP has one configuration register for each of 8 Tx DMA/FIFO channels + * supported in hardware; config regs are separated by 0x20 bytes. + * + * To use a Tx DMA channel, driver must initialize its + * + * + * All other bits should be 0. + * + * Bit fields: + * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, + * '10' operate normally + * 29- 4: Reserved, set to "0" + * 3: Enable internal DMA requests (1, normal operation), disable (0) + * 2- 0: Reserved, set to "0" + */ +#define IWP_FH_TCSR_UPPER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0xE60) + +#define IWP_FH_TCSR_CHNL_NUM (7) + +/* + * Tx Shared Status Registers (TSSR) + * + * After stopping Tx DMA channel (writing 0 to + * IWP_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle + * (channel's buffers empty | no pending requests). + * + * Bit fields: + * 31-24: 1 = Channel buffers empty (channel 7:0) + * 23-16: 1 = No pending requests (channel 7:0) + */ +#define IWP_FH_TSSR_LOWER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0xEA0) +#define IWP_FH_TSSR_UPPER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0xEC0) + +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG (IWP_FH_TSSR_LOWER_BOUND + 0x008) +#define IWP_FH_TSSR_TX_STATUS_REG (IWP_FH_TSSR_LOWER_BOUND + 0x010) + +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) + +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00) + +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) + +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) +#define IWP_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) + +#define IWP_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ + ((1 << (_chnl)) << 24) +#define IWP_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ + ((1 << (_chnl)) << 16) + +#define IWP_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ + (IWP_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ + IWP_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) + +/* + * TFDIB + */ +#define IWP_FH_TFDIB_UPPER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0x958) +#define IWP_FH_TFDIB_CTRL1_REG_POS_MSB (28) +#define IWP_FH_TFDIB_LOWER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0x900) + +#define IWP_FH_TFDIB_CTRL0_REG(_chnl)\ + (IWP_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl) + +#define IWP_FH_TFDIB_CTRL1_REG(_chnl)\ + (IWP_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl + 0x4) + +/* + * Debug Monitor Area + */ +#define FH_MEM_DM_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEE0) +#define FH_MEM_DM_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEF0) +#define FH_MEM_DM_CONTROL_MASK_REG (FH_MEM_DM_LOWER_BOUND) +#define FH_MEM_DM_CONTROL_START_REG (FH_MEM_DM_LOWER_BOUND + 0x004) +#define FH_MEM_DM_CONTROL_STATUS_REG (FH_MEM_DM_LOWER_BOUND + 0x008) +#define FH_MEM_DM_MONITOR_REG (FH_MEM_DM_LOWER_BOUND + 0x00C) + +#define FH_TB1_ADDR_LOW_MASK (0xFFFFFFFF) /* bits 31:0 */ +#define FH_TB1_ADDR_HIGH_MASK (0xF00000000) /* bits 35:32 */ +#define FH_TB2_ADDR_LOW_MASK (0x0000FFFF) /* bits 15:0 */ +#define FH_TB2_ADDR_HIGH_MASK (0xFFFFF0000) /* bits 35:16 */ + +#define FH_TB1_ADDR_LOW_BITSHIFT (0) +#define FH_TB1_ADDR_HIGH_BITSHIFT (32) +#define FH_TB2_ADDR_LOW_BITSHIFT (0) +#define FH_TB2_ADDR_HIGH_BITSHIFT (16) + +#define FH_TB1_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ +#define FH_TB2_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ + +/* + * number of FH channels including 2 service mode + */ +#define NUM_OF_FH_CHANNELS (10) + +/* + * ctrl field bitology + */ +#define FH_TFD_CTRL_PADDING_MASK (0xC0000000) /* bits 31:30 */ +#define FH_TFD_CTRL_NUMTB_MASK (0x1F000000) /* bits 28:24 */ + +#define FH_TFD_CTRL_PADDING_BITSHIFT (30) +#define FH_TFD_CTRL_NUMTB_BITSHIFT (24) + +#define FH_TFD_GET_NUM_TBS(ctrl) \ + ((ctrl & FH_TFD_CTRL_NUMTB_MASK) >> FH_TFD_CTRL_NUMTB_BITSHIFT) +#define FH_TFD_GET_PADDING(ctrl) \ + ((ctrl & FH_TFD_CTRL_PADDING_MASK) >> FH_TFD_CTRL_PADDING_BITSHIFT) + +/* + * TCSR: tx_config register values + */ +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) + + +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) + +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) + +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) + +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) + +#define IWP_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) + +#define IWP_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) + +#define IWP_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl)\ + (IWP_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) + +#define IWP_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl)\ + (IWP_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4) + +#define IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl)\ + (IWP_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8) +#define IWP_FH_TCSR_CHNL_NUM (7) + +/* + * CBB table + */ +#define FH_CBB_ADDR_MASK 0x0FFFFFFF /* bits 27:0 */ +#define FH_CBB_ADDR_BIT_SHIFT (8) + +/* + * RCSR: channel 0 rx_config register defines + */ +#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ +#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ +#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ +#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ +#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ +#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ + +#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) +#define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) + +#define FH_RCSR_GET_RDBC_SIZE(reg) \ + ((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \ + FH_RCSR_RX_CONFIG_RDBC_SIZE_BITSHIFT) + +/* + * RCSR: channel 1 rx_config register defines + */ +#define FH_RCSR_CHNL1_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ +#define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_MASK (0x00003000) /* bits 12-13 */ + +/* + * RCSR: rx_config register values + */ +#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) +#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) +#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) +#define FH_RCSR_RX_CONFIG_SINGLE_FRAME_MODE (0x00008000) + +#define FH_RCSR_RX_CONFIG_RDRBD_DISABLE_VAL (0x00000000) +#define FH_RCSR_RX_CONFIG_RDRBD_ENABLE_VAL (0x20000000) + +#define IWP_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) +#define IWP_TX_RTS_RETRY_LIMIT (60) +#define IWP_TX_DATA_RETRY_LIMIT (15) + +#define IWP_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) +#define IWP_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) +#define IWP_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) + +/* + * RCSR channel 0 config register values + */ +#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) +#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) + +/* + * RCSR channel 1 config register values + */ +#define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) +#define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) +#define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_RTC_VAL (0x00002000) +#define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_RTC_VAL (0x00003000) + +/* + * RCSR: rb status register defines + */ +#define FH_RCSR_RB_BYTE_TO_SEND_MASK (0x0001FFFF) /* bits 0-16 */ + +/* + * RSCSR: defs used in normal mode + */ +#define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */ + +/* + * RSCSR: defs used in service mode + */ +#define FH_RSCSR_CHNL1_SRAM_ADDR_MASK (0x00FFFFFF) /* bits 0-23 */ +#define FH_RSCSR_CHNL1_RB_WPTR_MASK (0x0FFFFFFF) /* bits 0-27 */ +#define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_MASK (0x000000FF) /* bits 0-7 */ + +/* + * RSSR: RX Enable Error IRQ to Driver register defines + */ +#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV_NO_RBD (0x00400000) /* bit 22 */ + +#define FH_DRAM2SRAM_DRAM_ADDR_HIGH_MASK (0xFFFFFFF00) /* bits 8-35 */ +#define FH_DRAM2SRAM_DRAM_ADDR_LOW_MASK (0x000000FF) /* bits 0-7 */ + +#define FH_DRAM2SRAM_DRAM_ADDR_HIGH_BITSHIFT (8) /* bits 8-35 */ + +/* + * RX DRAM status regs definitions + */ +#define FH_RX_RB_NUM_MASK (0x00000FFF) /* bits 0-11 */ +#define FH_RX_FRAME_NUM_MASK (0x0FFF0000) /* bits 16-27 */ + +#define FH_RX_RB_NUM_BITSHIFT (0) +#define FH_RX_FRAME_NUM_BITSHIFT (16) + +/* + * Tx Scheduler + * + * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs + * (Transmit Frame Descriptors) from up to 16 circular queues resident in + * host DRAM. It steers each frame's Tx command (which contains the frame + * data) through one of up to 7 prioritized Tx DMA FIFO channels within the + * device. A queue maps to only one (selectable by driver) Tx DMA channel, + * but one DMA channel may take input from several queues. + * + * Tx DMA channels have dedicated purposes. For SP, and are used as follows: + * BMC TODO: CONFIRM channel assignments, esp for 0/1 + * + * 0 -- EDCA BK (background) frames, lowest priority + * 1 -- EDCA BE (best effort) frames, normal priority + * 2 -- EDCA VI (video) frames, higher priority + * 3 -- EDCA VO (voice) and management frames, highest priority + * 4 -- Commands (e.g. RXON, etc.) + * 5 -- HCCA short frames + * 6 -- HCCA long frames + * 7 -- not used by driver (device-internal only) + * + * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. + * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to + * support 11n aggregation via EDCA DMA channels. BMC confirm. + * + * The driver sets up each queue to work in one of two modes: + * + * 1) Scheduler-Ack, in which the scheduler automatically supports a + * block-ack (BA) window of up to 64 TFDs. In this mode, each queue + * contains TFDs for a unique combination of Recipient Address (RA) + * and Traffic Identifier (TID), that is, traffic of a given + * Quality-Of-Service (QOS) priority, destined for a single station. + * + * In scheduler-ack mode, the scheduler keeps track of the Tx status of + * each frame within the BA window, including whether it's been transmitted, + * and whether it's been acknowledged by the receiving station. The device + * automatically processes block-acks received from the receiving STA, + * and reschedules un-acked frames to be retransmitted (successful + * Tx completion may end up being out-of-order). + * + * The driver must maintain the queue's Byte Count table in host DRAM + * (struct iwp_sched_queue_byte_cnt_tbl) for this mode. + * This mode does not support fragmentation. + * + * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. + * The device may automatically retry Tx, but will retry only one frame + * at a time, until receiving ACK from receiving station, or reaching + * retry limit and giving up. + * + * The command queue (#4) must use this mode! + * This mode does not require use of the Byte Count table in host DRAM. + * + * Driver controls scheduler operation via 3 means: + * 1) Scheduler registers + * 2) Shared scheduler data base in internal 4956 SRAM + * 3) Shared data in host DRAM + * + * Initialization: + * + * When loading, driver should allocate memory for: + * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. + * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory + * (1024 bytes for each queue). + * + * After receiving "Alive" response from uCode, driver must initialize + * the following (especially for queue #4, the command queue, otherwise + * the driver can't issue commands!): + * + * 1) SP's scheduler data base area in SRAM: + * a) Read SRAM address of data base area from SCD_SRAM_BASE_ADDR + * b) Clear and Init SCD_CONTEXT_DATA_OFFSET area (size 128 bytes) + * c) Clear SCD_TX_STTS_BITMAP_OFFSET area (size 256 bytes) + * d) Clear (BMC and init?) SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) + * + * 2) Init SCD_DRAM_BASE_ADDR with physical base of Tx byte count circular + * buffer array, allocated by driver in host DRAM. + * + * 3) + */ + +/* + * Max Tx window size is the max number of contiguous TFDs that the scheduler + * can keep track of at one time when creating block-ack chains of frames. + * Note that "64" matches the number of ack bits in a block-ack. + * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize + * SCD_CONTEXT_QUEUE_OFFSET(x) values. + */ +#define SCD_WIN_SIZE 64 +#define SCD_FRAME_LIMIT 64 + +/* + * Driver may need to update queue-empty bits after changing queue's + * write and read pointers (indexes) during (re-)initialization (i.e. when + * scheduler is not tracking what's happening). + * Bit fields: + * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit + * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty + * NOTE BMC: THIS REGISTER NOT USED BY LINUX DRIVER. + */ +#define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4) + +/* + * Physical base address of array of byte count (BC) circular buffers (CBs). + * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. + * This register points to BC CB for queue 0, must be on 1024-byte boundary. + * Others are spaced by 1024 bytes. + * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. + * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). + * Bit fields: + * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. + */ +#define SCD_AIT (SCD_START_OFFSET + 0x18) + +/* + * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. + * Initialized and updated by driver as new TFDs are added to queue. + * NOTE: If using Block Ack, index must correspond to frame's + * Start Sequence Number; index = (SSN & 0xff) + * NOTE BMC: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? + */ +#define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4) + +/* + * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. + * For FIFO mode, index indicates next frame to transmit. + * For Scheduler-ACK mode, index indicates first frame in Tx window. + * Initialized by driver, updated by scheduler. + */ +#define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4) +#define SCD_SETQUEUENUM (SCD_START_OFFSET + 0xa4) +#define SCD_SET_TXSTAT_TXED (SCD_START_OFFSET + 0xa8) +#define SCD_SET_TXSTAT_DONE (SCD_START_OFFSET + 0xac) +#define SCD_SET_TXSTAT_NOT_SCHD (SCD_START_OFFSET + 0xb0) +#define SCD_DECREASE_CREDIT (SCD_START_OFFSET + 0xb4) +#define SCD_DECREASE_SCREDIT (SCD_START_OFFSET + 0xb8) +#define SCD_LOAD_CREDIT (SCD_START_OFFSET + 0xbc) +#define SCD_LOAD_SCREDIT (SCD_START_OFFSET + 0xc0) +#define SCD_BAR (SCD_START_OFFSET + 0xc4) +#define SCD_BAR_DW0 (SCD_START_OFFSET + 0xc8) +#define SCD_BAR_DW1 (SCD_START_OFFSET + 0xcc) + +/* + * Select which queues work in chain mode (1) vs. not (0). + * Use chain mode to build chains of aggregated frames. + * Bit fields: + * 31-16: Reserved + * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time + * NOTE: If driver sets up queue for chain mode, it should be also set up + * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). + */ +#define SCD_QUERY_REQ (SCD_START_OFFSET + 0xd8) +#define SCD_QUERY_RES (SCD_START_OFFSET + 0xdc) +#define SCD_PENDING_FRAMES (SCD_START_OFFSET + 0xe0) + +/* + * Select which queues interrupt driver when read pointer (index) increments. + * Bit fields: + * 31-16: Reserved + * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled + * NOTE BMC: THIS FUNCTIONALITY IS APPARENTLY A NO-OP. + */ +#define SCD_INTERRUPT_THRESHOLD (SCD_START_OFFSET + 0xe8) +#define SCD_QUERY_MIN_FRAME_SIZE (SCD_START_OFFSET + 0x100) + + +/* + * SP internal SRAM structures for scheduler, shared with driver ... + * Driver should clear and initialize the following areas after receiving + * "Alive" response from SP uCode, i.e. after initial + * uCode load, or after a uCode load done for error recovery: + * + * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) + * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) + * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) + * + * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. + * All OFFSET values must be added to this base address. + * Use HBUS_TARG_MEM_* registers to access SRAM. + */ + +/* + * Queue context. One 8-byte entry for each of 16 queues. + * + * Driver should clear this entire area (size 0x80) to 0 after receiving + * "Alive" notification from uCode. Additionally, driver should init + * each queue's entry as follows: + * + * LS Dword bit fields: + * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. + * + * MS Dword bit fields: + * 16-22: Frame limit. Driver should init to 10 (0xa). + * + * Driver should init all other bits to 0. + * + * Init must be done after driver receives "Alive" response from SP uCode, + * and when setting up queue for aggregation. + */ +#define SCD_CONTEXT_DATA_OFFSET 0x380 + +/* + * Tx Status Bitmap + * + * Driver should clear this entire area (size 0x100) to 0 after receiving + * "Alive" notification from uCode. Area is used only by device itself; + * no other support (besides clearing) is required from driver. + */ +#define SCD_TX_STTS_BITMAP_OFFSET 0x400 + +/* + * RAxTID to queue translation mapping. + * + * When queue is in Scheduler-ACK mode, frames placed in a that queue must be + * for only one combination of receiver address (RA) and traffic ID (TID), i.e. + * one QOS priority level destined for one station (for this link, not final + * destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit mappings, + * one for each of the 16 queues. If queue is not in Scheduler-ACK mode, the + * device ignores the mapping value. + * + * Bit fields, for each 16-bit map: + * 15-9: Reserved, set to 0 + * 8-4: Index into device's station table for recipient station + * 3-0: Traffic ID (tid), range 0-15 + * + * Driver should clear this entire area (size 32 bytes) to 0 after receiving + * "Alive" notification from uCode. To update a 16-bit map value, driver + * must read a dword-aligned value from device SRAM, replace the 16-bit map + * value of interest, and write the dword value back into device SRAM. + */ +#define SCD_TRANSLATE_TBL_OFFSET 0x500 +#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) +#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ + ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) + +/* + * Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". + */ +#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ + ((1<<(hi))|((1<<(hi))-(1<<(lo)))) + +#define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0) +#define SCD_MODE_REG_BIT_SBYP_MODE (1<<1) + +#define SCD_TXFIFO_POS_TID (0) +#define SCD_TXFIFO_POS_RA (4) +#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) +#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) + +#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) + +#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) +#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) +#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) +#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) +#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) +#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) +#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) +#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) + +#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) +#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) +#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) +#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) +#define CSR_HW_IF_CONFIG_REG_EEP_SEM (0x00200000) +#define IWP_CSR_ANA_PLL_CFG (0x00880300) + +/* IWP-END */ + + +#define STATISTICS_FLG_CLEAR (0x1) +#define STATISTICS_FLG_DISABLE_NOTIFICATION (0x2) + +#define STATISTICS_REPLY_FLG_CLEAR (0x1) +#define STATISTICS_REPLY_FLG_BAND_24G_MSK (0x2) +#define STATISTICS_REPLY_FLG_TGJ_NARROW_BAND_MSK (0x4) +#define STATISTICS_REPLY_FLG_FAT_MODE_MSK (0x8) +#define RX_PHY_FLAGS_ANTENNAE_OFFSET (4) +#define RX_PHY_FLAGS_ANTENNAE_MASK (0x70) + +/* + * Register and values + */ +#define CSR_BASE (0x0) +#define HBUS_BASE (0x400) + +#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) + +/* + * CSR (control and status registers) + */ +#define CSR_SW_VER (CSR_BASE+0x000) +#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ +#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ +#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ +#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ +#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ +#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ +#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ +#define CSR_GP_CNTRL (CSR_BASE+0x024) +#define CSR_HW_REV (CSR_BASE+0x028) +#define CSR_EEPROM_REG (CSR_BASE+0x02c) +#define CSR_EEPROM_GP (CSR_BASE+0x030) +#define CSR_GP_DRIVER_REG (CSR_BASE+0x050) +#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) +#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) +#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) +#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) +#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) +#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) +#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) + +/* + * BSM (Bootstrap State Machine) + */ +#define BSM_BASE (CSR_BASE + 0x3400) + +#define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ +#define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ +#define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ +#define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ +#define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ + +/* + * BSM special memory, stays powered during power-save sleeps + */ +#define BSM_SRAM_LOWER_BOUND (CSR_BASE + 0x3800) +#define BSM_SRAM_SIZE (1024) + + +/* + * card static random access memory (SRAM) for processor data and instructs + */ +#define RTC_INST_LOWER_BOUND (0x000000) +#define RTC_INST_UPPER_BOUND (0x040000) + +#define RTC_DATA_LOWER_BOUND (0x800000) +#define RTC_DATA_UPPER_BOUND (0x814000) + +#define RTC_INST_SIZE\ + (RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) +#define RTC_DATA_SIZE\ + (RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) + +/* + * HBUS (Host-side bus) + */ +#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) +#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) +#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) +#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) +#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) +#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) +#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) +#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) +#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) + +/* + * HW I/F configuration + */ +#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) +#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) +#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) +#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) +#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) +#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) + +#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) +#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) +#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) +#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) + +#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) +#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) +#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) +#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) +#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER + +#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) +#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_MIX (0x00000000) +#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_MIX (0x00000001) +#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) + +/* + * interrupt flags in INTA, set by uCode or hardware (e.g. dma), + * acknowledged (reset) by host writing "1" to flagged bits. + */ +#define BIT_INT_FH_RX \ + (((uint32_t)1) << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ +#define BIT_INT_ERR (1<<29) /* DMA hardware error FH_INT[31] */ +#define BIT_INT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ +#define BIT_INT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ +#define BIT_INT_SWERROR (1<<25) /* uCode error */ +#define BIT_INT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ +#define BIT_INT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ +#define BIT_INT_SW_RX (1<<3) /* Rx, command responses, 3945 */ +#define BIT_INT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ +#define BIT_INT_ALIVE (1<<0) /* uCode interrupts once it initializes */ + +#define CSR_INI_SET_MASK (BIT_INT_FH_RX | \ + BIT_INT_ERR | \ + BIT_INT_FH_TX | \ + BIT_INT_SWERROR | \ + BIT_INT_RF_KILL | \ + BIT_INT_SW_RX | \ + BIT_INT_WAKEUP | \ + BIT_INT_ALIVE) + +/* + * interrupt flags in FH (flow handler) (PCI busmaster DMA) + */ +#define BIT_FH_INT_ERR (((uint32_t)1) << 31) /* Error */ +#define BIT_FH_INT_HI_PRIOR (1<<30) /* High priority Rx,bypass coalescing */ +#define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */ +#define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */ +#define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */ +#define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */ +#define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */ +#define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */ + +#define FH_INT_RX_MASK (BIT_FH_INT_HI_PRIOR | \ + BIT_FH_INT_RX_CHNL1 | \ + BIT_FH_INT_RX_CHNL0) + +#define FH_INT_TX_MASK (BIT_FH_INT_TX_CHNL6 | \ + BIT_FH_INT_TX_CHNL1 | \ + BIT_FH_INT_TX_CHNL0) + +/* + * RESET + */ +#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) +#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) +#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) +#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) +#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) + +/* + * GP (general purpose) CONTROL + */ +#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) +#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) +#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) +#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) + +#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) + +#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) +#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) +#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) + +/* + * APMG (power management) constants + */ +#define APMG_CLK_CTRL_REG (0x003000) +#define ALM_APMG_CLK_EN (0x003004) +#define ALM_APMG_CLK_DIS (0x003008) +#define ALM_APMG_PS_CTL (0x00300c) +#define ALM_APMG_PCIDEV_STT (0x003010) +#define ALM_APMG_RFKILL (0x003014) +#define ALM_APMG_LARC_INT (0x00301c) +#define ALM_APMG_LARC_INT_MSK (0x003020) + +#define APMG_CLK_REG_VAL_DMA_CLK_RQT (0x00000200) +#define APMG_CLK_REG_VAL_BSM_CLK_RQT (0x00000800) + +#define APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ (0x04000000) + +#define APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE (0x00000800) + +#define APMG_PS_CTRL_REG_MSK_POWER_SRC (0x03000000) +#define APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN (0x00000000) +#define APMG_PS_CTRL_REG_VAL_POWER_SRC_VAUX (0x01000000) + +/* + * BSM (bootstrap state machine) + */ +/* + * start boot load now + */ +#define BSM_WR_CTRL_REG_BIT_START (0x80000000) +/* + * enable boot after power up + */ +#define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) + +/* + * DBM + */ +#define ALM_FH_SRVC_CHNL (6) +#define IWP_FH_SRVC_LOWER_BOUND (IWP_FH_REGS_LOWER_BOUND + 0x9C8) +#define IWP_FH_SRVC_CHNL (9) + + +#define IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl)\ + (IWP_FH_SRVC_LOWER_BOUND + (_chnl - 9) * 0x4) + +#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) +#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) + +#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) +#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) +#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) +#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) +#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) +#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) +#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) +#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) +#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) +#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) + +#define ALM_TB_MAX_BYTES_COUNT (0xFFF0) + +#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ + ((1LU << _channel) << 24) +#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ + ((1LU << _channel) << 16) + +#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ + (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ + ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) +#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ +#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ +#define PCI_CFG_RETRY_TIMEOUT (0x41) + +#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) + +#define TFD_QUEUE_MIN 0 +#define TFD_QUEUE_MAX 6 +#define TFD_QUEUE_SIZE_MAX (256) + +/* + * spectrum and channel data structures + */ +#define IWP_NUM_SCAN_RATES (2) + +#define IWP_SCAN_FLAG_24GHZ (1<<0) +#define IWP_SCAN_FLAG_52GHZ (1<<1) +#define IWP_SCAN_FLAG_ACTIVE (1<<2) +#define IWP_SCAN_FLAG_DIRECT (1<<3) + +#define IWP_MAX_CMD_SIZE 1024 + +#define IWP_DEFAULT_TX_RETRY 15 +#define IWP_MAX_TX_RETRY 16 + +#define RFD_SIZE 4 +#define NUM_TFD_CHUNKS 4 + +#define RX_QUEUE_SIZE 256 +#define RX_QUEUE_SIZE_LOG 8 + +/* + * TX Queue Flag Definitions + */ +/* + * use short preamble + */ +#define DCT_FLAG_LONG_PREAMBLE 0x00 +#define DCT_FLAG_SHORT_PREAMBLE 0x04 + +/* + * ACK rx is expected to follow + */ +#define DCT_FLAG_ACK_REQD 0x80 + +#define IWP_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24 +#define IWP_MB_ROAMING_THRESHOLD_DEFAULT 8 +#define IWP_REAL_RATE_RX_PACKET_THRESHOLD 300 + +/* + * QoS definitions + */ + +#define AC_NUM (4) /* the number of access category */ + +/* + * index of every AC in firmware + */ +#define QOS_AC_BK (0) +#define QOS_AC_BE (1) +#define QOS_AC_VI (2) +#define QOS_AC_VO (3) +#define QOS_AC_INVALID (-1) + +#define QOS_CW_RANGE_MIN (0) /* exponential of 2 */ +#define QOS_CW_RANGE_MAX (15) /* exponential of 2 */ +#define QOS_TXOP_MIN (0) /* unit of 32 microsecond */ +#define QOS_TXOP_MAX (255) /* unit of 32 microsecond */ +#define QOS_AIFSN_MIN (2) +#define QOS_AIFSN_MAX (15) /* undefined */ + +/* + * masks for flags of QoS parameter command + */ +#define QOS_PARAM_FLG_UPDATE_EDCA (0x01) +#define QOS_PARAM_FLG_TGN (0x02) + +/* + * index of TX queue for every AC + */ +#define QOS_AC_BK_TO_TXQ (3) +#define QOS_AC_BE_TO_TXQ (2) +#define QOS_AC_VI_TO_TXQ (1) +#define QOS_AC_VO_TO_TXQ (0) +#define TXQ_FOR_AC_MIN (0) +#define TXQ_FOR_AC_MAX (3) +#define TXQ_FOR_AC_INVALID (-1) +#define NON_QOS_TXQ QOS_AC_BE_TO_TXQ +#define QOS_TXQ_FOR_MGT QOS_AC_VO_TO_TXQ + +#define WME_TID_MIN (0) +#define WME_TID_MAX (7) +#define WME_TID_INVALID (-1) + +/* + * HT definitions + */ + +/* + * HT capabilities masks + */ +#define HT_CAP_SUP_WIDTH (0x0002) +#define HT_CAP_MIMO_PS (0x000c) +#define HT_CAP_GRN_FLD (0x0010) +#define HT_CAP_SGI_20 (0x0020) +#define HT_CAP_SGI_40 (0x0040) +#define HT_CAP_DELAY_BA (0x0400) +#define HT_CAP_MAX_AMSDU (0x0800) +#define HT_CAP_MCS_TX_DEFINED (0x01) +#define HT_CAP_MCS_TX_RX_DIFF (0x02) +#define HT_CAP_MCS_TX_STREAMS (0x0c) +#define HT_CAP_MCS_TX_UEQM (0x10) + +#define HT_CAP_MIMO_PS_STATIC (0) +#define HT_CAP_MIMO_PS_DYNAMIC (1) +#define HT_CAP_MIMO_PS_INVALID (2) +#define HT_CAP_MIMO_PS_NONE (3) + +#define HT_RX_AMPDU_FACTOR_8K (0x0) +#define HT_RX_AMPDU_FACTOR_16K (0x1) +#define HT_RX_AMPDU_FACTOR_32K (0x2) +#define HT_RX_AMPDU_FACTOR_64K (0x3) +#define HT_RX_AMPDU_FACTOR HT_RX_AMPDU_FACTOR_8K +#define HT_RX_AMPDU_FACTOR_MSK (0x3) + +#define HT_MPDU_DENSITY_4USEC (0x5) +#define HT_MPDU_DENSITY_8USEC (0x6) +#define HT_MPDU_DENSITY HT_MPDU_DENSITY_4USEC +#define HT_MPDU_DENSITY_MSK (0x1c) +#define HT_MPDU_DENSITY_POS (2) + +#define HT_RATESET_NUM (16) +#define HT_1CHAIN_RATE_MIN_IDX (0x0) +#define HT_1CHAIN_RATE_MAX_IDX (0x7) +#define HT_2CHAIN_RATE_MIN_IDX (0x8) +#define HT_2CHAIN_RATE_MAX_IDX (0xf) + +struct iwp_ampdu_param { + uint8_t factor; + uint8_t density; +}; + +typedef struct iwp_ht_conf { + uint8_t ht_support; + uint16_t cap; + struct iwp_ampdu_param ampdu_p; + uint8_t tx_support_mcs[HT_RATESET_NUM]; + uint8_t rx_support_mcs[HT_RATESET_NUM]; + uint8_t valid_chains; + uint8_t tx_stream_count; + uint8_t rx_stream_count; + uint8_t ht_protection; +} iwp_ht_conf_t; + +#define NO_HT_PROT (0) +#define HT_PROT_CHAN_NON_HT (1) +#define HT_PROT_FAT (2) +#define HT_PROT_ASSOC_NON_HT (3) + +/* + * HT flags for RXON command. + */ +#define RXON_FLG_CONTROL_CHANNEL_LOCATION_MSK 0x400000 +#define RXON_FLG_CONTROL_CHANNEL_LOC_LOW_MSK 0x000000 +#define RXON_FLG_CONTROL_CHANNEL_LOC_HIGH_MSK 0x400000 + +#define RXON_FLG_HT_OPERATING_MODE_POS (23) +#define RXON_FLG_HT_PROT_MSK 0x800000 +#define RXON_FLG_FAT_PROT_MSK 0x1000000 + +#define RXON_FLG_CHANNEL_MODE_POS (25) +#define RXON_FLG_CHANNEL_MODE_MSK 0x06000000 +#define RXON_FLG_CHANNEL_MODE_LEGACY_MSK 0x00000000 +#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK 0x02000000 +#define RXON_FLG_CHANNEL_MODE_MIXED_MSK 0x04000000 + +#define RXON_RX_CHAIN_DRIVER_FORCE_MSK (0x1<<0) +#define RXON_RX_CHAIN_VALID_MSK (0x7<<1) +#define RXON_RX_CHAIN_VALID_POS (1) +#define RXON_RX_CHAIN_FORCE_SEL_MSK (0x7<<4) +#define RXON_RX_CHAIN_FORCE_SEL_POS (4) +#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7<<7) +#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7) +#define RXON_RX_CHAIN_CNT_MSK (0x3<<10) +#define RXON_RX_CHAIN_CNT_POS (10) +#define RXON_RX_CHAIN_MIMO_CNT_MSK (0x3<<12) +#define RXON_RX_CHAIN_MIMO_CNT_POS (12) +#define RXON_RX_CHAIN_MIMO_FORCE_MSK (0x1<<14) +#define RXON_RX_CHAIN_MIMO_FORCE_POS (14) +#define RXON_RX_CHAIN_A_MSK (1) +#define RXON_RX_CHAIN_B_MSK (2) +#define RXON_RX_CHAIN_C_MSK (4) + +/* + * Generic queue structure + * + * Contains common data for Rx and Tx queues + */ +#define TFD_CTL_COUNT_SET(n) (n<<24) +#define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7) +#define TFD_CTL_PAD_SET(n) (n<<28) +#define TFD_CTL_PAD_GET(ctl) (ctl>>28) + +#define TFD_TX_CMD_SLOTS 64 +#define TFD_CMD_SLOTS 32 + +/* + * Tx/Rx Queues + * + * Most communication between driver and SP is via queues of data buffers. + * For example, all commands that the driver issues to device's embedded + * controller (uCode) are via the command queue (one of the Tx queues). All + * uCode command responses/replies/notifications, including Rx frames, are + * conveyed from uCode to driver via the Rx queue. + * + * Most support for these queues, including handshake support, resides in + * structures in host DRAM, shared between the driver and the device. When + * allocating this memory, the driver must make sure that data written by + * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's + * cache memory), so DRAM and cache are consistent, and the device can + * immediately see changes made by the driver. + * + * SP supports up to 16 DRAM-based Tx queues, and services these queues via + * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array + * in DRAM containing 256 Transmit Frame Descriptors (TFDs). + */ +#define IWP_MAX_WIN_SIZE 64 +#define IWP_QUEUE_SIZE 256 +#define IWP_NUM_FIFOS 7 +#define IWP_NUM_QUEUES 20 +#define IWP_CMD_QUEUE_NUM 4 +#define IWP_KW_SIZE 0x1000 /* 4k */ +#define IWP_CMD_FIFO_NUM 7 + +struct iwp_rate { + union { + struct { + uint8_t rate; + uint8_t flags; + uint16_t ext_flags; + } s; + uint32_t rate_n_flags; + } r; +}; + +struct iwp_dram_scratch { + uint8_t try_cnt; + uint8_t bt_kill_cnt; + uint16_t reserved; +}; + + +struct iwp_tx_power { + uint8_t tx_gain; /* gain for analog radio */ + uint8_t dsp_atten; /* gain for DSP */ +}; + + +union iwp_tx_power_triple_stream { + struct { + uint8_t radio_tx_gain[3]; + uint8_t reserved1; + uint8_t dsp_predis_atten[3]; + uint8_t reserved2; + }s; + uint32_t val1; + uint32_t val2; +}; + +struct iwp_tx_power_db { + union iwp_tx_power_triple_stream ht_ofdm_power[24]; + union iwp_tx_power_triple_stream cck_power[2]; +}; + +typedef struct iwp_tx_power_table_cmd { + uint8_t band; + uint8_t pa_measurements; + uint8_t channel; + uint8_t max_mcs; + struct iwp_tx_power_db db; +} iwp_tx_power_table_cmd_t; + +/* + * Hardware rate scaling set by iwp_ap_lq function. + * Given a particular initial rate and mode, the driver uses the + * following formula to fill the rs_table[LINK_QUAL_MAX_RETRY_NUM] + * rate table in the Link Quality command: + * + * 1) If using High-throughput(HT)(SISO or MIMO) initial rate: + * a) Use this same initial rate for first 3 entries. + * b) Find next lower available rate using same mode(SISO or MIMO), + * use for next 3 entries. If no lower rate available, switch to + * legacy mode(no FAT channel, no MIMO, no short guard interval). + * c) If using MIMO, set command's mimo_delimeter to number of + * entries using MIMO(3 or 6). + * d) After trying 2 HT rates, switch to legacy mode(no FAT channel, + * no MIMO, no short qguard interval), at the next lower bit rate + * (e.g. if second HT bit rate was 54, try 48 legacy),and follow + * legacy procedure for remaining table entries. + * + * 2) If using legacy initial rate: + * a) Use the initial rate for only one entry. + * b) For each following entry, reduce the rate to next lower available + * rate, until reaching the lowest available rate. + * c) When reducing rate, also switch antenna selection. + * b) Once lowest available rate is reached, repreat this rate until + * rate table is filled(16 entries),switching antenna each entry. + */ + +/* + * OFDM HT rate masks + */ +#define R_MCS_6M_MSK 0x1 +#define R_MCS_12M_MSK 0x2 +#define R_MCS_18M_MSK 0x4 +#define R_MCS_24M_MSK 0x8 +#define R_MCS_36M_MSK 0x10 +#define R_MCS_48M_MSK 0x20 +#define R_MCS_54M_MSK 0x40 +#define R_MCS_60M_MSK 0x80 +#define R_MCS_12M_DUAL_MSK 0x100 +#define R_MCS_24M_DUAL_MSK 0x200 +#define R_MCS_36M_DUAL_MSK 0x400 +#define R_MCS_48M_DUAL_MSK 0x800 + +#define RATE_MCS_CODE_MSK 0x7 +#define RATE_MCS_MIMO_POS 3 +#define RATE_MCS_MIMO_MSK 0x8 +#define RATE_MCS_HT_DUP_POS 5 +#define RATE_MCS_HT_DUP_MSK 0x20 +#define RATE_MCS_FLAGS_POS 8 +#define RATE_MCS_HT_POS 8 +#define RATE_MCS_HT_MSK 0x100 +#define RATE_MCS_CCK_POS 9 +#define RATE_MCS_CCK_MSK 0x200 +#define RATE_MCS_GF_POS 10 +#define RATE_MCS_GF_MSK 0x400 + +#define RATE_MCS_FAT_POS 11 +#define RATE_MCS_FAT_MSK 0x800 +#define RATE_MCS_DUP_POS 12 +#define RATE_MCS_DUP_MSK 0x1000 +#define RATE_MCS_SGI_POS 13 +#define RATE_MCS_SGI_MSK 0x2000 + +#define EEPROM_SEM_TIMEOUT 10 +#define EEPROM_SEM_RETRY_LIMIT 1000 + +/* + * Antenna masks: + * bit14:15 01 B inactive, A active + * 10 B active, A inactive + * 11 Both active + */ +#define RATE_MCS_ANT_A_POS 14 +#define RATE_MCS_ANT_B_POS 15 +#define RATE_MCS_ANT_A_MSK 0x4000 +#define RATE_MCS_ANT_B_MSK 0x8000 +#define RATE_MCS_ANT_AB_MSK 0xc000 + +#define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) +#define is_siso(tbl) (((tbl) == LQ_SISO)) +#define is_mimo(tbl) (((tbl) == LQ_MIMO)) +#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) +#define is_a_band(tbl) (((tbl) == LQ_A)) +#define is_g_and(tbl) (((tbl) == LQ_G)) + +/* + * RS_NEW_API: only TLC_RTS remains and moved to bit 0 + */ +#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0) + +#define LINK_QUAL_AC_NUM 4 +#define LINK_QUAL_MAX_RETRY_NUM 16 + +#define LINK_QUAL_ANT_A_MSK (1<<0) +#define LINK_QUAL_ANT_B_MSK (1<<1) +#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK) + +struct iwp_link_qual_general_params { + uint8_t flags; + uint8_t mimo_delimiter; + uint8_t single_stream_ant_msk; + uint8_t dual_stream_ant_msk; + uint8_t start_rate_index[LINK_QUAL_AC_NUM]; +}; + +struct iwp_link_qual_agg_params { + uint16_t agg_time_limit; + uint8_t agg_dis_start_th; + uint8_t agg_frame_cnt_limit; + uint32_t reserved; +}; + +typedef struct iwp_link_quality_cmd { + uint8_t sta_id; + uint8_t reserved1; + uint16_t control; + struct iwp_link_qual_general_params general_params; + struct iwp_link_qual_agg_params agg_params; + uint32_t rate_n_flags[LINK_QUAL_MAX_RETRY_NUM]; + uint32_t reserved2; +} iwp_link_quality_cmd_t; + +struct iwp_rx_mpdu_body_size { + uint16_t byte_count; + uint16_t reserved; +}; + +typedef struct iwp_rx_phy_res { + uint8_t non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ + uint8_t cfg_phy_cnt; /* configurable DSP phy data byte count */ + uint8_t stat_id; /* configurable DSP phy data set ID */ + uint8_t reserved1; + uint32_t timestampl; /* TSF at on air rise */ + uint32_t timestamph; + uint32_t beacon_time_stamp; /* beacon at on-air rise */ + uint16_t phy_flags; /* general phy flags: band, modulation, ... */ + uint16_t channel; /* channel number */ + /* for various implementations of non_cfg_phy */ + uint8_t non_cfg_phy[32]; + struct iwp_rate rate; /* rate in ucode internal format */ + uint16_t byte_count; /* frame's byte-count */ + uint16_t reserved3; +} iwp_rx_phy_res_t; + +struct iwp_rx_mpdu_res_start { + uint16_t byte_count; + uint16_t reserved; +}; + +#define IWP_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ +#define IWP_AGC_DB_POS (7) + +#define IWP_RX_RES_PHY_CNT (8) +#define IWP_RX_RES_AGC_IDX (1) +#define IWP_RX_RES_RSSI_AB_IDX (2) +#define IWP_RX_RES_RSSI_C_IDX (3) +#define IWP_OFDM_AGC_MSK (0xFE00) +#define IWP_OFDM_AGC_BIT_POS (9) +#define IWP_OFDM_RSSI_A_MSK (0x00FF) +#define IWP_OFDM_RSSI_A_BIT_POS (0) +#define IWP_OFDM_RSSI_B_MSK (0xFF0000) +#define IWP_OFDM_RSSI_B_BIT_POS (16) +#define IWP_OFDM_RSSI_C_MSK (0x00FF) +#define IWP_OFDM_RSSI_C_BIT_POS (0) +#define IWP_RSSI_OFFSET (44) + +/* + * Fixed (non-configurable) rx data from phy + */ +struct iwp_rx_non_cfg_phy { + uint32_t non_cfg_phy[IWP_RX_RES_PHY_CNT]; /* upto 8 phy entries */ +}; + +/* + * Byte Count Table Entry + * + * Bit fields: + * 15-12: reserved + * 11- 0: total to-be-transmitted byte count of frame (does not include command) + */ +struct iwp_queue_byte_cnt_entry { + uint16_t val; +}; + +/* + * Byte Count table + * + * Each Tx queue uses a byte-count table containing 320 entries: + * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that + * duplicate the first 64 entries (to avoid wrap-around within a Tx window; + * max Tx window is 64 TFDs). + * + * When driver sets up a new TFD, it must also enter the total byte count + * of the frame to be transmitted into the corresponding entry in the byte + * count table for the chosen Tx queue. If the TFD index is 0-63, the driver + * must duplicate the byte count entry in corresponding index 256-319. + * + * "dont_care" padding puts each byte count table on a 1024-byte boundary; + * SP assumes tables are separated by 1024 bytes. + */ +struct iwp_sched_queue_byte_cnt_tbl { + struct iwp_queue_byte_cnt_entry tfd_offset[IWP_QUEUE_SIZE + + IWP_MAX_WIN_SIZE]; +}; + +/* + * struct iwp_shared, handshake area for Tx and Rx + * + * For convenience in allocating memory, this structure combines 2 areas of + * DRAM which must be shared between driver and SP. These do not need to + * be combined, if better allocation would result from keeping them separate: + * TODO: Split these; carried over from 3945, doesn't work well for SP. + * + * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for + * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell SP where to find + * the first of these tables. SP assumes tables are 1024 bytes apart. + * + * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses + * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell SP where to find this area. + * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD) + * that has been filled by the SP. + * + * Bit fields val0: + * 31-12: Not used + * 11- 0: Index of last filled Rx buffer descriptor (SP writes, driver reads) + * + * Bit fields val1: + * 31- 0: Not used + */ +typedef struct iwp_shared { + struct iwp_sched_queue_byte_cnt_tbl + queues_byte_cnt_tbls[IWP_NUM_QUEUES]; + uint32_t val0; + uint32_t val1; + uint32_t padding1; /* so that allocation will be aligned to 16B */ + uint32_t padding2; +} iwp_shared_t; + + +/* + * struct iwp_tfd_frame_data + * + * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. + * Each buffer must be on dword boundary. + * Up to 10 iwp_tfd_frame_data structures, describing up to 20 buffers, + * may be filled within a TFD (iwp_tfd_frame). + * + * Bit fields in tb1_addr: + * 31- 0: Tx buffer 1 address bits [31:0] + * + * Bit fields in val1: + * 31-16: Tx buffer 2 address bits [15:0] + * 15- 4: Tx buffer 1 length (bytes) + * 3- 0: Tx buffer 1 address bits [32:32] + * + * Bit fields in val2: + * 31-20: Tx buffer 2 length (bytes) + * 19- 0: Tx buffer 2 address bits [35:16] + */ +struct iwp_tfd_frame_data { + uint32_t tb1_addr; + uint32_t val1; + uint32_t val2; +}; + +typedef struct iwp_tx_desc { + uint32_t val0; + struct iwp_tfd_frame_data pa[10]; + uint32_t reserved; +} iwp_tx_desc_t; + +struct agg_tx_status { + uint16_t status; + uint16_t sequence; +}; + +typedef struct iwp_tx_stat { + uint8_t frame_count; + uint8_t bt_kill_count; + uint8_t nrts; + uint8_t ntries; + struct iwp_rate rate; + uint16_t duration; + uint16_t reserved; + uint32_t pa_power1; + uint32_t pa_power2; + uint32_t tfd_info; + uint16_t seq_ctl; + uint16_t byte_cnt; + uint32_t tlc_info; + struct agg_tx_status status; +} iwp_tx_stat_t; + +struct iwp_cmd_header { + uint8_t type; + uint8_t flags; + uint8_t idx; + uint8_t qid; +}; + +typedef struct iwp_rx_desc { + uint32_t len; + struct iwp_cmd_header hdr; +} iwp_rx_desc_t; + +typedef struct iwp_rx_stat { + uint8_t len; + uint8_t id; + uint8_t rssi; /* received signal strength */ + uint8_t agc; /* access gain control */ + uint16_t signal; + uint16_t noise; +} iwp_rx_stat_t; + +typedef struct iwp_rx_head { + uint16_t chan; + uint16_t flags; + uint8_t reserved; + uint8_t rate; + uint16_t len; +} iwp_rx_head_t; + +typedef struct iwp_rx_tail { + uint32_t flags; + uint32_t timestampl; + uint32_t timestamph; + uint32_t tbeacon; +} iwp_rx_tail_t; + +enum { + IWP_AP_ID = 0, + IWP_MULTICAST_ID, + IWP_STA_ID, + IWP_BROADCAST_ID = 15, + IWP_STATION_COUNT = 16, + IWP_INVALID_STATION +}; + +/* + * key flags + */ +enum { + STA_KEY_FLG_ENCRYPT_MSK = 0x7, + STA_KEY_FLG_NO_ENC = 0x0, + STA_KEY_FLG_WEP = 0x1, + STA_KEY_FLG_CCMP = 0x2, + STA_KEY_FLG_TKIP = 0x3, + + STA_KEY_FLG_KEYID_POS = 8, + STA_KEY_FLG_INVALID = 0x0800, +}; + +/* + * modify flags + */ +enum { + STA_MODIFY_KEY_MASK = 0x01, + STA_MODIFY_TID_DISABLE_TX = 0x02, + STA_MODIFY_TX_RATE_MSK = 0x04 +}; + +enum { + RX_RES_STATUS_NO_CRC32_ERROR = (1 << 0), + RX_RES_STATUS_NO_RXE_OVERFLOW = (1 << 1), +}; + +enum { + RX_RES_PHY_FLAGS_BAND_24_MSK = (1 << 0), + RX_RES_PHY_FLAGS_MOD_CCK_MSK = (1 << 1), + RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK = (1 << 2), + RX_RES_PHY_FLAGS_NARROW_BAND_MSK = (1 << 3), + RX_RES_PHY_FLAGS_ANTENNA_MSK = 0xf0, + + RX_RES_STATUS_SEC_TYPE_MSK = (0x7 << 8), + RX_RES_STATUS_SEC_TYPE_NONE = (STA_KEY_FLG_NO_ENC << 8), + RX_RES_STATUS_SEC_TYPE_WEP = (STA_KEY_FLG_WEP << 8), + RX_RES_STATUS_SEC_TYPE_TKIP = (STA_KEY_FLG_TKIP << 8), + RX_RES_STATUS_SEC_TYPE_CCMP = (STA_KEY_FLG_CCMP << 8), + + RX_RES_STATUS_DECRYPT_TYPE_MSK = (0x3 << 11), + RX_RES_STATUS_NOT_DECRYPT = (0x0 << 11), + RX_RES_STATUS_DECRYPT_OK = (0x3 << 11), + RX_RES_STATUS_BAD_ICV_MIC = (0x1 << 11), + RX_RES_STATUS_BAD_KEY_TTAK = (0x2 << 11), +}; + +enum { + REPLY_ALIVE = 0x1, + REPLY_ERROR = 0x2, + + /* RXON state commands */ + REPLY_RXON = 0x10, + REPLY_RXON_ASSOC = 0x11, + REPLY_QOS_PARAM = 0x13, + REPLY_RXON_TIMING = 0x14, + + /* Multi-Station support */ + REPLY_ADD_STA = 0x18, + REPLY_REMOVE_STA = 0x19, + REPLY_REMOVE_ALL_STA = 0x1a, + + /* RX, TX */ + + REPLY_TX = 0x1c, + + /* timers commands */ + REPLY_BCON = 0x27, + + REPLY_SHUTDOWN = 0x40, + + /* MISC commands */ + REPLY_RATE_SCALE = 0x47, + REPLY_LEDS_CMD = 0x48, + REPLY_TX_LINK_QUALITY_CMD = 0x4e, + + COEX_PRIORITY_TABLE_CMD = 0x5a, + CALIBRATION_CFG_CMD = 0x65, + CALIBRATION_RES_NOTIFICATION = 0x66, + CALIBRATION_COMPLETE_NOTIFICATION = 0x67, + + /* 802.11h related */ + RADAR_NOTIFICATION = 0x70, + REPLY_QUIET_CMD = 0x71, + REPLY_CHANNEL_SWITCH = 0x72, + CHANNEL_SWITCH_NOTIFICATION = 0x73, + REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74, + SPECTRUM_MEASURE_NOTIFICATION = 0x75, + + /* Power Management *** */ + POWER_TABLE_CMD = 0x77, + PM_SLEEP_NOTIFICATION = 0x7A, + PM_DEBUG_STATISTIC_NOTIFIC = 0x7B, + + /* Scan commands and notifications */ + REPLY_SCAN_CMD = 0x80, + REPLY_SCAN_ABORT_CMD = 0x81, + + SCAN_START_NOTIFICATION = 0x82, + SCAN_RESULTS_NOTIFICATION = 0x83, + SCAN_COMPLETE_NOTIFICATION = 0x84, + + /* IBSS/AP commands */ + BEACON_NOTIFICATION = 0x90, + REPLY_TX_BEACON = 0x91, + WHO_IS_AWAKE_NOTIFICATION = 0x94, + + QUIET_NOTIFICATION = 0x96, + REPLY_TX_PWR_TABLE_CMD = 0x97, + MEASURE_ABORT_NOTIFICATION = 0x99, + + REPLY_CALIBRATION_TUNE = 0x9a, + + /* BT config command */ + REPLY_BT_CONFIG = 0x9b, + REPLY_STATISTICS_CMD = 0x9c, + STATISTICS_NOTIFICATION = 0x9d, + + /* RF-KILL commands and notifications *** */ + REPLY_CARD_STATE_CMD = 0xa0, + CARD_STATE_NOTIFICATION = 0xa1, + + /* Missed beacons notification */ + MISSED_BEACONS_NOTIFICATION = 0xa2, + MISSED_BEACONS_NOTIFICATION_TH_CMD = 0xa3, + + REPLY_CT_KILL_CONFIG_CMD = 0xa4, + SENSITIVITY_CMD = 0xa8, + REPLY_PHY_CALIBRATION_CMD = 0xb0, + REPLY_RX_PHY_CMD = 0xc0, + REPLY_RX_MPDU_CMD = 0xc1, + REPLY_SP_RX = 0xc3, + REPLY_COMPRESSED_BA = 0xc5, + REPLY_MAX = 0xff +}; + +typedef struct iwp_cmd { + struct iwp_cmd_header hdr; + uint8_t data[1024]; +} iwp_cmd_t; + +/* + * Alive Command & Response + */ +#define UCODE_VALID_OK (0x1) +#define INITIALIZE_SUBTYPE (9) + +struct iwp_alive_resp { + uint8_t ucode_minor; + uint8_t ucode_major; + uint16_t reserved1; + uint8_t sw_rev[8]; + uint8_t ver_type; + uint8_t ver_subtype; + uint16_t reserved2; + uint32_t log_event_table_ptr; + uint32_t error_event_table_ptr; + uint32_t timestamp; + uint32_t is_valid; +}; + +struct iwp_init_alive_resp { + struct iwp_alive_resp s; + /* calibration values from "initialize" uCode */ + uint32_t voltage; /* signed */ + uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */ + uint32_t therm_r2[2]; /* signed */ + uint32_t therm_r3[2]; /* signed */ + uint32_t therm_r4[2]; /* signed */ + /* + * signed MIMO gain comp, 5 freq groups, 2 Tx chains + */ + uint32_t tx_atten[5][2]; +}; + +/* + * Rx config defines & structure + */ +/* + * rx_config device types + */ +enum { + RXON_DEV_TYPE_AP = 1, + RXON_DEV_TYPE_ESS = 3, + RXON_DEV_TYPE_IBSS = 4, + RXON_DEV_TYPE_SNIFFER = 6, +}; + +/* + * rx_config flags + */ +enum { + /* band & modulation selection */ + RXON_FLG_BAND_24G_MSK = (1 << 0), + RXON_FLG_CCK_MSK = (1 << 1), + /* auto detection enable */ + RXON_FLG_AUTO_DETECT_MSK = (1 << 2), + /* TGg protection when tx */ + RXON_FLG_TGG_PROTECT_MSK = (1 << 3), + /* cck short slot & preamble */ + RXON_FLG_SHORT_SLOT_MSK = (1 << 4), + RXON_FLG_SHORT_PREAMBLE_MSK = (1 << 5), + /* antenna selection */ + RXON_FLG_DIS_DIV_MSK = (1 << 7), + RXON_FLG_ANT_SEL_MSK = 0x0f00, + RXON_FLG_ANT_A_MSK = (1 << 8), + RXON_FLG_ANT_B_MSK = (1 << 9), + /* radar detection enable */ + RXON_FLG_RADAR_DETECT_MSK = (1 << 12), + RXON_FLG_TGJ_NARROW_BAND_MSK = (1 << 13), + /* + * rx response to host with 8-byte TSF + * (according to ON_AIR deassertion) + */ + RXON_FLG_TSF2HOST_MSK = (1 << 15), + RXON_FLG_DIS_ACQUISITION = (1 << 27), + RXON_FLG_DIS_RE_ACQUISITION = (1 << 28), + RXON_FLG_DIS_BEAMFORM = (1 << 29) +}; + +/* + * rx_config filter flags + */ +enum { + /* accept all data frames */ + RXON_FILTER_PROMISC_MSK = (1 << 0), + /* pass control & management to host */ + RXON_FILTER_CTL2HOST_MSK = (1 << 1), + /* accept multi-cast */ + RXON_FILTER_ACCEPT_GRP_MSK = (1 << 2), + /* don't decrypt uni-cast frames */ + RXON_FILTER_DIS_DECRYPT_MSK = (1 << 3), + /* don't decrypt multi-cast frames */ + RXON_FILTER_DIS_GRP_DECRYPT_MSK = (1 << 4), + /* STA is associated */ + RXON_FILTER_ASSOC_MSK = (1 << 5), + /* transfer to host non bssid beacons in associated state */ + RXON_FILTER_BCON_AWARE_MSK = (1 << 6) +}; + + +/* + * structure for RXON Command & Response + */ +typedef struct iwp_rxon_cmd { + uint8_t node_addr[IEEE80211_ADDR_LEN]; + uint16_t reserved1; + uint8_t bssid[IEEE80211_ADDR_LEN]; + uint16_t reserved2; + uint8_t wlap_bssid[IEEE80211_ADDR_LEN]; + uint16_t reserved3; + uint8_t dev_type; + uint8_t air_propagation; + uint16_t rx_chain; + uint8_t ofdm_basic_rates; + uint8_t cck_basic_rates; + uint16_t assoc_id; + uint32_t flags; + uint32_t filter_flags; + uint16_t chan; + uint8_t ofdm_ht_single_stream_basic_rates; + uint8_t ofdm_ht_dual_stream_basic_rates; + uint8_t ofdm_ht_triple_stream_basic_rates; + uint8_t reserved4; + uint16_t acquisition_data; + uint16_t reserved5; +} iwp_rxon_cmd_t; + +typedef struct iwp_compressed_ba_resp { + uint32_t sta_addr_lo32; + uint16_t sta_addr_hi16; + uint16_t reserved; + uint8_t sta_id; + uint8_t tid; + uint16_t ba_seq_ctl; + uint32_t ba_bitmap0; + uint32_t ba_bitmap1; + uint16_t scd_flow; + uint16_t scd_ssn; +} iwp_compressed_ba_resp_t; + +#define PHY_CALIBRATE_DIFF_GAIN_CMD (7) +#define PHY_CALIBRATE_LO_CMD (9) +#define PHY_CALIBRATE_TX_IQ_CMD (11) +#define PHY_CALIBRATE_CRYSTAL_FRQ_CMD (15) +#define PHY_CALIBRATE_BASE_BAND_CMD (16) +#define PHY_CALIBRATE_TX_IQ_PERD_CMD (17) +#define HD_TABLE_SIZE (11) + +/* + * Param table within SENSITIVITY_CMD + */ +#define HD_MIN_ENERGY_CCK_DET_INDEX (0) +#define HD_MIN_ENERGY_OFDM_DET_INDEX (1) +#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) +#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) +#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) +#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) +#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) +#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) +#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) +#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) +#define HD_OFDM_ENERGY_TH_IN_INDEX (10) + +typedef struct iwp_sensitivity_cmd { + uint16_t control; + uint16_t table[HD_TABLE_SIZE]; +} iwp_sensitivity_cmd_t; + +typedef struct iwp_calibration_cmd { + uint8_t opCode; + uint8_t flags; + uint16_t reserved; + char diff_gain_a; + char diff_gain_b; + char diff_gain_c; + uint8_t reserved1; +} iwp_calibation_cmd_t; + + +struct iwp_calib_hdr { + uint8_t op_code; + uint8_t first_group; + uint8_t groups_num; + uint8_t data_valid; +}; + +#define FH_RSCSR_FRAME_SIZE_MASK (0x00003FFF) + +struct iwp_calib_results { + void *tx_iq_res; + uint32_t tx_iq_res_len; + void *tx_iq_perd_res; + uint32_t tx_iq_perd_res_len; + void *lo_res; + uint32_t lo_res_len; + void *base_band_res; + uint32_t base_band_res_len; +}; + +#define IWP_CALIB_INIT_CFG_ALL (0xFFFFFFFF) + +struct iwp_calib_cfg_elmnt_s { + uint32_t is_enable; + uint32_t start; + uint32_t send_res; + uint32_t apply_res; + uint32_t resered; +}; + +struct iwp_calib_cfg_status_s { + struct iwp_calib_cfg_elmnt_s once; + struct iwp_calib_cfg_elmnt_s perd; + uint32_t flags; +}; + +struct iwp_calib_cfg_cmd { + struct iwp_calib_cfg_status_s ucd_calib_cfg; + struct iwp_calib_cfg_status_s drv_calib_cfg; + uint32_t reserved1; +}; + +struct iwp_cal_crystal_freq { + uint8_t cap_pin1; + uint8_t cap_pin2; +}; + +typedef struct iwp_calibration_crystal_cmd { + uint8_t opCode; + uint8_t first_group; + uint8_t num_group; + uint8_t all_data_valid; + struct iwp_cal_crystal_freq data; +} iwp_calibration_crystal_cmd_t; + +#define COEX_NUM_OF_EVENTS (16) + +struct iwp_wimax_coex_event_entry { + uint8_t request_prio; + uint8_t win_medium_prio; + uint8_t reserved; + uint8_t flags; +}; + +typedef struct iwp_wimax_coex_cmd { + uint8_t flags; + uint8_t reserved[3]; + struct iwp_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS]; +} iwp_wimax_coex_cmd_t; + +typedef struct iwp_missed_beacon_notif { + uint32_t consequtive_missed_beacons; + uint32_t total_missed_becons; + uint32_t num_expected_beacons; + uint32_t num_recvd_beacons; +} iwp_missed_beacon_notif_t; + +typedef struct iwp_ct_kill_config { + uint32_t reserved; + uint32_t critical_temperature_M; + uint32_t critical_temperature_R; +} iwp_ct_kill_config_t; + +/* + * structure for command IWP_CMD_ASSOCIATE + */ +typedef struct iwp_assoc { + uint32_t flags; + uint32_t filter; + uint8_t ofdm_mask; + uint8_t cck_mask; + uint8_t ofdm_ht_single_stream_basic_rates; + uint8_t ofdm_ht_dual_stream_basic_rates; + uint16_t rx_chain_select_flags; + uint16_t reserved; +} iwp_assoc_t; + +/* + * structure for command IWP_CMD_TSF + */ +typedef struct iwp_cmd_tsf { + uint32_t timestampl; + uint32_t timestamph; + uint16_t bintval; + uint16_t atim; + uint32_t binitval; + uint16_t lintval; + uint16_t reserved; +} iwp_cmd_tsf_t; + +/* + * structure for IWP_CMD_ADD_NODE + */ +#define STA_MODE_ADD_MSK (0) +#define STA_MODE_MODIFY_MSK (1) + +#define STA_FLG_RTS_MIMO_PROT (1 << 17) +#define STA_FLG_MAX_AMPDU_POS (19) +#define STA_FLG_AMPDU_DENSITY_POS (23) +#define STA_FLG_FAT_EN (1 << 21) + +#define STA_MODIFY_KEY_MASK (0x01) +#define STA_MODIFY_TID_DISABLE_TX (0x02) +#define STA_MODIFY_TX_RATE_MSK (0x04) +#define STA_MODIFY_ADDBA_TID_MSK (0x08) +#define STA_MODIFY_DELBA_TID_MSK (0x10) + +struct sta_id_modify { + uint8_t addr[6]; + uint16_t reserved1; + uint8_t sta_id; + uint8_t modify_mask; + uint16_t reserved2; +}; + +struct iwp_keyinfo { + uint16_t key_flags; + uint8_t tkip_rx_tsc_byte2; + uint8_t reserved1; + uint16_t tkip_rx_ttak[5]; + uint8_t key_offset; + uint8_t reserved2; + uint8_t key[16]; + uint32_t tx_secur_seq_cnt1; + uint32_t tx_secur_seq_cnt2; + uint32_t hw_tkip_mic_rx_key1; + uint32_t hw_tkip_mic_rx_key2; + uint32_t hw_tkip_mic_tx_key1; + uint32_t hw_tkip_mic_tx_key2; +}; +typedef struct iwp_add_sta { + uint8_t mode; + uint8_t reserved[3]; + struct sta_id_modify sta; + struct iwp_keyinfo key; + uint32_t station_flags; + uint32_t station_flags_msk; + uint16_t disable_tx; + uint16_t reserved1; + uint8_t add_immediate_ba_tid; + uint8_t remove_immediate_ba_tid; + uint16_t add_immediate_ba_ssn; + uint32_t reserved2; +} iwp_add_sta_t; + +typedef struct iwp_rem_sta { + uint8_t num_sta; /* number of removed stations */ + uint8_t reserved1[3]; + uint8_t addr[6]; /* MAC address of the first station */ + uint8_t reserved2[2]; +} iwp_rem_sta_t; + +/* + * Tx flags + */ +enum { + TX_CMD_FLG_RTS_MSK = (1 << 1), + TX_CMD_FLG_CTS_MSK = (1 << 2), + TX_CMD_FLG_ACK_MSK = (1 << 3), + TX_CMD_FLG_STA_RATE_MSK = (1 << 4), + TX_CMD_FLG_IMM_BA_RSP_MASK = (1 << 6), + TX_CMD_FLG_FULL_TXOP_PROT_MSK = (1 << 7), + TX_CMD_FLG_ANT_SEL_MSK = 0xf00, + TX_CMD_FLG_ANT_A_MSK = (1 << 8), + TX_CMD_FLG_ANT_B_MSK = (1 << 9), + + /* ucode ignores BT priority for this frame */ + TX_CMD_FLG_BT_DIS_MSK = (1 << 12), + + /* ucode overrides sequence control */ + TX_CMD_FLG_SEQ_CTL_MSK = (1 << 13), + + /* signal that this frame is non-last MPDU */ + TX_CMD_FLG_MORE_FRAG_MSK = (1 << 14), + + /* calculate TSF in outgoing frame */ + TX_CMD_FLG_TSF_MSK = (1 << 16), + + /* activate TX calibration. */ + TX_CMD_FLG_CALIB_MSK = (1 << 17), + + /* + * signals that 2 bytes pad was inserted + * after the MAC header + */ + TX_CMD_FLG_MH_PAD_MSK = (1 << 20), + + /* HCCA-AP - disable duration overwriting. */ + TX_CMD_FLG_DUR_MSK = (1 << 25), +}; + + +/* + * structure for command IWP_CMD_TX_DATA + */ +typedef struct iwp_tx_cmd { + uint16_t len; + uint16_t next_frame_len; + uint32_t tx_flags; + struct iwp_dram_scratch scratch; + struct iwp_rate rate; + uint8_t sta_id; + uint8_t sec_ctl; + uint8_t initial_rate_index; + uint8_t reserved; + uint8_t key[16]; + uint16_t next_frame_flags; + uint16_t reserved2; + union { + uint32_t life_time; + uint32_t attempt; + } stop_time; + uint32_t dram_lsb_ptr; + uint8_t dram_msb_ptr; + uint8_t rts_retry_limit; + uint8_t data_retry_limit; + uint8_t tid_tspec; + union { + uint16_t pm_frame_timeout; + uint16_t attempt_duration; + } timeout; + uint16_t driver_txop; +} iwp_tx_cmd_t; + + +/* + * structure for command "TX beacon" + */ + +typedef struct iwp_tx_beacon_cmd { + iwp_tx_cmd_t config; + uint16_t tim_idx; + uint8_t tim_size; + uint8_t reserved; + uint8_t bcon_frame[2342]; +} iwp_tx_beacon_cmd_t; + + +/* + * LEDs Command & Response + * REPLY_LEDS_CMD = 0x48 (command, has simple generic response) + * + * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), + * this command turns it on or off, or sets up a periodic blinking cycle. + */ +typedef struct iwp_led_cmd { + uint32_t interval; /* "interval" in uSec */ + uint8_t id; /* 1: Activity, 2: Link, 3: Tech */ + /* + * # intervals off while blinking; + * "0", with > 0 "on" value, turns LED on + */ + uint8_t off; + /* + * # intervals on while blinking; + * "0", regardless of "off", turns LED off + */ + uint8_t on; + uint8_t reserved; +} iwp_led_cmd_t; + +/* + * structure for IWP_CMD_SET_POWER_MODE + */ +typedef struct iwp_powertable_cmd { + uint16_t flags; + uint8_t keep_alive_seconds; + uint8_t debug_flags; + uint32_t rx_timeout; + uint32_t tx_timeout; + uint32_t sleep[5]; + uint32_t keep_alive_beacons; +} iwp_powertable_cmd_t; + +struct iwp_ssid_ie { + uint8_t id; + uint8_t len; + uint8_t ssid[32]; +}; +/* + * structure for command IWP_CMD_SCAN + */ +typedef struct iwp_scan_hdr { + uint16_t len; + uint8_t reserved1; + uint8_t nchan; + /* + * dwell only this long on quiet chnl + * (active scan) + */ + uint16_t quiet_time; + uint16_t quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ + uint16_t good_crc_th; /* passive -> active promotion threshold */ + uint16_t rx_chain; + /* + * max usec to be out of associated (service) + * chnl + */ + uint32_t max_out_time; + /* + * pause scan this long when returning to svc + * chnl. + * SP -- 31:22 # beacons, 21:0 additional usec. + */ + uint32_t suspend_time; + uint32_t flags; + uint32_t filter_flags; + struct iwp_tx_cmd tx_cmd; + struct iwp_ssid_ie direct_scan[20]; + /* followed by probe request body */ + /* followed by nchan x iwp_scan_chan */ +} iwp_scan_hdr_t; + +typedef struct iwp_scan_chan { + uint32_t type; + uint16_t chan; + struct iwp_tx_power tpc; + uint16_t active_dwell; /* dwell time */ + uint16_t passive_dwell; /* dwell time */ +} iwp_scan_chan_t; + +/* + * structure for IWP_CMD_BLUETOOTH + */ +typedef struct iwp_bt_cmd { + uint8_t flags; + uint8_t lead_time; + uint8_t max_kill; + uint8_t reserved; + uint32_t kill_ack_mask; + uint32_t kill_cts_mask; +} iwp_bt_cmd_t; + +typedef struct iwp_wme_param { + uint8_t aifsn; + uint8_t cwmin_e; + uint8_t cwmax_e; + uint16_t txop; +} iwp_wme_param_t; +/* + * QoS parameter command (REPLY_QOS_PARAM = 0x13) + * FIFO0-background, FIFO1-best effort, FIFO2-video, FIFO3-voice + */ + +struct iwp_edca_param { + uint16_t cw_min; + uint16_t cw_max; + uint8_t aifsn; + uint8_t reserved; + uint16_t txop; +}; + +typedef struct iwp_qos_param_cmd { + uint32_t flags; + struct iwp_edca_param ac[AC_NUM]; +} iwp_qos_param_cmd_t; + +/* + * firmware image header + */ +typedef struct iwp_firmware_hdr { + uint32_t version; + uint32_t bld_nu; + uint32_t textsz; + uint32_t datasz; + uint32_t init_textsz; + uint32_t init_datasz; + uint32_t bootsz; +} iwp_firmware_hdr_t; + +/* + * structure for IWP_START_SCAN notification + */ +typedef struct iwp_start_scan { + uint32_t timestampl; + uint32_t timestamph; + uint32_t tbeacon; + uint8_t chan; + uint8_t band; + uint16_t reserved; + uint32_t status; +} iwp_start_scan_t; + +/* + * structure for IWK_SCAN_COMPLETE notification + */ +typedef struct iwp_stop_scan { + uint8_t nchan; + uint8_t status; + uint8_t reserved; + uint8_t chan; + uint8_t tsf; +} iwp_stop_scan_t; + + +#define IWP_READ(sc, reg) \ + ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg))) + +#define IWP_WRITE(sc, reg, val) \ + ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val)) + +/* + * Driver can access peripheral registers + * and ram via HBUS_TARG_PRPH_* registers. + */ + +#define PRPH_BASE (0x00000) +#define PRPH_END (0xFFFFF) + +#define IWP_SCD_BASE (PRPH_BASE + 0xA02C00) + +#define IWP_SCD_SRAM_BASE_ADDR (IWP_SCD_BASE + 0x0) +#define IWP_SCD_DRAM_BASE_ADDR (IWP_SCD_BASE + 0x8) +#define IWP_SCD_QUEUECHAIN_SEL (IWP_SCD_BASE + 0xE8) +#define IWP_SCD_AGGR_SEL (IWP_SCD_BASE + 0x248) +#define IWP_SCD_QUEUE_RDPTR(x) (IWP_SCD_BASE + 0x68 + (x) * 4) +#define IWP_SCD_INTERRUPT_MASK (IWP_SCD_BASE + 0x108) +#define IWP_SCD_TXFACT (IWP_SCD_BASE + 0x1C) +#define IWP_SCD_QUEUE_STATUS_BITS(x) (IWP_SCD_BASE + 0x10C + (x) * 4) + +#define IWP_SCD_CONTEXT_DATA_OFFSET (0x600) +#define IWP_SCD_TX_STTS_BITMAP_OFFSET (0x7B1) +#define IWP_SCD_TRANSLATE_TBL_OFFSET (0x7E0) + +#define IWP_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) +#define IWP_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) +#define IWP_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) +#define IWP_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) + +#define IWP_SCD_QUEUECHAIN_SEL_ALL(x) (((1 << (x)) - 1) &\ + (~(1 << IWP_CMD_QUEUE_NUM))) + +#define IWP_SCD_CONTEXT_QUEUE_OFFSET(x)\ + (IWP_SCD_CONTEXT_DATA_OFFSET + (x) * 8) + +#define IWP_SCD_QUEUE_STTS_REG_POS_TXF (0) +#define IWP_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) +#define IWP_SCD_QUEUE_STTS_REG_POS_WSL (4) +#define IWP_SCD_QUEUE_STTS_REG_MSK (0x00FF0000) + +/* TX command security control */ +#define TX_CMD_SEC_WEP (0x01) +#define TX_CMD_SEC_CCM (0x02) +#define TX_CMD_SEC_TKIP (0x03) +#define TX_CMD_SEC_MSK (0x03) +#define TX_CMD_SEC_SHIFT (6) +#define TX_CMD_SEC_KEY128 (0x08) + +#define WEP_IV_LEN (4) +#define WEP_ICV_LEN (4) +#define CCMP_MIC_LEN (8) +#define TKIP_ICV_LEN (4) + +#ifdef __cplusplus +} +#endif + +#endif /* _IWP_HW_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/common/io/iwp/iwp_var.h Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,257 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +/* + * Copyright (c) 2009, Intel Corporation + * All rights reserved. + */ + +/* + * Copyright (c) 2006 + * Copyright (c) 2007 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _IWP_VAR_H +#define _IWP_VAR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define IWP_DMA_SYNC(area, flag) \ + (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ + (area).alength, (flag)) + +#define IWP_CHK_FAST_RECOVER(sc) \ + (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ + sc->sc_ic.ic_opmode == IEEE80211_M_STA) + +typedef struct iwp_dma_area { + ddi_acc_handle_t acc_hdl; /* handle for memory */ + caddr_t mem_va; /* CPU VA of memory */ + uint32_t nslots; /* number of slots */ + uint32_t size; /* size per slot */ + size_t alength; /* allocated size */ + /* >= product of above */ + ddi_dma_handle_t dma_hdl; /* DMA handle */ + offset_t offset; /* relative to handle */ + ddi_dma_cookie_t cookie; /* associated cookie */ + uint32_t ncookies; + uint32_t token; /* arbitrary identifier */ +} iwp_dma_t; + +typedef struct iwp_tx_data { + iwp_dma_t dma_data; /* for sending frames */ + iwp_tx_desc_t *desc; + uint32_t paddr_desc; + iwp_cmd_t *cmd; + uint32_t paddr_cmd; +} iwp_tx_data_t; + +typedef struct iwp_tx_ring { + iwp_dma_t dma_desc; /* for descriptor itself */ + iwp_dma_t dma_cmd; /* for command to ucode */ + iwp_tx_data_t *data; + int qid; /* ID of queue */ + int count; + int window; + int queued; + int cur; + int desc_cur; +} iwp_tx_ring_t; + +typedef struct iwp_rx_data { + iwp_dma_t dma_data; +} iwp_rx_data_t; + +typedef struct iwp_rx_ring { + iwp_dma_t dma_desc; + uint32_t *desc; + iwp_rx_data_t data[RX_QUEUE_SIZE]; + int cur; +} iwp_rx_ring_t; + + +typedef struct iwp_amrr { + ieee80211_node_t in; + uint32_t txcnt; + uint32_t retrycnt; + uint32_t success; + uint32_t success_threshold; + int recovery; + volatile uint32_t ht_mcs_idx; +} iwp_amrr_t; + +struct iwp_phy_rx { + uint8_t flag; + uint8_t reserved[3]; + uint8_t buf[128]; +}; + +struct iwp_beacon_missed { + uint32_t consecutive; + uint32_t total; + uint32_t expected; + uint32_t received; +}; + +#define PHY_MODE_G (0x1) +#define PHY_MODE_A (0x2) +#define PHY_MODE_N (0x4) + +#define ANT_A (0x1) +#define ANT_B (0x2) +#define ANT_C (0x4) + +#define PA_TYPE_SYSTEM (0) +#define PA_TYPE_MIX (1) +#define PA_TYPE_INTER (2) + +struct iwp_chip_param { + uint32_t phy_mode; + uint8_t tx_ant; + uint8_t rx_ant; + uint16_t pa_type; +}; + +typedef struct iwp_softc { + struct ieee80211com sc_ic; + dev_info_t *sc_dip; + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + void (*sc_recv_action)(ieee80211_node_t *, + const uint8_t *, const uint8_t *); + int (*sc_send_action)(ieee80211_node_t *, + int, int, uint16_t[4]); + volatile uint32_t sc_cmd_flag; + volatile uint32_t sc_cmd_accum; + + enum ieee80211_state sc_ostate; + kmutex_t sc_glock; + kmutex_t sc_mt_lock; + kmutex_t sc_tx_lock; + kcondvar_t sc_mt_cv; + kcondvar_t sc_tx_cv; + kcondvar_t sc_cmd_cv; + kcondvar_t sc_fw_cv; + kcondvar_t sc_put_seg_cv; + kcondvar_t sc_ucode_cv; + + kthread_t *sc_mf_thread; + volatile uint32_t sc_mf_thread_switch; + + volatile uint32_t sc_flags; + uint32_t sc_dmabuf_sz; + uint16_t sc_clsz; + uint8_t sc_rev; + uint8_t sc_resv; + uint16_t sc_assoc_id; + uint16_t sc_reserved0; + + /* shared area */ + iwp_dma_t sc_dma_sh; + iwp_shared_t *sc_shared; + /* keep warm area */ + iwp_dma_t sc_dma_kw; + /* tx scheduler base address */ + uint32_t sc_scd_base_addr; + + uint32_t sc_hw_rev; + struct iwp_phy_rx sc_rx_phy_res; + + iwp_tx_ring_t sc_txq[IWP_NUM_QUEUES]; + iwp_rx_ring_t sc_rxq; + + /* firmware dma */ + iwp_firmware_hdr_t *sc_hdr; + char *sc_boot; + iwp_dma_t sc_dma_fw_text; + iwp_dma_t sc_dma_fw_init_text; + iwp_dma_t sc_dma_fw_data; + iwp_dma_t sc_dma_fw_data_bak; + iwp_dma_t sc_dma_fw_init_data; + + ddi_acc_handle_t sc_cfg_handle; + caddr_t sc_cfg_base; + ddi_acc_handle_t sc_handle; + caddr_t sc_base; + ddi_intr_handle_t *sc_intr_htable; + uint_t sc_intr_pri; + + iwp_rxon_cmd_t sc_config; + iwp_rxon_cmd_t sc_config_save; + + uint8_t sc_eep_map[IWP_SP_EEPROM_SIZE]; + struct iwp_eep_calibration *sc_eep_calib; + struct iwp_calib_results sc_calib_results; + uint32_t sc_scd_base; + + struct iwp_alive_resp sc_card_alive_run; + struct iwp_init_alive_resp sc_card_alive_init; + iwp_ht_conf_t sc_ht_conf; + uint16_t sc_dev_id; + + uint32_t sc_tx_timer; + uint32_t sc_scan_pending; + uint8_t *sc_fw_bin; + + ddi_softint_handle_t sc_soft_hdl; + + uint32_t sc_rx_softint_pending; + uint32_t sc_need_reschedule; + + clock_t sc_clk; + + struct iwp_chip_param sc_chip_param; + + /* kstats */ + uint32_t sc_tx_nobuf; + uint32_t sc_rx_nobuf; + uint32_t sc_tx_err; + uint32_t sc_rx_err; + uint32_t sc_tx_retries; +} iwp_sc_t; + +#define SC_CMD_FLG_NONE (0) +#define SC_CMD_FLG_PENDING (1) +#define SC_CMD_FLG_DONE (2) + +#define IWP_F_ATTACHED (1 << 0) +#define IWP_F_CMD_DONE (1 << 1) +#define IWP_F_FW_INIT (1 << 2) +#define IWP_F_HW_ERR_RECOVER (1 << 3) +#define IWP_F_RATE_AUTO_CTL (1 << 4) +#define IWP_F_RUNNING (1 << 5) +#define IWP_F_SCANNING (1 << 6) +#define IWP_F_SUSPEND (1 << 7) +#define IWP_F_RADIO_OFF (1 << 8) +#define IWP_F_STATISTICS (1 << 9) +#define IWP_F_READY (1 << 10) +#define IWP_F_PUT_SEG (1 << 11) +#define IWP_F_QUIESCED (1 << 12) +#define IWP_F_LAZY_RESUME (1 << 13) + +#define IWP_SUCCESS 0 +#define IWP_FAIL EIO + + +#ifdef __cplusplus +} +#endif + +#endif /* _IWP_VAR_H */
--- a/usr/src/uts/intel/Makefile.intel.shared Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/uts/intel/Makefile.intel.shared Wed Oct 28 11:45:14 2009 +0800 @@ -260,6 +260,7 @@ DRV_KMODS += iwh DRV_KMODS += iwi DRV_KMODS += iwk +DRV_KMODS += iwp DRV_KMODS += iwscn DRV_KMODS += kb8042 DRV_KMODS += keysock
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/usr/src/uts/intel/iwp/Makefile Wed Oct 28 11:45:14 2009 +0800 @@ -0,0 +1,90 @@ +# +# CDDL HEADER START +# +# The contents of this file are subject to the terms of the +# Common Development and Distribution License (the "License"). +# You may not use this file except in compliance with the License. +# +# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE +# or http://www.opensolaris.org/os/licensing. +# See the License for the specific language governing permissions +# and limitations under the License. +# +# When distributing Covered Code, include this CDDL HEADER in each +# file and include the License file at usr/src/OPENSOLARIS.LICENSE. +# If applicable, add the following below this CDDL HEADER, with the +# fields enclosed by brackets "[]" replaced with your own identifying +# information: Portions Copyright [yyyy] [name of copyright owner] +# +# CDDL HEADER END +# +# +# Copyright 2009 Sun Microsystems, Inc. All rights reserved. +# Use is subject to license terms. +# + +# +# This makefile drives the production of the iwp driver kernel module. +# +# i86pc architecture dependent +# + +# +# Path to the base of the uts directory tree (usually /usr/src/uts). +# +UTSBASE = ../.. + +# +# Define the module and object file sets. +# +MODULE = iwp +OBJECTS = $(IWP_OBJS:%=$(OBJS_DIR)/%) +LINTS = $(IWP_OBJS:%.o=$(LINTS_DIR)/%.ln) +ROOTMODULE = $(ROOT_DRV_DIR)/$(MODULE) + +# +# Include common rules. +# +include $(UTSBASE)/intel/Makefile.intel + +# +# Define targets +# +ALL_TARGET = $(BINARY) $(CONFMOD) $(ITUMOD) +LINT_TARGET = $(MODULE).lint +INSTALL_TARGET = $(BINARY) $(ROOTMODULE) + +# +# Overrides +# +LINTTAGS += -erroff=E_BAD_PTR_CAST_ALIGN + +CPPFLAGS += -I. -D_KERNEL + +LDFLAGS += -dy -Nmisc/mac -Nmisc/net80211 -Ndrv/random -Ndrv/ip + +# +# Default build targets. +# +.KEEP_STATE: + +def: $(DEF_DEPS) + +all: $(ALL_DEPS) + +clean: $(CLEAN_DEPS) + +clobber: $(CLOBBER_DEPS) + +lint: $(LINT_DEPS) + +modlintlib: $(MODLINTLIB_DEPS) + +clean.lint: $(CLEAN_LINT_DEPS) + +install: $(INSTALL_DEPS) + +# +# Include common targets. +# +include $(UTSBASE)/intel/Makefile.targ
--- a/usr/src/uts/intel/os/minor_perm Tue Oct 27 15:27:51 2009 -0700 +++ b/usr/src/uts/intel/os/minor_perm Wed Oct 28 11:45:14 2009 +0800 @@ -137,6 +137,7 @@ clone:iwh 0666 root sys clone:iwi 0666 root sys clone:iwk 0666 root sys +clone:iwp 0666 root sys clone:mwl 0666 root sys clone:pcwl 0666 root sys clone:pcan 0666 root sys @@ -173,6 +174,7 @@ iwh:* 0666 root sys iwi:* 0666 root sys iwk:* 0666 root sys +iwp:* 0666 root sys mwl:* 0666 root sys pcwl:* 0666 root sys pcan:* 0666 root sys