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changeset 10841:d3e4a10fc7d5

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6842387 Too many EQs are reserved for PCI-E messages on platforms with a large number of available EQs
author Alan Adamson, SD OSSD <Alan.Adamson@Sun.COM>
date Thu, 22 Oct 2009 15:10:46 -0700
parents 7df556caf412
children e5e88c478ff5
files usr/src/uts/sun4/io/px/px_intr.c usr/src/uts/sun4/io/px/px_msiq.c usr/src/uts/sun4/io/px/px_msiq.h usr/src/uts/sun4/io/px/px_space.c usr/src/uts/sun4/io/px/px_space.h
diffstat 5 files changed, 49 insertions(+), 14 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/sun4/io/px/px_intr.c	Thu Oct 22 11:21:27 2009 -0700
+++ b/usr/src/uts/sun4/io/px/px_intr.c	Thu Oct 22 15:10:46 2009 -0700
@@ -1144,8 +1144,9 @@
 
 	mutex_enter(&ib_p->ib_ino_lst_mutex);
 
-	ret = (cpu_id == -1) ? px_msiq_alloc(px_p, rec_type, msiq_id_p) :
-	    px_msiq_alloc_based_on_cpuid(px_p, rec_type, cpu_id, msiq_id_p);
+	ret = (cpu_id == -1) ? px_msiq_alloc(px_p, rec_type, msg_code,
+	    msiq_id_p) : px_msiq_alloc_based_on_cpuid(px_p, rec_type,
+	    cpu_id, msiq_id_p);
 
 	if (ret != DDI_SUCCESS) {
 		DBG(DBG_MSIQ, dip, "px_add_msiq_intr: "
--- a/usr/src/uts/sun4/io/px/px_msiq.c	Thu Oct 22 11:21:27 2009 -0700
+++ b/usr/src/uts/sun4/io/px/px_msiq.c	Thu Oct 22 15:10:46 2009 -0700
@@ -32,6 +32,7 @@
 #include <sys/conf.h>
 #include <sys/ddi.h>
 #include <sys/sunddi.h>
+#include <sys/sysmacros.h>
 #include <sys/machsystm.h>	/* intr_dist_add */
 #include <sys/modctl.h>
 #include <sys/disp.h>
@@ -49,7 +50,7 @@
 {
 	px_ib_t		*ib_p = px_p->px_ib_p;
 	px_msiq_state_t	*msiq_state_p = &ib_p->ib_msiq_state;
-	int		i, ret = DDI_SUCCESS;
+	int		qcnt, i, ret = DDI_SUCCESS;
 
 	DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_attach\n");
 
@@ -66,8 +67,10 @@
 	 * Around 90% of available MSIQs are reserved for the MSI/Xs.
 	 */
 	msiq_state_p->msiq_msg_qcnt = howmany(msiq_state_p->msiq_cnt, 10);
-	msiq_state_p->msiq_msi_qcnt = msiq_state_p->msiq_cnt -
-	    msiq_state_p->msiq_msg_qcnt;
+
+	qcnt = MIN(msiq_state_p->msiq_msg_qcnt, px_max_msiq_msgs);
+	msiq_state_p->msiq_msg_qcnt = qcnt = MAX(qcnt, px_min_msiq_msgs);
+	msiq_state_p->msiq_msi_qcnt = msiq_state_p->msiq_cnt - qcnt;
 
 	msiq_state_p->msiq_1st_msi_qid = msiq_state_p->msiq_1st_msiq_id;
 	msiq_state_p->msiq_1st_msg_qid = msiq_state_p->msiq_1st_msiq_id +
@@ -137,7 +140,8 @@
  * px_msiq_alloc()
  */
 int
-px_msiq_alloc(px_t *px_p, msiq_rec_type_t rec_type, msiqid_t *msiq_id_p)
+px_msiq_alloc(px_t *px_p, msiq_rec_type_t rec_type, msgcode_t msg_code,
+    msiqid_t *msiq_id_p)
 {
 	px_ib_t		*ib_p = px_p->px_ib_p;
 	px_msiq_state_t	*msiq_state_p = &ib_p->ib_msiq_state;
@@ -152,8 +156,36 @@
 	mutex_enter(&msiq_state_p->msiq_mutex);
 
 	if (rec_type == MSG_REC) {
-		msiq_cnt = msiq_state_p->msiq_msg_qcnt;
+		/*
+		 * The first MSG EQ is dedicated to PCIE_MSG_CODE_ERR_COR
+		 * messages. All other messages will be spread across
+		 * the remaining MSG EQs.
+		 */
 		first_msiq_id = msiq_state_p->msiq_1st_msg_qid;
+
+		if (msg_code == PCIE_MSG_CODE_ERR_COR) {
+			msiq_state_p->msiq_p[first_msiq_id].msiq_state =
+			    MSIQ_STATE_INUSE;
+
+			(void) px_lib_msiq_gethead(px_p->px_dip, first_msiq_id,
+			    &msiq_state_p->msiq_p[first_msiq_id].
+			    msiq_curr_head_index);
+
+			*msiq_id_p =
+			    msiq_state_p->msiq_p[first_msiq_id].msiq_id;
+
+			msiq_state_p->msiq_p[first_msiq_id].msiq_refcnt++;
+
+			DBG(DBG_MSIQ, px_p->px_dip,
+			    "px_msiq_alloc: msiq_id 0x%x\n", *msiq_id_p);
+
+			mutex_exit(&msiq_state_p->msiq_mutex);
+			return (DDI_SUCCESS);
+		}
+
+		/* Jump past the first/dedicated EQ */
+		first_msiq_id++;
+		msiq_cnt = msiq_state_p->msiq_msg_qcnt - 1;
 	} else {
 		msiq_cnt = msiq_state_p->msiq_msi_qcnt;
 		first_msiq_id = msiq_state_p->msiq_1st_msi_qid;
--- a/usr/src/uts/sun4/io/px/px_msiq.h	Thu Oct 22 11:21:27 2009 -0700
+++ b/usr/src/uts/sun4/io/px/px_msiq.h	Thu Oct 22 15:10:46 2009 -0700
@@ -94,7 +94,7 @@
 extern	void	px_msiq_resume(px_t *px_p);
 
 extern	int	px_msiq_alloc(px_t *px_p, msiq_rec_type_t rec_type,
-		    msiqid_t *msiq_id_p);
+		    msgcode_t msg_code, msiqid_t *msiq_id_p);
 extern	int	px_msiq_alloc_based_on_cpuid(px_t *px_p,
 		    msiq_rec_type_t rec_type, cpuid_t cpuid,
 		    msiqid_t *msiq_id_p);
--- a/usr/src/uts/sun4/io/px/px_space.c	Thu Oct 22 11:21:27 2009 -0700
+++ b/usr/src/uts/sun4/io/px/px_space.c	Thu Oct 22 15:10:46 2009 -0700
@@ -19,12 +19,10 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * PCI Express nexus driver tunables
  */
@@ -140,6 +138,9 @@
 uint_t px_disable_fdvma = 0;
 uint_t px_mmu_ctx_lock_failure = 0;
 
+uint_t px_max_msiq_msgs = 4;
+uint_t px_min_msiq_msgs = 2;
+
 /*
  * memory callback list id callback list for kmem_alloc failure clients
  */
--- a/usr/src/uts/sun4/io/px/px_space.h	Thu Oct 22 11:21:27 2009 -0700
+++ b/usr/src/uts/sun4/io/px/px_space.h	Thu Oct 22 15:10:46 2009 -0700
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_SYS_PX_SPACE_H
 #define	_SYS_PX_SPACE_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -95,6 +93,9 @@
 extern uint_t px_iommu_ctx_lock_failure;
 extern uintptr_t px_kmem_clid;
 
+extern uint_t px_max_msiq_msgs;
+extern uint_t px_min_msiq_msgs;
+
 /* timeout length in micro seconds */
 #define	PX_MSEC_TO_USEC	1000
 #define	PX_PME_TO_ACK_TIMEOUT	(1000 * PX_MSEC_TO_USEC)