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changeset 8590:d56635da4e5c

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6793353 Nevada 105 PCIEX panics on X6250
author Alan Adamson, SD OSSD <Alan.Adamson@Sun.COM>
date Tue, 20 Jan 2009 21:15:01 -0800
parents 90d41bc81368
children c2ef2f9a3ec0
files usr/src/uts/intel/io/pciex/pcie_nb5000.h usr/src/uts/intel/io/pciex/pcie_pci.c
diffstat 2 files changed, 33 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/intel/io/pciex/pcie_nb5000.h	Tue Jan 20 23:08:33 2009 -0500
+++ b/usr/src/uts/intel/io/pciex/pcie_nb5000.h	Tue Jan 20 21:15:01 2009 -0800
@@ -20,7 +20,7 @@
  */
 
 /*
- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -43,6 +43,9 @@
 #define	INTEL_ESB2_SW_PCIE_DEV_ID(did) (((did) >= 0x3500 && (did) <= 0x3503) ||\
 	((did) >= 0x3510 && (did) <= 0x351B))
 
+#define	INTEL_NB5000_PEXCTRL_OFFSET		0x48
+#define	INTEL_NB5000_PEXCTRL_COALESCE_EN	0x400
+
 #ifdef	__cplusplus
 }
 #endif
--- a/usr/src/uts/intel/io/pciex/pcie_pci.c	Tue Jan 20 23:08:33 2009 -0500
+++ b/usr/src/uts/intel/io/pciex/pcie_pci.c	Tue Jan 20 21:15:01 2009 -0800
@@ -254,6 +254,7 @@
 /* Intel Workarounds */
 static void	pepb_intel_serr_workaround(dev_info_t *dip, boolean_t mcheck);
 static void	pepb_intel_rber_workaround(dev_info_t *dip);
+static void	pepb_intel_mps_workaround(dev_info_t *dip);
 static void	pepb_intel_sw_workaround(dev_info_t *dip);
 int pepb_intel_workaround_disable = 0;
 
@@ -442,6 +443,7 @@
 	pepb_intel_serr_workaround(devi, pepb->pepb_no_aer_msi);
 	pepb_intel_rber_workaround(devi);
 	pepb_intel_sw_workaround(devi);
+	pepb_intel_mps_workaround(devi);
 
 	/*
 	 * If this is a root port, determine and set the max payload size.
@@ -1360,8 +1362,6 @@
 
 /*
  * 5400 Northbridge Root Ports.
- * MSIs are not working currently, so the MSI settings are the same as the
- * machinecheck settings
  */
 static x86_error_reg_t intel_5400_rp_regs[] = {
 	/* Command Register - Enable SERR */
@@ -1674,6 +1674,33 @@
 }
 
 /*
+ * The Intel 5000 Chipset has an errata that requires read completion
+ * coalescing to be disabled if the Max Payload Size is set to 256 bytes.
+ */
+static void
+pepb_intel_mps_workaround(dev_info_t *dip)
+{
+	uint16_t		vid, did;
+	uint32_t		pexctrl;
+	pcie_bus_t		*bus_p = PCIE_DIP2UPBUS(dip);
+
+	vid = bus_p->bus_dev_ven_id & 0xFFFF;
+	did = bus_p->bus_dev_ven_id >> 16;
+
+	if ((vid == INTEL_VENDOR_ID) && INTEL_NB5000_PCIE_DEV_ID(did)) {
+		pexctrl = pci_config_get32(bus_p->bus_cfg_hdl,
+		    INTEL_NB5000_PEXCTRL_OFFSET);
+		/*
+		 * Turn off coalescing (bit 10)
+		 */
+		pexctrl &= ~INTEL_NB5000_PEXCTRL_COALESCE_EN;
+
+		pci_config_put32(bus_p->bus_cfg_hdl,
+		    INTEL_NB5000_PEXCTRL_OFFSET, pexctrl);
+	}
+}
+
+/*
  * Common interrupt handler for hotplug, PME and errors.
  */
 static uint_t