Mercurial > illumos > illumos-gate
changeset 3300:ddd4335d2a41
6502647 OPL panel intr should not use cmn_err() logging at high PIL
6502648 OPL panel: Clearing PNLINT HW flag may be delayed
6502649 OPL panel: intr_enqueue_req() needs IE disabled
| author | hyw |
|---|---|
| date | Wed, 20 Dec 2006 17:22:30 -0800 |
| parents | 8139b10ae6b7 |
| children | e97e39bb84ec |
| files | usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c |
| diffstat | 1 files changed, 11 insertions(+), 8 deletions(-) [+] |
line wrap: on
line diff
--- a/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c Wed Dec 20 17:02:04 2006 -0800 +++ b/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c Wed Dec 20 17:22:30 2006 -0800 @@ -350,26 +350,27 @@ static uint_t panel_intr(caddr_t arg) { - int instance; struct panel_state *statep = (struct panel_state *)arg; - instance = ddi_get_instance(statep->dip); - - DCMN_ERR((CE_CONT, "%s%d: intr\n", panel_name, instance)); - /* to confirm the validity of the interrupt */ if (!(ddi_get8(statep->panel_regs_handle, statep->panelregs) & PNLINT_MASK)) { - cmn_err(CE_WARN, "%s%d: spurious interrupt detected.", - panel_name, instance); return (DDI_INTR_UNCLAIMED); } - /* clear the PNLINT bit */ + /* + * Clear the PNLINT bit + * HW reported that there might be a delay in the PNLINT bit + * clearing. We force synchronization by attempting to read + * back the reg after clearing the bit. + */ panel_ddi_put8(statep->panel_regs_handle, statep->panelregs, statep->panelregs_state | PNLINT_MASK); + ddi_get8(statep->panel_regs_handle, statep->panelregs); if (panel_enable) { + uint_t pstate_save; + /* avoid double panic */ panel_enable = 0; @@ -384,7 +385,9 @@ * to minimize exposure of this new logic to other existing * platforms. */ + pstate_save = disable_vec_intr(); intr_enqueue_req(PIL_15, cpc_level15_inum); + enable_vec_intr(pstate_save); cmn_err(CE_PANIC, "System Panel Driver: Emergency panic request "