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changeset 4330:dfd7c5e23fa0

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6551951 BGE need to support NetXtreme 5755
author ml149210
date Sat, 26 May 2007 05:29:40 -0700
parents 35ac1e4ee309
children f784727d3d6a
files usr/src/pkgdefs/SUNWbge/postinstall usr/src/uts/common/io/bge/bge_chip2.c usr/src/uts/common/io/bge/bge_hw.h usr/src/uts/common/io/bge/bge_main2.c
diffstat 4 files changed, 50 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/pkgdefs/SUNWbge/postinstall	Fri May 25 13:25:30 2007 -0700
+++ b/usr/src/pkgdefs/SUNWbge/postinstall	Sat May 26 05:29:40 2007 -0700
@@ -161,6 +161,7 @@
 	"pci14e4,1678"
 	"pci14e4,1679"
 	"pciex14e4,167a"
+	"pciex14e4,167b"
 	"pci14e4,167d"
 	"pciex14e4,169d"' \
 	-b "$BASEDIR" bge
@@ -185,6 +186,7 @@
 	"pci14e4,1677"
 	"pci14e4,1678"
 	"pciex14e4,167a"
+	"pciex14e4,167b"
 	"pci14e4,167d"' \
 	-b "$BASEDIR" bge
 	fi
--- a/usr/src/uts/common/io/bge/bge_chip2.c	Fri May 25 13:25:30 2007 -0700
+++ b/usr/src/uts/common/io/bge/bge_chip2.c	Sat May 26 05:29:40 2007 -0700
@@ -1856,6 +1856,7 @@
 	case DEVICE_ID_5752:
 	case DEVICE_ID_5752M:
 	case DEVICE_ID_5754:
+	case DEVICE_ID_5755:
 	case DEVICE_ID_5721:
 	case DEVICE_ID_5714C:
 	case DEVICE_ID_5714S:
@@ -2047,6 +2048,24 @@
 		dev_ok = B_TRUE;
 		break;
 
+	case DEVICE_ID_5755:
+		cidp->chip_label = 5755;
+		cidp->pci_type = BGE_PCI_E;
+		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
+		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
+		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
+		cidp->mbuf_base = bge_mbuf_pool_base_5705;
+		cidp->mbuf_length = bge_mbuf_pool_len_5705;
+		cidp->recv_slots = BGE_RECV_SLOTS_5705;
+		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
+		cidp->flags |= CHIP_FLAG_NO_JUMBO;
+		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
+		cidp->statistic_type = BGE_STAT_REG;
+		dev_ok = B_TRUE;
+		break;
+
 	case DEVICE_ID_5706:
 		cidp->chip_label = 5706;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
@@ -2436,7 +2455,9 @@
 				if (bgep->chipid.asic_rev ==
 				    MHCR_CHIP_REV_5751_A0 ||
 				    bgep->chipid.asic_rev ==
-				    MHCR_CHIP_REV_5721_A0) {
+				    MHCR_CHIP_REV_5721_A0 ||
+				    bgep->chipid.asic_rev ==
+				    MHCR_CHIP_REV_5755_A0) {
 					val32 = bge_reg_get32(bgep,
 					    PHY_TEST_CTRL_REG);
 					if (val32 == (PHY_PCIE_SCRAM_MODE |
@@ -3140,6 +3161,7 @@
 	if ((bgep->chipid.chip_label == 5721) ||
 		(bgep->chipid.chip_label == 5751) ||
 		(bgep->chipid.chip_label == 5752) ||
+		(bgep->chipid.chip_label == 5755) ||
 		(bgep->chipid.chip_label == 5789))
 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
 
@@ -3345,6 +3367,7 @@
 	uint32_t mtu;
 	uint32_t maxring;
 	uint32_t stats_mask;
+	uint32_t dma_wrprio;
 	uint64_t ring;
 	int retval = DDI_SUCCESS;
 
@@ -3690,8 +3713,14 @@
 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
 			retval = DDI_FAILURE;
+	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
+				ALL_DMA_ATTN_BITS;
+	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
+		MHCR_CHIP_ASIC_REV_5755) {
+		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
+	}
 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
-	    (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
+			dma_wrprio))
 		retval = DDI_FAILURE;
 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
--- a/usr/src/uts/common/io/bge/bge_hw.h	Fri May 25 13:25:30 2007 -0700
+++ b/usr/src/uts/common/io/bge/bge_hw.h	Sat May 26 05:29:40 2007 -0700
@@ -78,6 +78,7 @@
 #define	DEVICE_ID_5752			0x1600
 #define	DEVICE_ID_5752M			0x1601
 #define	DEVICE_ID_5754			0x167a
+#define	DEVICE_ID_5755			0x167b
 #define	DEVICE_ID_5721			0x1659
 #define	DEVICE_ID_5714C			0x1668
 #define	DEVICE_ID_5714S			0x1669
@@ -157,7 +158,8 @@
 		(bgep->chipid.device == DEVICE_ID_5782) ||\
 		(bgep->chipid.device == DEVICE_ID_5788) ||\
 		(bgep->chipid.device == DEVICE_ID_5705_2) ||\
-		(bgep->chipid.device == DEVICE_ID_5754))
+		(bgep->chipid.device == DEVICE_ID_5754) ||\
+		(bgep->chipid.device == DEVICE_ID_5755))
 
 #define	DEVICE_5721_SERIES_CHIPSETS(bgep) \
 		((bgep->chipid.device == DEVICE_ID_5721) ||\
@@ -257,6 +259,9 @@
 #define	MHCR_CHIP_REV_5754_A0		0xb0000000
 #define	MHCR_CHIP_REV_5754_A1		0xb0010000
 
+#define	MHCR_CHIP_REV_5755_A0		0xa0000000
+#define	MHCR_CHIP_REV_5755_A1		0xa0010000
+
 #define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) & 0xf0000000)
 #define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
 #define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
@@ -267,6 +272,7 @@
 #define	MHCR_CHIP_ASIC_REV_5714 	(0x5 << 28)
 #define	MHCR_CHIP_ASIC_REV_5752		(0x6 << 28)
 #define	MHCR_CHIP_ASIC_REV_5754		(0xb << 28)
+#define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
 #define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
 
 
@@ -576,6 +582,15 @@
 #define	ALL_DMA_ATTN_BITS		0x000003fc
 
 /*
+ * BCM5755, 5755M, 5906, 5906M only
+ * 1 - Enable Fix. Device will send out the status block before
+ *     the interrupt message
+ * 0 - Disable fix. Device will send out the interrupt message
+ *     before the status block
+ */
+#define	DMA_STATUS_TAG_FIX_CQ12384	0x20000000
+
+/*
  * End of state machine control register definitions
  */
 
--- a/usr/src/uts/common/io/bge/bge_main2.c	Fri May 25 13:25:30 2007 -0700
+++ b/usr/src/uts/common/io/bge/bge_main2.c	Sat May 26 05:29:40 2007 -0700
@@ -33,7 +33,7 @@
  * This is the string displayed by modinfo, etc.
  * Make sure you keep the version ID up to date!
  */
-static char bge_ident[] = "Broadcom Gb Ethernet v0.56";
+static char bge_ident[] = "Broadcom Gb Ethernet v0.57";
 
 /*
  * Property names