Mercurial > illumos > illumos-gate
changeset 2044:e977a1204f72
6427002 Connect(cfgadm) fails after hotplug into empty slots 2,3 and 4
6427559 Oberon hotplug requires updates from Oberon Spec v1.01
| author | jj156685 |
|---|---|
| date | Tue, 23 May 2006 13:37:34 -0700 |
| parents | cce0c9bf5c8d |
| children | 473cc947ba84 |
| files | usr/src/uts/sun4u/io/px/px_hlib.c usr/src/uts/sun4u/io/px/px_lib4u.c |
| diffstat | 2 files changed, 25 insertions(+), 0 deletions(-) [+] |
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--- a/usr/src/uts/sun4u/io/px/px_hlib.c Tue May 23 13:13:29 2006 -0700 +++ b/usr/src/uts/sun4u/io/px/px_hlib.c Tue May 23 13:37:34 2006 -0700 @@ -3143,6 +3143,7 @@ oberon_hp_pwroff(caddr_t csr_base) { volatile uint64_t reg; + volatile uint64_t reg_tluue, reg_tluce; DBG(DBG_HP, NULL, "oberon_hp_pwroff the slot\n"); @@ -3156,6 +3157,13 @@ CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); delay(drv_usectohz(10000)); + /* Save the TLU registers */ + reg_tluue = CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE); + reg_tluce = CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE); + /* All clear */ + CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, 0); + CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, 0); + /* Disable port */ CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS); @@ -3177,6 +3185,10 @@ /* write 0 to bit 7 of ILU Error Log Enable Register */ CSR_BC(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3); + /* Set back TLU registers */ + CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, reg_tluue); + CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, reg_tluce); + /* Power LED off */ reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
--- a/usr/src/uts/sun4u/io/px/px_lib4u.c Tue May 23 13:13:29 2006 -0700 +++ b/usr/src/uts/sun4u/io/px/px_lib4u.c Tue May 23 13:37:34 2006 -0700 @@ -238,6 +238,19 @@ px_err_reg_enable(px_p, PX_ERR_TLU_UE); px_err_reg_enable(px_p, PX_ERR_TLU_CE); px_err_reg_enable(px_p, PX_ERR_TLU_OE); + + /* + * Oberon hotplug uses SPARE3 field in ILU Error Log Enable + * register to indicate the status of leaf reset, + * we need to preserve the value of this bit, and keep it in + * px_ilu_log_mask to reflect the state of the bit + */ + if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) + px_ilu_log_mask |= (1ull << + ILU_ERROR_LOG_ENABLE_SPARE3); + else + px_ilu_log_mask &= ~(1ull << + ILU_ERROR_LOG_ENABLE_SPARE3); px_err_reg_enable(px_p, PX_ERR_ILU); px_fabric_die_rc_ue |= PCIE_AER_UCE_UC;