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changeset 11016:efcd833e2d40

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6871527 FCoE, qlge driver - Add NIC side of support for new Qlogic FCoE adapter, Europa (fix lint)
author Sukumar Swaminathan <Sukumar.Swaminathan@Sun.COM>
date Mon, 09 Nov 2009 17:37:50 -0800
parents 0a0751599d31
children d8051a5359bd
files usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_flash.c usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_gld.c usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_mpi.c
diffstat 5 files changed, 97 insertions(+), 88 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c	Mon Nov 09 16:53:15 2009 -0800
+++ b/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c	Mon Nov 09 17:37:50 2009 -0800
@@ -563,7 +563,7 @@
 ql_sem_unlock(qlge_t *qlge, uint32_t sem_mask)
 {
 	ql_write_reg(qlge, REG_SEMAPHORE, sem_mask);
-	ql_read_reg(qlge, REG_SEMAPHORE);	/* flush */
+	(void) ql_read_reg(qlge, REG_SEMAPHORE);	/* flush */
 }
 
 /*
@@ -2561,7 +2561,7 @@
 {
 	qlge_t *qlge = (qlge_t *)((void *)arg1);
 
-	ql_reset_mpi_risc(qlge);
+	(void) ql_reset_mpi_risc(qlge);
 	return (DDI_INTR_CLAIMED);
 }
 
@@ -2698,7 +2698,8 @@
 				ql_disable_completion_interrupt(qlge,
 				    rx_ring->irq);
 				if (rx_ring->type == TX_Q) {
-					ql_clean_outbound_rx_ring(rx_ring);
+					(void) ql_clean_outbound_rx_ring(
+					    rx_ring);
 					ql_enable_completion_interrupt(
 					    rx_ring->qlge, rx_ring->irq);
 				} else {
@@ -2738,7 +2739,7 @@
 	_NOTE(ARGUNUSED(arg2));
 
 	++qlge->rx_interrupts[rx_ring->cq_id];
-	ql_clean_outbound_rx_ring(rx_ring);
+	(void) ql_clean_outbound_rx_ring(rx_ring);
 	ql_enable_completion_interrupt(rx_ring->qlge, rx_ring->irq);
 
 	return (DDI_INTR_CLAIMED);
@@ -3993,7 +3994,7 @@
 	ql_stop_timer(qlge);
 
 	if (qlge->sequence & INIT_MAC_REGISTERED) {
-		mac_unregister(qlge->mh);
+		(void) mac_unregister(qlge->mh);
 		qlge->sequence &= ~INIT_MAC_REGISTERED;
 	}
 
@@ -4079,10 +4080,10 @@
 ql_set_promiscuous(qlge_t *qlge, int mode)
 {
 	if (mode) {
-		ql_set_routing_reg(qlge, RT_IDX_PROMISCUOUS_SLOT,
+		(void) ql_set_routing_reg(qlge, RT_IDX_PROMISCUOUS_SLOT,
 		    RT_IDX_VALID, 1);
 	} else {
-		ql_set_routing_reg(qlge, RT_IDX_PROMISCUOUS_SLOT,
+		(void) ql_set_routing_reg(qlge, RT_IDX_PROMISCUOUS_SLOT,
 		    RT_IDX_VALID, 0);
 	}
 }
@@ -4212,7 +4213,7 @@
 		bcopy(ep, qlge->multicast_list[index].addr.ether_addr_octet,
 		    ETHERADDRL);
 		/* increment the total number of addresses in multicast list */
-		ql_add_multicast_address(qlge, index);
+		(void) ql_add_multicast_address(qlge, index);
 		qlge->multicast_list_count++;
 		QL_PRINT(DBG_GLD,
 		    ("%s(%d): added to index of multicast list= 0x%x, "
@@ -4276,10 +4277,10 @@
 			 */
 			for (i = rmv_index; i < qlge->multicast_list_count;
 			    i++) {
-				ql_add_multicast_address(qlge, i);
+				(void) ql_add_multicast_address(qlge, i);
 			}
 			/* and disable the last one */
-			ql_remove_multicast_address(qlge, i);
+			(void) ql_remove_multicast_address(qlge, i);
 
 			/* disable multicast promiscuous mode */
 			if (qlge->multicast_promisc) {
@@ -5034,7 +5035,7 @@
 	mutex_enter(&qlge->hw_mutex);
 
 	/* Reset adapter */
-	ql_asic_reset(qlge);
+	(void) ql_asic_reset(qlge);
 
 	lbq_buf_size = (uint16_t)
 	    ((qlge->mtu == ETHERMTU)? NORMAL_FRAME_SIZE : JUMBO_FRAME_SIZE);
@@ -5077,8 +5078,8 @@
 			for (i = 0; i < qlge->rx_ring_count; i++) {
 				rx_ring = &qlge->rx_ring[i];
 				if (rx_ring->type != TX_Q) {
-					ql_alloc_sbufs(qlge, rx_ring);
-					ql_alloc_lbufs(qlge, rx_ring);
+					(void) ql_alloc_sbufs(qlge, rx_ring);
+					(void) ql_alloc_lbufs(qlge, rx_ring);
 				}
 			}
 		}
@@ -5488,16 +5489,16 @@
 	if (ql_sem_spinlock(qlge, qlge->xgmac_sem_mask)) {
 		return (0);
 	}
-	ql_read_xgmac_reg(qlge, REG_XGMAC_FLOW_CONTROL, &val32);
+	(void) ql_read_xgmac_reg(qlge, REG_XGMAC_FLOW_CONTROL, &val32);
 	(knp++)->value.ui32 = val32;
 
-	ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_TX_PAUSE_PKTS, &val32);
+	(void) ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_TX_PAUSE_PKTS, &val32);
 	(knp++)->value.ui32 = val32;
 
-	ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_RX_PAUSE_PKTS, &val32);
+	(void) ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_RX_PAUSE_PKTS, &val32);
 	(knp++)->value.ui32 = val32;
 
-	ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_RX_FIFO_DROPS, &val32);
+	(void) ql_read_xgmac_reg(qlge, REG_XGMAC_MAC_RX_FIFO_DROPS, &val32);
 	(knp++)->value.ui32 = val32;
 
 	ql_sem_unlock(qlge, qlge->xgmac_sem_mask);
@@ -6344,7 +6345,7 @@
 
 		/* if need to update port configuration */
 		if (update_port_config)
-			ql_set_port_cfg(qlge);
+			(void) ql_set_port_cfg(qlge);
 	} else
 		cmn_err(CE_WARN, "ql_get_port_cfg failed");
 
@@ -6570,7 +6571,7 @@
 	return (DDI_SUCCESS);
 
 err_bringup:
-	ql_asic_reset(qlge);
+	(void) ql_asic_reset(qlge);
 	return (DDI_FAILURE);
 }
 
@@ -6763,7 +6764,7 @@
 		    ADAPTER_NAME, instance));
 
 		/* Initialize mutex, need the interrupt priority */
-		ql_init_rx_tx_locks(qlge);
+		(void) ql_init_rx_tx_locks(qlge);
 
 		qlge->sequence |= INIT_LOCKS_CREATED;
 
@@ -7052,7 +7053,7 @@
 		status = ql_sem_spinlock(qlge, SEM_RT_IDX_MASK);
 		if (status)
 			return (status);
-		ql_stop_routing(qlge);
+		(void) ql_stop_routing(qlge);
 		ql_sem_unlock(qlge, SEM_RT_IDX_MASK);
 		/*
 		 * Set the flag for receive and transmit
@@ -7089,7 +7090,7 @@
 
 		mutex_enter(&qlge->hw_mutex);
 		/* Reset adapter */
-		ql_asic_reset(qlge);
+		(void) ql_asic_reset(qlge);
 		/*
 		 * Unbind all tx dma handles to prevent pending tx descriptors'
 		 * dma handles from being re-used.
@@ -7146,7 +7147,7 @@
 		mutex_enter(&qlge->gen_mutex);
 		if ((qlge->mac_flags == QL_MAC_ATTACHED) ||
 		    (qlge->mac_flags == QL_MAC_STARTED)) {
-			ql_do_stop(qlge);
+			(void) ql_do_stop(qlge);
 		}
 		qlge->mac_flags = QL_MAC_SUSPENDED;
 		mutex_exit(&qlge->gen_mutex);
@@ -7180,8 +7181,8 @@
 
 	if (CFG_IST(qlge, CFG_CHIP_8100)) {
 		/* stop forwarding external packets to driver */
-		ql_sem_spinlock(qlge, SEM_RT_IDX_MASK);
-		ql_stop_routing(qlge);
+		(void) ql_sem_spinlock(qlge, SEM_RT_IDX_MASK);
+		(void) ql_stop_routing(qlge);
 		ql_sem_unlock(qlge, SEM_RT_IDX_MASK);
 		/* Stop all the request queues */
 		for (i = 0; i < qlge->tx_ring_count; i++) {
@@ -7207,7 +7208,7 @@
 		qlge_delay(QL_ONE_SEC_DELAY/4);
 		qlge->mac_flags = QL_MAC_STOPPED;
 		/* Reset adapter */
-		ql_asic_reset(qlge);
+		(void) ql_asic_reset(qlge);
 		qlge_delay(100);
 	}
 
--- a/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c	Mon Nov 09 16:53:15 2009 -0800
+++ b/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c	Mon Nov 09 17:37:50 2009 -0800
@@ -1064,10 +1064,11 @@
 			prop_ptr =
 			    (struct qlnic_prop_info *)(void *)dmp->b_rptr;
 			/* get various properties */
-			ql_get_firmware_version(qlge,
+			(void) ql_get_firmware_version(qlge,
 			    &prop_ptr->mpi_version);
-			ql_get_fw_state(qlge, &prop_ptr->fw_state);
-			qlge_get_link_status(qlge, &prop_ptr->link_status);
+			(void) ql_get_fw_state(qlge, &prop_ptr->fw_state);
+			(void) qlge_get_link_status(qlge,
+			    &prop_ptr->link_status);
 			break;
 
 		case QLA_LIST_ADAPTER_INFO:
@@ -1164,12 +1165,12 @@
 			if (qlge->ioctl_transferred_bytes >=
 			    qlge->ioctl_total_length) {
 				region = pheader->option[0];
-				ql_get_flash_table_region_info(qlge, region,
-				    &addr, &size);
+				(void) ql_get_flash_table_region_info(qlge,
+				    region, &addr, &size);
 				QL_PRINT(DBG_GLD, ("write data to region 0x%x,"
 				    " addr 0x%x, max size %d bytes\n",
 				    region, addr, size));
-				qlge_load_flash(qlge,
+				(void) qlge_load_flash(qlge,
 				    (uint8_t *)qlge->ioctl_buf_ptr,
 				    qlge->ioctl_transferred_bytes /* size */,
 				    addr);
@@ -1230,7 +1231,7 @@
 			break;
 
 		case QLA_TRIGGER_SYS_ERROR_EVENT:
-			ql_trigger_system_error_event(qlge);
+			(void) ql_trigger_system_error_event(qlge);
 			break;
 
 		case QLA_READ_VPD:
@@ -1250,7 +1251,8 @@
 			len = (uint32_t)iocp->ioc_count;
 			QL_PRINT(DBG_GLD, (" 0x%x user buffer available \n",
 			    len));
-			ql_flash_vpd(qlge, (uint8_t *)qlge->ioctl_buf_ptr);
+			(void) ql_flash_vpd(qlge,
+			    (uint8_t *)qlge->ioctl_buf_ptr);
 			pheader = (ioctl_header_info_t *)(void *)dmp->b_rptr;
 			/* build initial ioctl packet header */
 			build_init_pkt_header(qlge, pheader,
@@ -1685,21 +1687,23 @@
 		/* if dumping all */
 		if ((requested_dumps & DUMP_REQUEST_ALL) != 0) {
 			ql_dump_header_ptr->num_dumps = 2;
-			ql_8xxx_binary_core_dump_with_header(qlge, bp, &size);
+			(void) ql_8xxx_binary_core_dump_with_header(qlge,
+			    bp, &size);
 			length += size;
 			bp = (caddr_t)qlge->ioctl_buf_ptr + length;
-			ql_8xxx_binary_register_dump_with_header(qlge,
+			(void) ql_8xxx_binary_register_dump_with_header(qlge,
 			    bp, &size);
 			length += size;
 			bp = (caddr_t)qlge->ioctl_buf_ptr + length;
 		} else if ((requested_dumps & DUMP_REQUEST_CORE) != 0) {
 			ql_dump_header_ptr->num_dumps = 1;
-			ql_8xxx_binary_core_dump_with_header(qlge, bp, &size);
+			(void) ql_8xxx_binary_core_dump_with_header(qlge,
+			    bp, &size);
 			length += size;
 			bp = (caddr_t)qlge->ioctl_buf_ptr + length;
 		} else if ((requested_dumps & DUMP_REQUEST_REGISTER) != 0) {
 			ql_dump_header_ptr->num_dumps = 1;
-			ql_8xxx_binary_register_dump_with_header(qlge,
+			(void) ql_8xxx_binary_register_dump_with_header(qlge,
 			    bp, &size);
 			length += size;
 			bp = (caddr_t)qlge->ioctl_buf_ptr + length;
@@ -2326,7 +2330,7 @@
 	/*
 	 * First we have to enable the probe mux
 	 */
-	ql_write_processor_data(qlge, 0x100e, 0x18a20000);
+	(void) ql_write_processor_data(qlge, 0x100e, 0x18a20000);
 
 	buf = ql_get_probe(qlge, SYS_CLOCK, sys_clock_valid_modules, buf);
 
@@ -2642,10 +2646,11 @@
 	    (uint8_t *)"Core Registers");
 
 	/* first, read 127 core registers */
-	ql_get_mpi_regs(qlge, &mpi_coredump->mpi_core_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->mpi_core_regs[0],
 	    MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT);
 	/* read the next 16 shadow registers */
-	ql_get_mpi_shadow_regs(qlge, &mpi_coredump->mpi_core_sh_regs[0]);
+	(void) ql_get_mpi_shadow_regs(qlge,
+	    &mpi_coredump->mpi_core_sh_regs[0]);
 
 	/* 2:MPI Test Logic Registers */
 	ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
@@ -2654,7 +2659,7 @@
 	    sizeof (mpi_coredump->test_logic_regs),
 	    (uint8_t *)"Test Logic Regs");
 
-	ql_get_mpi_regs(qlge, &mpi_coredump->test_logic_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->test_logic_regs[0],
 	    TEST_REGS_ADDR, TEST_REGS_CNT);
 
 	/* 3:RMII Registers */
@@ -2663,7 +2668,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->rmii_regs),
 	    (uint8_t *)"RMII Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->rmii_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->rmii_regs[0],
 	    RMII_REGS_ADDR, RMII_REGS_CNT);
 
 	/* 4:FCMAC1 Registers */
@@ -2672,7 +2677,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->fcmac1_regs),
 	    (uint8_t *)"FCMAC1 Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->fcmac1_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->fcmac1_regs[0],
 	    FCMAC1_REGS_ADDR, FCMAC_REGS_CNT);
 
 	/* 5:FCMAC2 Registers */
@@ -2681,7 +2686,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->fcmac2_regs),
 	    (uint8_t *)"FCMAC2 Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->fcmac2_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->fcmac2_regs[0],
 	    FCMAC2_REGS_ADDR, FCMAC_REGS_CNT);
 
 	/* 6:FC1 Mailbox Registers */
@@ -2690,7 +2695,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->fc1_mbx_regs),
 	    (uint8_t *)"FC1 MBox Regs");
-	ql_get_mpi_regs(qlge, &mpi_coredump->fc1_mbx_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->fc1_mbx_regs[0],
 	    FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
 
 	/* 7:IDE Registers */
@@ -2699,7 +2704,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->ide_regs),
 	    (uint8_t *)"IDE Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->ide_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->ide_regs[0],
 	    IDE_REGS_ADDR, IDE_REGS_CNT);
 
 	/* 8:Host1 Mailbox Registers */
@@ -2708,7 +2713,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->nic1_mbx_regs),
 	    (uint8_t *)"NIC1 MBox Regs");
-	ql_get_mpi_regs(qlge, &mpi_coredump->nic1_mbx_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->nic1_mbx_regs[0],
 	    NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
 
 	/* 9:SMBus Registers */
@@ -2717,7 +2722,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->smbus_regs),
 	    (uint8_t *)"SMBus Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->smbus_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->smbus_regs[0],
 	    SMBUS_REGS_ADDR, SMBUS_REGS_CNT);
 
 	/* 10:FC2 Mailbox Registers */
@@ -2726,7 +2731,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->fc2_mbx_regs),
 	    (uint8_t *)"FC2 MBox Regs");
-	ql_get_mpi_regs(qlge, &mpi_coredump->fc2_mbx_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->fc2_mbx_regs[0],
 	    FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
 
 	/* 11:Host2 Mailbox Registers */
@@ -2735,7 +2740,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->nic2_mbx_regs),
 	    (uint8_t *)"NIC2 MBox Regs");
-	ql_get_mpi_regs(qlge, &mpi_coredump->nic2_mbx_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->nic2_mbx_regs[0],
 	    NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
 
 	/* 12:i2C Registers */
@@ -2744,7 +2749,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->i2c_regs),
 	    (uint8_t *)"I2C Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->i2c_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->i2c_regs[0],
 	    I2C_REGS_ADDR, I2C_REGS_CNT);
 
 	/* 13:MEMC Registers */
@@ -2753,7 +2758,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->memc_regs),
 	    (uint8_t *)"MEMC Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->memc_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->memc_regs[0],
 	    MEMC_REGS_ADDR, MEMC_REGS_CNT);
 
 	/* 14:PBus Registers */
@@ -2762,7 +2767,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->pbus_regs),
 	    (uint8_t *)"PBUS Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->pbus_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->pbus_regs[0],
 	    PBUS_REGS_ADDR, PBUS_REGS_CNT);
 
 	/* 15:MDE Registers */
@@ -2771,7 +2776,7 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->mde_regs),
 	    (uint8_t *)"MDE Registers");
-	ql_get_mpi_regs(qlge, &mpi_coredump->mde_regs[0],
+	(void) ql_get_mpi_regs(qlge, &mpi_coredump->mde_regs[0],
 	    MDE_REGS_ADDR, MDE_REGS_CNT);
 
 	ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
@@ -2822,7 +2827,7 @@
 	    sizeof (mpi_coredump->serdes_xfi_hss_pll),
 	    (uint8_t *)"XFI HSS PLL Registers");
 
-	ql_get_serdes_regs(qlge, mpi_coredump);
+	(void) ql_get_serdes_regs(qlge, mpi_coredump);
 
 	/* 16:NIC Ctrl Registers Port1 */
 	ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
@@ -2848,14 +2853,14 @@
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->xgmac),
 	    (uint8_t *)"NIC XGMac Registers");
-	ql_get_xgmac_regs(qlge, &mpi_coredump->xgmac[0]);
+	(void) ql_get_xgmac_regs(qlge, &mpi_coredump->xgmac[0]);
 
 	ql_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr,
 	    PROBE_DUMP_SEG_NUM,
 	    sizeof (mpi_coredump_segment_header_t) +
 	    sizeof (mpi_coredump->probe_dump),
 	    (uint8_t *)"Probe Dump");
-	ql_get_probe_dump(qlge, &mpi_coredump->probe_dump[0]);
+	(void) ql_get_probe_dump(qlge, &mpi_coredump->probe_dump[0]);
 
 	ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
 	    ROUTING_INDEX_SEG_NUM,
@@ -2879,7 +2884,7 @@
 	    sizeof (mpi_coredump->ets),
 	    (uint8_t *)"ETS Registers");
 
-	ql_get_ets_regs(qlge, &mpi_coredump->ets[0]);
+	(void) ql_get_ets_regs(qlge, &mpi_coredump->ets[0]);
 
 	/* clear the pause */
 	if (ql_unpause_mpi_risc(qlge) != DDI_SUCCESS) {
--- a/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_flash.c	Mon Nov 09 16:53:15 2009 -0800
+++ b/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_flash.c	Mon Nov 09 17:37:50 2009 -0800
@@ -248,7 +248,7 @@
 		return (DDI_FAILURE);
 	}
 
-	ql_unprotect_flash(qlge);
+	(void) ql_unprotect_flash(qlge);
 
 	get_sector_number(qlge, faddr, &start_block);
 	get_sector_number(qlge, faddr + len - 1, &end_block);
@@ -284,7 +284,7 @@
 	}
 	rval = DDI_SUCCESS;
 out:
-	ql_protect_flash(qlge);
+	(void) ql_protect_flash(qlge);
 	kmem_free(temp, sector_size);
 
 	ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
@@ -928,8 +928,8 @@
 				    ISP_8100_NIC_PARAM1_ADDR;
 		}
 	}
-	ql_flash_desc(qlge);
-	ql_flash_nic_config(qlge);
+	(void) ql_flash_desc(qlge);
+	(void) ql_flash_nic_config(qlge);
 
 out:
 	ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
@@ -980,8 +980,8 @@
 			    (qlge->flash_nic_config_table_addr == 0)) {
 				rval = ql_flash_flt(qlge);
 				if (rval == DDI_SUCCESS) {
-					ql_flash_desc(qlge);
-					ql_flash_nic_config(qlge);
+					(void) ql_flash_desc(qlge);
+					(void) ql_flash_nic_config(qlge);
 				} else {
 					rval = DDI_FAILURE;
 					goto out;
@@ -1114,7 +1114,7 @@
 	if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
 	    == DDI_SUCCESS) {
 		do {
-			ql_read_flash_status(qlge, &reg_status);
+			(void) ql_read_flash_status(qlge, &reg_status);
 			if (reg_status & BIT_1)
 				break;
 			drv_usecwait(10);
@@ -1153,7 +1153,7 @@
 	    == DDI_SUCCESS) {
 		/* wait Write In Progress (WIP) bit to reset */
 		do {
-			ql_read_flash_status(qlge, &flash_status);
+			(void) ql_read_flash_status(qlge, &flash_status);
 			if ((flash_status & BIT_0 /* WIP */) == 0)
 				break;
 			drv_usecwait(10);
@@ -1191,7 +1191,8 @@
 		if ((addr & FLASH_ADDR_MASK) == FLASH_CONF_ADDR) {
 			/* wait Write In Progress (WIP) bit to reset */
 			do {
-				ql_read_flash_status(qlge, &flash_status);
+				(void) ql_read_flash_status(qlge,
+				    &flash_status);
 				if ((flash_status & BIT_0 /* WIP */) == 0)
 					break;
 				drv_usecwait(10);
@@ -1313,39 +1314,39 @@
 	uint32_t addr = 0;
 
 	addr = (test_addr / 4);
-	ql_read_flash(qlge, addr, &old_data);
+	(void) ql_read_flash(qlge, addr, &old_data);
 	QL_PRINT(DBG_FLASH, ("read addr %x old value %x\n", test_addr,
 	    old_data));
 
 	/* enable writing to flash */
-	ql_unprotect_flash(qlge);
+	(void) ql_unprotect_flash(qlge);
 
 	/* erase the sector */
-	ql_flash_erase_sector(qlge, test_addr);
-	ql_read_flash(qlge, addr, &data);
+	(void) ql_flash_erase_sector(qlge, test_addr);
+	(void) ql_read_flash(qlge, addr, &data);
 	QL_PRINT(DBG_FLASH, ("after sector erase, addr %x value %x\n",
 	    test_addr, data));
 
 	/* write new value to it and read back to confirm */
 	data = 0x33445566;
-	ql_write_flash(qlge, addr, data);
+	(void) ql_write_flash(qlge, addr, data);
 	QL_PRINT(DBG_FLASH, ("new value written to addr %x value %x\n",
 	    test_addr, data));
-	ql_read_flash(qlge, addr, &data);
+	(void) ql_read_flash(qlge, addr, &data);
 	if (data != 0x33445566) {
 		cmn_err(CE_WARN, "flash write test failed, get data %x"
 		    " after writing", data);
 	}
 
 	/* write old value to it and read back to restore */
-	ql_flash_erase_sector(qlge, test_addr);
-	ql_write_flash(qlge, addr, old_data);
-	ql_read_flash(qlge, addr, &data);
+	(void) ql_flash_erase_sector(qlge, test_addr);
+	(void) ql_write_flash(qlge, addr, old_data);
+	(void) ql_read_flash(qlge, addr, &data);
 	QL_PRINT(DBG_FLASH, ("write back old value addr %x value %x\n",
 	    test_addr, data));
 
 	/* test done, protect the flash to forbid any more flash writting */
-	ql_protect_flash(qlge);
+	(void) ql_protect_flash(qlge);
 
 }
 
@@ -1355,7 +1356,7 @@
 {
 	uint32_t data, old_data;
 
-	qlge_dump_fcode(qlge, (uint8_t *)&old_data, sizeof (old_data),
+	(void) qlge_dump_fcode(qlge, (uint8_t *)&old_data, sizeof (old_data),
 	    test_addr);
 	QL_PRINT(DBG_FLASH, ("read addr %x old value %x\n",
 	    test_addr, old_data));
@@ -1364,7 +1365,8 @@
 
 	QL_PRINT(DBG_FLASH, ("write new test value %x\n", data));
 	qlge_load_flash(qlge, (uint8_t *)&data, sizeof (data), test_addr);
-	qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data), test_addr);
+	(void) qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data),
+	    test_addr);
 	if (data != 0x12345678) {
 		cmn_err(CE_WARN,
 		    "flash write test failed, get data %x after writing",
@@ -1373,7 +1375,7 @@
 	/* write old value to it and read back to restore */
 	qlge_load_flash(qlge, (uint8_t *)&old_data, sizeof (old_data),
 	    test_addr);
-	qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data),
+	(void) qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data),
 	    test_addr);
 	QL_PRINT(DBG_FLASH, ("write back old value addr %x value %x verified\n",
 	    test_addr, data));
--- a/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_gld.c	Mon Nov 09 16:53:15 2009 -0800
+++ b/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_gld.c	Mon Nov 09 17:37:50 2009 -0800
@@ -95,7 +95,7 @@
 	 * Write default ethernet address to chip register Mac
 	 * Address slot 0 and Enable Primary Mac Function.
 	 */
-	ql_unicst_set(qlge,
+	(void) ql_unicst_set(qlge,
 	    (uint8_t *)qlge->unicst_addr[0].addr.ether_addr_octet, 0);
 	qlge->stats.rpackets = 0;
 	qlge->stats.rbytes = 0;
@@ -103,7 +103,7 @@
 	qlge->stats.obytes = 0;
 	mutex_exit(&qlge->hw_mutex);
 
-	ql_do_start(qlge);
+	(void) ql_do_start(qlge);
 	mutex_exit(&qlge->gen_mutex);
 
 	mutex_enter(&qlge->mbx_mutex);
@@ -126,7 +126,7 @@
 		mutex_exit(&qlge->gen_mutex);
 		return;
 	}
-	ql_do_stop(qlge);
+	(void) ql_do_stop(qlge);
 	mutex_exit(&qlge->gen_mutex);
 	qlge->mac_flags = QL_MAC_STOPPED;
 }
--- a/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_mpi.c	Mon Nov 09 16:53:15 2009 -0800
+++ b/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_mpi.c	Mon Nov 09 17:37:50 2009 -0800
@@ -250,7 +250,7 @@
 		    == DDI_SUCCESS) {
 			QL_PRINT(DBG_MBX, ("%s(%d) PI Intr received",
 			    __func__, qlge->instance));
-			ql_read_mailbox_cmd(qlge, p_results, 0);
+			(void) ql_read_mailbox_cmd(qlge, p_results, 0);
 			/*
 			 * Sometimes, the incoming messages is not what we are
 			 * waiting for, ie. async events, then, continue to
@@ -381,7 +381,7 @@
 		    "Firmware Ver# %x",
 		    __func__, qlge->instance, mbx_cmds->mb[1],
 		    mbx_cmds->mb[2], mbx_cmds->mb[3]);
-		ql_8xxx_binary_core_dump(qlge, &qlge->ql_mpi_coredump);
+		(void) ql_8xxx_binary_core_dump(qlge, &qlge->ql_mpi_coredump);
 		break;
 	case MBA_LINK_UP /* 8011h */:
 		QL_PRINT(DBG_MBX, ("%s(%d): MBA_LINK_UP received\n",
@@ -664,7 +664,8 @@
 	 */
 	mutex_enter(&qlge->mbx_mutex);
 
-	ql_read_mailbox_cmd(qlge, &qlge->received_mbx_cmds, qlge->max_read_mbx);
+	(void) ql_read_mailbox_cmd(qlge, &qlge->received_mbx_cmds,
+	    qlge->max_read_mbx);
 
 	/*
 	 * process PI interrupt as async events, if not done,
@@ -719,7 +720,7 @@
 	    == DDI_SUCCESS) {
 		QL_PRINT(DBG_MBX, ("%s(%d) PI Intr received",
 		    __func__, qlge->instance));
-		ql_read_mailbox_cmd(qlge, &mbx_results, 0);
+		(void) ql_read_mailbox_cmd(qlge, &mbx_results, 0);
 
 		ql_write_reg(qlge, REG_HOST_CMD_STATUS,
 		    HOST_CMD_CLEAR_RISC_TO_HOST_INTR);