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changeset 10305:f6df05de8700

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6848306 ixgbe need to update the latest shared code (2.9.1.1) from Intel 6790324 NICDRV case02 ping auto may fail on ixgbe 6855939 Niantic UDP packet rate is 30% lower than Oplin due to excessive TX interrupt 6865071 workaround for 82598/82599 h/w tx descriptor limit can panic the system 6863015 ixgbe driver does not need to drop tx packets when some function calls fail
author Paul Guo <Paul.Guo@Sun.COM>
date Fri, 14 Aug 2009 11:26:28 +0800
parents af5a60358231
children 599f03fafdf3
files usr/src/pkgdefs/SUNWixgbe/postinstall usr/src/uts/common/io/ixgbe/ixgbe_82598.c usr/src/uts/common/io/ixgbe/ixgbe_82599.c usr/src/uts/common/io/ixgbe/ixgbe_api.c usr/src/uts/common/io/ixgbe/ixgbe_api.h usr/src/uts/common/io/ixgbe/ixgbe_common.c usr/src/uts/common/io/ixgbe/ixgbe_common.h usr/src/uts/common/io/ixgbe/ixgbe_main.c usr/src/uts/common/io/ixgbe/ixgbe_phy.c usr/src/uts/common/io/ixgbe/ixgbe_phy.h usr/src/uts/common/io/ixgbe/ixgbe_sw.h usr/src/uts/common/io/ixgbe/ixgbe_tx.c usr/src/uts/common/io/ixgbe/ixgbe_type.h
diffstat 13 files changed, 612 insertions(+), 149 deletions(-) [+]
line wrap: on
line diff
--- a/usr/src/pkgdefs/SUNWixgbe/postinstall	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/pkgdefs/SUNWixgbe/postinstall	Fri Aug 14 11:26:28 2009 +0800
@@ -141,6 +141,7 @@
 	"pciex8086,10f7"
 	"pciex8086,10f9"
 	"pciex8086,10fb"
+	"pciex8086,10fc"
 	"pciex8086,1507"
 	"pciex8086,1508"
 	"pciex8086,1514"'	\
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82598.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82598.c	Fri Aug 14 11:26:28 2009 +0800
@@ -26,13 +26,14 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.138 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.144 v2-9-1-1_2009-6-10_NSW1 */
 
 #include "ixgbe_type.h"
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 
+u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
     ixgbe_link_speed *speed, bool *autoneg);
@@ -59,6 +60,7 @@
     u8 *eeprom_data);
 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
+void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
 
 /*
  * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
@@ -113,6 +115,7 @@
 	    &ixgbe_get_supported_physical_layer_82598;
 	mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
 	mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
+	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
 
 	/* RAR, Multicast, VLAN */
 	mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
@@ -133,12 +136,6 @@
 	/* SFP+ Module */
 	phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
 
-	/*
-	 * Call PHY identify routine to assign the phy type for PHY init
-	 * and media type determination
-	 */
-	phy->ops.identify(hw);
-
 	/* Link */
 	mac->ops.check_link = &ixgbe_check_mac_link_82598;
 	mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
@@ -184,6 +181,10 @@
 		phy->ops.get_firmware_version =
 		    &ixgbe_get_phy_firmware_version_tnx;
 		break;
+	case ixgbe_phy_aq:
+		phy->ops.get_firmware_version =
+		    &ixgbe_get_phy_firmware_version_aq;
+		break;
 	case ixgbe_phy_nl:
 		phy->ops.reset = &ixgbe_reset_phy_nl;
 
@@ -283,7 +284,8 @@
 
 	/* Detect if there is a copper PHY attached. */
 	if (hw->phy.type == ixgbe_phy_cu_unknown ||
-	    hw->phy.type == ixgbe_phy_tn) {
+	    hw->phy.type == ixgbe_phy_tn ||
+	    hw->phy.type == ixgbe_phy_aq) {
 		media_type = ixgbe_media_type_copper;
 		goto out;
 	}
@@ -411,7 +413,7 @@
 	}
 
 	/* Configure pause time (2 TCs per register) */
-	reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
+	reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
 	if ((packetbuf_num & 1) == 0)
 		reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 	else
@@ -673,6 +675,7 @@
 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
+	s32 phy_status = IXGBE_SUCCESS;
 	u32 ctrl;
 	u32 gheccr;
 	u32 i;
@@ -720,13 +723,16 @@
 		/* PHY ops must be identified and initialized prior to reset */
 
 		/* Init PHY and function pointers, perform SFP setup */
-		status = hw->phy.ops.init(hw);
-		/* Do not return error if SFP module is not supported. */
-		status = IXGBE_SUCCESS;
+		phy_status = hw->phy.ops.init(hw);
+		if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
+			goto reset_hw_out;
+		else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
+			goto no_phy_reset;
 
 		hw->phy.ops.reset(hw);
 	}
 
+no_phy_reset:
 	/*
 	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 	 * access and verify no pending requests before reset
@@ -776,14 +782,18 @@
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 	}
 
+	/* Store the permanent mac address */
+	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
 	/*
 	 * Store MAC address from RAR0, clear receive address registers, and
 	 * clear the multicast table
 	 */
 	hw->mac.ops.init_rx_addrs(hw);
 
-	/* Store the permanent mac address */
-	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+reset_hw_out:
+	if (phy_status != IXGBE_SUCCESS)
+		status = phy_status;
 
 	return (status);
 }
@@ -1107,3 +1117,33 @@
 out:
 	return (physical_layer);
 }
+
+/*
+ * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
+ * port devices.
+ * @hw: pointer to the HW structure
+ *
+ * Calls common function and corrects issue with some single port devices
+ * that enable LAN1 but not LAN0.
+ */
+void
+ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
+{
+	struct ixgbe_bus_info *bus = &hw->bus;
+	u16 pci_gen, pci_ctrl2;
+
+	ixgbe_set_lan_id_multi_port_pcie(hw);
+
+	/* check if LAN0 is disabled */
+	hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
+	if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
+		hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
+
+		/* if LAN0 is completely disabled force function to 0 */
+		if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
+		    !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
+		    !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
+			bus->func = 0;
+		}
+	}
+}
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82599.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82599.c	Fri Aug 14 11:26:28 2009 +0800
@@ -26,13 +26,14 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.155 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.176 v2-9-1-1_2009-6-10_NSW1 */
 
 #include "ixgbe_type.h"
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 
+u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw);
 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
     ixgbe_link_speed *speed, bool *autoneg);
@@ -73,6 +74,7 @@
 s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps);
+static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
 
 void
 ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
@@ -115,6 +117,8 @@
 
 	/* Identify the PHY or SFP module */
 	ret_val = phy->ops.identify(hw);
+	if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
+		goto init_phy_ops_out;
 
 	/* Setup function pointers based on detected SFP module and speeds */
 	ixgbe_init_mac_link_ops_82599(hw);
@@ -137,10 +141,15 @@
 		phy->ops.get_firmware_version =
 		    &ixgbe_get_phy_firmware_version_tnx;
 		break;
+	case ixgbe_phy_aq:
+		phy->ops.get_firmware_version =
+		    &ixgbe_get_phy_firmware_version_aq;
+		break;
 	default:
 		break;
 	}
 
+init_phy_ops_out:
 	return (ret_val);
 }
 
@@ -163,16 +172,27 @@
 		if (ret_val != IXGBE_SUCCESS)
 			goto setup_sfp_out;
 
+		/* PHY config will finish before releasing the semaphore */
+		ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
+		if (ret_val != IXGBE_SUCCESS) {
+			ret_val = IXGBE_ERR_SWFW_SYNC;
+			goto setup_sfp_out;
+		}
+
 		hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		while (data_value != 0xffff) {
 			IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 			IXGBE_WRITE_FLUSH(hw);
 			hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		}
-		/* Now restart DSP */
-		IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
-		IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
-		IXGBE_WRITE_FLUSH(hw);
+		/* Now restart DSP by setting Restart_AN */
+		IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
+		    (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
+
+		/* Release the semaphore */
+		ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
+		/* Delay obtaining semaphore again to allow FW access */
+		msec_delay(hw->eeprom.semaphore_delay);
 	}
 
 setup_sfp_out:
@@ -368,7 +388,8 @@
 
 	/* Detect if there is a copper PHY attached. */
 	if (hw->phy.type == ixgbe_phy_cu_unknown ||
-	    hw->phy.type == ixgbe_phy_tn) {
+	    hw->phy.type == ixgbe_phy_tn ||
+	    hw->phy.type == ixgbe_phy_aq) {
 		media_type = ixgbe_media_type_copper;
 		goto out;
 	}
@@ -376,6 +397,7 @@
 	switch (hw->device_id) {
 	case IXGBE_DEV_ID_82599_KX4:
 	case IXGBE_DEV_ID_82599_KX4_SIK:
+	case IXGBE_DEV_ID_82599_XAUI_LOM:
 		/* Default device ID is mezzanine card KX/KX4 */
 		media_type = ixgbe_media_type_backplane;
 		break;
@@ -481,6 +503,7 @@
 	ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	u32 speedcnt = 0;
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
+	u32 i = 0;
 	bool link_up = false;
 	bool negotiation;
 
@@ -491,6 +514,25 @@
 
 	speed &= link_speed;
 
+	/* Set autoneg_advertised value based on input link speed */
+	hw->phy.autoneg_advertised = 0;
+
+	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
+		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
+
+	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
+		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
+
+	/*
+	 * When the driver changes the link speeds that it can support,
+	 * it sets autotry_restart to true to indicate that we need to
+	 * initiate a new autotry session with the link partner.  To do
+	 * so, we set the speed then disable and re-enable the tx laser, to
+	 * alert the link partner that it also needs to restart autotry on its
+	 * end.  This is consistent with true clause 37 autoneg, which also
+	 * involves a loss of signal.
+	 */
+
 	/*
 	 * Try each speed one by one, highest priority first.  We do this in
 	 * software because 10gb fiber doesn't support speed autonegotiation.
@@ -507,7 +549,7 @@
 		if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
 			goto out;
 
-		/* Set hardware SDP's */
+		/* Set the module link speed */
 		esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 
@@ -520,15 +562,35 @@
 		if (status != IXGBE_SUCCESS)
 			goto out;
 
-		msec_delay(100);
+		/* Flap the tx laser if it has not already been done */
+		if (hw->mac.autotry_restart) {
+			/* Disable tx laser; allow 100us to go dark per spec */
+			esdp_reg |= IXGBE_ESDP_SDP3;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			usec_delay(100);
+
+			/* Enable tx laser; allow 2ms to light up per spec */
+			esdp_reg &= ~IXGBE_ESDP_SDP3;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			msec_delay(2);
+
+			hw->mac.autotry_restart = false;
+		}
 
-		/* If we have link, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
-		if (status != IXGBE_SUCCESS)
-			goto out;
+		/* The controller may take up to 500ms at 10g to acquire link */
+		for (i = 0; i < 5; i++) {
+			/* Wait for the link partner to also set speed */
+			msec_delay(100);
 
-		if (link_up)
-			goto out;
+			/* If we have link, just jump out */
+			status = ixgbe_check_link(hw, &link_speed,
+			    &link_up, false);
+			if (status != IXGBE_SUCCESS)
+				goto out;
+
+			if (link_up)
+				goto out;
+		}
 	}
 
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
@@ -544,7 +606,7 @@
 		if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
 			goto out;
 
-		/* Set hardware SDP's */
+		/* Set the module link speed */
 		esdp_reg &= ~IXGBE_ESDP_SDP5;
 		esdp_reg |= IXGBE_ESDP_SDP5_DIR;
 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
@@ -558,6 +620,22 @@
 		if (status != IXGBE_SUCCESS)
 			goto out;
 
+		/* Flap the tx laser if it has not already been done */
+		if (hw->mac.autotry_restart) {
+			/* Disable tx laser; allow 100us to go dark per spec */
+			esdp_reg |= IXGBE_ESDP_SDP3;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			usec_delay(100);
+
+			/* Enable tx laser; allow 2ms to light up per spec */
+			esdp_reg &= ~IXGBE_ESDP_SDP3;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			msec_delay(2);
+
+			hw->mac.autotry_restart = false;
+		}
+
+		/* Wait for the link partner to also set speed */
 		msec_delay(100);
 
 		/* If we have link, just jump out */
@@ -651,6 +729,8 @@
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
+	u32 start_autoc = autoc;
+	u32 orig_autoc = 0;
 	u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 	u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
@@ -667,15 +747,26 @@
 
 	if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 		status = IXGBE_ERR_LINK_SETUP;
-	} else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
+		goto out;
+	}
+
+	/*
+	 * Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support
+	 */
+	if (hw->mac.orig_link_settings_stored)
+		orig_autoc = hw->mac.orig_autoc;
+	else
+		orig_autoc = autoc;
+
+	if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 		/* Set KX4/KX/KR support according to speed requested */
 		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 		if (speed & IXGBE_LINK_SPEED_10GB_FULL)
-			if (autoc & IXGBE_AUTOC_KX4_SUPP)
+			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 				autoc |= IXGBE_AUTOC_KX4_SUPP;
-			if (autoc & IXGBE_AUTOC_KR_SUPP)
+			if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
 				autoc |= IXGBE_AUTOC_KR_SUPP;
 		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 			autoc |= IXGBE_AUTOC_KX_SUPP;
@@ -701,7 +792,7 @@
 			}
 	}
 
-	if (status == IXGBE_SUCCESS) {
+	if (autoc != start_autoc) {
 		/* Restart link */
 		autoc |= IXGBE_AUTOC_AN_RESTART;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
@@ -803,12 +894,18 @@
 	/* Identify PHY and related function pointers */
 	status = hw->phy.ops.init(hw);
 
+	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
+		goto reset_hw_out;
+
 	/* Setup SFP module if there is one present. */
 	if (hw->phy.sfp_setup_needed) {
 		status = hw->mac.ops.setup_sfp(hw);
 		hw->phy.sfp_setup_needed = false;
 	}
 
+	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
+		goto reset_hw_out;
+
 	/* Reset PHY */
 	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
 		hw->phy.ops.reset(hw);
@@ -877,6 +974,9 @@
 		}
 	}
 
+	/* Store the permanent mac address */
+	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
 	/*
 	 * Store MAC address from RAR0, clear receive address registers, and
 	 * clear the multicast table.  Also reset num_rar_entries to 128,
@@ -885,8 +985,8 @@
 	hw->mac.num_rar_entries = 128;
 	hw->mac.ops.init_rx_addrs(hw);
 
-	/* Store the permanent mac address */
-	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+	/* Store the permanent SAN mac address */
+	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 
 	/* Add the SAN MAC address to the RAR only if it's a valid address */
 	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
@@ -897,6 +997,7 @@
 		hw->mac.num_rar_entries--;
 	}
 
+reset_hw_out:
 	return (status);
 }
 
@@ -1011,6 +1112,7 @@
 		}
 	} else {
 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return (IXGBE_ERR_PARAM);
 	}
 done:
 	return (IXGBE_SUCCESS);
@@ -1040,6 +1142,7 @@
 		}
 	} else {
 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return (IXGBE_ERR_PARAM);
 	}
 
 	return (IXGBE_SUCCESS);
@@ -1115,6 +1218,7 @@
 				regindex = first_empty_slot;
 			else {
 				DEBUGOUT("No space in VLVF.\n");
+				goto out;
 			}
 		}
 
@@ -1162,6 +1266,7 @@
 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
 	}
 
+out:
 	return (IXGBE_SUCCESS);
 }
 
@@ -1211,16 +1316,75 @@
 s32
 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
 {
+	int i;
 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
 	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
+
+	/*
+	 * Before starting reinitialization process,
+	 * FDIRCMD.CMD must be zero.
+	 */
+	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
+		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
+		    IXGBE_FDIRCMD_CMD_MASK))
+			break;
+		usec_delay(10);
+	}
+	if (i >= IXGBE_FDIRCMD_CMD_POLL) {
+		DEBUGOUT("Flow Director previous command isn't complete, "
+		    "aborting table re-initialization. \n");
+		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+	}
+
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
 	IXGBE_WRITE_FLUSH(hw);
+	/*
+	 * 82599 adapters flow director init flow cannot be restarted,
+	 * Workaround 82599 silicon errata by performing the following steps
+	 * before re-writing the FDIRCTRL control register with the same value.
+	 * - write 1 to bit 8 of FDIRCMD register &
+	 * - write 0 to bit 8 of FDIRCMD register
+	 */
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
+	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
+	    IXGBE_FDIRCMD_CLEARHT));
+	IXGBE_WRITE_FLUSH(hw);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
+	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
+	    ~IXGBE_FDIRCMD_CLEARHT));
+	IXGBE_WRITE_FLUSH(hw);
+	/*
+	 * Clear FDIR Hash register to clear any leftover hashes
+	 * waiting to be programmed.
+	 */
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
+	IXGBE_WRITE_FLUSH(hw);
+
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
+	IXGBE_WRITE_FLUSH(hw);
+
+	/* Poll init-done after we write FDIRCTRL register */
+	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
+		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
+		    IXGBE_FDIRCTRL_INIT_DONE)
+			break;
+		usec_delay(10);
+	}
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
+		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+	}
+
+	/* Clear FDIR statistics registers (read to clear) */
+	(void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
+	(void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
+	(void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
+	(void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
+	(void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
 
 	return (IXGBE_SUCCESS);
 }
 
-#define	IXGBE_FDIR_INIT_DONE_POLL	10
 /*
  * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
  * @hw: pointer to hardware structure
@@ -1446,26 +1610,33 @@
 	 *    hash[15:0] = 0;
 	 *    for (i = 0; i < 351; i++) {
 	 *	if (int_key[i])
-	 *	hash ^= int_stream[(i + 15):i];
+	 *		hash ^= int_stream[(i + 15):i];
 	 *    }
 	 */
 
 	union {
-		u32	key[11];
-		u8	key_stream[44];
+		u64 fill[6];
+		u32 key[11];
+		u8 key_stream[44];
 	} tmp_key;
 
 	u8 *stream = (u8 *)atr_input;
 	u8 int_key[44];		/* upper-most bit unused */
 	u8 hash_str[46];	/* upper-most 2 bits unused */
 	u16 hash_result = 0;
-	u16 tmp = 0;
 	int i, j, k, h;
 
-	(void) memset(&tmp_key, 0, sizeof (tmp_key));
+	/*
+	 * Initialize the fill member to prevent warnings
+	 * on some compilers
+	 */
+	tmp_key.fill[0] = 0;
+
 	/* First load the temporary key stream */
-	for (i = 0; i < 11; i++)
-		tmp_key.key[i] = key;
+	for (i = 0; i < 6; i++) {
+		u64 fillkey = ((u64)key << 32) | key;
+		tmp_key.fill[i] = fillkey;
+	}
 
 	/*
 	 * Set the interim key for the hashing.  Bit 352 is unused, so we must
@@ -1473,9 +1644,9 @@
 	 */
 	int_key[0] = tmp_key.key_stream[0] >> 1;
 	for (i = 1, j = 0; i < 44; i++) {
-		int_key[i] = (tmp_key.key_stream[j] & 0x1) << 7;
+		unsigned int this_key = tmp_key.key_stream[j] << 7;
 		j++;
-		int_key[i] |= tmp_key.key_stream[j] >> 1;
+		int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
 	}
 
 	/*
@@ -1484,11 +1655,11 @@
 	 */
 	hash_str[0] = (stream[40] & 0x7f) >> 1;
 	for (i = 1, j = 40; i < 46; i++) {
-		hash_str[i] = (stream[j] & 0x1) << 7;
+		unsigned int this_str = stream[j] << 7;
 		j++;
 		if (j > 41)
 			j = 0;
-		hash_str[i] |= stream[j] >> 1;
+		hash_str[i] = (u8)(this_str | (stream[j] >> 1));
 	}
 
 	/*
@@ -1498,7 +1669,7 @@
 	 */
 	for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
 		for (h = 0; h < 8 && k < 351; h++, k++) {
-			if ((int_key[j] >> h) & 0x1) {
+			if (int_key[j] & (1 << h)) {
 				/*
 				 * Key bit is set, XOR in the current 16-bit
 				 * string.  Example of processing:
@@ -1513,11 +1684,11 @@
 				 *		(hash_str[i - 1] & 0xff << 1) |
 				 *		(hash_str[i] & 0x80 >> 7)
 				 */
-				tmp = ((hash_str[i] & (0xff << h)) >> h);
-				tmp |= ((hash_str[i - 1] & 0xff) << (8 - h));
-				tmp |= (hash_str[i - 2] & (0xff >> (8 - h)))
+				int tmp = (hash_str[i] >> h);
+				tmp |= (hash_str[i - 1] << (8 - h));
+				tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
 				    << (16 - h);
-				hash_result ^= tmp;
+				hash_result ^= (u16)tmp;
 			}
 		}
 	}
@@ -2152,6 +2323,12 @@
 	}
 	IXGBE_WRITE_FLUSH(hw);
 
+	/* We need to run link autotry after the driver loads */
+	hw->mac.autotry_restart = true;
+
+	if (ret_val == IXGBE_SUCCESS)
+		ret_val = ixgbe_verify_fw_version_82599(hw);
+
 	return (ret_val);
 }
 
@@ -2206,6 +2383,7 @@
 	hw->phy.ops.identify(hw);
 
 	if (hw->phy.type == ixgbe_phy_tn ||
+	    hw->phy.type == ixgbe_phy_tn ||
 	    hw->phy.type == ixgbe_phy_cu_unknown) {
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
@@ -2225,14 +2403,17 @@
 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
 			    IXGBE_PHYSICAL_LAYER_1000BASE_BX;
 			goto out;
-		} else
+		} else {
 			/* SFI mode so read SFP module */
 			goto sfp_check;
+		}
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
+		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
+			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
 		goto out;
 	case IXGBE_AUTOC_LMS_10G_SERIAL:
 		if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
@@ -2458,3 +2639,50 @@
 san_mac_addr_out:
 	return (status);
 }
+
+/*
+ * ixgbe_verify_fw_version_82599 - verify fw version for 82599
+ * @hw: pointer to hardware structure
+ *
+ * Verifies that installed the firmware version is 0.6 or higher
+ * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
+ *
+ * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
+ * if the FW version is not supported.
+ */
+static s32
+ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
+{
+	s32 status = IXGBE_ERR_EEPROM_VERSION;
+	u16 fw_offset, fw_ptp_cfg_offset;
+	u16 fw_version = 0;
+
+	/* firmware check is only necessary for SFI devices */
+	if (hw->phy.media_type != ixgbe_media_type_fiber) {
+		status = IXGBE_SUCCESS;
+		goto fw_version_out;
+	}
+
+	/* get the offset to the Firmware Module block */
+	hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
+
+	if ((fw_offset == 0) || (fw_offset == 0xFFFF))
+		goto fw_version_out;
+
+	/* get the offset to the Pass Through Patch Configuration block */
+	hw->eeprom.ops.read(hw, (fw_offset +
+	    IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset);
+
+	if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
+		goto fw_version_out;
+
+	/* get the firmware version */
+	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4),
+	    &fw_version);
+
+	if (fw_version > 0x5)
+		status = IXGBE_SUCCESS;
+
+fw_version_out:
+	return (status);
+}
--- a/usr/src/uts/common/io/ixgbe/ixgbe_api.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.c	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.117 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.120 v2-9-1-1_2009-6-10_NSW1 */
 
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -102,6 +102,7 @@
 			break;
 		case IXGBE_DEV_ID_82599_KX4:
 		case IXGBE_DEV_ID_82599_KX4_SIK:
+		case IXGBE_DEV_ID_82599_XAUI_LOM:
 		case IXGBE_DEV_ID_82599_SFP:
 		case IXGBE_DEV_ID_82599_SPW:
 		case IXGBE_DEV_ID_82599_CX4:
@@ -986,3 +987,33 @@
 	return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
 	    (hw, regval), IXGBE_NOT_IMPLEMENTED);
 }
+
+/*
+ * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to acquire
+ *
+ * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
+ * function (CSR, PHY0, PHY1, EEPROM, Flash)
+ */
+s32
+ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
+{
+	return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
+	    (hw, mask), IXGBE_NOT_IMPLEMENTED);
+}
+
+/*
+ * ixgbe_release_swfw_semaphore - Release SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to release
+ *
+ * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
+ * function (CSR, PHY0, PHY1, EEPROM, Flash)
+ */
+void
+ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
+{
+	if (hw->mac.ops.release_swfw_sync)
+		hw->mac.ops.release_swfw_sync(hw, mask);
+}
--- a/usr/src/uts/common/io/ixgbe/ixgbe_api.h	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.h	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.73 v2-7-8_2009-4-7  */
+/* IntelVersion: 1.74 v2-9-1-1_2009-6-10_NSW1 */
 
 #ifndef _IXGBE_API_H
 #define	_IXGBE_API_H
@@ -147,5 +147,7 @@
 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
 
 #endif /* _IXGBE_API_H */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.c	Fri Aug 14 11:26:28 2009 +0800
@@ -25,7 +25,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.199 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.206 v2-9-1-1_2009-6-10_NSW1 */
 
 #include "ixgbe_common.h"
 #include "ixgbe_api.h"
@@ -83,6 +83,8 @@
 	mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
 	mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
 	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
+	mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
+	mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
 
 	/* LEDs */
 	mac->ops.led_on = &ixgbe_led_on_generic;
@@ -136,9 +138,6 @@
 
 	/* PHY ops initialization must be done in reset_hw() */
 
-	/* Identify the PHY */
-	hw->phy.ops.identify(hw);
-
 	/* Clear the VLAN filter table */
 	hw->mac.ops.clear_vfta(hw);
 
@@ -624,8 +623,6 @@
 		ixgbe_shift_out_eeprom_bits(hw, data, 16);
 		ixgbe_standby_eeprom(hw);
 
-		msec_delay(hw->eeprom.semaphore_delay);
-
 		/* Done with writing - release the EEPROM */
 		ixgbe_release_eeprom(hw);
 	}
@@ -820,13 +817,10 @@
 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM;
-	u32 timeout;
+	u32 timeout = 2000;
 	u32 i;
 	u32 swsm;
 
-	/* Set timeout value based on size of EEPROM */
-	timeout = hw->eeprom.word_size + 1;
-
 	/* Get SMBI software semaphore between device drivers first */
 	for (i = 0; i < timeout; i++) {
 		/*
@@ -838,7 +832,7 @@
 			status = IXGBE_SUCCESS;
 			break;
 		}
-		msec_delay(1);
+		usec_delay(50);
 	}
 
 	/* Now get the semaphore between SW/FW through the SWESMBI bit */
@@ -1114,6 +1108,9 @@
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 
 	ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+
+	/* Delay before attempt to obtain semaphore again to allow FW access */
+	msec_delay(hw->eeprom.semaphore_delay);
 }
 
 /*
@@ -1685,6 +1682,7 @@
 	s32 ret_val = IXGBE_SUCCESS;
 	u32 mflcn_reg, fccfg_reg;
 	u32 reg;
+	u32 rx_pba_size;
 
 	DEBUGFUNC("ixgbe_fc_enable_generic");
 
@@ -1751,22 +1749,42 @@
 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
 
-	/* Set up and enable Rx high/low water mark thresholds, enable XON. */
-	if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-		if (hw->fc.send_xon) {
-			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
-			    (hw->fc.low_water | IXGBE_FCRTL_XONE));
-		} else {
-			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
-			    hw->fc.low_water);
+	reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
+	/* Thresholds are different for link flow control when in DCB mode */
+	if (reg & IXGBE_MTQC_RT_ENA) {
+		rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+
+		/* Always disable XON for LFC when in DCB mode */
+		reg = (rx_pba_size >> 5) & 0xFFE0;
+		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
+
+		reg = (rx_pba_size >> 2) & 0xFFE0;
+		if (hw->fc.current_mode & ixgbe_fc_tx_pause)
+			reg |= IXGBE_FCRTH_FCEN;
+		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
+	} else {
+		/*
+		 * Set up and enable Rx high/low water mark thresholds,
+		 * enable XON.
+		 */
+		if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
+			if (hw->fc.send_xon) {
+				IXGBE_WRITE_REG(hw,
+				    IXGBE_FCRTL_82599(packetbuf_num),
+				    (hw->fc.low_water | IXGBE_FCRTL_XONE));
+			} else {
+				IXGBE_WRITE_REG(hw,
+				    IXGBE_FCRTL_82599(packetbuf_num),
+				    hw->fc.low_water);
+			}
+
+			IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
+			    (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 		}
-
-		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
-		    (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 	}
 
 	/* Configure pause time (2 TCs per register) */
-	reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
+	reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
 	if ((packetbuf_num & 1) == 0)
 		reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 	else
@@ -2134,6 +2152,7 @@
 	hw->mac.ops.check_link(hw, &speed, &link_up, false);
 
 	if (!link_up) {
+		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 		autoc_reg |= IXGBE_AUTOC_FLU;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 		msec_delay(10);
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.h	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.h	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.90 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.90 v2-9-1-1_2009-6-10_NSW1 */
 
 #ifndef _IXGBE_COMMON_H
 #define	_IXGBE_COMMON_H
--- a/usr/src/uts/common/io/ixgbe/ixgbe_main.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_main.c	Fri Aug 14 11:26:28 2009 +0800
@@ -1212,7 +1212,7 @@
 ixgbe_chip_start(ixgbe_t *ixgbe)
 {
 	struct ixgbe_hw *hw = &ixgbe->hw;
-	int i;
+	int ret_val, i;
 
 	ASSERT(mutex_owned(&ixgbe->gen_lock));
 
@@ -1237,9 +1237,17 @@
 	/*
 	 * Configure/Initialize hardware
 	 */
-	if (ixgbe_init_hw(hw) != IXGBE_SUCCESS) {
-		ixgbe_error(ixgbe, "Failed to initialize hardware");
-		return (IXGBE_FAILURE);
+	ret_val = ixgbe_init_hw(hw);
+	if (ret_val != IXGBE_SUCCESS) {
+		if (ret_val == IXGBE_ERR_EEPROM_VERSION) {
+			ixgbe_error(ixgbe,
+			    "This 82599 device is pre-release and contains"
+			    " outdated firmware, please contact your hardware"
+			    " vendor for a replacement.");
+		} else {
+			ixgbe_error(ixgbe, "Failed to initialize hardware");
+			return (IXGBE_FAILURE);
+		}
 	}
 
 	/*
@@ -2476,8 +2484,8 @@
 	    DEFAULT_RX_LIMIT_PER_INTR);
 
 	/*
-	 * Interrupt throttling is per 256ns in 82598 and 2 usec increments
-	 * in 82599.
+	 * Interrupt throttling is per 256ns in 82598 and 2.048usec
+	 * (256ns * 8) increments in 82599.
 	 */
 	switch (hw->mac.type) {
 	case ixgbe_mac_82598EB:
@@ -2491,6 +2499,14 @@
 		    PROP_INTR_THROTTLING,
 		    MIN_INTR_THROTTLING, MAX_INTR_THROTTLING_82599,
 		    DEFAULT_INTR_THROTTLING_82599);
+
+		/*
+		 * 82599 requires the interupt throttling rate is
+		 * a multiple of 8. This is enforced by the register
+		 * definiton.
+		 */
+		ixgbe->intr_throttling[0] = ixgbe->intr_throttling[0] &
+		    0xFF8;
 		break;
 	}
 }
@@ -2740,7 +2756,9 @@
 	result = B_FALSE;
 	for (i = 0; i < ixgbe->num_tx_rings; i++) {
 		tx_ring = &ixgbe->tx_rings[i];
-		tx_ring->tx_recycle(tx_ring);
+		if (tx_ring->tbd_free <= tx_ring->recycle_thresh) {
+			tx_ring->tx_recycle(tx_ring);
+		}
 
 		if (tx_ring->recycle_fail > 0)
 			tx_ring->stall_watchdog++;
@@ -3296,8 +3314,8 @@
 		if ((ddi_taskq_dispatch(ixgbe->lsc_taskq,
 		    ixgbe_sfp_check, (void *)ixgbe,
 		    DDI_NOSLEEP)) != DDI_SUCCESS) {
-			ixgbe_log(ixgbe,
-			    "No memory available to dispatch taskq");
+			ixgbe_log(ixgbe, "No memory available to dispatch "
+			    "taskq for SFP check");
 		}
 	}
 }
@@ -4633,6 +4651,13 @@
 	ixgbe_enable_ivar(ixgbe, r_idx, 0);
 
 	BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
+
+	/*
+	 * To trigger a Rx interrupt to on this ring
+	 */
+	IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_EICS, (1 << v_idx));
+	IXGBE_WRITE_FLUSH(&ixgbe->hw);
+
 	mutex_exit(&ixgbe->gen_lock);
 
 	return (0);
--- a/usr/src/uts/common/io/ixgbe/ixgbe_phy.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_phy.c	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.83 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.94 v2-9-1-1_2009-6-10_NSW1 */
 
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -189,6 +189,9 @@
 	case TN1010_PHY_ID:
 		phy_type = ixgbe_phy_tn;
 		break;
+	case AQ1002_PHY_ID:
+		phy_type = ixgbe_phy_aq;
+		break;
 	case QT2022_PHY_ID:
 		phy_type = ixgbe_phy_qt;
 		break;
@@ -450,7 +453,7 @@
 s32
 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_NOT_IMPLEMENTED;
+	s32 status = IXGBE_SUCCESS;
 	u32 time_out;
 	u32 max_time_out = 10;
 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@@ -491,7 +494,6 @@
 
 		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
-			status = IXGBE_SUCCESS;
 			break;
 		}
 	}
@@ -525,10 +527,14 @@
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 	}
+
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 	}
 
+	if (speed & IXGBE_LINK_SPEED_100_FULL)
+		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
+
 	/* Setup link based on the new speed settings */
 	hw->phy.ops.setup_link(hw);
 
@@ -560,6 +566,8 @@
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
+		if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
+			*speed |= IXGBE_LINK_SPEED_100_FULL;
 	}
 
 	return (status);
@@ -631,6 +639,22 @@
 }
 
 /*
+ * ixgbe_get_phy_firmware_version_aq - Gets the PHY Firmware Version
+ * @hw: pointer to hardware structure
+ * @firmware_version: pointer to the PHY Firmware Version
+ */
+s32
+ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw, u16 *firmware_version)
+{
+	s32 status = IXGBE_SUCCESS;
+
+	status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
+	    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version);
+
+	return (status);
+}
+
+/*
  * ixgbe_reset_phy_nl - Performs a PHY reset
  * @hw: pointer to hardware structure
  */
@@ -743,9 +767,15 @@
 	u8 comp_codes_1g = 0;
 	u8 comp_codes_10g = 0;
 	u8 oui_bytes[3] = {0, 0, 0};
-	u8 transmission_media = 0;
+	u8 cable_tech = 0;
 	u16 enforce_sfp = 0;
 
+	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
+		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
+		status = IXGBE_ERR_SFP_NOT_PRESENT;
+		goto out;
+	}
+
 	status = hw->phy.ops.read_i2c_eeprom(hw,
 	    IXGBE_SFF_IDENTIFIER, &identifier);
 
@@ -762,13 +792,16 @@
 	/* LAN ID is needed for sfp_type determination */
 	hw->mac.ops.set_lan_id(hw);
 
-	if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
+	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
+		hw->phy.type = ixgbe_phy_sfp_unsupported;
+		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+	} else {
 		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
 		    &comp_codes_1g);
 		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
 		    &comp_codes_10g);
-		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
-		    &transmission_media);
+		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
+		    &cable_tech);
 
 		/*
 		 * ID  Module
@@ -782,7 +815,7 @@
 		 * 6	SFP_SR/LR_CORE1 - 82599-specific
 		 */
 		if (hw->mac.type == ixgbe_mac_82598EB) {
-			if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
+			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 				hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 			else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 				hw->phy.sfp_type = ixgbe_sfp_type_sr;
@@ -791,7 +824,7 @@
 			else
 				hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 		} else if (hw->mac.type == ixgbe_mac_82599EB) {
-			if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
+			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 				if (hw->bus.lan_id == 0)
 					hw->phy.sfp_type =
 					    ixgbe_sfp_type_da_cu_core0;
@@ -820,6 +853,7 @@
 			hw->phy.sfp_setup_needed = true;
 
 		/* Determine if the SFP+ PHY is dual speed or not. */
+		hw->phy.multispeed_fiber = false;
 		if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 		    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 		    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
@@ -844,8 +878,7 @@
 
 			switch (vendor_oui) {
 			case IXGBE_SFF_VENDOR_OUI_TYCO:
-				if (transmission_media &
-				    IXGBE_SFF_TWIN_AX_CAPABLE)
+				if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 					hw->phy.type = ixgbe_phy_tw_tyco;
 				break;
 			case IXGBE_SFF_VENDOR_OUI_FTL:
@@ -858,8 +891,7 @@
 				hw->phy.type = ixgbe_phy_sfp_intel;
 				break;
 			default:
-				if (transmission_media &
-				    IXGBE_SFF_TWIN_AX_CAPABLE)
+				if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 					hw->phy.type = ixgbe_phy_tw_unknown;
 				else
 					hw->phy.type = ixgbe_phy_sfp_unknown;
@@ -867,11 +899,21 @@
 			}
 		}
 
-		if (hw->mac.type == ixgbe_mac_82598EB ||
-		    (hw->phy.sfp_type != ixgbe_sfp_type_sr &&
-		    hw->phy.sfp_type != ixgbe_sfp_type_lr &&
-		    hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 &&
-		    hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) {
+		/* All passive DA cables are supported */
+		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
+			status = IXGBE_SUCCESS;
+			goto out;
+		}
+
+		/* 1G SFP modules are not supported */
+		if (comp_codes_10g == 0) {
+			hw->phy.type = ixgbe_phy_sfp_unsupported;
+			status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+			goto out;
+		}
+
+		/* Anything else 82598-based is supported */
+		if (hw->mac.type == ixgbe_mac_82598EB) {
 			status = IXGBE_SUCCESS;
 			goto out;
 		}
@@ -1009,7 +1051,7 @@
     u8 dev_addr, u8 *data)
 {
 	s32 status = IXGBE_SUCCESS;
-	u32 max_retry = 1;
+	u32 max_retry = 10;
 	u32 retry = 0;
 	u16 swfw_mask = 0;
 	bool nack = 1;
@@ -1021,12 +1063,12 @@
 	else
 		swfw_mask = IXGBE_GSSR_PHY0_SM;
 
-	if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
-		status = IXGBE_ERR_SWFW_SYNC;
-		goto read_byte_out;
-	}
+	do {
+		if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
+			status = IXGBE_ERR_SWFW_SYNC;
+			goto read_byte_out;
+		}
 
-	do {
 		ixgbe_i2c_start(hw);
 
 		/* Device Address and write indication */
@@ -1069,6 +1111,8 @@
 		break;
 
 fail:
+		ixgbe_release_swfw_sync(hw, swfw_mask);
+		msec_delay(100);
 		ixgbe_i2c_bus_clear(hw);
 		retry++;
 		if (retry < max_retry)
--- a/usr/src/uts/common/io/ixgbe/ixgbe_phy.h	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_phy.h	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.32 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.34 v2-9-1-1_2009-6-10_NSW1 */
 
 #ifndef _IXGBE_PHY_H
 #define	_IXGBE_PHY_H
@@ -43,10 +43,10 @@
 #define	IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
 #define	IXGBE_SFF_1GBE_COMP_CODES	0x6
 #define	IXGBE_SFF_10GBE_COMP_CODES	0x3
-#define	IXGBE_SFF_TRANSMISSION_MEDIA	0x9
+#define	IXGBE_SFF_CABLE_TECHNOLOGY	0x8
 
 /* Bitmasks */
-#define	IXGBE_SFF_TWIN_AX_CAPABLE	0x80
+#define	IXGBE_SFF_DA_PASSIVE_CABLE	0x4
 #define	IXGBE_SFF_1GBASESX_CAPABLE	0x1
 #define	IXGBE_SFF_1GBASELX_CAPABLE	0x2
 #define	IXGBE_SFF_10GBASESR_CAPABLE	0x10
@@ -102,6 +102,8 @@
     ixgbe_link_speed *speed, bool *link_up);
 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
     u16 *firmware_version);
+s32 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw,
+    u16 *firmware_version);
 
 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
--- a/usr/src/uts/common/io/ixgbe/ixgbe_sw.h	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_sw.h	Fri Aug 14 11:26:28 2009 +0800
@@ -112,8 +112,8 @@
 
 #define	MAX_MTU				16366
 #define	MAX_RX_LIMIT_PER_INTR		4096
-#define	MAX_INTR_THROTTLING_82598	65535
-#define	MAX_INTR_THROTTLING_82599	0x7FC
+#define	MAX_INTR_THROTTLING_82598	0xFFFF
+#define	MAX_INTR_THROTTLING_82599	0xFF8
 
 #define	MAX_RX_COPY_THRESHOLD		9216
 #define	MAX_TX_COPY_THRESHOLD		9216
@@ -147,7 +147,7 @@
 #define	DEFAULT_MTU			ETHERMTU
 #define	DEFAULT_RX_LIMIT_PER_INTR	256
 #define	DEFAULT_INTR_THROTTLING_82598	200	/* In unit of 256 nsec */
-#define	DEFAULT_INTR_THROTTLING_82599	26	/* In unit of 2 usec */
+#define	DEFAULT_INTR_THROTTLING_82599	200	/* In unit of 256 nsec */
 #define	DEFAULT_RX_COPY_THRESHOLD	128
 #define	DEFAULT_TX_COPY_THRESHOLD	512
 #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
--- a/usr/src/uts/common/io/ixgbe/ixgbe_tx.c	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_tx.c	Fri Aug 14 11:26:28 2009 +0800
@@ -87,7 +87,7 @@
 	size_t mbsize;
 	int desc_num;
 	boolean_t copy_done, eop;
-	mblk_t *current_mp, *next_mp, *nmp;
+	mblk_t *current_mp, *next_mp, *nmp, *pull_mp = NULL;
 	tx_control_block_t *tcb;
 	ixgbe_tx_context_t tx_context, *ctx;
 	link_list_t pending_list;
@@ -400,34 +400,54 @@
 		/*
 		 * pull up the mblk and send it out with bind way
 		 */
-		if ((nmp = msgpullup(mp, -1)) == NULL) {
-			freemsg(mp);
-			return (NULL);
-		} else {
-			freemsg(mp);
-			mp = nmp;
+		if ((pull_mp = msgpullup(mp, -1)) == NULL) {
+			tx_ring->reschedule = B_TRUE;
+			return (mp);
 		}
 
 		LINK_LIST_INIT(&pending_list);
+		desc_total = 0;
+
+		/*
+		 * if the packet is a LSO packet, we simply
+		 * transmit the header in one descriptor using the copy way
+		 */
+		if ((ctx != NULL) && ctx->lso_flag) {
+			hdr_len = ctx->ip_hdr_len + ctx->mac_hdr_len +
+			    ctx->l4_hdr_len;
+
+			tcb = ixgbe_get_free_list(tx_ring);
+			if (tcb == NULL) {
+				IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tcb);
+				goto tx_failure;
+			}
+			desc_num = ixgbe_tx_copy(tx_ring, tcb, pull_mp,
+			    hdr_len, B_TRUE);
+			LIST_PUSH_TAIL(&pending_list, &tcb->link);
+			desc_total  += desc_num;
+
+			pull_mp->b_rptr += hdr_len;
+		}
+
 		tcb = ixgbe_get_free_list(tx_ring);
 		if (tcb == NULL) {
 			IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tcb);
-			freemsg(mp);
-			return (NULL);
+			goto tx_failure;
+		}
+		if ((ctx != NULL) && ctx->lso_flag) {
+			desc_num = ixgbe_tx_bind(tx_ring, tcb, pull_mp,
+			    mbsize - hdr_len);
+		} else {
+			desc_num = ixgbe_tx_bind(tx_ring, tcb, pull_mp,
+			    mbsize);
+		}
+		if (desc_num < 0) {
+			goto tx_failure;
 		}
 		LIST_PUSH_TAIL(&pending_list, &tcb->link);
 
-		desc_num = ixgbe_tx_bind(tx_ring, tcb, mp, mbsize);
-		if ((desc_num < 0) ||
-		    ((desc_num + 1) > IXGBE_TX_DESC_LIMIT)) {
-			ixgbe_free_tcb(tcb);
-			ixgbe_put_free_list(tx_ring, &pending_list);
-			freemsg(mp);
-			return (NULL);
-		}
-
-		desc_total = desc_num;
-		tcb->mp = mp;
+		desc_total += desc_num;
+		tcb->mp = pull_mp;
 	}
 
 	/*
@@ -462,10 +482,25 @@
 
 	mutex_exit(&tx_ring->tx_lock);
 
+	/*
+	 * now that the transmission succeeds, need to free the original
+	 * mp if we used the pulling up mblk for transmission.
+	 */
+	if (pull_mp) {
+		freemsg(mp);
+	}
+
 	return (NULL);
 
 tx_failure:
 	/*
+	 * If transmission fails, need to free the pulling up mblk.
+	 */
+	if (pull_mp) {
+		freemsg(pull_mp);
+	}
+
+	/*
 	 * Discard the mblk and free the used resources
 	 */
 	tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list);
--- a/usr/src/uts/common/io/ixgbe/ixgbe_type.h	Thu Aug 13 15:30:27 2009 -0700
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_type.h	Fri Aug 14 11:26:28 2009 +0800
@@ -26,7 +26,7 @@
  * Use is subject to license terms.
  */
 
-/* IntelVersion: 1.316 v2-7-8_2009-4-7 */
+/* IntelVersion: 1.338 v2-9-1-1_2009-6-10_NSW1 */
 
 #ifndef _IXGBE_TYPE_H
 #define	_IXGBE_TYPE_H
@@ -53,6 +53,7 @@
 #define	IXGBE_DEV_ID_82599_CX4			0x10F9
 #define	IXGBE_DEV_ID_82599_SFP			0x10FB
 #define	IXGBE_DEV_ID_82599_SPW			0x1507
+#define	IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
 
 /* General Registers */
 #define	IXGBE_CTRL	0x00000
@@ -113,7 +114,7 @@
 #define	IXGBE_MAX_EITR		0x00000FF8
 #define	IXGBE_MIN_EITR		8
 #define	IXGBE_EITR(_i)	(((_i) <= 23) ? \
-	(0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
+	(0x00820 + ((_i) * 4)) : (0x012300 + (((_i) - 24) * 4)))
 #define	IXGBE_EITR_ITR_INT_MASK	0x00000FF8
 #define	IXGBE_EITR_LLI_MOD	0x00008000
 #define	IXGBE_EITR_CNT_WDIS	0x80000000
@@ -232,10 +233,10 @@
 #define	IXGBE_L34T_IMIR(_i)	(0x0E800 + ((_i) * 4))
 				/* 128 of these (0-127) */
 #define	IXGBE_LLITHRESH	0x0EC90
-#define	IXGBE_VMD_CTL	0x0581C
 #define	IXGBE_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 #define	IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 #define	IXGBE_IMIRVP	0x05AC0
+#define	IXGBE_VMD_CTL	0x0581C
 #define	IXGBE_RETA(_i)	(0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 #define	IXGBE_RSSRK(_i)	(0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 
@@ -279,6 +280,7 @@
 #define	IXGBE_DTXCTL	0x07E00
 
 #define	IXGBE_DMATXCTL		0x04A80
+#define	IXGBE_PFDTXGSWC		0x08220
 #define	IXGBE_DTXMXSZRQ		0x08100
 #define	IXGBE_DTXTCPFLGL	0x04A88
 #define	IXGBE_DTXTCPFLGH	0x04A8C
@@ -289,6 +291,8 @@
 #define	IXGBE_DMATXCTL_NS	0x2 /* No Snoop LSO hdr buffer */
 #define	IXGBE_DMATXCTL_GDV	0x8 /* Global Double VLAN */
 #define	IXGBE_DMATXCTL_VT_SHIFT	16  /* VLAN EtherType */
+
+#define	IXGBE_PFDTXGSWC_VT_LBEN	0x1 /* Local L2 VT switch enable */
 #define	IXGBE_DCA_TXCTRL(_i)	(0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 /* Tx DCA Control register : 128 of these (0-127) */
 #define	IXGBE_DCA_TXCTRL_82599(_i)	(0x0600C + ((_i) * 0x40))
@@ -481,6 +485,7 @@
 /* DCB registers */
 #define	IXGBE_RTRPCS		0x02430
 #define	IXGBE_RTTDCS		0x04900
+#define	IXGBE_RTTDCS_ARBDIS	0x00000040 /* DCB arbiter disable */
 #define	IXGBE_RTTPCS		0x0CD00
 #define	IXGBE_RTRUP2TC		0x03020
 #define	IXGBE_RTTUP2TC		0x0C800
@@ -681,7 +686,7 @@
 #define	IXGBE_DCA_ID	0x11070
 #define	IXGBE_DCA_CTRL	0x11074
 
-/* PCI-E registers 82599 Specific */
+/* PCI-E registers 82599-Specific */
 #define	IXGBE_GCR_EXT		0x11050
 #define	IXGBE_GSCL_5_82599	0x11030
 #define	IXGBE_GSCL_6_82599	0x11034
@@ -980,6 +985,7 @@
 #define	IXGBE_MDIO_PHY_SPEED_ABILITY	0x4 /* Speed Ability Reg */
 #define	IXGBE_MDIO_PHY_SPEED_10G	0x0001 /* 10G capable */
 #define	IXGBE_MDIO_PHY_SPEED_1G		0x0010 /* 1G capable */
+#define	IXGBE_MDIO_PHY_SPEED_100M	0x0020 /* 100M capable */
 #define	IXGBE_MDIO_PHY_EXT_ABILITY	0xB /* Ext Ability Reg */
 #define	IXGBE_MDIO_PHY_10GBASET_ABILITY	0x0004 /* 10GBaseT capable */
 #define	IXGBE_MDIO_PHY_1000BASET_ABILITY	0x0020 /* 1000BaseT capable */
@@ -1004,6 +1010,8 @@
 /* PHY IDs */
 #define	TN1010_PHY_ID		0x00A19410
 #define	TNX_FW_REV		0xB
+#define	AQ1002_PHY_ID		0x03A1B420
+#define	AQ_FW_REV		0x20
 #define	QT2022_PHY_ID		0x0043A400
 #define	ATH_PHY_ID		0x03429050
 
@@ -1093,6 +1101,8 @@
 /* VFRE bitmask */
 #define	IXGBE_VFRE_ENABLE_ALL	0xFFFFFFFF
 
+#define	IXGBE_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
+
 /* RDHMPN and TDHMPN bitmasks */
 #define	IXGBE_RDHMPN_RDICADDR		0x007FF800
 #define	IXGBE_RDHMPN_RDICRDREQ		0x00800000
@@ -1318,12 +1328,10 @@
  *
  * Current filters:
  *    EAPOL 802.1x (0x888e): Filter 0
- *    BCN (0x8904):          Filter 1
  *    FCoE (0x8906):         Filter 2
  *    1588 (0x88f7):         Filter 3
  */
 #define	IXGBE_ETQF_FILTER_EAPOL	0
-#define	IXGBE_ETQF_FILTER_BCN	1
 #define	IXGBE_ETQF_FILTER_FCOE	2
 #define	IXGBE_ETQF_FILTER_1588	3
 
@@ -1349,8 +1357,10 @@
 #define	IXGBE_STATUS_LAN_ID_1	0x00000004 /* LAN ID 1 */
 
 /* ESDP Bit Masks */
-#define	IXGBE_ESDP_SDP0		0x00000001
-#define	IXGBE_ESDP_SDP1		0x00000002
+#define	IXGBE_ESDP_SDP0		0x00000001 /* SDP0 Data Value */
+#define	IXGBE_ESDP_SDP1		0x00000002 /* SDP1 Data Value */
+#define	IXGBE_ESDP_SDP2		0x00000004 /* SDP2 Data Value */
+#define	IXGBE_ESDP_SDP3		0x00000008 /* SDP3 Data Value */
 #define	IXGBE_ESDP_SDP4		0x00000010 /* SDP4 Data Value */
 #define	IXGBE_ESDP_SDP5		0x00000020 /* SDP5 Data Value */
 #define	IXGBE_ESDP_SDP6		0x00000040 /* SDP6 Data Value */
@@ -1523,6 +1533,7 @@
 #define	IXGBE_PBANUM1_PTR	0x16
 #define	IXGBE_SAN_MAC_ADDR_PTR	0x28
 #define	IXGBE_DEVICE_CAPS	0x2C
+#define	IXGBE_SERIAL_NUMBER_MAC_ADDR	0x11
 #define	IXGBE_PCIE_MSIX_82599_CAPS	0x72
 #define	IXGBE_PCIE_MSIX_82598_CAPS	0x62
 
@@ -1566,10 +1577,17 @@
 #define	IXGBE_EERD_ATTEMPTS 100000
 #endif
 
+#define	IXGBE_PCIE_CTRL2		0x5	/* PCIe Control 2 Offset */
+#define	IXGBE_PCIE_CTRL2_DUMMY_ENABLE	0x8	/* Dummy Function Enable */
+#define	IXGBE_PCIE_CTRL2_LAN_DISABLE	0x2	/* LAN PCI Disable */
+#define	IXGBE_PCIE_CTRL2_DISABLE_SELECT	0x1	/* LAN Disable Select */
+
 #define	IXGBE_SAN_MAC_ADDR_PORT0_OFFSET	0x0
 #define	IXGBE_SAN_MAC_ADDR_PORT1_OFFSET	0x3
 #define	IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP	0x1
 #define	IXGBE_DEVICE_CAPS_FCOE_OFFLOADS	0x2
+#define	IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR	0x4
+#define	IXGBE_FW_PATCH_VERSION_4	0x7
 
 /* PCI Bus Info */
 #define	IXGBE_PCI_LINK_STATUS		0xB2
@@ -1629,7 +1647,7 @@
 #define	IXGBE_MAX_FRAME_SZ	0x40040000
 
 #define	IXGBE_TDWBAL_HEAD_WB_ENABLE	0x1 /* Tx head write-back enable */
-#define	IXGBE_TDWBAL_SEQNUM_WB_ENABLE	0x2 /* Tx seq. # write-back enable */
+#define	IXGBE_TDWBAL_SEQNUM_WB_ENABLE	0x2 /* Tx seq# write-back enable */
 
 /* Receive Config masks */
 #define	IXGBE_RXCTRL_RXEN	0x00000001  /* Enable Receiver */
@@ -1770,6 +1788,7 @@
 #define	IXGBE_PSRTYPE_UDPHDR		0x00000020
 #define	IXGBE_PSRTYPE_IPV4HDR		0x00000100
 #define	IXGBE_PSRTYPE_IPV6HDR		0x00000200
+#define	IXGBE_PSRTYPE_L2HDR		0x00001000
 
 /* SRRCTL bit definitions */
 #define	IXGBE_SRRCTL_BSIZEPKT_SHIFT	10	/* so many KBs */
@@ -1857,6 +1876,12 @@
 #define	IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
 #define	IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
 
+/* SR-IOV specific macros */
+#define	IXGBE_MBVFICR_INDEX(vf_number)	(vf_number >> 4)
+#define	IXGBE_MBVFICR(_i)		(0x00710 + (_i * 4))
+#define	IXGBE_VFLRE(_i)			(((_i & 1) ? 0x001C0 : 0x00600))
+#define	IXGBE_VFLREC(_i)		(0x00700 + (_i * 4))
+
 #ifndef	__le16
 /* Little Endian defines */
 #define	__le16	u16
@@ -1925,6 +1950,7 @@
 #define	IXGBE_FDIRHASH_BUCKET_VALID_SHIFT	15
 #define	IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT	16
 
+#define	IXGBE_FDIRCMD_CMD_MASK			0x00000003
 #define	IXGBE_FDIRCMD_CMD_ADD_FLOW		0x00000001
 #define	IXGBE_FDIRCMD_CMD_REMOVE_FLOW		0x00000002
 #define	IXGBE_FDIRCMD_CMD_QUERY_REM_FILT	0x00000003
@@ -1935,6 +1961,7 @@
 #define	IXGBE_FDIRCMD_L4TYPE_TCP		0x00000040
 #define	IXGBE_FDIRCMD_L4TYPE_SCTP		0x00000060
 #define	IXGBE_FDIRCMD_IPV6			0x00000080
+#define	IXGBE_FDIRCMD_CLEARHT			0x00000100
 #define	IXGBE_FDIRCMD_DROP			0x00000200
 #define	IXGBE_FDIRCMD_INT			0x00000400
 #define	IXGBE_FDIRCMD_LAST			0x00000800
@@ -1942,6 +1969,8 @@
 #define	IXGBE_FDIRCMD_QUEUE_EN			0x00008000
 #define	IXGBE_FDIRCMD_RX_QUEUE_SHIFT		16
 #define	IXGBE_FDIRCMD_VT_POOL_SHIFT		24
+#define	IXGBE_FDIR_INIT_DONE_POLL		10
+#define	IXGBE_FDIRCMD_CMD_POLL			10
 
 /* Transmit Descriptor - Legacy */
 struct ixgbe_legacy_tx_desc {
@@ -2113,6 +2142,7 @@
 #define	IXGBE_PHYSICAL_LAYER_1000BASE_KX	0x0200
 #define	IXGBE_PHYSICAL_LAYER_1000BASE_BX	0x0400
 #define	IXGBE_PHYSICAL_LAYER_10GBASE_KR		0x0800
+#define	IXGBE_PHYSICAL_LAYER_10GBASE_XAUI	0x1000
 
 /* Software ATR hash keys */
 #define	IXGBE_ATR_BUCKET_HASH_KEY	0xE214AD3D
@@ -2171,8 +2201,9 @@
 	ixgbe_phy_unknown = 0,
 	ixgbe_phy_none,
 	ixgbe_phy_tn,
+	ixgbe_phy_aq,
+	ixgbe_phy_cu_unknown,
 	ixgbe_phy_qt,
-	ixgbe_phy_cu_unknown,
 	ixgbe_phy_xaui,
 	ixgbe_phy_nl,
 	ixgbe_phy_tw_tyco,
@@ -2400,6 +2431,8 @@
 	s32 (*write_analog_reg8)(struct ixgbe_hw *, u32, u8);
 	s32 (*setup_sfp)(struct ixgbe_hw *);
 	s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
+	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
+	void (*release_swfw_sync)(struct ixgbe_hw *, u16);
 
 	/* Link */
 	s32 (*setup_link)(struct ixgbe_hw *);
@@ -2483,6 +2516,7 @@
 	bool				orig_link_settings_stored;
 	bool				autoneg;
 	bool				autoneg_succeeded;
+	bool				autotry_restart;
 };
 
 struct ixgbe_phy_info {
@@ -2544,10 +2578,12 @@
 #define	IXGBE_ERR_SFP_NOT_PRESENT		-20
 #define	IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT	-21
 #define	IXGBE_ERR_NO_SAN_ADDR_PTR		-22
+#define	IXGBE_ERR_FDIR_REINIT_FAILED		-23
+#define	IXGBE_ERR_EEPROM_VERSION		-24
 #define	IXGBE_NOT_IMPLEMENTED			0x7FFFFFFF
 
 #ifndef UNREFERENCED_PARAMETER
-#define	UNREFERENCED_PARAMETER(_p)
+#define	UNREFERENCED_PARAMETER(_p)		(_p);
 #endif
 
 #endif /* _IXGBE_TYPE_H */