diff usr/src/uts/intel/sys/controlregs.h @ 25257:b821679919bb

12999 MSR_AMD_DE_CFG is twice defined Reviewed by: Robert Mustacchi <rm@fingolfin.org> Approved by: Dan McDonald <danmcd@joyent.com>
author Patrick Mooney <pmooney@pfmooney.com>
date Wed, 29 Jul 2020 22:37:40 +0000
parents 654bceb67d77
children 30063115dff3
line wrap: on
line diff
--- a/usr/src/uts/intel/sys/controlregs.h	Tue Jul 28 20:24:52 2020 +0000
+++ b/usr/src/uts/intel/sys/controlregs.h	Wed Jul 29 22:37:40 2020 +0000
@@ -238,9 +238,15 @@
 
 #define	AMD_BU_CFG_E298			(UINT64_C(1) << 1)
 
+/*
+ * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
+ * decoding. Most notably, for the AMD variant of retpolines, we must improve
+ * the serializability of lfence for the lfence based method to work.
+ */
 #define	MSR_AMD_DE_CFG	0xc0011029
 
-#define	AMD_DE_CFG_E721			(UINT64_C(1))
+#define	AMD_DE_CFG_E721			(1UL << 0)
+#define	AMD_DE_CFG_LFENCE_DISPATCH	(1UL << 1)
 
 /* AMD's osvw MSRs */
 #define	MSR_AMD_OSVW_ID_LEN		0xc0010140