Mercurial > illumos > git > illumos-joyent
annotate usr/src/uts/intel/sys/controlregs.h @ 25257:b821679919bb
12999 MSR_AMD_DE_CFG is twice defined
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@joyent.com>
| author | Patrick Mooney <pmooney@pfmooney.com> |
|---|---|
| date | Wed, 29 Jul 2020 22:37:40 +0000 |
| parents | 654bceb67d77 |
| children | 30063115dff3 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * CDDL HEADER START | |
| 3 * | |
| 4 * The contents of this file are subject to the terms of the | |
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5 * Common Development and Distribution License (the "License"). |
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6 * You may not use this file except in compliance with the License. |
| 0 | 7 * |
| 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
| 9 * or http://www.opensolaris.org/os/licensing. | |
| 10 * See the License for the specific language governing permissions | |
| 11 * and limitations under the License. | |
| 12 * | |
| 13 * When distributing Covered Code, include this CDDL HEADER in each | |
| 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
| 15 * If applicable, add the following below this CDDL HEADER, with the | |
| 16 * fields enclosed by brackets "[]" replaced with your own identifying | |
| 17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
| 18 * | |
| 19 * CDDL HEADER END | |
| 20 */ | |
| 21 /* | |
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22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. |
| 17220 | 23 * Copyright 2018, Joyent, Inc. |
| 0 | 24 */ |
| 25 | |
| 26 #ifndef _SYS_CONTROLREGS_H | |
| 27 #define _SYS_CONTROLREGS_H | |
| 28 | |
| 29 #ifndef _ASM | |
| 30 #include <sys/types.h> | |
| 31 #endif | |
| 32 | |
| 33 #ifdef __cplusplus | |
| 34 extern "C" { | |
| 35 #endif | |
| 36 | |
| 37 /* | |
| 38 * This file describes the x86 architecture control registers which | |
| 39 * are part of the privileged architecture. | |
| 40 * | |
| 41 * Many of these definitions are shared between IA-32-style and | |
| 42 * AMD64-style processors. | |
| 43 */ | |
| 44 | |
| 45 /* CR0 Register */ | |
| 46 | |
| 47 #define CR0_PG 0x80000000 /* paging enabled */ | |
| 48 #define CR0_CD 0x40000000 /* cache disable */ | |
| 49 #define CR0_NW 0x20000000 /* not writethrough */ | |
| 50 #define CR0_AM 0x00040000 /* alignment mask */ | |
| 51 #define CR0_WP 0x00010000 /* write protect */ | |
| 52 #define CR0_NE 0x00000020 /* numeric error */ | |
| 53 #define CR0_ET 0x00000010 /* extension type */ | |
| 54 #define CR0_TS 0x00000008 /* task switch */ | |
| 55 #define CR0_EM 0x00000004 /* emulation */ | |
| 56 #define CR0_MP 0x00000002 /* monitor coprocessor */ | |
| 57 #define CR0_PE 0x00000001 /* protection enabled */ | |
| 58 | |
| 59 /* XX64 eliminate these compatibility defines */ | |
| 60 | |
| 61 #define CR0_CE CR0_CD | |
| 62 #define CR0_WT CR0_NW | |
| 63 | |
| 64 #define FMT_CR0 \ | |
| 65 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" | |
| 66 | |
| 3446 | 67 /* |
| 68 * Set the FPU-related control bits to explain to the processor that | |
| 69 * we're managing FPU state: | |
| 70 * - set monitor coprocessor (allow TS bit to control FPU) | |
| 71 * - set numeric exception (disable IGNNE# mechanism) | |
| 72 * - set task switch (#nm on first fp instruction) | |
| 73 * - clear emulate math bit (cause we're not emulating!) | |
| 74 */ | |
| 75 #define CR0_ENABLE_FPU_FLAGS(cr) \ | |
| 76 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM) | |
| 77 | |
| 78 /* | |
| 79 * Set the FPU-related control bits to explain to the processor that | |
| 80 * we're -not- managing FPU state: | |
| 81 * - set emulate (all fp instructions cause #nm) | |
| 82 * - clear monitor coprocessor (so fwait/wait doesn't #nm) | |
| 83 */ | |
| 84 #define CR0_DISABLE_FPU_FLAGS(cr) \ | |
| 85 (((cr) | CR0_EM) & (uint32_t)~CR0_MP) | |
| 86 | |
| 0 | 87 /* CR3 Register */ |
| 88 | |
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89 #define CR3_PCD 0x00000010 /* cache disable */ |
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90 #define CR3_PWT 0x00000008 /* write through */ |
| 17220 | 91 #if defined(_ASM) |
| 92 #define CR3_NOINVL_BIT 0x8000000000000000 | |
| 93 #else | |
| 94 #define CR3_NOINVL_BIT 0x8000000000000000ULL /* no invalidation */ | |
| 95 #endif | |
| 96 #define PCID_NONE 0x000 /* generic PCID */ | |
| 97 #define PCID_KERNEL 0x000 /* kernel's PCID */ | |
| 98 #define PCID_USER 0x001 /* user-space PCID */ | |
| 0 | 99 |
| 100 /* CR4 Register */ | |
| 101 | |
| 102 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ | |
| 103 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ | |
| 104 #define CR4_TSD 0x0004 /* time stamp disable */ | |
| 105 #define CR4_DE 0x0008 /* debugging extensions */ | |
| 106 #define CR4_PSE 0x0010 /* page size extensions */ | |
| 107 #define CR4_PAE 0x0020 /* physical address extension */ | |
| 108 #define CR4_MCE 0x0040 /* machine check enable */ | |
| 109 #define CR4_PGE 0x0080 /* page global enable */ | |
| 110 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ | |
| 111 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ | |
| 112 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ | |
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113 #define CR4_UMIP 0x0800 /* user-mode instruction prevention */ |
| 3446 | 114 /* 0x1000 reserved */ |
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115 #define CR4_VMXE 0x2000 /* VMX enable */ |
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116 #define CR4_SMXE 0x4000 /* SMX enable */ |
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117 /* 0x8000 reserved */ |
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118 #define CR4_FSGSBASE 0x10000 /* FSGSBASE enable */ |
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119 #define CR4_PCIDE 0x20000 /* PCID enable */ |
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120 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */ |
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121 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */ |
| 15573 | 122 #define CR4_SMAP 0x200000 /* kernel can't access user pages */ |
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123 #define CR4_PKE 0x400000 /* protection key enable */ |
| 0 | 124 |
| 15573 | 125 #define FMT_CR4 \ |
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126 "\20\27pke\26smap\25smep\23osxsav" \ |
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127 "\22pcide\20fsgsbase\17smxe\16vmxe" \ |
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128 "\14umip\13xmme\12fxsr\11pce\10pge" \ |
| 3446 | 129 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" |
| 130 | |
| 131 /* | |
| 132 * Enable the SSE-related control bits to explain to the processor that | |
| 133 * we're managing XMM state and exceptions | |
| 134 */ | |
| 135 #define CR4_ENABLE_SSE_FLAGS(cr) \ | |
| 136 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT) | |
| 137 | |
| 138 /* | |
| 139 * Disable the SSE-related control bits to explain to the processor | |
| 140 * that we're NOT managing XMM state | |
| 141 */ | |
| 142 #define CR4_DISABLE_SSE_FLAGS(cr) \ | |
| 143 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT)) | |
| 0 | 144 |
| 145 /* Intel's SYSENTER configuration registers */ | |
| 146 | |
| 147 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ | |
| 148 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ | |
| 149 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ | |
| 150 | |
| 4581 | 151 /* Intel's microcode registers */ |
| 152 #define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */ | |
| 153 #define MSR_INTC_UCODE_REV 0x8b /* microcode revision */ | |
| 154 #define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */ | |
| 155 | |
| 156 /* Intel's platform identification */ | |
| 157 #define MSR_INTC_PLATFORM_ID 0x17 | |
| 158 #define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */ | |
| 159 #define INTC_PLATFORM_ID_MASK 0x7 | |
| 160 | |
| 0 | 161 /* AMD's EFER register */ |
| 162 | |
| 163 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ | |
| 164 | |
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165 #define AMD_EFER_TCE 0x8000 /* translation cache extension */ |
| 3446 | 166 #define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */ |
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167 #define AMD_EFER_LMSLE 0x2000 /* long mode segment limit enable */ |
| 3446 | 168 #define AMD_EFER_SVME 0x1000 /* svm enable */ |
| 169 #define AMD_EFER_NXE 0x0800 /* no-execute enable */ | |
| 170 #define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */ | |
| 171 #define AMD_EFER_LME 0x0100 /* long mode enable */ | |
| 172 #define AMD_EFER_SCE 0x0001 /* system call extensions */ | |
| 0 | 173 |
| 174 #define FMT_AMD_EFER \ | |
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175 "\20\20tce\17ffxsr\16lmsle\15svme\14nxe\13lma\11lme\1sce" |
| 0 | 176 |
| 177 /* AMD's SYSCFG register */ | |
| 178 | |
| 179 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ | |
| 180 | |
| 181 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ | |
| 182 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ | |
| 183 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ | |
| 184 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ | |
| 185 | |
| 186 #define FMT_AMD_SYSCFG \ | |
| 187 "\20\26tom2\25mvdm\24mfdm\23mfde" | |
| 188 | |
| 189 /* AMD's syscall/sysret MSRs */ | |
| 190 | |
| 191 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ | |
| 192 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ | |
| 193 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ | |
| 194 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ | |
| 195 | |
| 196 /* AMD's FS.base and GS.base MSRs */ | |
| 197 | |
| 198 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ | |
| 199 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ | |
| 200 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ | |
| 3446 | 201 #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */ |
| 0 | 202 |
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203 |
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204 /* AMD's SVM MSRs */ |
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205 |
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206 #define MSR_AMD_VM_CR 0xc0010114 /* SVM global control */ |
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207 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 /* SVM host save area address */ |
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208 |
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209 #define AMD_VM_CR_DPD (1 << 0) |
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210 #define AMD_VM_CR_R_INIT (1 << 1) |
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211 #define AMD_VM_CR_DIS_A20M (1 << 2) |
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212 #define AMD_VM_CR_LOCK (1 << 3) |
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213 #define AMD_VM_CR_SVMDIS (1 << 4) |
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214 |
| 0 | 215 /* AMD's configuration MSRs, weakly documented in the revision guide */ |
| 216 | |
| 217 #define MSR_AMD_DC_CFG 0xc0011022 | |
| 218 | |
| 219 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) | |
| 220 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) | |
| 221 | |
| 222 /* AMD's HWCR MSR */ | |
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223 |
| 0 | 224 #define MSR_AMD_HWCR 0xc0010015 |
| 225 | |
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226 #define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3) |
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227 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ |
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228 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ |
| 0 | 229 |
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230 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ |
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231 |
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232 #define MSR_AMD_NB_CFG 0xc001001f |
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233 |
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234 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) |
| 2519 | 235 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32) |
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236 |
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237 #define MSR_AMD_BU_CFG 0xc0011023 |
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238 |
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239 #define AMD_BU_CFG_E298 (UINT64_C(1) << 1) |
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240 |
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241 /* |
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242 * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction |
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243 * decoding. Most notably, for the AMD variant of retpolines, we must improve |
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244 * the serializability of lfence for the lfence based method to work. |
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245 */ |
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246 #define MSR_AMD_DE_CFG 0xc0011029 |
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247 |
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248 #define AMD_DE_CFG_E721 (1UL << 0) |
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249 #define AMD_DE_CFG_LFENCE_DISPATCH (1UL << 1) |
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250 |
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251 /* AMD's osvw MSRs */ |
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252 #define MSR_AMD_OSVW_ID_LEN 0xc0010140 |
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253 #define MSR_AMD_OSVW_STATUS 0xc0010141 |
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254 |
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255 |
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256 #define OSVW_ID_LEN_MASK 0xffffULL |
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257 #define OSVW_ID_CNT_PER_MSR 64 |
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258 |
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259 /* |
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260 * Enable PCI Extended Configuration Space (ECS) on Greyhound |
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261 */ |
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262 #define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46) |
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263 |
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264 /* AMD microcode patch loader */ |
| 0 | 265 #define MSR_AMD_PATCHLEVEL 0x8b |
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266 #define MSR_AMD_PATCHLOADER 0xc0010020 |
| 0 | 267 |
| 268 #ifdef __cplusplus | |
| 269 } | |
| 270 #endif | |
| 271 | |
| 272 #endif /* !_SYS_CONTROLREGS_H */ |