Mercurial > illumos > illumos-gate
annotate usr/src/uts/i86pc/os/cpuid.c @ 10080:29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
| author | Joe Bonasera <Joe.Bonasera@sun.com> |
|---|---|
| date | Tue, 14 Jul 2009 10:51:37 -0700 |
| parents | 6b40e106879c |
| children | dd9708d1f561 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * CDDL HEADER START | |
| 3 * | |
| 4 * The contents of this file are subject to the terms of the | |
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5 * Common Development and Distribution License (the "License"). |
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6 * You may not use this file except in compliance with the License. |
| 0 | 7 * |
| 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
| 9 * or http://www.opensolaris.org/os/licensing. | |
| 10 * See the License for the specific language governing permissions | |
| 11 * and limitations under the License. | |
| 12 * | |
| 13 * When distributing Covered Code, include this CDDL HEADER in each | |
| 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
| 15 * If applicable, add the following below this CDDL HEADER, with the | |
| 16 * fields enclosed by brackets "[]" replaced with your own identifying | |
| 17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
| 18 * | |
| 19 * CDDL HEADER END | |
| 20 */ | |
| 21 /* | |
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22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. |
| 0 | 23 * Use is subject to license terms. |
| 24 */ | |
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25 /* |
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26 * Copyright (c) 2009, Intel Corporation. |
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27 * All rights reserved. |
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28 */ |
| 0 | 29 |
| 30 /* | |
| 31 * Various routines to handle identification | |
| 32 * and classification of x86 processors. | |
| 33 */ | |
| 34 | |
| 35 #include <sys/types.h> | |
| 36 #include <sys/archsystm.h> | |
| 37 #include <sys/x86_archext.h> | |
| 38 #include <sys/kmem.h> | |
| 39 #include <sys/systm.h> | |
| 40 #include <sys/cmn_err.h> | |
| 41 #include <sys/sunddi.h> | |
| 42 #include <sys/sunndi.h> | |
| 43 #include <sys/cpuvar.h> | |
| 44 #include <sys/processor.h> | |
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45 #include <sys/sysmacros.h> |
| 3434 | 46 #include <sys/pg.h> |
| 0 | 47 #include <sys/fp.h> |
| 48 #include <sys/controlregs.h> | |
| 49 #include <sys/auxv_386.h> | |
| 50 #include <sys/bitmap.h> | |
| 51 #include <sys/memnode.h> | |
| 52 | |
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53 #ifdef __xpv |
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54 #include <sys/hypervisor.h> |
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55 #else |
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56 #include <sys/ontrap.h> |
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57 #endif |
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58 |
| 0 | 59 /* |
| 60 * Pass 0 of cpuid feature analysis happens in locore. It contains special code | |
| 61 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with | |
| 62 * them accordingly. For most modern processors, feature detection occurs here | |
| 63 * in pass 1. | |
| 64 * | |
| 65 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() | |
| 66 * for the boot CPU and does the basic analysis that the early kernel needs. | |
| 67 * x86_feature is set based on the return value of cpuid_pass1() of the boot | |
| 68 * CPU. | |
| 69 * | |
| 70 * Pass 1 includes: | |
| 71 * | |
| 72 * o Determining vendor/model/family/stepping and setting x86_type and | |
| 73 * x86_vendor accordingly. | |
| 74 * o Processing the feature flags returned by the cpuid instruction while | |
| 75 * applying any workarounds or tricks for the specific processor. | |
| 76 * o Mapping the feature flags into Solaris feature bits (X86_*). | |
| 77 * o Processing extended feature flags if supported by the processor, | |
| 78 * again while applying specific processor knowledge. | |
| 79 * o Determining the CMT characteristics of the system. | |
| 80 * | |
| 81 * Pass 1 is done on non-boot CPUs during their initialization and the results | |
| 82 * are used only as a meager attempt at ensuring that all processors within the | |
| 83 * system support the same features. | |
| 84 * | |
| 85 * Pass 2 of cpuid feature analysis happens just at the beginning | |
| 86 * of startup(). It just copies in and corrects the remainder | |
| 87 * of the cpuid data we depend on: standard cpuid functions that we didn't | |
| 88 * need for pass1 feature analysis, and extended cpuid functions beyond the | |
| 89 * simple feature processing done in pass1. | |
| 90 * | |
| 91 * Pass 3 of cpuid analysis is invoked after basic kernel services; in | |
| 92 * particular kernel memory allocation has been made available. It creates a | |
| 93 * readable brand string based on the data collected in the first two passes. | |
| 94 * | |
| 95 * Pass 4 of cpuid analysis is invoked after post_startup() when all | |
| 96 * the support infrastructure for various hardware features has been | |
| 97 * initialized. It determines which processor features will be reported | |
| 98 * to userland via the aux vector. | |
| 99 * | |
| 100 * All passes are executed on all CPUs, but only the boot CPU determines what | |
| 101 * features the kernel will use. | |
| 102 * | |
| 103 * Much of the worst junk in this file is for the support of processors | |
| 104 * that didn't really implement the cpuid instruction properly. | |
| 105 * | |
| 106 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, | |
| 107 * the pass numbers. Accordingly, changes to the pass code may require changes | |
| 108 * to the accessor code. | |
| 109 */ | |
| 110 | |
| 111 uint_t x86_feature = 0; | |
| 112 uint_t x86_vendor = X86_VENDOR_IntelClone; | |
| 113 uint_t x86_type = X86_TYPE_OTHER; | |
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114 uint_t x86_clflush_size = 0; |
| 0 | 115 |
| 116 uint_t pentiumpro_bug4046376; | |
| 117 uint_t pentiumpro_bug4064495; | |
| 118 | |
| 119 uint_t enable486; | |
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120 /* |
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121 * This is set to platform type Solaris is running on. |
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122 */ |
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123 static int platform_type = HW_NATIVE; |
| 0 | 124 |
| 125 /* | |
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126 * monitor/mwait info. |
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127 * |
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128 * size_actual and buf_actual are the real address and size allocated to get |
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129 * proper mwait_buf alignement. buf_actual and size_actual should be passed |
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130 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use |
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131 * processor cache-line alignment, but this is not guarantied in the furture. |
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132 */ |
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133 struct mwait_info { |
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134 size_t mon_min; /* min size to avoid missed wakeups */ |
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135 size_t mon_max; /* size to avoid false wakeups */ |
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136 size_t size_actual; /* size actually allocated */ |
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137 void *buf_actual; /* memory actually allocated */ |
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138 uint32_t support; /* processor support of monitor/mwait */ |
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139 }; |
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140 |
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141 /* |
| 0 | 142 * These constants determine how many of the elements of the |
| 143 * cpuid we cache in the cpuid_info data structure; the | |
| 144 * remaining elements are accessible via the cpuid instruction. | |
| 145 */ | |
| 146 | |
| 147 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ | |
| 148 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ | |
| 149 | |
| 150 struct cpuid_info { | |
| 151 uint_t cpi_pass; /* last pass completed */ | |
| 152 /* | |
| 153 * standard function information | |
| 154 */ | |
| 155 uint_t cpi_maxeax; /* fn 0: %eax */ | |
| 156 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ | |
| 157 uint_t cpi_vendor; /* enum of cpi_vendorstr */ | |
| 158 | |
| 159 uint_t cpi_family; /* fn 1: extended family */ | |
| 160 uint_t cpi_model; /* fn 1: extended model */ | |
| 161 uint_t cpi_step; /* fn 1: stepping */ | |
| 162 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ | |
| 163 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ | |
| 164 int cpi_clogid; /* fn 1: %ebx: thread # */ | |
| 1228 | 165 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ |
| 0 | 166 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ |
| 167 uint_t cpi_ncache; /* fn 2: number of elements */ | |
| 4606 | 168 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ |
| 169 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ | |
| 170 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ | |
| 171 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ | |
| 1228 | 172 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ |
| 0 | 173 /* |
| 174 * extended function information | |
| 175 */ | |
| 176 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ | |
| 177 char cpi_brandstr[49]; /* fn 0x8000000[234] */ | |
| 178 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ | |
| 179 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ | |
| 1228 | 180 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ |
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181 id_t cpi_coreid; /* same coreid => strands share core */ |
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182 int cpi_pkgcoreid; /* core number within single package */ |
| 1228 | 183 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ |
| 184 /* Intel: fn 4: %eax[31-26] */ | |
| 0 | 185 /* |
| 186 * supported feature information | |
| 187 */ | |
| 3446 | 188 uint32_t cpi_support[5]; |
| 0 | 189 #define STD_EDX_FEATURES 0 |
| 190 #define AMD_EDX_FEATURES 1 | |
| 191 #define TM_EDX_FEATURES 2 | |
| 192 #define STD_ECX_FEATURES 3 | |
| 3446 | 193 #define AMD_ECX_FEATURES 4 |
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194 /* |
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195 * Synthesized information, where known. |
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196 */ |
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197 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ |
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198 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ |
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199 uint32_t cpi_socket; /* Chip package/socket type */ |
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200 |
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201 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ |
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202 uint32_t cpi_apicid; |
| 0 | 203 }; |
| 204 | |
| 205 | |
| 206 static struct cpuid_info cpuid_info0; | |
| 207 | |
| 208 /* | |
| 209 * These bit fields are defined by the Intel Application Note AP-485 | |
| 210 * "Intel Processor Identification and the CPUID Instruction" | |
| 211 */ | |
| 212 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) | |
| 213 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) | |
| 214 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) | |
| 215 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) | |
| 216 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) | |
| 217 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) | |
| 218 | |
| 219 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) | |
| 220 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) | |
| 221 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) | |
| 222 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) | |
| 223 | |
| 224 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) | |
| 225 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) | |
| 226 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) | |
| 227 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) | |
| 228 | |
| 229 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ | |
| 230 #define CPI_XMAXEAX_MAX 0x80000100 | |
| 4606 | 231 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ |
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232 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ |
| 4606 | 233 |
| 234 /* | |
| 235 * Function 4 (Deterministic Cache Parameters) macros | |
| 236 * Defined by Intel Application Note AP-485 | |
| 237 */ | |
| 238 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) | |
| 239 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) | |
| 240 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) | |
| 241 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) | |
| 242 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) | |
| 243 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) | |
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244 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) |
| 4606 | 245 |
| 246 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) | |
| 247 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) | |
| 248 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) | |
| 249 | |
| 250 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) | |
| 251 | |
| 252 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) | |
| 253 | |
| 0 | 254 |
| 255 /* | |
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256 * A couple of shorthand macros to identify "later" P6-family chips |
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257 * like the Pentium M and Core. First, the "older" P6-based stuff |
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258 * (loosely defined as "pre-Pentium-4"): |
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259 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon |
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260 */ |
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261 |
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262 #define IS_LEGACY_P6(cpi) ( \ |
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263 cpi->cpi_family == 6 && \ |
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264 (cpi->cpi_model == 1 || \ |
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265 cpi->cpi_model == 3 || \ |
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266 cpi->cpi_model == 5 || \ |
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267 cpi->cpi_model == 6 || \ |
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268 cpi->cpi_model == 7 || \ |
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269 cpi->cpi_model == 8 || \ |
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270 cpi->cpi_model == 0xA || \ |
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271 cpi->cpi_model == 0xB) \ |
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272 ) |
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273 |
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274 /* A "new F6" is everything with family 6 that's not the above */ |
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275 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) |
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276 |
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277 /* Extended family/model support */ |
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278 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ |
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279 cpi->cpi_family >= 0xf) |
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280 |
|
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281 /* |
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282 * Info for monitor/mwait idle loop. |
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283 * |
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284 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's |
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285 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November |
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286 * 2006. |
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287 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual |
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288 * Documentation Updates" #33633, Rev 2.05, December 2006. |
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289 */ |
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290 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ |
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291 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ |
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292 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ |
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293 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) |
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294 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) |
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295 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) |
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296 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) |
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297 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) |
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298 /* |
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299 * Number of sub-cstates for a given c-state. |
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300 */ |
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301 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ |
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302 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) |
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303 |
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304 /* |
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305 * Functions we consune from cpuid_subr.c; don't publish these in a header |
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306 * file to try and keep people using the expected cpuid_* interfaces. |
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307 */ |
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308 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); |
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309 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); |
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310 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); |
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311 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); |
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312 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); |
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313 |
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314 /* |
| 3446 | 315 * Apply up various platform-dependent restrictions where the |
| 316 * underlying platform restrictions mean the CPU can be marked | |
| 317 * as less capable than its cpuid instruction would imply. | |
| 318 */ | |
| 5084 | 319 #if defined(__xpv) |
| 320 static void | |
| 321 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) | |
| 322 { | |
| 323 switch (eax) { | |
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324 case 1: { |
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325 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? |
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326 0 : CPUID_INTC_EDX_MCA; |
| 5084 | 327 cp->cp_edx &= |
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328 ~(mcamask | |
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329 CPUID_INTC_EDX_PSE | |
| 5084 | 330 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | |
| 331 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | | |
| 332 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | | |
| 333 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
| 334 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); | |
| 335 break; | |
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336 } |
| 5084 | 337 |
| 338 case 0x80000001: | |
| 339 cp->cp_edx &= | |
| 340 ~(CPUID_AMD_EDX_PSE | | |
| 341 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | | |
| 342 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | | |
| 343 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | | |
| 344 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
| 345 CPUID_AMD_EDX_TSCP); | |
| 346 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; | |
| 347 break; | |
| 348 default: | |
| 349 break; | |
| 350 } | |
| 351 | |
| 352 switch (vendor) { | |
| 353 case X86_VENDOR_Intel: | |
| 354 switch (eax) { | |
| 355 case 4: | |
| 356 /* | |
| 357 * Zero out the (ncores-per-chip - 1) field | |
| 358 */ | |
| 359 cp->cp_eax &= 0x03fffffff; | |
| 360 break; | |
| 361 default: | |
| 362 break; | |
| 363 } | |
| 364 break; | |
| 365 case X86_VENDOR_AMD: | |
| 366 switch (eax) { | |
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367 |
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368 case 0x80000001: |
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369 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; |
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370 break; |
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371 |
| 5084 | 372 case 0x80000008: |
| 373 /* | |
| 374 * Zero out the (ncores-per-chip - 1) field | |
| 375 */ | |
| 376 cp->cp_ecx &= 0xffffff00; | |
| 377 break; | |
| 378 default: | |
| 379 break; | |
| 380 } | |
| 381 break; | |
| 382 default: | |
| 383 break; | |
| 384 } | |
| 385 } | |
| 386 #else | |
| 3446 | 387 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ |
| 5084 | 388 #endif |
| 3446 | 389 |
| 390 /* | |
| 0 | 391 * Some undocumented ways of patching the results of the cpuid |
| 392 * instruction to permit running Solaris 10 on future cpus that | |
| 393 * we don't currently support. Could be set to non-zero values | |
| 394 * via settings in eeprom. | |
| 395 */ | |
| 396 | |
| 397 uint32_t cpuid_feature_ecx_include; | |
| 398 uint32_t cpuid_feature_ecx_exclude; | |
| 399 uint32_t cpuid_feature_edx_include; | |
| 400 uint32_t cpuid_feature_edx_exclude; | |
| 401 | |
| 3446 | 402 void |
| 403 cpuid_alloc_space(cpu_t *cpu) | |
| 404 { | |
| 405 /* | |
| 406 * By convention, cpu0 is the boot cpu, which is set up | |
| 407 * before memory allocation is available. All other cpus get | |
| 408 * their cpuid_info struct allocated here. | |
| 409 */ | |
| 410 ASSERT(cpu->cpu_id != 0); | |
| 411 cpu->cpu_m.mcpu_cpi = | |
| 412 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); | |
| 413 } | |
| 414 | |
| 415 void | |
| 416 cpuid_free_space(cpu_t *cpu) | |
| 417 { | |
| 4606 | 418 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 419 int i; | |
| 420 | |
| 3446 | 421 ASSERT(cpu->cpu_id != 0); |
| 4606 | 422 |
| 423 /* | |
| 424 * Free up any function 4 related dynamic storage | |
| 425 */ | |
| 426 for (i = 1; i < cpi->cpi_std_4_size; i++) | |
| 427 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); | |
| 428 if (cpi->cpi_std_4_size > 0) | |
| 429 kmem_free(cpi->cpi_std_4, | |
| 430 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); | |
| 431 | |
| 3446 | 432 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); |
| 433 } | |
| 434 | |
|
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435 #if !defined(__xpv) |
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436 |
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437 static void |
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438 determine_platform() |
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439 { |
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440 struct cpuid_regs cp; |
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441 char *xen_str; |
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442 uint32_t xen_signature[4]; |
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443 |
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444 /* |
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445 * In a fully virtualized domain, Xen's pseudo-cpuid function |
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446 * 0x40000000 returns a string representing the Xen signature in |
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447 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid |
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448 * function. |
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449 */ |
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450 cp.cp_eax = 0x40000000; |
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451 (void) __cpuid_insn(&cp); |
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452 xen_signature[0] = cp.cp_ebx; |
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453 xen_signature[1] = cp.cp_ecx; |
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454 xen_signature[2] = cp.cp_edx; |
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455 xen_signature[3] = 0; |
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456 xen_str = (char *)xen_signature; |
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457 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) { |
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458 platform_type = HW_XEN_HVM; |
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459 } else if (vmware_platform()) { /* running under vmware hypervisor? */ |
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460 platform_type = HW_VMWARE; |
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461 } |
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462 } |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
463 |
|
7a9c5c9ed60d
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Stuart Maybee <Stuart.Maybee@Sun.COM>
parents:
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diff
changeset
|
464 int |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
465 get_hwenv(void) |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
466 { |
|
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6775011 bad trap page fault while starting dom0
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|
467 return (platform_type); |
|
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|
468 } |
|
9000
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
469 |
|
7a9c5c9ed60d
6775011 bad trap page fault while starting dom0
Stuart Maybee <Stuart.Maybee@Sun.COM>
parents:
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diff
changeset
|
470 int |
|
7a9c5c9ed60d
6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
471 is_controldom(void) |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
472 { |
|
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6775011 bad trap page fault while starting dom0
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|
473 return (0); |
|
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6775011 bad trap page fault while starting dom0
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parents:
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|
474 } |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
475 |
|
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6775011 bad trap page fault while starting dom0
Stuart Maybee <Stuart.Maybee@Sun.COM>
parents:
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diff
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|
476 #else |
|
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6775011 bad trap page fault while starting dom0
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diff
changeset
|
477 |
|
7a9c5c9ed60d
6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
478 int |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
479 get_hwenv(void) |
|
7a9c5c9ed60d
6775011 bad trap page fault while starting dom0
Stuart Maybee <Stuart.Maybee@Sun.COM>
parents:
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diff
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|
480 { |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
481 return (HW_XEN_PV); |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
482 } |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
483 |
|
7a9c5c9ed60d
6775011 bad trap page fault while starting dom0
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diff
changeset
|
484 int |
|
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6775011 bad trap page fault while starting dom0
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diff
changeset
|
485 is_controldom(void) |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
changeset
|
486 { |
|
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6775011 bad trap page fault while starting dom0
Stuart Maybee <Stuart.Maybee@Sun.COM>
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diff
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|
487 return (DOMAIN_IS_INITDOMAIN(xen_info)); |
|
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6775011 bad trap page fault while starting dom0
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parents:
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diff
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|
488 } |
|
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diff
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|
489 |
|
5741
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PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains
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|
490 #endif /* __xpv */ |
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|
491 |
| 0 | 492 uint_t |
| 493 cpuid_pass1(cpu_t *cpu) | |
| 494 { | |
| 495 uint32_t mask_ecx, mask_edx; | |
| 496 uint_t feature = X86_CPUID; | |
| 497 struct cpuid_info *cpi; | |
| 1228 | 498 struct cpuid_regs *cp; |
| 0 | 499 int xcpuid; |
| 5084 | 500 #if !defined(__xpv) |
|
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501 extern int idle_cpu_prefer_mwait; |
| 5084 | 502 #endif |
| 3446 | 503 |
|
9482
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diff
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|
504 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
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505 #if !defined(__xpv) |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
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|
506 determine_platform(); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
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|
507 #endif |
| 0 | 508 /* |
| 3446 | 509 * Space statically allocated for cpu0, ensure pointer is set |
| 0 | 510 */ |
| 511 if (cpu->cpu_id == 0) | |
| 3446 | 512 cpu->cpu_m.mcpu_cpi = &cpuid_info0; |
| 513 cpi = cpu->cpu_m.mcpu_cpi; | |
| 514 ASSERT(cpi != NULL); | |
| 0 | 515 cp = &cpi->cpi_std[0]; |
| 1228 | 516 cp->cp_eax = 0; |
| 517 cpi->cpi_maxeax = __cpuid_insn(cp); | |
| 0 | 518 { |
| 519 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; | |
| 520 *iptr++ = cp->cp_ebx; | |
| 521 *iptr++ = cp->cp_edx; | |
| 522 *iptr++ = cp->cp_ecx; | |
| 523 *(char *)&cpi->cpi_vendorstr[12] = '\0'; | |
| 524 } | |
| 525 | |
|
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|
526 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); |
| 0 | 527 x86_vendor = cpi->cpi_vendor; /* for compatibility */ |
| 528 | |
| 529 /* | |
| 530 * Limit the range in case of weird hardware | |
| 531 */ | |
| 532 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) | |
| 533 cpi->cpi_maxeax = CPI_MAXEAX_MAX; | |
| 534 if (cpi->cpi_maxeax < 1) | |
| 535 goto pass1_done; | |
| 536 | |
| 537 cp = &cpi->cpi_std[1]; | |
| 1228 | 538 cp->cp_eax = 1; |
| 539 (void) __cpuid_insn(cp); | |
| 0 | 540 |
| 541 /* | |
| 542 * Extract identifying constants for easy access. | |
| 543 */ | |
| 544 cpi->cpi_model = CPI_MODEL(cpi); | |
| 545 cpi->cpi_family = CPI_FAMILY(cpi); | |
| 546 | |
|
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547 if (cpi->cpi_family == 0xf) |
| 0 | 548 cpi->cpi_family += CPI_FAMILY_XTD(cpi); |
|
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|
549 |
|
2001
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6427092 extended-model CPUID information is different between AMD and Intel
dmick
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diff
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|
550 /* |
|
4265
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6555108 workarounds being applied for errata not present in greyhound processors
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551 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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diff
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552 * Intel, and presumably everyone else, uses model == 0xf, as |
|
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6427092 extended-model CPUID information is different between AMD and Intel
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diff
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553 * one would expect (max value means possible overflow). Sigh. |
|
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6427092 extended-model CPUID information is different between AMD and Intel
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diff
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|
554 */ |
|
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diff
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|
555 |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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diff
changeset
|
556 switch (cpi->cpi_vendor) { |
|
4855
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
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diff
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|
557 case X86_VENDOR_Intel: |
|
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
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diff
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|
558 if (IS_EXTENDED_MODEL_INTEL(cpi)) |
|
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6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
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parents:
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diff
changeset
|
559 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
4858
08409e2eed12
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint)
ksadhukh
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4855
diff
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|
560 break; |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
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1975
diff
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|
561 case X86_VENDOR_AMD: |
|
4265
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kchow
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diff
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|
562 if (CPI_FAMILY(cpi) == 0xf) |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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1975
diff
changeset
|
563 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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1975
diff
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|
564 break; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
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1975
diff
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|
565 default: |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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diff
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|
566 if (cpi->cpi_model == 0xf) |
|
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6427092 extended-model CPUID information is different between AMD and Intel
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diff
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|
567 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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diff
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|
568 break; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
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diff
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|
569 } |
| 0 | 570 |
| 571 cpi->cpi_step = CPI_STEP(cpi); | |
| 572 cpi->cpi_brandid = CPI_BRANDID(cpi); | |
| 573 | |
| 574 /* | |
| 575 * *default* assumptions: | |
| 576 * - believe %edx feature word | |
| 577 * - ignore %ecx feature word | |
| 578 * - 32-bit virtual and physical addressing | |
| 579 */ | |
| 580 mask_edx = 0xffffffff; | |
| 581 mask_ecx = 0; | |
| 582 | |
| 583 cpi->cpi_pabits = cpi->cpi_vabits = 32; | |
| 584 | |
| 585 switch (cpi->cpi_vendor) { | |
| 586 case X86_VENDOR_Intel: | |
| 587 if (cpi->cpi_family == 5) | |
| 588 x86_type = X86_TYPE_P5; | |
|
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6183891 Missing brand ID strings for several common x86 CPUs
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1727
diff
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|
589 else if (IS_LEGACY_P6(cpi)) { |
| 0 | 590 x86_type = X86_TYPE_P6; |
| 591 pentiumpro_bug4046376 = 1; | |
| 592 pentiumpro_bug4064495 = 1; | |
| 593 /* | |
| 594 * Clear the SEP bit when it was set erroneously | |
| 595 */ | |
| 596 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) | |
| 597 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; | |
|
1975
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diff
changeset
|
598 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { |
| 0 | 599 x86_type = X86_TYPE_P4; |
| 600 /* | |
| 601 * We don't currently depend on any of the %ecx | |
| 602 * features until Prescott, so we'll only check | |
| 603 * this from P4 onwards. We might want to revisit | |
| 604 * that idea later. | |
| 605 */ | |
| 606 mask_ecx = 0xffffffff; | |
| 607 } else if (cpi->cpi_family > 0xf) | |
| 608 mask_ecx = 0xffffffff; | |
|
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
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4628
diff
changeset
|
609 /* |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
610 * We don't support MONITOR/MWAIT if leaf 5 is not available |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
611 * to obtain the monitor linesize. |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
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|
612 */ |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
613 if (cpi->cpi_maxeax < 5) |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
614 mask_ecx &= ~CPUID_INTC_ECX_MON; |
| 0 | 615 break; |
| 616 case X86_VENDOR_IntelClone: | |
| 617 default: | |
| 618 break; | |
| 619 case X86_VENDOR_AMD: | |
| 620 #if defined(OPTERON_ERRATUM_108) | |
| 621 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { | |
| 622 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; | |
| 623 cpi->cpi_model = 0xc; | |
| 624 } else | |
| 625 #endif | |
| 626 if (cpi->cpi_family == 5) { | |
| 627 /* | |
| 628 * AMD K5 and K6 | |
| 629 * | |
| 630 * These CPUs have an incomplete implementation | |
| 631 * of MCA/MCE which we mask away. | |
| 632 */ | |
| 1228 | 633 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); |
| 634 | |
| 635 /* | |
| 636 * Model 0 uses the wrong (APIC) bit | |
| 637 * to indicate PGE. Fix it here. | |
| 638 */ | |
| 0 | 639 if (cpi->cpi_model == 0) { |
| 640 if (cp->cp_edx & 0x200) { | |
| 641 cp->cp_edx &= ~0x200; | |
| 642 cp->cp_edx |= CPUID_INTC_EDX_PGE; | |
| 643 } | |
| 1228 | 644 } |
| 645 | |
| 646 /* | |
| 647 * Early models had problems w/ MMX; disable. | |
| 648 */ | |
| 649 if (cpi->cpi_model < 6) | |
| 650 mask_edx &= ~CPUID_INTC_EDX_MMX; | |
| 651 } | |
| 652 | |
| 653 /* | |
| 654 * For newer families, SSE3 and CX16, at least, are valid; | |
| 655 * enable all | |
| 656 */ | |
| 657 if (cpi->cpi_family >= 0xf) | |
|
771
1c25a2120ec0
6327969 cpuid sse3 feature bit not noted on any AMD processor
dmick
parents:
359
diff
changeset
|
658 mask_ecx = 0xffffffff; |
|
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
659 /* |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
660 * We don't support MONITOR/MWAIT if leaf 5 is not available |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
661 * to obtain the monitor linesize. |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
662 */ |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
663 if (cpi->cpi_maxeax < 5) |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
664 mask_ecx &= ~CPUID_INTC_ECX_MON; |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
665 |
| 5084 | 666 #if !defined(__xpv) |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
667 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
668 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
669 * processors. AMD does not intend MWAIT to be used in the cpu |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
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diff
changeset
|
670 * idle loop on current and future processors. 10h and future |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
671 * AMD processors use more power in MWAIT than HLT. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
672 * Pre-family-10h Opterons do not have the MWAIT instruction. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
673 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
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diff
changeset
|
674 idle_cpu_prefer_mwait = 0; |
| 5084 | 675 #endif |
|
5045
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6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
676 |
| 0 | 677 break; |
| 678 case X86_VENDOR_TM: | |
| 679 /* | |
| 680 * workaround the NT workaround in CMS 4.1 | |
| 681 */ | |
| 682 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && | |
| 683 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) | |
| 684 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 685 break; | |
| 686 case X86_VENDOR_Centaur: | |
| 687 /* | |
| 688 * workaround the NT workarounds again | |
| 689 */ | |
| 690 if (cpi->cpi_family == 6) | |
| 691 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 692 break; | |
| 693 case X86_VENDOR_Cyrix: | |
| 694 /* | |
| 695 * We rely heavily on the probing in locore | |
| 696 * to actually figure out what parts, if any, | |
| 697 * of the Cyrix cpuid instruction to believe. | |
| 698 */ | |
| 699 switch (x86_type) { | |
| 700 case X86_TYPE_CYRIX_486: | |
| 701 mask_edx = 0; | |
| 702 break; | |
| 703 case X86_TYPE_CYRIX_6x86: | |
| 704 mask_edx = 0; | |
| 705 break; | |
| 706 case X86_TYPE_CYRIX_6x86L: | |
| 707 mask_edx = | |
| 708 CPUID_INTC_EDX_DE | | |
| 709 CPUID_INTC_EDX_CX8; | |
| 710 break; | |
| 711 case X86_TYPE_CYRIX_6x86MX: | |
| 712 mask_edx = | |
| 713 CPUID_INTC_EDX_DE | | |
| 714 CPUID_INTC_EDX_MSR | | |
| 715 CPUID_INTC_EDX_CX8 | | |
| 716 CPUID_INTC_EDX_PGE | | |
| 717 CPUID_INTC_EDX_CMOV | | |
| 718 CPUID_INTC_EDX_MMX; | |
| 719 break; | |
| 720 case X86_TYPE_CYRIX_GXm: | |
| 721 mask_edx = | |
| 722 CPUID_INTC_EDX_MSR | | |
| 723 CPUID_INTC_EDX_CX8 | | |
| 724 CPUID_INTC_EDX_CMOV | | |
| 725 CPUID_INTC_EDX_MMX; | |
| 726 break; | |
| 727 case X86_TYPE_CYRIX_MediaGX: | |
| 728 break; | |
| 729 case X86_TYPE_CYRIX_MII: | |
| 730 case X86_TYPE_VIA_CYRIX_III: | |
| 731 mask_edx = | |
| 732 CPUID_INTC_EDX_DE | | |
| 733 CPUID_INTC_EDX_TSC | | |
| 734 CPUID_INTC_EDX_MSR | | |
| 735 CPUID_INTC_EDX_CX8 | | |
| 736 CPUID_INTC_EDX_PGE | | |
| 737 CPUID_INTC_EDX_CMOV | | |
| 738 CPUID_INTC_EDX_MMX; | |
| 739 break; | |
| 740 default: | |
| 741 break; | |
| 742 } | |
| 743 break; | |
| 744 } | |
| 745 | |
| 5084 | 746 #if defined(__xpv) |
| 747 /* | |
| 748 * Do not support MONITOR/MWAIT under a hypervisor | |
| 749 */ | |
| 750 mask_ecx &= ~CPUID_INTC_ECX_MON; | |
| 751 #endif /* __xpv */ | |
| 752 | |
| 0 | 753 /* |
| 754 * Now we've figured out the masks that determine | |
| 755 * which bits we choose to believe, apply the masks | |
| 756 * to the feature words, then map the kernel's view | |
| 757 * of these feature words into its feature word. | |
| 758 */ | |
| 759 cp->cp_edx &= mask_edx; | |
| 760 cp->cp_ecx &= mask_ecx; | |
| 761 | |
| 762 /* | |
| 3446 | 763 * apply any platform restrictions (we don't call this |
| 764 * immediately after __cpuid_insn here, because we need the | |
| 765 * workarounds applied above first) | |
| 0 | 766 */ |
| 3446 | 767 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); |
| 0 | 768 |
| 3446 | 769 /* |
| 770 * fold in overrides from the "eeprom" mechanism | |
| 771 */ | |
| 0 | 772 cp->cp_edx |= cpuid_feature_edx_include; |
| 773 cp->cp_edx &= ~cpuid_feature_edx_exclude; | |
| 774 | |
| 775 cp->cp_ecx |= cpuid_feature_ecx_include; | |
| 776 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; | |
| 777 | |
| 778 if (cp->cp_edx & CPUID_INTC_EDX_PSE) | |
| 779 feature |= X86_LARGEPAGE; | |
| 780 if (cp->cp_edx & CPUID_INTC_EDX_TSC) | |
| 781 feature |= X86_TSC; | |
| 782 if (cp->cp_edx & CPUID_INTC_EDX_MSR) | |
| 783 feature |= X86_MSR; | |
| 784 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) | |
| 785 feature |= X86_MTRR; | |
| 786 if (cp->cp_edx & CPUID_INTC_EDX_PGE) | |
| 787 feature |= X86_PGE; | |
| 788 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) | |
| 789 feature |= X86_CMOV; | |
| 790 if (cp->cp_edx & CPUID_INTC_EDX_MMX) | |
| 791 feature |= X86_MMX; | |
| 792 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && | |
| 793 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) | |
| 794 feature |= X86_MCA; | |
| 795 if (cp->cp_edx & CPUID_INTC_EDX_PAE) | |
| 796 feature |= X86_PAE; | |
| 797 if (cp->cp_edx & CPUID_INTC_EDX_CX8) | |
| 798 feature |= X86_CX8; | |
| 799 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) | |
| 800 feature |= X86_CX16; | |
| 801 if (cp->cp_edx & CPUID_INTC_EDX_PAT) | |
| 802 feature |= X86_PAT; | |
| 803 if (cp->cp_edx & CPUID_INTC_EDX_SEP) | |
| 804 feature |= X86_SEP; | |
| 805 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { | |
| 806 /* | |
| 807 * In our implementation, fxsave/fxrstor | |
| 808 * are prerequisites before we'll even | |
| 809 * try and do SSE things. | |
| 810 */ | |
| 811 if (cp->cp_edx & CPUID_INTC_EDX_SSE) | |
| 812 feature |= X86_SSE; | |
| 813 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) | |
| 814 feature |= X86_SSE2; | |
| 815 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) | |
| 816 feature |= X86_SSE3; | |
|
5269
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817 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
818 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) |
|
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
819 feature |= X86_SSSE3; |
|
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
820 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) |
|
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
821 feature |= X86_SSE4_1; |
|
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|
822 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) |
|
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|
823 feature |= X86_SSE4_2; |
|
9370
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|
824 if (cp->cp_ecx & CPUID_INTC_ECX_AES) |
|
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
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changeset
|
825 feature |= X86_AES; |
|
5269
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|
826 } |
| 0 | 827 } |
| 828 if (cp->cp_edx & CPUID_INTC_EDX_DE) | |
| 3446 | 829 feature |= X86_DE; |
|
7716
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|
830 #if !defined(__xpv) |
|
4481
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831 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { |
|
7716
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|
832 |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
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|
833 /* |
|
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|
834 * We require the CLFLUSH instruction for erratum workaround |
|
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6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
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|
835 * to use MONITOR/MWAIT. |
|
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|
836 */ |
|
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|
837 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
|
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|
838 cpi->cpi_mwait.support |= MWAIT_SUPPORT; |
|
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|
839 feature |= X86_MWAIT; |
|
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|
840 } else { |
|
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|
841 extern int idle_cpu_assert_cflush_monitor; |
|
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|
842 |
|
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|
843 /* |
|
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|
844 * All processors we are aware of which have |
|
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845 * MONITOR/MWAIT also have CLFLUSH. |
|
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846 */ |
|
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|
847 if (idle_cpu_assert_cflush_monitor) { |
|
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848 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && |
|
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849 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); |
|
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850 } |
|
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|
851 } |
|
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852 } |
|
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|
853 #endif /* __xpv */ |
| 0 | 854 |
|
7589
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855 /* |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
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|
856 * Only need it first time, rest of the cpus would follow suite. |
|
7de800909a06
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857 * we only capture this for the bootcpu. |
|
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858 */ |
|
7de800909a06
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|
859 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
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|
860 feature |= X86_CLFSH; |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
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|
861 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); |
|
7de800909a06
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862 } |
|
7de800909a06
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|
863 |
| 0 | 864 if (feature & X86_PAE) |
| 865 cpi->cpi_pabits = 36; | |
| 866 | |
| 867 /* | |
| 868 * Hyperthreading configuration is slightly tricky on Intel | |
| 869 * and pure clones, and even trickier on AMD. | |
| 870 * | |
| 871 * (AMD chose to set the HTT bit on their CMP processors, | |
| 872 * even though they're not actually hyperthreaded. Thus it | |
| 873 * takes a bit more work to figure out what's really going | |
| 3446 | 874 * on ... see the handling of the CMP_LGCY bit below) |
| 0 | 875 */ |
| 876 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { | |
| 877 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); | |
| 878 if (cpi->cpi_ncpu_per_chip > 1) | |
| 879 feature |= X86_HTT; | |
| 1228 | 880 } else { |
| 881 cpi->cpi_ncpu_per_chip = 1; | |
| 0 | 882 } |
| 883 | |
| 884 /* | |
| 885 * Work on the "extended" feature information, doing | |
| 886 * some basic initialization for cpuid_pass2() | |
| 887 */ | |
| 888 xcpuid = 0; | |
| 889 switch (cpi->cpi_vendor) { | |
| 890 case X86_VENDOR_Intel: | |
|
1975
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6183891 Missing brand ID strings for several common x86 CPUs
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891 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) |
| 0 | 892 xcpuid++; |
| 893 break; | |
| 894 case X86_VENDOR_AMD: | |
| 895 if (cpi->cpi_family > 5 || | |
| 896 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 897 xcpuid++; | |
| 898 break; | |
| 899 case X86_VENDOR_Cyrix: | |
| 900 /* | |
| 901 * Only these Cyrix CPUs are -known- to support | |
| 902 * extended cpuid operations. | |
| 903 */ | |
| 904 if (x86_type == X86_TYPE_VIA_CYRIX_III || | |
| 905 x86_type == X86_TYPE_CYRIX_GXm) | |
| 906 xcpuid++; | |
| 907 break; | |
| 908 case X86_VENDOR_Centaur: | |
| 909 case X86_VENDOR_TM: | |
| 910 default: | |
| 911 xcpuid++; | |
| 912 break; | |
| 913 } | |
| 914 | |
| 915 if (xcpuid) { | |
| 916 cp = &cpi->cpi_extd[0]; | |
| 1228 | 917 cp->cp_eax = 0x80000000; |
| 918 cpi->cpi_xmaxeax = __cpuid_insn(cp); | |
| 0 | 919 } |
| 920 | |
| 921 if (cpi->cpi_xmaxeax & 0x80000000) { | |
| 922 | |
| 923 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) | |
| 924 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; | |
| 925 | |
| 926 switch (cpi->cpi_vendor) { | |
| 927 case X86_VENDOR_Intel: | |
| 928 case X86_VENDOR_AMD: | |
| 929 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 930 break; | |
| 931 cp = &cpi->cpi_extd[1]; | |
| 1228 | 932 cp->cp_eax = 0x80000001; |
| 933 (void) __cpuid_insn(cp); | |
| 3446 | 934 |
| 0 | 935 if (cpi->cpi_vendor == X86_VENDOR_AMD && |
| 936 cpi->cpi_family == 5 && | |
| 937 cpi->cpi_model == 6 && | |
| 938 cpi->cpi_step == 6) { | |
| 939 /* | |
| 940 * K6 model 6 uses bit 10 to indicate SYSC | |
| 941 * Later models use bit 11. Fix it here. | |
| 942 */ | |
| 943 if (cp->cp_edx & 0x400) { | |
| 944 cp->cp_edx &= ~0x400; | |
| 945 cp->cp_edx |= CPUID_AMD_EDX_SYSC; | |
| 946 } | |
| 947 } | |
| 948 | |
| 3446 | 949 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); |
| 950 | |
| 0 | 951 /* |
| 952 * Compute the additions to the kernel's feature word. | |
| 953 */ | |
| 954 if (cp->cp_edx & CPUID_AMD_EDX_NX) | |
| 955 feature |= X86_NX; | |
| 956 | |
|
7656
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957 /* |
|
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|
958 * Regardless whether or not we boot 64-bit, |
|
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|
959 * we should have a way to identify whether |
|
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|
960 * the CPU is capable of running 64-bit. |
|
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|
961 */ |
|
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|
962 if (cp->cp_edx & CPUID_AMD_EDX_LM) |
|
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|
963 feature |= X86_64; |
|
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|
964 |
|
5349
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|
965 #if defined(__amd64) |
|
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|
966 /* 1 GB large page - enable only for 64 bit kernel */ |
|
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|
967 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) |
|
01422ec04372
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|
968 feature |= X86_1GPG; |
|
01422ec04372
6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages
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|
969 #endif |
|
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970 |
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971 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && |
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972 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && |
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973 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) |
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974 feature |= X86_SSE4A; |
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975 |
| 0 | 976 /* |
| 3446 | 977 * If both the HTT and CMP_LGCY bits are set, |
| 1228 | 978 * then we're not actually HyperThreaded. Read |
| 979 * "AMD CPUID Specification" for more details. | |
| 0 | 980 */ |
| 981 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
| 1228 | 982 (feature & X86_HTT) && |
| 3446 | 983 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { |
| 0 | 984 feature &= ~X86_HTT; |
| 1228 | 985 feature |= X86_CMP; |
| 986 } | |
| 3446 | 987 #if defined(__amd64) |
| 0 | 988 /* |
| 989 * It's really tricky to support syscall/sysret in | |
| 990 * the i386 kernel; we rely on sysenter/sysexit | |
| 991 * instead. In the amd64 kernel, things are -way- | |
| 992 * better. | |
| 993 */ | |
| 994 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) | |
| 995 feature |= X86_ASYSC; | |
| 996 | |
| 997 /* | |
| 998 * While we're thinking about system calls, note | |
| 999 * that AMD processors don't support sysenter | |
| 1000 * in long mode at all, so don't try to program them. | |
| 1001 */ | |
| 1002 if (x86_vendor == X86_VENDOR_AMD) | |
| 1003 feature &= ~X86_SEP; | |
| 1004 #endif | |
| 6657 | 1005 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) |
| 3446 | 1006 feature |= X86_TSCP; |
| 0 | 1007 break; |
| 1008 default: | |
| 1009 break; | |
| 1010 } | |
| 1011 | |
| 1228 | 1012 /* |
| 1013 * Get CPUID data about processor cores and hyperthreads. | |
| 1014 */ | |
| 0 | 1015 switch (cpi->cpi_vendor) { |
| 1016 case X86_VENDOR_Intel: | |
| 1228 | 1017 if (cpi->cpi_maxeax >= 4) { |
| 1018 cp = &cpi->cpi_std[4]; | |
| 1019 cp->cp_eax = 4; | |
| 1020 cp->cp_ecx = 0; | |
| 1021 (void) __cpuid_insn(cp); | |
| 3446 | 1022 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); |
| 1228 | 1023 } |
| 1024 /*FALLTHROUGH*/ | |
| 0 | 1025 case X86_VENDOR_AMD: |
| 1026 if (cpi->cpi_xmaxeax < 0x80000008) | |
| 1027 break; | |
| 1028 cp = &cpi->cpi_extd[8]; | |
| 1228 | 1029 cp->cp_eax = 0x80000008; |
| 1030 (void) __cpuid_insn(cp); | |
| 3446 | 1031 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); |
| 1032 | |
| 0 | 1033 /* |
| 1034 * Virtual and physical address limits from | |
| 1035 * cpuid override previously guessed values. | |
| 1036 */ | |
| 1037 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); | |
| 1038 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); | |
| 1039 break; | |
| 1040 default: | |
| 1041 break; | |
| 1042 } | |
| 1228 | 1043 |
| 4606 | 1044 /* |
| 1045 * Derive the number of cores per chip | |
| 1046 */ | |
| 1228 | 1047 switch (cpi->cpi_vendor) { |
| 1048 case X86_VENDOR_Intel: | |
| 1049 if (cpi->cpi_maxeax < 4) { | |
| 1050 cpi->cpi_ncore_per_chip = 1; | |
| 1051 break; | |
| 1052 } else { | |
| 1053 cpi->cpi_ncore_per_chip = | |
| 1054 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; | |
| 1055 } | |
| 1056 break; | |
| 1057 case X86_VENDOR_AMD: | |
| 1058 if (cpi->cpi_xmaxeax < 0x80000008) { | |
| 1059 cpi->cpi_ncore_per_chip = 1; | |
| 1060 break; | |
| 1061 } else { | |
|
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1062 /* |
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1063 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is |
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1064 * 1 less than the number of physical cores on |
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1065 * the chip. In family 0x10 this value can |
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1066 * be affected by "downcoring" - it reflects |
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1067 * 1 less than the number of cores actually |
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1068 * enabled on this node. |
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1069 */ |
| 1228 | 1070 cpi->cpi_ncore_per_chip = |
| 1071 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; | |
| 1072 } | |
| 1073 break; | |
| 1074 default: | |
| 1075 cpi->cpi_ncore_per_chip = 1; | |
| 1076 break; | |
| 1077 } | |
|
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1078 |
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1079 /* |
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1080 * Get CPUID data about TSC Invariance in Deep C-State. |
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1081 */ |
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1082 switch (cpi->cpi_vendor) { |
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1083 case X86_VENDOR_Intel: |
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1084 if (cpi->cpi_maxeax >= 7) { |
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1085 cp = &cpi->cpi_extd[7]; |
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1086 cp->cp_eax = 0x80000007; |
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1087 cp->cp_ecx = 0; |
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1088 (void) __cpuid_insn(cp); |
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1089 } |
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1090 break; |
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1091 default: |
|
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1092 break; |
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|
1093 } |
| 5284 | 1094 } else { |
| 1095 cpi->cpi_ncore_per_chip = 1; | |
| 0 | 1096 } |
| 1097 | |
| 1228 | 1098 /* |
| 1099 * If more than one core, then this processor is CMP. | |
| 1100 */ | |
| 1101 if (cpi->cpi_ncore_per_chip > 1) | |
| 1102 feature |= X86_CMP; | |
| 3446 | 1103 |
| 1228 | 1104 /* |
| 1105 * If the number of cores is the same as the number | |
| 1106 * of CPUs, then we cannot have HyperThreading. | |
| 1107 */ | |
| 1108 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) | |
| 1109 feature &= ~X86_HTT; | |
| 1110 | |
| 0 | 1111 if ((feature & (X86_HTT | X86_CMP)) == 0) { |
| 1228 | 1112 /* |
| 1113 * Single-core single-threaded processors. | |
| 1114 */ | |
| 0 | 1115 cpi->cpi_chipid = -1; |
| 1116 cpi->cpi_clogid = 0; | |
| 1228 | 1117 cpi->cpi_coreid = cpu->cpu_id; |
|
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1118 cpi->cpi_pkgcoreid = 0; |
| 0 | 1119 } else if (cpi->cpi_ncpu_per_chip > 1) { |
| 1228 | 1120 uint_t i; |
| 1121 uint_t chipid_shift = 0; | |
| 1122 uint_t coreid_shift = 0; | |
| 1123 uint_t apic_id = CPI_APIC_ID(cpi); | |
| 1124 | |
| 1125 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) | |
| 1126 chipid_shift++; | |
| 1127 cpi->cpi_chipid = apic_id >> chipid_shift; | |
| 1128 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); | |
| 0 | 1129 |
| 1228 | 1130 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
| 1131 if (feature & X86_CMP) { | |
| 1132 /* | |
| 1133 * Multi-core (and possibly multi-threaded) | |
| 1134 * processors. | |
| 1135 */ | |
| 1136 uint_t ncpu_per_core; | |
| 1137 if (cpi->cpi_ncore_per_chip == 1) | |
| 1138 ncpu_per_core = cpi->cpi_ncpu_per_chip; | |
| 1139 else if (cpi->cpi_ncore_per_chip > 1) | |
| 1140 ncpu_per_core = cpi->cpi_ncpu_per_chip / | |
| 1141 cpi->cpi_ncore_per_chip; | |
| 1142 /* | |
| 1143 * 8bit APIC IDs on dual core Pentiums | |
| 1144 * look like this: | |
| 1145 * | |
| 1146 * +-----------------------+------+------+ | |
| 1147 * | Physical Package ID | MC | HT | | |
| 1148 * +-----------------------+------+------+ | |
| 1149 * <------- chipid --------> | |
| 1150 * <------- coreid ---------------> | |
| 1151 * <--- clogid --> | |
|
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1152 * <------> |
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1153 * pkgcoreid |
| 1228 | 1154 * |
| 1155 * Where the number of bits necessary to | |
| 1156 * represent MC and HT fields together equals | |
| 1157 * to the minimum number of bits necessary to | |
| 1158 * store the value of cpi->cpi_ncpu_per_chip. | |
| 1159 * Of those bits, the MC part uses the number | |
| 1160 * of bits necessary to store the value of | |
| 1161 * cpi->cpi_ncore_per_chip. | |
| 1162 */ | |
| 1163 for (i = 1; i < ncpu_per_core; i <<= 1) | |
| 1164 coreid_shift++; | |
|
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1165 cpi->cpi_coreid = apic_id >> coreid_shift; |
|
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1166 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> |
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1167 coreid_shift; |
| 1228 | 1168 } else if (feature & X86_HTT) { |
| 1169 /* | |
| 1170 * Single-core multi-threaded processors. | |
| 1171 */ | |
| 1172 cpi->cpi_coreid = cpi->cpi_chipid; | |
|
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1173 cpi->cpi_pkgcoreid = 0; |
| 1228 | 1174 } |
| 1175 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { | |
| 1176 /* | |
|
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1177 * AMD CMP chips currently have a single thread per |
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1178 * core, with 2 cores on family 0xf and 2, 3 or 4 |
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1179 * cores on family 0x10. |
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1180 * |
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1181 * Since no two cpus share a core we must assign a |
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1182 * distinct coreid per cpu, and we do this by using |
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1183 * the cpu_id. This scheme does not, however, |
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1184 * guarantee that sibling cores of a chip will have |
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1185 * sequential coreids starting at a multiple of the |
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1186 * number of cores per chip - that is usually the |
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1187 * case, but if the ACPI MADT table is presented |
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1188 * in a different order then we need to perform a |
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1189 * few more gymnastics for the pkgcoreid. |
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1190 * |
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1191 * In family 0xf CMPs there are 2 cores on all nodes |
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1192 * present - no mixing of single and dual core parts. |
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1193 * |
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1194 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] |
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1195 * "ApicIdCoreIdSize[3:0]" tells us how |
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1196 * many least-significant bits in the ApicId |
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1197 * are used to represent the core number |
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1198 * within the node. Cores are always |
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1199 * numbered sequentially from 0 regardless |
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1200 * of how many or which are disabled, and |
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1201 * there seems to be no way to discover the |
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1202 * real core id when some are disabled. |
| 1228 | 1203 */ |
| 1204 cpi->cpi_coreid = cpu->cpu_id; | |
|
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1205 |
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1206 if (cpi->cpi_family == 0x10 && |
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1207 cpi->cpi_xmaxeax >= 0x80000008) { |
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1208 int coreidsz = |
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1209 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); |
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1210 |
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1211 cpi->cpi_pkgcoreid = |
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1212 apic_id & ((1 << coreidsz) - 1); |
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1213 } else { |
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1214 cpi->cpi_pkgcoreid = cpi->cpi_clogid; |
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1215 } |
| 1228 | 1216 } else { |
| 1217 /* | |
| 1218 * All other processors are currently | |
| 1219 * assumed to have single cores. | |
| 1220 */ | |
| 1221 cpi->cpi_coreid = cpi->cpi_chipid; | |
|
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|
1222 cpi->cpi_pkgcoreid = 0; |
| 1228 | 1223 } |
| 0 | 1224 } |
| 1225 | |
|
7282
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6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
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|
1226 cpi->cpi_apicid = CPI_APIC_ID(cpi); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1227 |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1228 /* |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1229 * Synthesize chip "revision" and socket type |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1230 */ |
|
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1231 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1232 cpi->cpi_model, cpi->cpi_step); |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
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diff
changeset
|
1233 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1234 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1235 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1236 cpi->cpi_model, cpi->cpi_step); |
|
2869
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PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
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diff
changeset
|
1237 |
| 0 | 1238 pass1_done: |
| 1239 cpi->cpi_pass = 1; | |
| 1240 return (feature); | |
| 1241 } | |
| 1242 | |
| 1243 /* | |
| 1244 * Make copies of the cpuid table entries we depend on, in | |
| 1245 * part for ease of parsing now, in part so that we have only | |
| 1246 * one place to correct any of it, in part for ease of | |
| 1247 * later export to userland, and in part so we can look at | |
| 1248 * this stuff in a crash dump. | |
| 1249 */ | |
| 1250 | |
| 1251 /*ARGSUSED*/ | |
| 1252 void | |
| 1253 cpuid_pass2(cpu_t *cpu) | |
| 1254 { | |
| 1255 uint_t n, nmax; | |
| 1256 int i; | |
| 1228 | 1257 struct cpuid_regs *cp; |
| 0 | 1258 uint8_t *dp; |
| 1259 uint32_t *iptr; | |
| 1260 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1261 | |
| 1262 ASSERT(cpi->cpi_pass == 1); | |
| 1263 | |
| 1264 if (cpi->cpi_maxeax < 1) | |
| 1265 goto pass2_done; | |
| 1266 | |
| 1267 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) | |
| 1268 nmax = NMAX_CPI_STD; | |
| 1269 /* | |
| 1270 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1271 */ | |
| 1272 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { | |
| 1228 | 1273 cp->cp_eax = n; |
| 4606 | 1274 |
| 1275 /* | |
| 1276 * CPUID function 4 expects %ecx to be initialized | |
| 1277 * with an index which indicates which cache to return | |
| 1278 * information about. The OS is expected to call function 4 | |
| 1279 * with %ecx set to 0, 1, 2, ... until it returns with | |
| 1280 * EAX[4:0] set to 0, which indicates there are no more | |
| 1281 * caches. | |
| 1282 * | |
| 1283 * Here, populate cpi_std[4] with the information returned by | |
| 1284 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() | |
| 1285 * when dynamic memory allocation becomes available. | |
| 1286 * | |
| 1287 * Note: we need to explicitly initialize %ecx here, since | |
| 1288 * function 4 may have been previously invoked. | |
| 1289 */ | |
| 1290 if (n == 4) | |
| 1291 cp->cp_ecx = 0; | |
| 1292 | |
| 1228 | 1293 (void) __cpuid_insn(cp); |
| 3446 | 1294 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); |
| 0 | 1295 switch (n) { |
| 1296 case 2: | |
| 1297 /* | |
| 1298 * "the lower 8 bits of the %eax register | |
| 1299 * contain a value that identifies the number | |
| 1300 * of times the cpuid [instruction] has to be | |
| 1301 * executed to obtain a complete image of the | |
| 1302 * processor's caching systems." | |
| 1303 * | |
| 1304 * How *do* they make this stuff up? | |
| 1305 */ | |
| 1306 cpi->cpi_ncache = sizeof (*cp) * | |
| 1307 BITX(cp->cp_eax, 7, 0); | |
| 1308 if (cpi->cpi_ncache == 0) | |
| 1309 break; | |
| 1310 cpi->cpi_ncache--; /* skip count byte */ | |
| 1311 | |
| 1312 /* | |
| 1313 * Well, for now, rather than attempt to implement | |
| 1314 * this slightly dubious algorithm, we just look | |
| 1315 * at the first 15 .. | |
| 1316 */ | |
| 1317 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) | |
| 1318 cpi->cpi_ncache = sizeof (*cp) - 1; | |
| 1319 | |
| 1320 dp = cpi->cpi_cacheinfo; | |
| 1321 if (BITX(cp->cp_eax, 31, 31) == 0) { | |
| 1322 uint8_t *p = (void *)&cp->cp_eax; | |
|
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
1323 for (i = 1; i < 4; i++) |
| 0 | 1324 if (p[i] != 0) |
| 1325 *dp++ = p[i]; | |
| 1326 } | |
| 1327 if (BITX(cp->cp_ebx, 31, 31) == 0) { | |
| 1328 uint8_t *p = (void *)&cp->cp_ebx; | |
| 1329 for (i = 0; i < 4; i++) | |
| 1330 if (p[i] != 0) | |
| 1331 *dp++ = p[i]; | |
| 1332 } | |
| 1333 if (BITX(cp->cp_ecx, 31, 31) == 0) { | |
| 1334 uint8_t *p = (void *)&cp->cp_ecx; | |
| 1335 for (i = 0; i < 4; i++) | |
| 1336 if (p[i] != 0) | |
| 1337 *dp++ = p[i]; | |
| 1338 } | |
| 1339 if (BITX(cp->cp_edx, 31, 31) == 0) { | |
| 1340 uint8_t *p = (void *)&cp->cp_edx; | |
| 1341 for (i = 0; i < 4; i++) | |
| 1342 if (p[i] != 0) | |
| 1343 *dp++ = p[i]; | |
| 1344 } | |
| 1345 break; | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1346 |
| 0 | 1347 case 3: /* Processor serial number, if PSN supported */ |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1348 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1349 |
| 0 | 1350 case 4: /* Deterministic cache parameters */ |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1351 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1352 |
| 0 | 1353 case 5: /* Monitor/Mwait parameters */ |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1354 { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1355 size_t mwait_size; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1356 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1357 /* |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1358 * check cpi_mwait.support which was set in cpuid_pass1 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1359 */ |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1360 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1361 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1362 |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1363 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1364 * Protect ourself from insane mwait line size. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1365 * Workaround for incomplete hardware emulator(s). |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1366 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1367 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1368 if (mwait_size < sizeof (uint32_t) || |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1369 !ISP2(mwait_size)) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1370 #if DEBUG |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1371 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1372 "size %ld", cpu->cpu_id, (long)mwait_size); |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1373 #endif |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1374 break; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1375 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1376 |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1377 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1378 cpi->cpi_mwait.mon_max = mwait_size; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1379 if (MWAIT_EXTENSION(cpi)) { |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1380 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1381 if (MWAIT_INT_ENABLE(cpi)) |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1382 cpi->cpi_mwait.support |= |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1383 MWAIT_ECX_INT_ENABLE; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1384 } |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1385 break; |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1386 } |
| 0 | 1387 default: |
| 1388 break; | |
| 1389 } | |
| 1390 } | |
| 1391 | |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1392 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1393 struct cpuid_regs regs; |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1394 |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1395 cp = ®s; |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1396 cp->cp_eax = 0xB; |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1397 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1398 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1399 (void) __cpuid_insn(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1400 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1401 /* |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1402 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1403 * indicates that the extended topology enumeration leaf is |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1404 * available. |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1405 */ |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1406 if (cp->cp_ebx) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1407 uint32_t x2apic_id; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1408 uint_t coreid_shift = 0; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1409 uint_t ncpu_per_core = 1; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1410 uint_t chipid_shift = 0; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1411 uint_t ncpu_per_chip = 1; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1412 uint_t i; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1413 uint_t level; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1414 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1415 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1416 cp->cp_eax = 0xB; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1417 cp->cp_ecx = i; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1418 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1419 (void) __cpuid_insn(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1420 level = CPI_CPU_LEVEL_TYPE(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1421 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1422 if (level == 1) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1423 x2apic_id = cp->cp_edx; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1424 coreid_shift = BITX(cp->cp_eax, 4, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1425 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1426 } else if (level == 2) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1427 x2apic_id = cp->cp_edx; |
|
5b3b6674ac91
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1428 chipid_shift = BITX(cp->cp_eax, 4, 0); |
|
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1429 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); |
|
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1430 } |
|
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|
1431 } |
|
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|
1432 |
|
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|
1433 cpi->cpi_apicid = x2apic_id; |
|
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|
1434 cpi->cpi_ncpu_per_chip = ncpu_per_chip; |
|
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changeset
|
1435 cpi->cpi_ncore_per_chip = ncpu_per_chip / |
|
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parents:
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changeset
|
1436 ncpu_per_core; |
|
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changeset
|
1437 cpi->cpi_chipid = x2apic_id >> chipid_shift; |
|
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changeset
|
1438 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); |
|
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changeset
|
1439 cpi->cpi_coreid = x2apic_id >> coreid_shift; |
|
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parents:
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diff
changeset
|
1440 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; |
|
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|
1441 } |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
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parents:
7716
diff
changeset
|
1442 |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
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parents:
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diff
changeset
|
1443 /* Make cp NULL so that we don't stumble on others */ |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1444 cp = NULL; |
|
7282
5b3b6674ac91
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|
1445 } |
|
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|
1446 |
| 0 | 1447 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) |
| 1448 goto pass2_done; | |
| 1449 | |
| 1450 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) | |
| 1451 nmax = NMAX_CPI_EXTD; | |
| 1452 /* | |
| 1453 * Copy the extended properties, fixing them as we go. | |
| 1454 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1455 */ | |
| 1456 iptr = (void *)cpi->cpi_brandstr; | |
| 1457 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { | |
| 1228 | 1458 cp->cp_eax = 0x80000000 + n; |
| 1459 (void) __cpuid_insn(cp); | |
| 3446 | 1460 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); |
| 0 | 1461 switch (n) { |
| 1462 case 2: | |
| 1463 case 3: | |
| 1464 case 4: | |
| 1465 /* | |
| 1466 * Extract the brand string | |
| 1467 */ | |
| 1468 *iptr++ = cp->cp_eax; | |
| 1469 *iptr++ = cp->cp_ebx; | |
| 1470 *iptr++ = cp->cp_ecx; | |
| 1471 *iptr++ = cp->cp_edx; | |
| 1472 break; | |
| 1473 case 5: | |
| 1474 switch (cpi->cpi_vendor) { | |
| 1475 case X86_VENDOR_AMD: | |
| 1476 /* | |
| 1477 * The Athlon and Duron were the first | |
| 1478 * parts to report the sizes of the | |
| 1479 * TLB for large pages. Before then, | |
| 1480 * we don't trust the data. | |
| 1481 */ | |
| 1482 if (cpi->cpi_family < 6 || | |
| 1483 (cpi->cpi_family == 6 && | |
| 1484 cpi->cpi_model < 1)) | |
| 1485 cp->cp_eax = 0; | |
| 1486 break; | |
| 1487 default: | |
| 1488 break; | |
| 1489 } | |
| 1490 break; | |
| 1491 case 6: | |
| 1492 switch (cpi->cpi_vendor) { | |
| 1493 case X86_VENDOR_AMD: | |
| 1494 /* | |
| 1495 * The Athlon and Duron were the first | |
| 1496 * AMD parts with L2 TLB's. | |
| 1497 * Before then, don't trust the data. | |
| 1498 */ | |
| 1499 if (cpi->cpi_family < 6 || | |
| 1500 cpi->cpi_family == 6 && | |
| 1501 cpi->cpi_model < 1) | |
| 1502 cp->cp_eax = cp->cp_ebx = 0; | |
| 1503 /* | |
| 1504 * AMD Duron rev A0 reports L2 | |
| 1505 * cache size incorrectly as 1K | |
| 1506 * when it is really 64K | |
| 1507 */ | |
| 1508 if (cpi->cpi_family == 6 && | |
| 1509 cpi->cpi_model == 3 && | |
| 1510 cpi->cpi_step == 0) { | |
| 1511 cp->cp_ecx &= 0xffff; | |
| 1512 cp->cp_ecx |= 0x400000; | |
| 1513 } | |
| 1514 break; | |
| 1515 case X86_VENDOR_Cyrix: /* VIA C3 */ | |
| 1516 /* | |
| 1517 * VIA C3 processors are a bit messed | |
| 1518 * up w.r.t. encoding cache sizes in %ecx | |
| 1519 */ | |
| 1520 if (cpi->cpi_family != 6) | |
| 1521 break; | |
| 1522 /* | |
| 1523 * model 7 and 8 were incorrectly encoded | |
| 1524 * | |
| 1525 * xxx is model 8 really broken? | |
| 1526 */ | |
| 1527 if (cpi->cpi_model == 7 || | |
| 1528 cpi->cpi_model == 8) | |
| 1529 cp->cp_ecx = | |
| 1530 BITX(cp->cp_ecx, 31, 24) << 16 | | |
| 1531 BITX(cp->cp_ecx, 23, 16) << 12 | | |
| 1532 BITX(cp->cp_ecx, 15, 8) << 8 | | |
| 1533 BITX(cp->cp_ecx, 7, 0); | |
| 1534 /* | |
| 1535 * model 9 stepping 1 has wrong associativity | |
| 1536 */ | |
| 1537 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) | |
| 1538 cp->cp_ecx |= 8 << 12; | |
| 1539 break; | |
| 1540 case X86_VENDOR_Intel: | |
| 1541 /* | |
| 1542 * Extended L2 Cache features function. | |
| 1543 * First appeared on Prescott. | |
| 1544 */ | |
| 1545 default: | |
| 1546 break; | |
| 1547 } | |
| 1548 break; | |
| 1549 default: | |
| 1550 break; | |
| 1551 } | |
| 1552 } | |
| 1553 | |
| 1554 pass2_done: | |
| 1555 cpi->cpi_pass = 2; | |
| 1556 } | |
| 1557 | |
| 1558 static const char * | |
| 1559 intel_cpubrand(const struct cpuid_info *cpi) | |
| 1560 { | |
| 1561 int i; | |
| 1562 | |
| 1563 if ((x86_feature & X86_CPUID) == 0 || | |
| 1564 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
| 1565 return ("i486"); | |
| 1566 | |
| 1567 switch (cpi->cpi_family) { | |
| 1568 case 5: | |
| 1569 return ("Intel Pentium(r)"); | |
| 1570 case 6: | |
| 1571 switch (cpi->cpi_model) { | |
| 1572 uint_t celeron, xeon; | |
| 1228 | 1573 const struct cpuid_regs *cp; |
| 0 | 1574 case 0: |
| 1575 case 1: | |
| 1576 case 2: | |
| 1577 return ("Intel Pentium(r) Pro"); | |
| 1578 case 3: | |
| 1579 case 4: | |
| 1580 return ("Intel Pentium(r) II"); | |
| 1581 case 6: | |
| 1582 return ("Intel Celeron(r)"); | |
| 1583 case 5: | |
| 1584 case 7: | |
| 1585 celeron = xeon = 0; | |
| 1586 cp = &cpi->cpi_std[2]; /* cache info */ | |
| 1587 | |
|
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
1588 for (i = 1; i < 4; i++) { |
| 0 | 1589 uint_t tmp; |
| 1590 | |
| 1591 tmp = (cp->cp_eax >> (8 * i)) & 0xff; | |
| 1592 if (tmp == 0x40) | |
| 1593 celeron++; | |
| 1594 if (tmp >= 0x44 && tmp <= 0x45) | |
| 1595 xeon++; | |
| 1596 } | |
| 1597 | |
| 1598 for (i = 0; i < 2; i++) { | |
| 1599 uint_t tmp; | |
| 1600 | |
| 1601 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; | |
| 1602 if (tmp == 0x40) | |
| 1603 celeron++; | |
| 1604 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1605 xeon++; | |
| 1606 } | |
| 1607 | |
| 1608 for (i = 0; i < 4; i++) { | |
| 1609 uint_t tmp; | |
| 1610 | |
| 1611 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; | |
| 1612 if (tmp == 0x40) | |
| 1613 celeron++; | |
| 1614 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1615 xeon++; | |
| 1616 } | |
| 1617 | |
| 1618 for (i = 0; i < 4; i++) { | |
| 1619 uint_t tmp; | |
| 1620 | |
| 1621 tmp = (cp->cp_edx >> (8 * i)) & 0xff; | |
| 1622 if (tmp == 0x40) | |
| 1623 celeron++; | |
| 1624 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 1625 xeon++; | |
| 1626 } | |
| 1627 | |
| 1628 if (celeron) | |
| 1629 return ("Intel Celeron(r)"); | |
| 1630 if (xeon) | |
| 1631 return (cpi->cpi_model == 5 ? | |
| 1632 "Intel Pentium(r) II Xeon(tm)" : | |
| 1633 "Intel Pentium(r) III Xeon(tm)"); | |
| 1634 return (cpi->cpi_model == 5 ? | |
| 1635 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : | |
| 1636 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); | |
| 1637 default: | |
| 1638 break; | |
| 1639 } | |
| 1640 default: | |
| 1641 break; | |
| 1642 } | |
| 1643 | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1644 /* BrandID is present if the field is nonzero */ |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1645 if (cpi->cpi_brandid != 0) { |
| 0 | 1646 static const struct { |
| 1647 uint_t bt_bid; | |
| 1648 const char *bt_str; | |
| 1649 } brand_tbl[] = { | |
| 1650 { 0x1, "Intel(r) Celeron(r)" }, | |
| 1651 { 0x2, "Intel(r) Pentium(r) III" }, | |
| 1652 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, | |
| 1653 { 0x4, "Intel(r) Pentium(r) III" }, | |
| 1654 { 0x6, "Mobile Intel(r) Pentium(r) III" }, | |
| 1655 { 0x7, "Mobile Intel(r) Celeron(r)" }, | |
| 1656 { 0x8, "Intel(r) Pentium(r) 4" }, | |
| 1657 { 0x9, "Intel(r) Pentium(r) 4" }, | |
| 1658 { 0xa, "Intel(r) Celeron(r)" }, | |
| 1659 { 0xb, "Intel(r) Xeon(tm)" }, | |
| 1660 { 0xc, "Intel(r) Xeon(tm) MP" }, | |
| 1661 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1662 { 0xf, "Mobile Intel(r) Celeron(r)" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1663 { 0x11, "Mobile Genuine Intel(r)" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1664 { 0x12, "Intel(r) Celeron(r) M" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1665 { 0x13, "Mobile Intel(r) Celeron(r)" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1666 { 0x14, "Intel(r) Celeron(r)" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1667 { 0x15, "Mobile Genuine Intel(r)" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1668 { 0x16, "Intel(r) Pentium(r) M" }, |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1669 { 0x17, "Mobile Intel(r) Celeron(r)" } |
| 0 | 1670 }; |
| 1671 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); | |
| 1672 uint_t sgn; | |
| 1673 | |
| 1674 sgn = (cpi->cpi_family << 8) | | |
| 1675 (cpi->cpi_model << 4) | cpi->cpi_step; | |
| 1676 | |
| 1677 for (i = 0; i < btblmax; i++) | |
| 1678 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) | |
| 1679 break; | |
| 1680 if (i < btblmax) { | |
| 1681 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) | |
| 1682 return ("Intel(r) Celeron(r)"); | |
| 1683 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) | |
| 1684 return ("Intel(r) Xeon(tm) MP"); | |
| 1685 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) | |
| 1686 return ("Intel(r) Xeon(tm)"); | |
| 1687 return (brand_tbl[i].bt_str); | |
| 1688 } | |
| 1689 } | |
| 1690 | |
| 1691 return (NULL); | |
| 1692 } | |
| 1693 | |
| 1694 static const char * | |
| 1695 amd_cpubrand(const struct cpuid_info *cpi) | |
| 1696 { | |
| 1697 if ((x86_feature & X86_CPUID) == 0 || | |
| 1698 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
| 1699 return ("i486 compatible"); | |
| 1700 | |
| 1701 switch (cpi->cpi_family) { | |
| 1702 case 5: | |
| 1703 switch (cpi->cpi_model) { | |
| 1704 case 0: | |
| 1705 case 1: | |
| 1706 case 2: | |
| 1707 case 3: | |
| 1708 case 4: | |
| 1709 case 5: | |
| 1710 return ("AMD-K5(r)"); | |
| 1711 case 6: | |
| 1712 case 7: | |
| 1713 return ("AMD-K6(r)"); | |
| 1714 case 8: | |
| 1715 return ("AMD-K6(r)-2"); | |
| 1716 case 9: | |
| 1717 return ("AMD-K6(r)-III"); | |
| 1718 default: | |
| 1719 return ("AMD (family 5)"); | |
| 1720 } | |
| 1721 case 6: | |
| 1722 switch (cpi->cpi_model) { | |
| 1723 case 1: | |
| 1724 return ("AMD-K7(tm)"); | |
| 1725 case 0: | |
| 1726 case 2: | |
| 1727 case 4: | |
| 1728 return ("AMD Athlon(tm)"); | |
| 1729 case 3: | |
| 1730 case 7: | |
| 1731 return ("AMD Duron(tm)"); | |
| 1732 case 6: | |
| 1733 case 8: | |
| 1734 case 10: | |
| 1735 /* | |
| 1736 * Use the L2 cache size to distinguish | |
| 1737 */ | |
| 1738 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? | |
| 1739 "AMD Athlon(tm)" : "AMD Duron(tm)"); | |
| 1740 default: | |
| 1741 return ("AMD (family 6)"); | |
| 1742 } | |
| 1743 default: | |
| 1744 break; | |
| 1745 } | |
| 1746 | |
| 1747 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && | |
| 1748 cpi->cpi_brandid != 0) { | |
| 1749 switch (BITX(cpi->cpi_brandid, 7, 5)) { | |
| 1750 case 3: | |
| 1751 return ("AMD Opteron(tm) UP 1xx"); | |
| 1752 case 4: | |
| 1753 return ("AMD Opteron(tm) DP 2xx"); | |
| 1754 case 5: | |
| 1755 return ("AMD Opteron(tm) MP 8xx"); | |
| 1756 default: | |
| 1757 return ("AMD Opteron(tm)"); | |
| 1758 } | |
| 1759 } | |
| 1760 | |
| 1761 return (NULL); | |
| 1762 } | |
| 1763 | |
| 1764 static const char * | |
| 1765 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) | |
| 1766 { | |
| 1767 if ((x86_feature & X86_CPUID) == 0 || | |
| 1768 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || | |
| 1769 type == X86_TYPE_CYRIX_486) | |
| 1770 return ("i486 compatible"); | |
| 1771 | |
| 1772 switch (type) { | |
| 1773 case X86_TYPE_CYRIX_6x86: | |
| 1774 return ("Cyrix 6x86"); | |
| 1775 case X86_TYPE_CYRIX_6x86L: | |
| 1776 return ("Cyrix 6x86L"); | |
| 1777 case X86_TYPE_CYRIX_6x86MX: | |
| 1778 return ("Cyrix 6x86MX"); | |
| 1779 case X86_TYPE_CYRIX_GXm: | |
| 1780 return ("Cyrix GXm"); | |
| 1781 case X86_TYPE_CYRIX_MediaGX: | |
| 1782 return ("Cyrix MediaGX"); | |
| 1783 case X86_TYPE_CYRIX_MII: | |
| 1784 return ("Cyrix M2"); | |
| 1785 case X86_TYPE_VIA_CYRIX_III: | |
| 1786 return ("VIA Cyrix M3"); | |
| 1787 default: | |
| 1788 /* | |
| 1789 * Have another wild guess .. | |
| 1790 */ | |
| 1791 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) | |
| 1792 return ("Cyrix 5x86"); | |
| 1793 else if (cpi->cpi_family == 5) { | |
| 1794 switch (cpi->cpi_model) { | |
| 1795 case 2: | |
| 1796 return ("Cyrix 6x86"); /* Cyrix M1 */ | |
| 1797 case 4: | |
| 1798 return ("Cyrix MediaGX"); | |
| 1799 default: | |
| 1800 break; | |
| 1801 } | |
| 1802 } else if (cpi->cpi_family == 6) { | |
| 1803 switch (cpi->cpi_model) { | |
| 1804 case 0: | |
| 1805 return ("Cyrix 6x86MX"); /* Cyrix M2? */ | |
| 1806 case 5: | |
| 1807 case 6: | |
| 1808 case 7: | |
| 1809 case 8: | |
| 1810 case 9: | |
| 1811 return ("VIA C3"); | |
| 1812 default: | |
| 1813 break; | |
| 1814 } | |
| 1815 } | |
| 1816 break; | |
| 1817 } | |
| 1818 return (NULL); | |
| 1819 } | |
| 1820 | |
| 1821 /* | |
| 1822 * This only gets called in the case that the CPU extended | |
| 1823 * feature brand string (0x80000002, 0x80000003, 0x80000004) | |
| 1824 * aren't available, or contain null bytes for some reason. | |
| 1825 */ | |
| 1826 static void | |
| 1827 fabricate_brandstr(struct cpuid_info *cpi) | |
| 1828 { | |
| 1829 const char *brand = NULL; | |
| 1830 | |
| 1831 switch (cpi->cpi_vendor) { | |
| 1832 case X86_VENDOR_Intel: | |
| 1833 brand = intel_cpubrand(cpi); | |
| 1834 break; | |
| 1835 case X86_VENDOR_AMD: | |
| 1836 brand = amd_cpubrand(cpi); | |
| 1837 break; | |
| 1838 case X86_VENDOR_Cyrix: | |
| 1839 brand = cyrix_cpubrand(cpi, x86_type); | |
| 1840 break; | |
| 1841 case X86_VENDOR_NexGen: | |
| 1842 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 1843 brand = "NexGen Nx586"; | |
| 1844 break; | |
| 1845 case X86_VENDOR_Centaur: | |
| 1846 if (cpi->cpi_family == 5) | |
| 1847 switch (cpi->cpi_model) { | |
| 1848 case 4: | |
| 1849 brand = "Centaur C6"; | |
| 1850 break; | |
| 1851 case 8: | |
| 1852 brand = "Centaur C2"; | |
| 1853 break; | |
| 1854 case 9: | |
| 1855 brand = "Centaur C3"; | |
| 1856 break; | |
| 1857 default: | |
| 1858 break; | |
| 1859 } | |
| 1860 break; | |
| 1861 case X86_VENDOR_Rise: | |
| 1862 if (cpi->cpi_family == 5 && | |
| 1863 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) | |
| 1864 brand = "Rise mP6"; | |
| 1865 break; | |
| 1866 case X86_VENDOR_SiS: | |
| 1867 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 1868 brand = "SiS 55x"; | |
| 1869 break; | |
| 1870 case X86_VENDOR_TM: | |
| 1871 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) | |
| 1872 brand = "Transmeta Crusoe TM3x00 or TM5x00"; | |
| 1873 break; | |
| 1874 case X86_VENDOR_NSC: | |
| 1875 case X86_VENDOR_UMC: | |
| 1876 default: | |
| 1877 break; | |
| 1878 } | |
| 1879 if (brand) { | |
| 1880 (void) strcpy((char *)cpi->cpi_brandstr, brand); | |
| 1881 return; | |
| 1882 } | |
| 1883 | |
| 1884 /* | |
| 1885 * If all else fails ... | |
| 1886 */ | |
| 1887 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), | |
| 1888 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, | |
| 1889 cpi->cpi_model, cpi->cpi_step); | |
| 1890 } | |
| 1891 | |
| 1892 /* | |
| 1893 * This routine is called just after kernel memory allocation | |
| 1894 * becomes available on cpu0, and as part of mp_startup() on | |
| 1895 * the other cpus. | |
| 1896 * | |
| 4606 | 1897 * Fixup the brand string, and collect any information from cpuid |
| 1898 * that requires dynamicically allocated storage to represent. | |
| 0 | 1899 */ |
| 1900 /*ARGSUSED*/ | |
| 1901 void | |
| 1902 cpuid_pass3(cpu_t *cpu) | |
| 1903 { | |
| 4606 | 1904 int i, max, shft, level, size; |
| 1905 struct cpuid_regs regs; | |
| 1906 struct cpuid_regs *cp; | |
| 0 | 1907 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 1908 | |
| 1909 ASSERT(cpi->cpi_pass == 2); | |
| 1910 | |
| 4606 | 1911 /* |
| 1912 * Function 4: Deterministic cache parameters | |
| 1913 * | |
| 1914 * Take this opportunity to detect the number of threads | |
| 1915 * sharing the last level cache, and construct a corresponding | |
| 1916 * cache id. The respective cpuid_info members are initialized | |
| 1917 * to the default case of "no last level cache sharing". | |
| 1918 */ | |
| 1919 cpi->cpi_ncpu_shr_last_cache = 1; | |
| 1920 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; | |
| 1921 | |
| 1922 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { | |
| 1923 | |
| 1924 /* | |
| 1925 * Find the # of elements (size) returned by fn 4, and along | |
| 1926 * the way detect last level cache sharing details. | |
| 1927 */ | |
| 1928 bzero(®s, sizeof (regs)); | |
| 1929 cp = ®s; | |
| 1930 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { | |
| 1931 cp->cp_eax = 4; | |
| 1932 cp->cp_ecx = i; | |
| 1933 | |
| 1934 (void) __cpuid_insn(cp); | |
| 1935 | |
| 1936 if (CPI_CACHE_TYPE(cp) == 0) | |
| 1937 break; | |
| 1938 level = CPI_CACHE_LVL(cp); | |
| 1939 if (level > max) { | |
| 1940 max = level; | |
| 1941 cpi->cpi_ncpu_shr_last_cache = | |
| 1942 CPI_NTHR_SHR_CACHE(cp) + 1; | |
| 1943 } | |
| 1944 } | |
| 1945 cpi->cpi_std_4_size = size = i; | |
| 1946 | |
| 1947 /* | |
| 1948 * Allocate the cpi_std_4 array. The first element | |
| 1949 * references the regs for fn 4, %ecx == 0, which | |
| 1950 * cpuid_pass2() stashed in cpi->cpi_std[4]. | |
| 1951 */ | |
| 1952 if (size > 0) { | |
| 1953 cpi->cpi_std_4 = | |
| 1954 kmem_alloc(size * sizeof (cp), KM_SLEEP); | |
| 1955 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; | |
| 1956 | |
| 1957 /* | |
| 1958 * Allocate storage to hold the additional regs | |
| 1959 * for function 4, %ecx == 1 .. cpi_std_4_size. | |
| 1960 * | |
| 1961 * The regs for fn 4, %ecx == 0 has already | |
| 1962 * been allocated as indicated above. | |
| 1963 */ | |
| 1964 for (i = 1; i < size; i++) { | |
| 1965 cp = cpi->cpi_std_4[i] = | |
| 1966 kmem_zalloc(sizeof (regs), KM_SLEEP); | |
| 1967 cp->cp_eax = 4; | |
| 1968 cp->cp_ecx = i; | |
| 1969 | |
| 1970 (void) __cpuid_insn(cp); | |
| 1971 } | |
| 1972 } | |
| 1973 /* | |
| 1974 * Determine the number of bits needed to represent | |
| 1975 * the number of CPUs sharing the last level cache. | |
| 1976 * | |
| 1977 * Shift off that number of bits from the APIC id to | |
| 1978 * derive the cache id. | |
| 1979 */ | |
| 1980 shft = 0; | |
| 1981 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) | |
| 1982 shft++; | |
|
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1983 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; |
| 0 | 1984 } |
| 1985 | |
| 1986 /* | |
| 4606 | 1987 * Now fixup the brand string |
| 0 | 1988 */ |
| 4606 | 1989 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { |
| 1990 fabricate_brandstr(cpi); | |
| 1991 } else { | |
| 0 | 1992 |
| 1993 /* | |
| 4606 | 1994 * If we successfully extracted a brand string from the cpuid |
| 1995 * instruction, clean it up by removing leading spaces and | |
| 1996 * similar junk. | |
| 0 | 1997 */ |
| 4606 | 1998 if (cpi->cpi_brandstr[0]) { |
| 1999 size_t maxlen = sizeof (cpi->cpi_brandstr); | |
| 2000 char *src, *dst; | |
| 2001 | |
| 2002 dst = src = (char *)cpi->cpi_brandstr; | |
| 2003 src[maxlen - 1] = '\0'; | |
| 2004 /* | |
| 2005 * strip leading spaces | |
| 2006 */ | |
| 2007 while (*src == ' ') | |
| 2008 src++; | |
| 2009 /* | |
| 2010 * Remove any 'Genuine' or "Authentic" prefixes | |
| 2011 */ | |
| 2012 if (strncmp(src, "Genuine ", 8) == 0) | |
| 2013 src += 8; | |
| 2014 if (strncmp(src, "Authentic ", 10) == 0) | |
| 2015 src += 10; | |
| 2016 | |
| 2017 /* | |
| 2018 * Now do an in-place copy. | |
| 2019 * Map (R) to (r) and (TM) to (tm). | |
| 2020 * The era of teletypes is long gone, and there's | |
| 2021 * -really- no need to shout. | |
| 2022 */ | |
| 2023 while (*src != '\0') { | |
| 2024 if (src[0] == '(') { | |
| 2025 if (strncmp(src + 1, "R)", 2) == 0) { | |
| 2026 (void) strncpy(dst, "(r)", 3); | |
| 2027 src += 3; | |
| 2028 dst += 3; | |
| 2029 continue; | |
| 2030 } | |
| 2031 if (strncmp(src + 1, "TM)", 3) == 0) { | |
| 2032 (void) strncpy(dst, "(tm)", 4); | |
| 2033 src += 4; | |
| 2034 dst += 4; | |
| 2035 continue; | |
| 2036 } | |
| 0 | 2037 } |
| 4606 | 2038 *dst++ = *src++; |
| 0 | 2039 } |
| 4606 | 2040 *dst = '\0'; |
| 2041 | |
| 2042 /* | |
| 2043 * Finally, remove any trailing spaces | |
| 2044 */ | |
| 2045 while (--dst > cpi->cpi_brandstr) | |
| 2046 if (*dst == ' ') | |
| 2047 *dst = '\0'; | |
| 2048 else | |
| 2049 break; | |
| 2050 } else | |
| 2051 fabricate_brandstr(cpi); | |
| 2052 } | |
| 0 | 2053 cpi->cpi_pass = 3; |
| 2054 } | |
| 2055 | |
| 2056 /* | |
| 2057 * This routine is called out of bind_hwcap() much later in the life | |
| 2058 * of the kernel (post_startup()). The job of this routine is to resolve | |
| 2059 * the hardware feature support and kernel support for those features into | |
| 2060 * what we're actually going to tell applications via the aux vector. | |
| 2061 */ | |
| 2062 uint_t | |
| 2063 cpuid_pass4(cpu_t *cpu) | |
| 2064 { | |
| 2065 struct cpuid_info *cpi; | |
| 2066 uint_t hwcap_flags = 0; | |
| 2067 | |
| 2068 if (cpu == NULL) | |
| 2069 cpu = CPU; | |
| 2070 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2071 | |
| 2072 ASSERT(cpi->cpi_pass == 3); | |
| 2073 | |
| 2074 if (cpi->cpi_maxeax >= 1) { | |
| 2075 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; | |
| 2076 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; | |
| 2077 | |
| 2078 *edx = CPI_FEATURES_EDX(cpi); | |
| 2079 *ecx = CPI_FEATURES_ECX(cpi); | |
| 2080 | |
| 2081 /* | |
| 2082 * [these require explicit kernel support] | |
| 2083 */ | |
| 2084 if ((x86_feature & X86_SEP) == 0) | |
| 2085 *edx &= ~CPUID_INTC_EDX_SEP; | |
| 2086 | |
| 2087 if ((x86_feature & X86_SSE) == 0) | |
| 2088 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); | |
| 2089 if ((x86_feature & X86_SSE2) == 0) | |
| 2090 *edx &= ~CPUID_INTC_EDX_SSE2; | |
| 2091 | |
| 2092 if ((x86_feature & X86_HTT) == 0) | |
| 2093 *edx &= ~CPUID_INTC_EDX_HTT; | |
| 2094 | |
| 2095 if ((x86_feature & X86_SSE3) == 0) | |
| 2096 *ecx &= ~CPUID_INTC_ECX_SSE3; | |
| 2097 | |
|
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2098 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
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2099 if ((x86_feature & X86_SSSE3) == 0) |
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2100 *ecx &= ~CPUID_INTC_ECX_SSSE3; |
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2101 if ((x86_feature & X86_SSE4_1) == 0) |
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2102 *ecx &= ~CPUID_INTC_ECX_SSE4_1; |
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2103 if ((x86_feature & X86_SSE4_2) == 0) |
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2104 *ecx &= ~CPUID_INTC_ECX_SSE4_2; |
|
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2105 if ((x86_feature & X86_AES) == 0) |
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2106 *ecx &= ~CPUID_INTC_ECX_AES; |
|
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2107 } |
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2108 |
| 0 | 2109 /* |
| 2110 * [no explicit support required beyond x87 fp context] | |
| 2111 */ | |
| 2112 if (!fpu_exists) | |
| 2113 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); | |
| 2114 | |
| 2115 /* | |
| 2116 * Now map the supported feature vector to things that we | |
| 2117 * think userland will care about. | |
| 2118 */ | |
| 2119 if (*edx & CPUID_INTC_EDX_SEP) | |
| 2120 hwcap_flags |= AV_386_SEP; | |
| 2121 if (*edx & CPUID_INTC_EDX_SSE) | |
| 2122 hwcap_flags |= AV_386_FXSR | AV_386_SSE; | |
| 2123 if (*edx & CPUID_INTC_EDX_SSE2) | |
| 2124 hwcap_flags |= AV_386_SSE2; | |
| 2125 if (*ecx & CPUID_INTC_ECX_SSE3) | |
| 2126 hwcap_flags |= AV_386_SSE3; | |
|
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2127 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
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2128 if (*ecx & CPUID_INTC_ECX_SSSE3) |
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2129 hwcap_flags |= AV_386_SSSE3; |
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2130 if (*ecx & CPUID_INTC_ECX_SSE4_1) |
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2131 hwcap_flags |= AV_386_SSE4_1; |
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2132 if (*ecx & CPUID_INTC_ECX_SSE4_2) |
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2133 hwcap_flags |= AV_386_SSE4_2; |
|
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2134 if (*ecx & CPUID_INTC_ECX_MOVBE) |
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2135 hwcap_flags |= AV_386_MOVBE; |
|
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2136 if (*ecx & CPUID_INTC_ECX_AES) |
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2137 hwcap_flags |= AV_386_AES; |
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2138 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) |
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2139 hwcap_flags |= AV_386_PCLMULQDQ; |
|
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2140 } |
|
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2141 if (*ecx & CPUID_INTC_ECX_POPCNT) |
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|
2142 hwcap_flags |= AV_386_POPCNT; |
| 0 | 2143 if (*edx & CPUID_INTC_EDX_FPU) |
| 2144 hwcap_flags |= AV_386_FPU; | |
| 2145 if (*edx & CPUID_INTC_EDX_MMX) | |
| 2146 hwcap_flags |= AV_386_MMX; | |
| 2147 | |
| 2148 if (*edx & CPUID_INTC_EDX_TSC) | |
| 2149 hwcap_flags |= AV_386_TSC; | |
| 2150 if (*edx & CPUID_INTC_EDX_CX8) | |
| 2151 hwcap_flags |= AV_386_CX8; | |
| 2152 if (*edx & CPUID_INTC_EDX_CMOV) | |
| 2153 hwcap_flags |= AV_386_CMOV; | |
| 2154 if (*ecx & CPUID_INTC_ECX_MON) | |
| 2155 hwcap_flags |= AV_386_MON; | |
| 2156 if (*ecx & CPUID_INTC_ECX_CX16) | |
| 2157 hwcap_flags |= AV_386_CX16; | |
| 2158 } | |
| 2159 | |
| 1228 | 2160 if (x86_feature & X86_HTT) |
| 0 | 2161 hwcap_flags |= AV_386_PAUSE; |
| 2162 | |
| 2163 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 2164 goto pass4_done; | |
| 2165 | |
| 2166 switch (cpi->cpi_vendor) { | |
| 1228 | 2167 struct cpuid_regs cp; |
| 3446 | 2168 uint32_t *edx, *ecx; |
| 0 | 2169 |
| 3446 | 2170 case X86_VENDOR_Intel: |
| 2171 /* | |
| 2172 * Seems like Intel duplicated what we necessary | |
| 2173 * here to make the initial crop of 64-bit OS's work. | |
| 2174 * Hopefully, those are the only "extended" bits | |
| 2175 * they'll add. | |
| 2176 */ | |
| 2177 /*FALLTHROUGH*/ | |
| 2178 | |
| 0 | 2179 case X86_VENDOR_AMD: |
| 2180 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; | |
| 3446 | 2181 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; |
| 0 | 2182 |
| 2183 *edx = CPI_FEATURES_XTD_EDX(cpi); | |
| 3446 | 2184 *ecx = CPI_FEATURES_XTD_ECX(cpi); |
| 2185 | |
| 2186 /* | |
| 2187 * [these features require explicit kernel support] | |
| 2188 */ | |
| 2189 switch (cpi->cpi_vendor) { | |
| 2190 case X86_VENDOR_Intel: | |
| 6657 | 2191 if ((x86_feature & X86_TSCP) == 0) |
| 2192 *edx &= ~CPUID_AMD_EDX_TSCP; | |
| 3446 | 2193 break; |
| 2194 | |
| 2195 case X86_VENDOR_AMD: | |
| 2196 if ((x86_feature & X86_TSCP) == 0) | |
| 2197 *edx &= ~CPUID_AMD_EDX_TSCP; | |
|
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2198 if ((x86_feature & X86_SSE4A) == 0) |
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2199 *ecx &= ~CPUID_AMD_ECX_SSE4A; |
| 3446 | 2200 break; |
| 2201 | |
| 2202 default: | |
| 2203 break; | |
| 2204 } | |
| 0 | 2205 |
| 2206 /* | |
| 2207 * [no explicit support required beyond | |
| 2208 * x87 fp context and exception handlers] | |
| 2209 */ | |
| 2210 if (!fpu_exists) | |
| 2211 *edx &= ~(CPUID_AMD_EDX_MMXamd | | |
| 2212 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); | |
| 2213 | |
| 2214 if ((x86_feature & X86_NX) == 0) | |
| 2215 *edx &= ~CPUID_AMD_EDX_NX; | |
| 3446 | 2216 #if !defined(__amd64) |
| 0 | 2217 *edx &= ~CPUID_AMD_EDX_LM; |
| 2218 #endif | |
| 2219 /* | |
| 2220 * Now map the supported feature vector to | |
| 2221 * things that we think userland will care about. | |
| 2222 */ | |
| 3446 | 2223 #if defined(__amd64) |
| 0 | 2224 if (*edx & CPUID_AMD_EDX_SYSC) |
| 2225 hwcap_flags |= AV_386_AMD_SYSC; | |
| 3446 | 2226 #endif |
| 0 | 2227 if (*edx & CPUID_AMD_EDX_MMXamd) |
| 2228 hwcap_flags |= AV_386_AMD_MMX; | |
| 2229 if (*edx & CPUID_AMD_EDX_3DNow) | |
| 2230 hwcap_flags |= AV_386_AMD_3DNow; | |
| 2231 if (*edx & CPUID_AMD_EDX_3DNowx) | |
| 2232 hwcap_flags |= AV_386_AMD_3DNowx; | |
| 3446 | 2233 |
| 2234 switch (cpi->cpi_vendor) { | |
| 2235 case X86_VENDOR_AMD: | |
| 2236 if (*edx & CPUID_AMD_EDX_TSCP) | |
| 2237 hwcap_flags |= AV_386_TSCP; | |
| 2238 if (*ecx & CPUID_AMD_ECX_AHF64) | |
| 2239 hwcap_flags |= AV_386_AHF; | |
|
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2240 if (*ecx & CPUID_AMD_ECX_SSE4A) |
|
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2241 hwcap_flags |= AV_386_AMD_SSE4A; |
|
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4606
diff
changeset
|
2242 if (*ecx & CPUID_AMD_ECX_LZCNT) |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
2243 hwcap_flags |= AV_386_AMD_LZCNT; |
| 3446 | 2244 break; |
| 2245 | |
| 2246 case X86_VENDOR_Intel: | |
| 6657 | 2247 if (*edx & CPUID_AMD_EDX_TSCP) |
| 2248 hwcap_flags |= AV_386_TSCP; | |
| 3446 | 2249 /* |
| 2250 * Aarrgh. | |
| 2251 * Intel uses a different bit in the same word. | |
| 2252 */ | |
| 2253 if (*ecx & CPUID_INTC_ECX_AHF64) | |
| 2254 hwcap_flags |= AV_386_AHF; | |
| 2255 break; | |
| 2256 | |
| 2257 default: | |
| 2258 break; | |
| 2259 } | |
| 0 | 2260 break; |
| 2261 | |
| 2262 case X86_VENDOR_TM: | |
| 1228 | 2263 cp.cp_eax = 0x80860001; |
| 2264 (void) __cpuid_insn(&cp); | |
| 2265 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; | |
| 0 | 2266 break; |
| 2267 | |
| 2268 default: | |
| 2269 break; | |
| 2270 } | |
| 2271 | |
| 2272 pass4_done: | |
| 2273 cpi->cpi_pass = 4; | |
| 2274 return (hwcap_flags); | |
| 2275 } | |
| 2276 | |
| 2277 | |
| 2278 /* | |
| 2279 * Simulate the cpuid instruction using the data we previously | |
| 2280 * captured about this CPU. We try our best to return the truth | |
| 2281 * about the hardware, independently of kernel support. | |
| 2282 */ | |
| 2283 uint32_t | |
| 1228 | 2284 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) |
| 0 | 2285 { |
| 2286 struct cpuid_info *cpi; | |
| 1228 | 2287 struct cpuid_regs *xcp; |
| 0 | 2288 |
| 2289 if (cpu == NULL) | |
| 2290 cpu = CPU; | |
| 2291 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2292 | |
| 2293 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2294 | |
| 2295 /* | |
| 2296 * CPUID data is cached in two separate places: cpi_std for standard | |
| 2297 * CPUID functions, and cpi_extd for extended CPUID functions. | |
| 2298 */ | |
| 1228 | 2299 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) |
| 2300 xcp = &cpi->cpi_std[cp->cp_eax]; | |
| 2301 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && | |
| 2302 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) | |
| 2303 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; | |
| 0 | 2304 else |
| 2305 /* | |
| 2306 * The caller is asking for data from an input parameter which | |
| 2307 * the kernel has not cached. In this case we go fetch from | |
| 2308 * the hardware and return the data directly to the user. | |
| 2309 */ | |
| 1228 | 2310 return (__cpuid_insn(cp)); |
| 2311 | |
| 2312 cp->cp_eax = xcp->cp_eax; | |
| 2313 cp->cp_ebx = xcp->cp_ebx; | |
| 2314 cp->cp_ecx = xcp->cp_ecx; | |
| 2315 cp->cp_edx = xcp->cp_edx; | |
| 0 | 2316 return (cp->cp_eax); |
| 2317 } | |
| 2318 | |
| 2319 int | |
| 2320 cpuid_checkpass(cpu_t *cpu, int pass) | |
| 2321 { | |
| 2322 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && | |
| 2323 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); | |
| 2324 } | |
| 2325 | |
| 2326 int | |
| 2327 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) | |
| 2328 { | |
| 2329 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2330 | |
| 2331 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); | |
| 2332 } | |
| 2333 | |
| 2334 int | |
| 1228 | 2335 cpuid_is_cmt(cpu_t *cpu) |
| 0 | 2336 { |
| 2337 if (cpu == NULL) | |
| 2338 cpu = CPU; | |
| 2339 | |
| 2340 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2341 | |
| 2342 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); | |
| 2343 } | |
| 2344 | |
| 2345 /* | |
| 2346 * AMD and Intel both implement the 64-bit variant of the syscall | |
| 2347 * instruction (syscallq), so if there's -any- support for syscall, | |
| 2348 * cpuid currently says "yes, we support this". | |
| 2349 * | |
| 2350 * However, Intel decided to -not- implement the 32-bit variant of the | |
| 2351 * syscall instruction, so we provide a predicate to allow our caller | |
| 2352 * to test that subtlety here. | |
| 5084 | 2353 * |
| 2354 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, | |
| 2355 * even in the case where the hardware would in fact support it. | |
| 0 | 2356 */ |
| 2357 /*ARGSUSED*/ | |
| 2358 int | |
| 2359 cpuid_syscall32_insn(cpu_t *cpu) | |
| 2360 { | |
| 2361 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); | |
| 2362 | |
| 5084 | 2363 #if !defined(__xpv) |
| 3446 | 2364 if (cpu == NULL) |
| 2365 cpu = CPU; | |
| 2366 | |
| 2367 /*CSTYLED*/ | |
| 2368 { | |
| 2369 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2370 | |
| 2371 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
| 2372 cpi->cpi_xmaxeax >= 0x80000001 && | |
| 2373 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) | |
| 2374 return (1); | |
| 2375 } | |
| 5084 | 2376 #endif |
| 0 | 2377 return (0); |
| 2378 } | |
| 2379 | |
| 2380 int | |
| 2381 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) | |
| 2382 { | |
| 2383 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2384 | |
| 2385 static const char fmt[] = | |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
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parents:
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diff
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|
2386 "x86 (%s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2387 static const char fmt_ht[] = |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
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3446
diff
changeset
|
2388 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2389 |
| 2390 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2391 | |
| 1228 | 2392 if (cpuid_is_cmt(cpu)) |
| 0 | 2393 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2394 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
|
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
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3446
diff
changeset
|
2395 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2396 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2397 return (snprintf(s, n, fmt, | |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
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parents:
3446
diff
changeset
|
2398 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
|
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
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3446
diff
changeset
|
2399 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2400 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2401 } | |
| 2402 | |
| 2403 const char * | |
| 2404 cpuid_getvendorstr(cpu_t *cpu) | |
| 2405 { | |
| 2406 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2407 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); | |
| 2408 } | |
| 2409 | |
| 2410 uint_t | |
| 2411 cpuid_getvendor(cpu_t *cpu) | |
| 2412 { | |
| 2413 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2414 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); | |
| 2415 } | |
| 2416 | |
| 2417 uint_t | |
| 2418 cpuid_getfamily(cpu_t *cpu) | |
| 2419 { | |
| 2420 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2421 return (cpu->cpu_m.mcpu_cpi->cpi_family); | |
| 2422 } | |
| 2423 | |
| 2424 uint_t | |
| 2425 cpuid_getmodel(cpu_t *cpu) | |
| 2426 { | |
| 2427 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2428 return (cpu->cpu_m.mcpu_cpi->cpi_model); | |
| 2429 } | |
| 2430 | |
| 2431 uint_t | |
| 2432 cpuid_get_ncpu_per_chip(cpu_t *cpu) | |
| 2433 { | |
| 2434 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2435 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); | |
| 2436 } | |
| 2437 | |
| 2438 uint_t | |
| 1228 | 2439 cpuid_get_ncore_per_chip(cpu_t *cpu) |
| 2440 { | |
| 2441 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2442 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); | |
| 2443 } | |
| 2444 | |
| 2445 uint_t | |
| 4606 | 2446 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) |
| 2447 { | |
| 2448 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2449 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); | |
| 2450 } | |
| 2451 | |
| 2452 id_t | |
| 2453 cpuid_get_last_lvl_cacheid(cpu_t *cpu) | |
| 2454 { | |
| 2455 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2456 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); | |
| 2457 } | |
| 2458 | |
| 2459 uint_t | |
| 0 | 2460 cpuid_getstep(cpu_t *cpu) |
| 2461 { | |
| 2462 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2463 return (cpu->cpu_m.mcpu_cpi->cpi_step); | |
| 2464 } | |
| 2465 | |
| 4581 | 2466 uint_t |
| 2467 cpuid_getsig(struct cpu *cpu) | |
| 2468 { | |
| 2469 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2470 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); | |
| 2471 } | |
| 2472 | |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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diff
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|
2473 uint32_t |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
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diff
changeset
|
2474 cpuid_getchiprev(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
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|
2475 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2476 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2477 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
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|
2478 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2479 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
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2584
diff
changeset
|
2480 const char * |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2481 cpuid_getchiprevstr(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2482 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2483 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2484 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2485 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2486 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2487 uint32_t |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
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|
2488 cpuid_getsockettype(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2489 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2490 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2491 return (cpu->cpu_m.mcpu_cpi->cpi_socket); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2492 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2493 |
|
9482
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2494 const char * |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
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9370
diff
changeset
|
2495 cpuid_getsocketstr(cpu_t *cpu) |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2496 { |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2497 static const char *socketstr = NULL; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2498 struct cpuid_info *cpi; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2499 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2500 ASSERT(cpuid_checkpass(cpu, 1)); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2501 cpi = cpu->cpu_m.mcpu_cpi; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2502 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2503 /* Assume that socket types are the same across the system */ |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2504 if (socketstr == NULL) |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2505 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2506 cpi->cpi_model, cpi->cpi_step); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2507 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2508 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2509 return (socketstr); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2510 } |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
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diff
changeset
|
2511 |
| 3434 | 2512 int |
| 2513 cpuid_get_chipid(cpu_t *cpu) | |
| 0 | 2514 { |
| 2515 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2516 | |
| 1228 | 2517 if (cpuid_is_cmt(cpu)) |
| 0 | 2518 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); |
| 2519 return (cpu->cpu_id); | |
| 2520 } | |
| 2521 | |
| 1228 | 2522 id_t |
| 3434 | 2523 cpuid_get_coreid(cpu_t *cpu) |
| 1228 | 2524 { |
| 2525 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2526 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); | |
| 2527 } | |
| 2528 | |
| 0 | 2529 int |
|
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2530 cpuid_get_pkgcoreid(cpu_t *cpu) |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2531 { |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2532 ASSERT(cpuid_checkpass(cpu, 1)); |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2533 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2534 } |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2535 |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2536 int |
| 3434 | 2537 cpuid_get_clogid(cpu_t *cpu) |
| 0 | 2538 { |
| 2539 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2540 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); | |
| 2541 } | |
| 2542 | |
|
10080
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2543 /*ARGSUSED*/ |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2544 int |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2545 cpuid_have_cr8access(cpu_t *cpu) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2546 { |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2547 #if defined(__amd64) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2548 return (1); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2549 #else |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2550 struct cpuid_info *cpi; |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2551 |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2552 ASSERT(cpu != NULL); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2553 cpi = cpu->cpu_m.mcpu_cpi; |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2554 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2555 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2556 return (1); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2557 return (0); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2558 #endif |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2559 } |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2560 |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2561 uint32_t |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2562 cpuid_get_apicid(cpu_t *cpu) |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2563 { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2564 ASSERT(cpuid_checkpass(cpu, 1)); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2565 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2566 return (UINT32_MAX); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2567 } else { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2568 return (cpu->cpu_m.mcpu_cpi->cpi_apicid); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2569 } |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2570 } |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2571 |
| 0 | 2572 void |
| 2573 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) | |
| 2574 { | |
| 2575 struct cpuid_info *cpi; | |
| 2576 | |
| 2577 if (cpu == NULL) | |
| 2578 cpu = CPU; | |
| 2579 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2580 | |
| 2581 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2582 | |
| 2583 if (pabits) | |
| 2584 *pabits = cpi->cpi_pabits; | |
| 2585 if (vabits) | |
| 2586 *vabits = cpi->cpi_vabits; | |
| 2587 } | |
| 2588 | |
| 2589 /* | |
| 2590 * Returns the number of data TLB entries for a corresponding | |
| 2591 * pagesize. If it can't be computed, or isn't known, the | |
| 2592 * routine returns zero. If you ask about an architecturally | |
| 2593 * impossible pagesize, the routine will panic (so that the | |
| 2594 * hat implementor knows that things are inconsistent.) | |
| 2595 */ | |
| 2596 uint_t | |
| 2597 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) | |
| 2598 { | |
| 2599 struct cpuid_info *cpi; | |
| 2600 uint_t dtlb_nent = 0; | |
| 2601 | |
| 2602 if (cpu == NULL) | |
| 2603 cpu = CPU; | |
| 2604 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2605 | |
| 2606 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2607 | |
| 2608 /* | |
| 2609 * Check the L2 TLB info | |
| 2610 */ | |
| 2611 if (cpi->cpi_xmaxeax >= 0x80000006) { | |
| 1228 | 2612 struct cpuid_regs *cp = &cpi->cpi_extd[6]; |
| 0 | 2613 |
| 2614 switch (pagesize) { | |
| 2615 | |
| 2616 case 4 * 1024: | |
| 2617 /* | |
| 2618 * All zero in the top 16 bits of the register | |
| 2619 * indicates a unified TLB. Size is in low 16 bits. | |
| 2620 */ | |
| 2621 if ((cp->cp_ebx & 0xffff0000) == 0) | |
| 2622 dtlb_nent = cp->cp_ebx & 0x0000ffff; | |
| 2623 else | |
| 2624 dtlb_nent = BITX(cp->cp_ebx, 27, 16); | |
| 2625 break; | |
| 2626 | |
| 2627 case 2 * 1024 * 1024: | |
| 2628 if ((cp->cp_eax & 0xffff0000) == 0) | |
| 2629 dtlb_nent = cp->cp_eax & 0x0000ffff; | |
| 2630 else | |
| 2631 dtlb_nent = BITX(cp->cp_eax, 27, 16); | |
| 2632 break; | |
| 2633 | |
| 2634 default: | |
| 2635 panic("unknown L2 pagesize"); | |
| 2636 /*NOTREACHED*/ | |
| 2637 } | |
| 2638 } | |
| 2639 | |
| 2640 if (dtlb_nent != 0) | |
| 2641 return (dtlb_nent); | |
| 2642 | |
| 2643 /* | |
| 2644 * No L2 TLB support for this size, try L1. | |
| 2645 */ | |
| 2646 if (cpi->cpi_xmaxeax >= 0x80000005) { | |
| 1228 | 2647 struct cpuid_regs *cp = &cpi->cpi_extd[5]; |
| 0 | 2648 |
| 2649 switch (pagesize) { | |
| 2650 case 4 * 1024: | |
| 2651 dtlb_nent = BITX(cp->cp_ebx, 23, 16); | |
| 2652 break; | |
| 2653 case 2 * 1024 * 1024: | |
| 2654 dtlb_nent = BITX(cp->cp_eax, 23, 16); | |
| 2655 break; | |
| 2656 default: | |
| 2657 panic("unknown L1 d-TLB pagesize"); | |
| 2658 /*NOTREACHED*/ | |
| 2659 } | |
| 2660 } | |
| 2661 | |
| 2662 return (dtlb_nent); | |
| 2663 } | |
| 2664 | |
| 2665 /* | |
| 2666 * Return 0 if the erratum is not present or not applicable, positive | |
| 2667 * if it is, and negative if the status of the erratum is unknown. | |
| 2668 * | |
| 2669 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) | |
|
359
a88cb999e7ec
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kucharsk
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0
diff
changeset
|
2670 * Processors" #25759, Rev 3.57, August 2005 |
| 0 | 2671 */ |
| 2672 int | |
| 2673 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) | |
| 2674 { | |
| 2675 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1228 | 2676 uint_t eax; |
| 0 | 2677 |
|
2584
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2678 /* |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2679 * Bail out if this CPU isn't an AMD CPU, or if it's |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2680 * a legacy (32-bit) AMD CPU. |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2681 */ |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2682 if (cpi->cpi_vendor != X86_VENDOR_AMD || |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2683 cpi->cpi_family == 4 || cpi->cpi_family == 5 || |
|
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2684 cpi->cpi_family == 6) |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2685 |
| 0 | 2686 return (0); |
| 2687 | |
| 2688 eax = cpi->cpi_std[1].cp_eax; | |
| 2689 | |
| 2690 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) | |
| 2691 #define SH_B3(eax) (eax == 0xf51) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2692 #define B(eax) (SH_B0(eax) || SH_B3(eax)) |
| 0 | 2693 |
| 2694 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) | |
| 2695 | |
| 2696 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) | |
| 2697 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) | |
| 2698 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2699 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) |
| 0 | 2700 |
| 2701 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) | |
| 2702 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) | |
| 2703 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2704 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) |
| 0 | 2705 |
| 2706 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) | |
| 2707 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ | |
| 2708 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) | |
| 2709 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) | |
| 2710 #define BH_E4(eax) (eax == 0x20fb1) | |
| 2711 #define SH_E5(eax) (eax == 0x20f42) | |
| 2712 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) | |
| 2713 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2714 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2715 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2716 DH_E6(eax) || JH_E6(eax)) |
| 0 | 2717 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2718 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2719 #define DR_B0(eax) (eax == 0x100f20) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2720 #define DR_B1(eax) (eax == 0x100f21) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2721 #define DR_BA(eax) (eax == 0x100f2a) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2722 #define DR_B2(eax) (eax == 0x100f22) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2723 #define DR_B3(eax) (eax == 0x100f23) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2724 #define RB_C0(eax) (eax == 0x100f40) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2725 |
| 0 | 2726 switch (erratum) { |
| 2727 case 1: | |
|
4265
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6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2728 return (cpi->cpi_family < 0x10); |
| 0 | 2729 case 51: /* what does the asterisk mean? */ |
| 2730 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2731 case 52: | |
| 2732 return (B(eax)); | |
| 2733 case 57: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2734 return (cpi->cpi_family <= 0x11); |
| 0 | 2735 case 58: |
| 2736 return (B(eax)); | |
| 2737 case 60: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2738 return (cpi->cpi_family <= 0x11); |
| 0 | 2739 case 61: |
| 2740 case 62: | |
| 2741 case 63: | |
| 2742 case 64: | |
| 2743 case 65: | |
| 2744 case 66: | |
| 2745 case 68: | |
| 2746 case 69: | |
| 2747 case 70: | |
| 2748 case 71: | |
| 2749 return (B(eax)); | |
| 2750 case 72: | |
| 2751 return (SH_B0(eax)); | |
| 2752 case 74: | |
| 2753 return (B(eax)); | |
| 2754 case 75: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2755 return (cpi->cpi_family < 0x10); |
| 0 | 2756 case 76: |
| 2757 return (B(eax)); | |
| 2758 case 77: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2759 return (cpi->cpi_family <= 0x11); |
| 0 | 2760 case 78: |
| 2761 return (B(eax) || SH_C0(eax)); | |
| 2762 case 79: | |
| 2763 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2764 case 80: | |
| 2765 case 81: | |
| 2766 case 82: | |
| 2767 return (B(eax)); | |
| 2768 case 83: | |
| 2769 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2770 case 85: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2771 return (cpi->cpi_family < 0x10); |
| 0 | 2772 case 86: |
| 2773 return (SH_C0(eax) || CG(eax)); | |
| 2774 case 88: | |
| 2775 #if !defined(__amd64) | |
| 2776 return (0); | |
| 2777 #else | |
| 2778 return (B(eax) || SH_C0(eax)); | |
| 2779 #endif | |
| 2780 case 89: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2781 return (cpi->cpi_family < 0x10); |
| 0 | 2782 case 90: |
| 2783 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2784 case 91: | |
| 2785 case 92: | |
| 2786 return (B(eax) || SH_C0(eax)); | |
| 2787 case 93: | |
| 2788 return (SH_C0(eax)); | |
| 2789 case 94: | |
| 2790 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2791 case 95: | |
| 2792 #if !defined(__amd64) | |
| 2793 return (0); | |
| 2794 #else | |
| 2795 return (B(eax) || SH_C0(eax)); | |
| 2796 #endif | |
| 2797 case 96: | |
| 2798 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 2799 case 97: | |
| 2800 case 98: | |
| 2801 return (SH_C0(eax) || CG(eax)); | |
| 2802 case 99: | |
| 2803 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2804 case 100: | |
| 2805 return (B(eax) || SH_C0(eax)); | |
| 2806 case 101: | |
| 2807 case 103: | |
| 2808 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2809 case 104: | |
| 2810 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2811 case 105: | |
| 2812 case 106: | |
| 2813 case 107: | |
| 2814 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2815 case 108: | |
| 2816 return (DH_CG(eax)); | |
| 2817 case 109: | |
| 2818 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2819 case 110: | |
| 2820 return (D0(eax) || EX(eax)); | |
| 2821 case 111: | |
| 2822 return (CG(eax)); | |
| 2823 case 112: | |
| 2824 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2825 case 113: | |
| 2826 return (eax == 0x20fc0); | |
| 2827 case 114: | |
| 2828 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 2829 case 115: | |
| 2830 return (SH_E0(eax) || JH_E1(eax)); | |
| 2831 case 116: | |
| 2832 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 2833 case 117: | |
| 2834 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 2835 case 118: | |
| 2836 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || | |
| 2837 JH_E6(eax)); | |
| 2838 case 121: | |
| 2839 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 2840 case 122: | |
|
6691
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6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2841 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); |
| 0 | 2842 case 123: |
| 2843 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); | |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
2844 case 131: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2845 return (cpi->cpi_family < 0x10); |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2846 case 6336786: |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2847 /* |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2848 * Test for AdvPowerMgmtInfo.TscPStateInvariant |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2849 * if this is a K8 family or newer processor |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2850 */ |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2851 if (CPI_FAMILY(cpi) == 0xf) { |
| 1228 | 2852 struct cpuid_regs regs; |
| 2853 regs.cp_eax = 0x80000007; | |
| 2854 (void) __cpuid_insn(®s); | |
| 2855 return (!(regs.cp_edx & 0x100)); | |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2856 } |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2857 return (0); |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2858 case 6323525: |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2859 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2860 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2861 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2862 case 6671130: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2863 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2864 * check for processors (pre-Shanghai) that do not provide |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2865 * optimal management of 1gb ptes in its tlb. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2866 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2867 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2868 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2869 case 298: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2870 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2871 DR_B2(eax) || RB_C0(eax)); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2872 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2873 default: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2874 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2875 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2876 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2877 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2878 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2879 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2880 * Determine if specified erratum is present via OSVW (OS Visible Workaround). |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2881 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2882 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2883 int |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2884 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2885 { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2886 struct cpuid_info *cpi; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2887 uint_t osvwid; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2888 static int osvwfeature = -1; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2889 uint64_t osvwlength; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2890 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2891 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2892 cpi = cpu->cpu_m.mcpu_cpi; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2893 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2894 /* confirm OSVW supported */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2895 if (osvwfeature == -1) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2896 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2897 } else { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2898 /* assert that osvw feature setting is consistent on all cpus */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2899 ASSERT(osvwfeature == |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2900 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2901 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2902 if (!osvwfeature) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2903 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2904 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2905 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2906 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2907 switch (erratum) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2908 case 298: /* osvwid is 0 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2909 osvwid = 0; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2910 if (osvwlength <= (uint64_t)osvwid) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2911 /* osvwid 0 is unknown */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2912 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2913 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2914 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2915 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2916 * Check the OSVW STATUS MSR to determine the state |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2917 * of the erratum where: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2918 * 0 - fixed by HW |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2919 * 1 - BIOS has applied the workaround when BIOS |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2920 * workaround is available. (Or for other errata, |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2921 * OS workaround is required.) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2922 * For a value of 1, caller will confirm that the |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2923 * erratum 298 workaround has indeed been applied by BIOS. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2924 * |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2925 * A 1 may be set in cpus that have a HW fix |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2926 * in a mixed cpu system. Regarding erratum 298: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2927 * In a multiprocessor platform, the workaround above |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2928 * should be applied to all processors regardless of |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2929 * silicon revision when an affected processor is |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2930 * present. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2931 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2932 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2933 return (rdmsr(MSR_AMD_OSVW_STATUS + |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2934 (osvwid / OSVW_ID_CNT_PER_MSR)) & |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2935 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2936 |
| 0 | 2937 default: |
| 2938 return (-1); | |
| 2939 } | |
| 2940 } | |
| 2941 | |
| 2942 static const char assoc_str[] = "associativity"; | |
| 2943 static const char line_str[] = "line-size"; | |
| 2944 static const char size_str[] = "size"; | |
| 2945 | |
| 2946 static void | |
| 2947 add_cache_prop(dev_info_t *devi, const char *label, const char *type, | |
| 2948 uint32_t val) | |
| 2949 { | |
| 2950 char buf[128]; | |
| 2951 | |
| 2952 /* | |
| 2953 * ndi_prop_update_int() is used because it is desirable for | |
| 2954 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. | |
| 2955 */ | |
| 2956 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) | |
| 2957 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); | |
| 2958 } | |
| 2959 | |
| 2960 /* | |
| 2961 * Intel-style cache/tlb description | |
| 2962 * | |
| 2963 * Standard cpuid level 2 gives a randomly ordered | |
| 2964 * selection of tags that index into a table that describes | |
| 2965 * cache and tlb properties. | |
| 2966 */ | |
| 2967 | |
| 2968 static const char l1_icache_str[] = "l1-icache"; | |
| 2969 static const char l1_dcache_str[] = "l1-dcache"; | |
| 2970 static const char l2_cache_str[] = "l2-cache"; | |
| 3446 | 2971 static const char l3_cache_str[] = "l3-cache"; |
| 0 | 2972 static const char itlb4k_str[] = "itlb-4K"; |
| 2973 static const char dtlb4k_str[] = "dtlb-4K"; | |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2974 static const char itlb2M_str[] = "itlb-2M"; |
| 0 | 2975 static const char itlb4M_str[] = "itlb-4M"; |
| 2976 static const char dtlb4M_str[] = "dtlb-4M"; | |
|
6334
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
2977 static const char dtlb24_str[] = "dtlb0-2M-4M"; |
| 0 | 2978 static const char itlb424_str[] = "itlb-4K-2M-4M"; |
|
6334
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
2979 static const char itlb24_str[] = "itlb-2M-4M"; |
| 0 | 2980 static const char dtlb44_str[] = "dtlb-4K-4M"; |
| 2981 static const char sl1_dcache_str[] = "sectored-l1-dcache"; | |
| 2982 static const char sl2_cache_str[] = "sectored-l2-cache"; | |
| 2983 static const char itrace_str[] = "itrace-cache"; | |
| 2984 static const char sl3_cache_str[] = "sectored-l3-cache"; | |
|
6334
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
2985 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; |
| 0 | 2986 |
| 2987 static const struct cachetab { | |
| 2988 uint8_t ct_code; | |
| 2989 uint8_t ct_assoc; | |
| 2990 uint16_t ct_line_size; | |
| 2991 size_t ct_size; | |
| 2992 const char *ct_label; | |
| 2993 } intel_ctab[] = { | |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2994 /* |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2995 * maintain descending order! |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2996 * |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2997 * Codes ignored - Reason |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2998 * ---------------------- |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
2999 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3000 * f0H/f1H - Currently we do not interpret prefetch size by design |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3001 */ |
|
6334
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3002 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, |
|
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3003 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, |
|
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3004 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, |
|
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3005 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, |
|
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3006 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, |
|
950d3f34a725
6662206 Add new CPUID.2 descriptors for upcoming Intel processor
ksadhukh
parents:
6317
diff
changeset
|
3007 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, |
|
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|
3008 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, |
|
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|
3009 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, |
|
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|
3010 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, |
|
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|
3011 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, |
|
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|
3012 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, |
|
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|
3013 { 0xd0, 4, 64, 512*1024, l3_cache_str}, |
|
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|
3014 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, |
|
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6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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|
3015 { 0xc0, 4, 0, 8, dtlb44_str }, |
|
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6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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diff
changeset
|
3016 { 0xba, 4, 0, 64, dtlb4k_str }, |
| 3446 | 3017 { 0xb4, 4, 0, 256, dtlb4k_str }, |
| 0 | 3018 { 0xb3, 4, 0, 128, dtlb4k_str }, |
|
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|
3019 { 0xb2, 4, 0, 64, itlb4k_str }, |
| 0 | 3020 { 0xb0, 4, 0, 128, itlb4k_str }, |
| 3021 { 0x87, 8, 64, 1024*1024, l2_cache_str}, | |
| 3022 { 0x86, 4, 64, 512*1024, l2_cache_str}, | |
| 3023 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, | |
| 3024 { 0x84, 8, 32, 1024*1024, l2_cache_str}, | |
| 3025 { 0x83, 8, 32, 512*1024, l2_cache_str}, | |
| 3026 { 0x82, 8, 32, 256*1024, l2_cache_str}, | |
|
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changeset
|
3027 { 0x80, 8, 64, 512*1024, l2_cache_str}, |
| 0 | 3028 { 0x7f, 2, 64, 512*1024, l2_cache_str}, |
| 3029 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, | |
| 3030 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, | |
| 3031 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, | |
| 3032 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, | |
| 3033 { 0x79, 8, 64, 128*1024, sl2_cache_str}, | |
| 3034 { 0x78, 8, 64, 1024*1024, l2_cache_str}, | |
| 3446 | 3035 { 0x73, 8, 0, 64*1024, itrace_str}, |
| 0 | 3036 { 0x72, 8, 0, 32*1024, itrace_str}, |
| 3037 { 0x71, 8, 0, 16*1024, itrace_str}, | |
| 3038 { 0x70, 8, 0, 12*1024, itrace_str}, | |
| 3039 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, | |
| 3040 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, | |
| 3041 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, | |
| 3042 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, | |
| 3043 { 0x5d, 0, 0, 256, dtlb44_str}, | |
| 3044 { 0x5c, 0, 0, 128, dtlb44_str}, | |
| 3045 { 0x5b, 0, 0, 64, dtlb44_str}, | |
|
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|
3046 { 0x5a, 4, 0, 32, dtlb24_str}, |
|
6964
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|
3047 { 0x59, 0, 0, 16, dtlb4k_str}, |
|
3eb8a0c8b90a
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|
3048 { 0x57, 4, 0, 16, dtlb4k_str}, |
|
3eb8a0c8b90a
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|
3049 { 0x56, 4, 0, 16, dtlb4M_str}, |
|
6334
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|
3050 { 0x55, 0, 0, 7, itlb24_str}, |
| 0 | 3051 { 0x52, 0, 0, 256, itlb424_str}, |
| 3052 { 0x51, 0, 0, 128, itlb424_str}, | |
| 3053 { 0x50, 0, 0, 64, itlb424_str}, | |
|
6964
3eb8a0c8b90a
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6691
diff
changeset
|
3054 { 0x4f, 0, 0, 32, itlb4k_str}, |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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6691
diff
changeset
|
3055 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, |
| 3446 | 3056 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, |
| 3057 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, | |
| 3058 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, | |
| 3059 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, | |
| 3060 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, | |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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6691
diff
changeset
|
3061 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, |
| 3446 | 3062 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, |
| 3063 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, | |
| 0 | 3064 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, |
| 3065 { 0x44, 4, 32, 1024*1024, l2_cache_str}, | |
| 3066 { 0x43, 4, 32, 512*1024, l2_cache_str}, | |
| 3067 { 0x42, 4, 32, 256*1024, l2_cache_str}, | |
| 3068 { 0x41, 4, 32, 128*1024, l2_cache_str}, | |
| 3446 | 3069 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, |
| 3070 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, | |
| 0 | 3071 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, |
| 3072 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, | |
| 3446 | 3073 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, |
| 0 | 3074 { 0x39, 4, 64, 128*1024, sl2_cache_str}, |
| 3075 { 0x30, 8, 64, 32*1024, l1_icache_str}, | |
| 3076 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, | |
| 3077 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, | |
| 3078 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, | |
| 3079 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, | |
| 3080 { 0x22, 4, 64, 512*1024, sl3_cache_str}, | |
|
6964
3eb8a0c8b90a
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6691
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|
3081 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, |
|
6334
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|
3082 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, |
| 0 | 3083 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, |
| 3446 | 3084 { 0x0b, 4, 0, 4, itlb4M_str}, |
| 0 | 3085 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, |
| 3086 { 0x08, 4, 32, 16*1024, l1_icache_str}, | |
| 3087 { 0x06, 4, 32, 8*1024, l1_icache_str}, | |
|
6964
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changeset
|
3088 { 0x05, 4, 0, 32, dtlb4M_str}, |
| 0 | 3089 { 0x04, 4, 0, 8, dtlb4M_str}, |
| 3090 { 0x03, 4, 0, 64, dtlb4k_str}, | |
| 3091 { 0x02, 4, 0, 2, itlb4M_str}, | |
| 3092 { 0x01, 4, 0, 32, itlb4k_str}, | |
| 3093 { 0 } | |
| 3094 }; | |
| 3095 | |
| 3096 static const struct cachetab cyrix_ctab[] = { | |
| 3097 { 0x70, 4, 0, 32, "tlb-4K" }, | |
| 3098 { 0x80, 4, 16, 16*1024, "l1-cache" }, | |
| 3099 { 0 } | |
| 3100 }; | |
| 3101 | |
| 3102 /* | |
| 3103 * Search a cache table for a matching entry | |
| 3104 */ | |
| 3105 static const struct cachetab * | |
| 3106 find_cacheent(const struct cachetab *ct, uint_t code) | |
| 3107 { | |
| 3108 if (code != 0) { | |
| 3109 for (; ct->ct_code != 0; ct++) | |
| 3110 if (ct->ct_code <= code) | |
| 3111 break; | |
| 3112 if (ct->ct_code == code) | |
| 3113 return (ct); | |
| 3114 } | |
| 3115 return (NULL); | |
| 3116 } | |
| 3117 | |
| 3118 /* | |
|
5438
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3119 * Populate cachetab entry with L2 or L3 cache-information using |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3120 * cpuid function 4. This function is called from intel_walk_cacheinfo() |
|
41d8edfa90d7
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|
3121 * when descriptor 0x49 is encountered. It returns 0 if no such cache |
|
41d8edfa90d7
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|
3122 * information is found. |
|
41d8edfa90d7
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|
3123 */ |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3124 static int |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3125 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) |
|
41d8edfa90d7
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|
3126 { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3127 uint32_t level, i; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3128 int ret = 0; |
|
41d8edfa90d7
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|
3129 |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3130 for (i = 0; i < cpi->cpi_std_4_size; i++) { |
|
41d8edfa90d7
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|
3131 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); |
|
41d8edfa90d7
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|
3132 |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3133 if (level == 2 || level == 3) { |
|
41d8edfa90d7
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diff
changeset
|
3134 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3135 ct->ct_line_size = |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3136 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; |
|
41d8edfa90d7
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ksadhukh
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|
3137 ct->ct_size = ct->ct_assoc * |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3138 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3139 ct->ct_line_size * |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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diff
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|
3140 (cpi->cpi_std_4[i]->cp_ecx + 1); |
|
41d8edfa90d7
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|
3141 |
|
41d8edfa90d7
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changeset
|
3142 if (level == 2) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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changeset
|
3143 ct->ct_label = l2_cache_str; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3144 } else if (level == 3) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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changeset
|
3145 ct->ct_label = l3_cache_str; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3146 } |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3147 ret = 1; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3148 } |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3149 } |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3150 |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3151 return (ret); |
|
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|
3152 } |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3153 |
|
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|
3154 /* |
| 0 | 3155 * Walk the cacheinfo descriptor, applying 'func' to every valid element |
| 3156 * The walk is terminated if the walker returns non-zero. | |
| 3157 */ | |
| 3158 static void | |
| 3159 intel_walk_cacheinfo(struct cpuid_info *cpi, | |
| 3160 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 3161 { | |
| 3162 const struct cachetab *ct; | |
|
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|
3163 struct cachetab des_49_ct, des_b1_ct; |
| 0 | 3164 uint8_t *dp; |
| 3165 int i; | |
| 3166 | |
| 3167 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 3168 return; | |
|
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|
3169 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { |
|
2ebe22df4dfc
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|
3170 /* |
|
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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|
3171 * For overloaded descriptor 0x49 we use cpuid function 4 |
|
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|
3172 * if supported by the current processor, to create |
|
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6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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|
3173 * cache information. |
|
6964
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|
3174 * For overloaded descriptor 0xb1 we use X86_PAE flag |
|
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6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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changeset
|
3175 * to disambiguate the cache information. |
|
4797
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|
3176 */ |
|
5438
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|
3177 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && |
|
41d8edfa90d7
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changeset
|
3178 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { |
|
41d8edfa90d7
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|
3179 ct = &des_49_ct; |
|
6964
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|
3180 } else if (*dp == 0xb1) { |
|
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diff
changeset
|
3181 des_b1_ct.ct_code = 0xb1; |
|
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changeset
|
3182 des_b1_ct.ct_assoc = 4; |
|
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changeset
|
3183 des_b1_ct.ct_line_size = 0; |
|
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6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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diff
changeset
|
3184 if (x86_feature & X86_PAE) { |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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changeset
|
3185 des_b1_ct.ct_size = 8; |
|
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6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
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changeset
|
3186 des_b1_ct.ct_label = itlb2M_str; |
|
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changeset
|
3187 } else { |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3188 des_b1_ct.ct_size = 4; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3189 des_b1_ct.ct_label = itlb4M_str; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3190 } |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3191 ct = &des_b1_ct; |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3192 } else { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3193 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3194 continue; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3195 } |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3196 } |
|
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3197 |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3198 if (func(arg, ct) != 0) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3199 break; |
| 0 | 3200 } |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3201 } |
| 0 | 3202 } |
| 3203 | |
| 3204 /* | |
| 3205 * (Like the Intel one, except for Cyrix CPUs) | |
| 3206 */ | |
| 3207 static void | |
| 3208 cyrix_walk_cacheinfo(struct cpuid_info *cpi, | |
| 3209 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 3210 { | |
| 3211 const struct cachetab *ct; | |
| 3212 uint8_t *dp; | |
| 3213 int i; | |
| 3214 | |
| 3215 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 3216 return; | |
| 3217 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { | |
| 3218 /* | |
| 3219 * Search Cyrix-specific descriptor table first .. | |
| 3220 */ | |
| 3221 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { | |
| 3222 if (func(arg, ct) != 0) | |
| 3223 break; | |
| 3224 continue; | |
| 3225 } | |
| 3226 /* | |
| 3227 * .. else fall back to the Intel one | |
| 3228 */ | |
| 3229 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { | |
| 3230 if (func(arg, ct) != 0) | |
| 3231 break; | |
| 3232 continue; | |
| 3233 } | |
| 3234 } | |
| 3235 } | |
| 3236 | |
| 3237 /* | |
| 3238 * A cacheinfo walker that adds associativity, line-size, and size properties | |
| 3239 * to the devinfo node it is passed as an argument. | |
| 3240 */ | |
| 3241 static int | |
| 3242 add_cacheent_props(void *arg, const struct cachetab *ct) | |
| 3243 { | |
| 3244 dev_info_t *devi = arg; | |
| 3245 | |
| 3246 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); | |
| 3247 if (ct->ct_line_size != 0) | |
| 3248 add_cache_prop(devi, ct->ct_label, line_str, | |
| 3249 ct->ct_line_size); | |
| 3250 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); | |
| 3251 return (0); | |
| 3252 } | |
| 3253 | |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3254 |
| 0 | 3255 static const char fully_assoc[] = "fully-associative?"; |
| 3256 | |
| 3257 /* | |
| 3258 * AMD style cache/tlb description | |
| 3259 * | |
| 3260 * Extended functions 5 and 6 directly describe properties of | |
| 3261 * tlbs and various cache levels. | |
| 3262 */ | |
| 3263 static void | |
| 3264 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 3265 { | |
| 3266 switch (assoc) { | |
| 3267 case 0: /* reserved; ignore */ | |
| 3268 break; | |
| 3269 default: | |
| 3270 add_cache_prop(devi, label, assoc_str, assoc); | |
| 3271 break; | |
| 3272 case 0xff: | |
| 3273 add_cache_prop(devi, label, fully_assoc, 1); | |
| 3274 break; | |
| 3275 } | |
| 3276 } | |
| 3277 | |
| 3278 static void | |
| 3279 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 3280 { | |
| 3281 if (size == 0) | |
| 3282 return; | |
| 3283 add_cache_prop(devi, label, size_str, size); | |
| 3284 add_amd_assoc(devi, label, assoc); | |
| 3285 } | |
| 3286 | |
| 3287 static void | |
| 3288 add_amd_cache(dev_info_t *devi, const char *label, | |
| 3289 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 3290 { | |
| 3291 if (size == 0 || line_size == 0) | |
| 3292 return; | |
| 3293 add_amd_assoc(devi, label, assoc); | |
| 3294 /* | |
| 3295 * Most AMD parts have a sectored cache. Multiple cache lines are | |
| 3296 * associated with each tag. A sector consists of all cache lines | |
| 3297 * associated with a tag. For example, the AMD K6-III has a sector | |
| 3298 * size of 2 cache lines per tag. | |
| 3299 */ | |
| 3300 if (lines_per_tag != 0) | |
| 3301 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 3302 add_cache_prop(devi, label, line_str, line_size); | |
| 3303 add_cache_prop(devi, label, size_str, size * 1024); | |
| 3304 } | |
| 3305 | |
| 3306 static void | |
| 3307 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 3308 { | |
| 3309 switch (assoc) { | |
| 3310 case 0: /* off */ | |
| 3311 break; | |
| 3312 case 1: | |
| 3313 case 2: | |
| 3314 case 4: | |
| 3315 add_cache_prop(devi, label, assoc_str, assoc); | |
| 3316 break; | |
| 3317 case 6: | |
| 3318 add_cache_prop(devi, label, assoc_str, 8); | |
| 3319 break; | |
| 3320 case 8: | |
| 3321 add_cache_prop(devi, label, assoc_str, 16); | |
| 3322 break; | |
| 3323 case 0xf: | |
| 3324 add_cache_prop(devi, label, fully_assoc, 1); | |
| 3325 break; | |
| 3326 default: /* reserved; ignore */ | |
| 3327 break; | |
| 3328 } | |
| 3329 } | |
| 3330 | |
| 3331 static void | |
| 3332 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 3333 { | |
| 3334 if (size == 0 || assoc == 0) | |
| 3335 return; | |
| 3336 add_amd_l2_assoc(devi, label, assoc); | |
| 3337 add_cache_prop(devi, label, size_str, size); | |
| 3338 } | |
| 3339 | |
| 3340 static void | |
| 3341 add_amd_l2_cache(dev_info_t *devi, const char *label, | |
| 3342 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 3343 { | |
| 3344 if (size == 0 || assoc == 0 || line_size == 0) | |
| 3345 return; | |
| 3346 add_amd_l2_assoc(devi, label, assoc); | |
| 3347 if (lines_per_tag != 0) | |
| 3348 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 3349 add_cache_prop(devi, label, line_str, line_size); | |
| 3350 add_cache_prop(devi, label, size_str, size * 1024); | |
| 3351 } | |
| 3352 | |
| 3353 static void | |
| 3354 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) | |
| 3355 { | |
| 1228 | 3356 struct cpuid_regs *cp; |
| 0 | 3357 |
| 3358 if (cpi->cpi_xmaxeax < 0x80000005) | |
| 3359 return; | |
| 3360 cp = &cpi->cpi_extd[5]; | |
| 3361 | |
| 3362 /* | |
| 3363 * 4M/2M L1 TLB configuration | |
| 3364 * | |
| 3365 * We report the size for 2M pages because AMD uses two | |
| 3366 * TLB entries for one 4M page. | |
| 3367 */ | |
| 3368 add_amd_tlb(devi, "dtlb-2M", | |
| 3369 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); | |
| 3370 add_amd_tlb(devi, "itlb-2M", | |
| 3371 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); | |
| 3372 | |
| 3373 /* | |
| 3374 * 4K L1 TLB configuration | |
| 3375 */ | |
| 3376 | |
| 3377 switch (cpi->cpi_vendor) { | |
| 3378 uint_t nentries; | |
| 3379 case X86_VENDOR_TM: | |
| 3380 if (cpi->cpi_family >= 5) { | |
| 3381 /* | |
| 3382 * Crusoe processors have 256 TLB entries, but | |
| 3383 * cpuid data format constrains them to only | |
| 3384 * reporting 255 of them. | |
| 3385 */ | |
| 3386 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) | |
| 3387 nentries = 256; | |
| 3388 /* | |
| 3389 * Crusoe processors also have a unified TLB | |
| 3390 */ | |
| 3391 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), | |
| 3392 nentries); | |
| 3393 break; | |
| 3394 } | |
| 3395 /*FALLTHROUGH*/ | |
| 3396 default: | |
| 3397 add_amd_tlb(devi, itlb4k_str, | |
| 3398 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); | |
| 3399 add_amd_tlb(devi, dtlb4k_str, | |
| 3400 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); | |
| 3401 break; | |
| 3402 } | |
| 3403 | |
| 3404 /* | |
| 3405 * data L1 cache configuration | |
| 3406 */ | |
| 3407 | |
| 3408 add_amd_cache(devi, l1_dcache_str, | |
| 3409 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), | |
| 3410 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 3411 | |
| 3412 /* | |
| 3413 * code L1 cache configuration | |
| 3414 */ | |
| 3415 | |
| 3416 add_amd_cache(devi, l1_icache_str, | |
| 3417 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), | |
| 3418 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); | |
| 3419 | |
| 3420 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 3421 return; | |
| 3422 cp = &cpi->cpi_extd[6]; | |
| 3423 | |
| 3424 /* Check for a unified L2 TLB for large pages */ | |
| 3425 | |
| 3426 if (BITX(cp->cp_eax, 31, 16) == 0) | |
| 3427 add_amd_l2_tlb(devi, "l2-tlb-2M", | |
| 3428 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3429 else { | |
| 3430 add_amd_l2_tlb(devi, "l2-dtlb-2M", | |
| 3431 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 3432 add_amd_l2_tlb(devi, "l2-itlb-2M", | |
| 3433 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3434 } | |
| 3435 | |
| 3436 /* Check for a unified L2 TLB for 4K pages */ | |
| 3437 | |
| 3438 if (BITX(cp->cp_ebx, 31, 16) == 0) { | |
| 3439 add_amd_l2_tlb(devi, "l2-tlb-4K", | |
| 3440 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3441 } else { | |
| 3442 add_amd_l2_tlb(devi, "l2-dtlb-4K", | |
| 3443 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 3444 add_amd_l2_tlb(devi, "l2-itlb-4K", | |
| 3445 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3446 } | |
| 3447 | |
| 3448 add_amd_l2_cache(devi, l2_cache_str, | |
| 3449 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), | |
| 3450 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 3451 } | |
| 3452 | |
| 3453 /* | |
| 3454 * There are two basic ways that the x86 world describes it cache | |
| 3455 * and tlb architecture - Intel's way and AMD's way. | |
| 3456 * | |
| 3457 * Return which flavor of cache architecture we should use | |
| 3458 */ | |
| 3459 static int | |
| 3460 x86_which_cacheinfo(struct cpuid_info *cpi) | |
| 3461 { | |
| 3462 switch (cpi->cpi_vendor) { | |
| 3463 case X86_VENDOR_Intel: | |
| 3464 if (cpi->cpi_maxeax >= 2) | |
| 3465 return (X86_VENDOR_Intel); | |
| 3466 break; | |
| 3467 case X86_VENDOR_AMD: | |
| 3468 /* | |
| 3469 * The K5 model 1 was the first part from AMD that reported | |
| 3470 * cache sizes via extended cpuid functions. | |
| 3471 */ | |
| 3472 if (cpi->cpi_family > 5 || | |
| 3473 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 3474 return (X86_VENDOR_AMD); | |
| 3475 break; | |
| 3476 case X86_VENDOR_TM: | |
| 3477 if (cpi->cpi_family >= 5) | |
| 3478 return (X86_VENDOR_AMD); | |
| 3479 /*FALLTHROUGH*/ | |
| 3480 default: | |
| 3481 /* | |
| 3482 * If they have extended CPU data for 0x80000005 | |
| 3483 * then we assume they have AMD-format cache | |
| 3484 * information. | |
| 3485 * | |
| 3486 * If not, and the vendor happens to be Cyrix, | |
| 3487 * then try our-Cyrix specific handler. | |
| 3488 * | |
| 3489 * If we're not Cyrix, then assume we're using Intel's | |
| 3490 * table-driven format instead. | |
| 3491 */ | |
| 3492 if (cpi->cpi_xmaxeax >= 0x80000005) | |
| 3493 return (X86_VENDOR_AMD); | |
| 3494 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) | |
| 3495 return (X86_VENDOR_Cyrix); | |
| 3496 else if (cpi->cpi_maxeax >= 2) | |
| 3497 return (X86_VENDOR_Intel); | |
| 3498 break; | |
| 3499 } | |
| 3500 return (-1); | |
| 3501 } | |
| 3502 | |
| 3503 void | |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3504 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3505 struct cpuid_info *cpi) |
| 0 | 3506 { |
| 3507 dev_info_t *cpu_devi; | |
| 3508 int create; | |
| 3509 | |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3510 cpu_devi = (dev_info_t *)dip; |
| 0 | 3511 |
| 3512 /* device_type */ | |
| 3513 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 3514 "device_type", "cpu"); | |
| 3515 | |
| 3516 /* reg */ | |
| 3517 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3518 "reg", cpu_id); | |
| 3519 | |
| 3520 /* cpu-mhz, and clock-frequency */ | |
| 3521 if (cpu_freq > 0) { | |
| 3522 long long mul; | |
| 3523 | |
| 3524 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3525 "cpu-mhz", cpu_freq); | |
| 3526 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) | |
| 3527 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3528 "clock-frequency", (int)mul); | |
| 3529 } | |
| 3530 | |
| 3531 if ((x86_feature & X86_CPUID) == 0) { | |
| 3532 return; | |
| 3533 } | |
| 3534 | |
| 3535 /* vendor-id */ | |
| 3536 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3537 "vendor-id", cpi->cpi_vendorstr); |
| 0 | 3538 |
| 3539 if (cpi->cpi_maxeax == 0) { | |
| 3540 return; | |
| 3541 } | |
| 3542 | |
| 3543 /* | |
| 3544 * family, model, and step | |
| 3545 */ | |
| 3546 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3547 "family", CPI_FAMILY(cpi)); |
| 0 | 3548 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3549 "cpu-model", CPI_MODEL(cpi)); |
| 0 | 3550 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3551 "stepping-id", CPI_STEP(cpi)); |
| 0 | 3552 |
| 3553 /* type */ | |
| 3554 switch (cpi->cpi_vendor) { | |
| 3555 case X86_VENDOR_Intel: | |
| 3556 create = 1; | |
| 3557 break; | |
| 3558 default: | |
| 3559 create = 0; | |
| 3560 break; | |
| 3561 } | |
| 3562 if (create) | |
| 3563 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3564 "type", CPI_TYPE(cpi)); |
| 0 | 3565 |
| 3566 /* ext-family */ | |
| 3567 switch (cpi->cpi_vendor) { | |
| 3568 case X86_VENDOR_Intel: | |
| 3569 case X86_VENDOR_AMD: | |
| 3570 create = cpi->cpi_family >= 0xf; | |
| 3571 break; | |
| 3572 default: | |
| 3573 create = 0; | |
| 3574 break; | |
| 3575 } | |
| 3576 if (create) | |
| 3577 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3578 "ext-family", CPI_FAMILY_XTD(cpi)); | |
| 3579 | |
| 3580 /* ext-model */ | |
| 3581 switch (cpi->cpi_vendor) { | |
| 3582 case X86_VENDOR_Intel: | |
|
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
3583 create = IS_EXTENDED_MODEL_INTEL(cpi); |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
3584 break; |
| 0 | 3585 case X86_VENDOR_AMD: |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3586 create = CPI_FAMILY(cpi) == 0xf; |
| 0 | 3587 break; |
| 3588 default: | |
| 3589 create = 0; | |
| 3590 break; | |
| 3591 } | |
| 3592 if (create) | |
| 3593 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3594 "ext-model", CPI_MODEL_XTD(cpi)); |
| 0 | 3595 |
| 3596 /* generation */ | |
| 3597 switch (cpi->cpi_vendor) { | |
| 3598 case X86_VENDOR_AMD: | |
| 3599 /* | |
| 3600 * AMD K5 model 1 was the first part to support this | |
| 3601 */ | |
| 3602 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 3603 break; | |
| 3604 default: | |
| 3605 create = 0; | |
| 3606 break; | |
| 3607 } | |
| 3608 if (create) | |
| 3609 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3610 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); | |
| 3611 | |
| 3612 /* brand-id */ | |
| 3613 switch (cpi->cpi_vendor) { | |
| 3614 case X86_VENDOR_Intel: | |
| 3615 /* | |
| 3616 * brand id first appeared on Pentium III Xeon model 8, | |
| 3617 * and Celeron model 8 processors and Opteron | |
| 3618 */ | |
| 3619 create = cpi->cpi_family > 6 || | |
| 3620 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); | |
| 3621 break; | |
| 3622 case X86_VENDOR_AMD: | |
| 3623 create = cpi->cpi_family >= 0xf; | |
| 3624 break; | |
| 3625 default: | |
| 3626 create = 0; | |
| 3627 break; | |
| 3628 } | |
| 3629 if (create && cpi->cpi_brandid != 0) { | |
| 3630 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3631 "brand-id", cpi->cpi_brandid); | |
| 3632 } | |
| 3633 | |
| 3634 /* chunks, and apic-id */ | |
| 3635 switch (cpi->cpi_vendor) { | |
| 3636 /* | |
| 3637 * first available on Pentium IV and Opteron (K8) | |
| 3638 */ | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3639 case X86_VENDOR_Intel: |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3640 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3641 break; |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3642 case X86_VENDOR_AMD: |
| 0 | 3643 create = cpi->cpi_family >= 0xf; |
| 3644 break; | |
| 3645 default: | |
| 3646 create = 0; | |
| 3647 break; | |
| 3648 } | |
| 3649 if (create) { | |
| 3650 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3651 "chunks", CPI_CHUNKS(cpi)); |
| 0 | 3652 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
3653 "apic-id", cpi->cpi_apicid); |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3654 if (cpi->cpi_chipid >= 0) { |
| 0 | 3655 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
| 3656 "chip#", cpi->cpi_chipid); | |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3657 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3658 "clog#", cpi->cpi_clogid); |
|
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3659 } |
| 0 | 3660 } |
| 3661 | |
| 3662 /* cpuid-features */ | |
| 3663 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3664 "cpuid-features", CPI_FEATURES_EDX(cpi)); | |
| 3665 | |
| 3666 | |
| 3667 /* cpuid-features-ecx */ | |
| 3668 switch (cpi->cpi_vendor) { | |
| 3669 case X86_VENDOR_Intel: | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3670 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
| 0 | 3671 break; |
| 3672 default: | |
| 3673 create = 0; | |
| 3674 break; | |
| 3675 } | |
| 3676 if (create) | |
| 3677 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3678 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); | |
| 3679 | |
| 3680 /* ext-cpuid-features */ | |
| 3681 switch (cpi->cpi_vendor) { | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3682 case X86_VENDOR_Intel: |
| 0 | 3683 case X86_VENDOR_AMD: |
| 3684 case X86_VENDOR_Cyrix: | |
| 3685 case X86_VENDOR_TM: | |
| 3686 case X86_VENDOR_Centaur: | |
| 3687 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 3688 break; | |
| 3689 default: | |
| 3690 create = 0; | |
| 3691 break; | |
| 3692 } | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3693 if (create) { |
| 0 | 3694 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3695 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3696 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3697 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3698 } |
| 0 | 3699 |
| 3700 /* | |
| 3701 * Brand String first appeared in Intel Pentium IV, AMD K5 | |
| 3702 * model 1, and Cyrix GXm. On earlier models we try and | |
| 3703 * simulate something similar .. so this string should always | |
| 3704 * same -something- about the processor, however lame. | |
| 3705 */ | |
| 3706 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 3707 "brand-string", cpi->cpi_brandstr); | |
| 3708 | |
| 3709 /* | |
| 3710 * Finally, cache and tlb information | |
| 3711 */ | |
| 3712 switch (x86_which_cacheinfo(cpi)) { | |
| 3713 case X86_VENDOR_Intel: | |
| 3714 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 3715 break; | |
| 3716 case X86_VENDOR_Cyrix: | |
| 3717 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 3718 break; | |
| 3719 case X86_VENDOR_AMD: | |
| 3720 amd_cache_info(cpi, cpu_devi); | |
| 3721 break; | |
| 3722 default: | |
| 3723 break; | |
| 3724 } | |
| 3725 } | |
| 3726 | |
| 3727 struct l2info { | |
| 3728 int *l2i_csz; | |
| 3729 int *l2i_lsz; | |
| 3730 int *l2i_assoc; | |
| 3731 int l2i_ret; | |
| 3732 }; | |
| 3733 | |
| 3734 /* | |
| 3735 * A cacheinfo walker that fetches the size, line-size and associativity | |
| 3736 * of the L2 cache | |
| 3737 */ | |
| 3738 static int | |
| 3739 intel_l2cinfo(void *arg, const struct cachetab *ct) | |
| 3740 { | |
| 3741 struct l2info *l2i = arg; | |
| 3742 int *ip; | |
| 3743 | |
| 3744 if (ct->ct_label != l2_cache_str && | |
| 3745 ct->ct_label != sl2_cache_str) | |
| 3746 return (0); /* not an L2 -- keep walking */ | |
| 3747 | |
| 3748 if ((ip = l2i->l2i_csz) != NULL) | |
| 3749 *ip = ct->ct_size; | |
| 3750 if ((ip = l2i->l2i_lsz) != NULL) | |
| 3751 *ip = ct->ct_line_size; | |
| 3752 if ((ip = l2i->l2i_assoc) != NULL) | |
| 3753 *ip = ct->ct_assoc; | |
| 3754 l2i->l2i_ret = ct->ct_size; | |
| 3755 return (1); /* was an L2 -- terminate walk */ | |
| 3756 } | |
| 3757 | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3758 /* |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3759 * AMD L2/L3 Cache and TLB Associativity Field Definition: |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3760 * |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3761 * Unlike the associativity for the L1 cache and tlb where the 8 bit |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3762 * value is the associativity, the associativity for the L2 cache and |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3763 * tlb is encoded in the following table. The 4 bit L2 value serves as |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3764 * an index into the amd_afd[] array to determine the associativity. |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3765 * -1 is undefined. 0 is fully associative. |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3766 */ |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3767 |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3768 static int amd_afd[] = |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3769 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3770 |
| 0 | 3771 static void |
| 3772 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) | |
| 3773 { | |
| 1228 | 3774 struct cpuid_regs *cp; |
| 0 | 3775 uint_t size, assoc; |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3776 int i; |
| 0 | 3777 int *ip; |
| 3778 | |
| 3779 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 3780 return; | |
| 3781 cp = &cpi->cpi_extd[6]; | |
| 3782 | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3783 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && |
| 0 | 3784 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { |
| 3785 uint_t cachesz = size * 1024; | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3786 assoc = amd_afd[i]; |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3787 |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3788 ASSERT(assoc != -1); |
| 0 | 3789 |
| 3790 if ((ip = l2i->l2i_csz) != NULL) | |
| 3791 *ip = cachesz; | |
| 3792 if ((ip = l2i->l2i_lsz) != NULL) | |
| 3793 *ip = BITX(cp->cp_ecx, 7, 0); | |
| 3794 if ((ip = l2i->l2i_assoc) != NULL) | |
| 3795 *ip = assoc; | |
| 3796 l2i->l2i_ret = cachesz; | |
| 3797 } | |
| 3798 } | |
| 3799 | |
| 3800 int | |
| 3801 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) | |
| 3802 { | |
| 3803 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 3804 struct l2info __l2info, *l2i = &__l2info; | |
| 3805 | |
| 3806 l2i->l2i_csz = csz; | |
| 3807 l2i->l2i_lsz = lsz; | |
| 3808 l2i->l2i_assoc = assoc; | |
| 3809 l2i->l2i_ret = -1; | |
| 3810 | |
| 3811 switch (x86_which_cacheinfo(cpi)) { | |
| 3812 case X86_VENDOR_Intel: | |
| 3813 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 3814 break; | |
| 3815 case X86_VENDOR_Cyrix: | |
| 3816 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 3817 break; | |
| 3818 case X86_VENDOR_AMD: | |
| 3819 amd_l2cacheinfo(cpi, l2i); | |
| 3820 break; | |
| 3821 default: | |
| 3822 break; | |
| 3823 } | |
| 3824 return (l2i->l2i_ret); | |
| 3825 } | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3826 |
| 5084 | 3827 #if !defined(__xpv) |
| 3828 | |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3829 uint32_t * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3830 cpuid_mwait_alloc(cpu_t *cpu) |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3831 { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3832 uint32_t *ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3833 size_t mwait_size; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3834 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3835 ASSERT(cpuid_checkpass(cpu, 2)); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3836 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3837 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3838 if (mwait_size == 0) |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3839 return (NULL); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3840 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3841 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3842 * kmem_alloc() returns cache line size aligned data for mwait_size |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3843 * allocations. mwait_size is currently cache line sized. Neither |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3844 * of these implementation details are guarantied to be true in the |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3845 * future. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3846 * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3847 * First try allocating mwait_size as kmem_alloc() currently returns |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3848 * correctly aligned memory. If kmem_alloc() does not return |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3849 * mwait_size aligned memory, then use mwait_size ROUNDUP. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3850 * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3851 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3852 * decide to free this memory. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3853 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3854 ret = kmem_zalloc(mwait_size, KM_SLEEP); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3855 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3856 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3857 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3858 *ret = MWAIT_RUNNING; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3859 return (ret); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3860 } else { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3861 kmem_free(ret, mwait_size); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3862 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3863 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3864 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3865 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3866 *ret = MWAIT_RUNNING; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3867 return (ret); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3868 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3869 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3870 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3871 void |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3872 cpuid_mwait_free(cpu_t *cpu) |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3873 { |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3874 ASSERT(cpuid_checkpass(cpu, 2)); |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3875 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3876 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3877 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3878 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3879 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3880 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3881 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3882 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3883 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3884 } |
| 5084 | 3885 |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3886 void |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3887 patch_tsc_read(int flag) |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3888 { |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3889 size_t cnt; |
|
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
3890 |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3891 switch (flag) { |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3892 case X86_NO_TSC: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3893 cnt = &_no_rdtsc_end - &_no_rdtsc_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
3894 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3895 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3896 case X86_HAVE_TSCP: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3897 cnt = &_tscp_end - &_tscp_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
3898 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3899 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3900 case X86_TSC_MFENCE: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3901 cnt = &_tsc_mfence_end - &_tsc_mfence_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
3902 (void) memcpy((void *)tsc_read, |
|
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
3903 (void *)&_tsc_mfence_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3904 break; |
|
6642
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
3905 case X86_TSC_LFENCE: |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
3906 cnt = &_tsc_lfence_end - &_tsc_lfence_start; |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
3907 (void) memcpy((void *)tsc_read, |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
3908 (void *)&_tsc_lfence_start, cnt); |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
3909 break; |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3910 default: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3911 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3912 } |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3913 } |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
3914 |
|
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3915 int |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3916 cpuid_deep_cstates_supported(void) |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3917 { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3918 struct cpuid_info *cpi; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3919 struct cpuid_regs regs; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3920 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3921 ASSERT(cpuid_checkpass(CPU, 1)); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3922 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3923 cpi = CPU->cpu_m.mcpu_cpi; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3924 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3925 if (!(x86_feature & X86_CPUID)) |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3926 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3927 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3928 switch (cpi->cpi_vendor) { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3929 case X86_VENDOR_Intel: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3930 if (cpi->cpi_xmaxeax < 0x80000007) |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3931 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3932 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3933 /* |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3934 * TSC run at a constant rate in all ACPI C-states? |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3935 */ |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3936 regs.cp_eax = 0x80000007; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3937 (void) __cpuid_insn(®s); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3938 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3939 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3940 default: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3941 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3942 } |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3943 } |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
3944 |
|
8930
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3945 #endif /* !__xpv */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3946 |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3947 void |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3948 post_startup_cpu_fixups(void) |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3949 { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3950 #ifndef __xpv |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3951 /* |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3952 * Some AMD processors support C1E state. Entering this state will |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3953 * cause the local APIC timer to stop, which we can't deal with at |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3954 * this time. |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3955 */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3956 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3957 on_trap_data_t otd; |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3958 uint64_t reg; |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3959 |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3960 if (!on_trap(&otd, OT_DATA_ACCESS)) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3961 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3962 /* Disable C1E state if it is enabled by BIOS */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3963 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3964 AMD_ACTONCMPHALT_MASK) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3965 reg &= ~(AMD_ACTONCMPHALT_MASK << |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3966 AMD_ACTONCMPHALT_SHIFT); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3967 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3968 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3969 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3970 no_trap(); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3971 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3972 #endif /* !__xpv */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3973 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
3974 |
|
9283
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
3975 /* |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
3976 * Starting with the Westmere processor the local |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
3977 * APIC timer will continue running in all C-states, |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
3978 * including the deepest C-states. |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
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3979 */ |
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3980 int |
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3981 cpuid_arat_supported(void) |
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3982 { |
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3983 struct cpuid_info *cpi; |
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3984 struct cpuid_regs regs; |
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3985 |
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3986 ASSERT(cpuid_checkpass(CPU, 1)); |
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3987 ASSERT(x86_feature & X86_CPUID); |
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3988 |
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3989 cpi = CPU->cpu_m.mcpu_cpi; |
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3990 |
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3991 switch (cpi->cpi_vendor) { |
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3992 case X86_VENDOR_Intel: |
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3993 /* |
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3994 * Always-running Local APIC Timer is |
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3995 * indicated by CPUID.6.EAX[2]. |
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3996 */ |
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3997 if (cpi->cpi_maxeax >= 6) { |
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3998 regs.cp_eax = 6; |
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3999 (void) cpuid_insn(NULL, ®s); |
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4000 return (regs.cp_eax & CPUID_CSTATE_ARAT); |
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4001 } else { |
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4002 return (0); |
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4003 } |
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4004 default: |
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4005 return (0); |
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4006 } |
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4007 } |
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4008 |
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4009 #if defined(__amd64) && !defined(__xpv) |
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4010 /* |
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4011 * Patch in versions of bcopy for high performance Intel Nhm processors |
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4012 * and later... |
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4013 */ |
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4014 void |
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4015 patch_memops(uint_t vendor) |
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4016 { |
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4017 size_t cnt, i; |
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4018 caddr_t to, from; |
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4019 |
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4020 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { |
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4021 cnt = &bcopy_patch_end - &bcopy_patch_start; |
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4022 to = &bcopy_ck_size; |
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4023 from = &bcopy_patch_start; |
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4024 for (i = 0; i < cnt; i++) { |
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4025 *to++ = *from++; |
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4026 } |
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4027 } |
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4028 } |
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4029 #endif /* __amd64 && !__xpv */ |