Mercurial > illumos > illumos-gate
annotate usr/src/uts/i86pc/os/cpuid.c @ 11013:3aa288b66f8e
6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module
6899220 chip_id is not correctly derived on Barcelona, leading to panics and/or wrong CPU topology
author | Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> |
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date | Mon, 09 Nov 2009 15:08:34 -0800 |
parents | 54a1c1cbd683 |
children | dd00b884e84f |
rev | line source |
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0 | 1 /* |
2 * CDDL HEADER START | |
3 * | |
4 * The contents of this file are subject to the terms of the | |
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5 * Common Development and Distribution License (the "License"). |
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6 * You may not use this file except in compliance with the License. |
0 | 7 * |
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
9 * or http://www.opensolaris.org/os/licensing. | |
10 * See the License for the specific language governing permissions | |
11 * and limitations under the License. | |
12 * | |
13 * When distributing Covered Code, include this CDDL HEADER in each | |
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
15 * If applicable, add the following below this CDDL HEADER, with the | |
16 * fields enclosed by brackets "[]" replaced with your own identifying | |
17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
18 * | |
19 * CDDL HEADER END | |
20 */ | |
21 /* | |
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22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. |
0 | 23 * Use is subject to license terms. |
24 */ | |
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25 /* |
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26 * Copyright (c) 2009, Intel Corporation. |
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27 * All rights reserved. |
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28 */ |
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29 /* |
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30 * Portions Copyright 2009 Advanced Micro Devices, Inc. |
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31 */ |
0 | 32 |
33 /* | |
34 * Various routines to handle identification | |
35 * and classification of x86 processors. | |
36 */ | |
37 | |
38 #include <sys/types.h> | |
39 #include <sys/archsystm.h> | |
40 #include <sys/x86_archext.h> | |
41 #include <sys/kmem.h> | |
42 #include <sys/systm.h> | |
43 #include <sys/cmn_err.h> | |
44 #include <sys/sunddi.h> | |
45 #include <sys/sunndi.h> | |
46 #include <sys/cpuvar.h> | |
47 #include <sys/processor.h> | |
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48 #include <sys/sysmacros.h> |
3434 | 49 #include <sys/pg.h> |
0 | 50 #include <sys/fp.h> |
51 #include <sys/controlregs.h> | |
52 #include <sys/auxv_386.h> | |
53 #include <sys/bitmap.h> | |
54 #include <sys/memnode.h> | |
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55 #include <sys/pci_cfgspace.h> |
0 | 56 |
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57 #ifdef __xpv |
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58 #include <sys/hypervisor.h> |
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59 #else |
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60 #include <sys/ontrap.h> |
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61 #endif |
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62 |
0 | 63 /* |
64 * Pass 0 of cpuid feature analysis happens in locore. It contains special code | |
65 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with | |
66 * them accordingly. For most modern processors, feature detection occurs here | |
67 * in pass 1. | |
68 * | |
69 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() | |
70 * for the boot CPU and does the basic analysis that the early kernel needs. | |
71 * x86_feature is set based on the return value of cpuid_pass1() of the boot | |
72 * CPU. | |
73 * | |
74 * Pass 1 includes: | |
75 * | |
76 * o Determining vendor/model/family/stepping and setting x86_type and | |
77 * x86_vendor accordingly. | |
78 * o Processing the feature flags returned by the cpuid instruction while | |
79 * applying any workarounds or tricks for the specific processor. | |
80 * o Mapping the feature flags into Solaris feature bits (X86_*). | |
81 * o Processing extended feature flags if supported by the processor, | |
82 * again while applying specific processor knowledge. | |
83 * o Determining the CMT characteristics of the system. | |
84 * | |
85 * Pass 1 is done on non-boot CPUs during their initialization and the results | |
86 * are used only as a meager attempt at ensuring that all processors within the | |
87 * system support the same features. | |
88 * | |
89 * Pass 2 of cpuid feature analysis happens just at the beginning | |
90 * of startup(). It just copies in and corrects the remainder | |
91 * of the cpuid data we depend on: standard cpuid functions that we didn't | |
92 * need for pass1 feature analysis, and extended cpuid functions beyond the | |
93 * simple feature processing done in pass1. | |
94 * | |
95 * Pass 3 of cpuid analysis is invoked after basic kernel services; in | |
96 * particular kernel memory allocation has been made available. It creates a | |
97 * readable brand string based on the data collected in the first two passes. | |
98 * | |
99 * Pass 4 of cpuid analysis is invoked after post_startup() when all | |
100 * the support infrastructure for various hardware features has been | |
101 * initialized. It determines which processor features will be reported | |
102 * to userland via the aux vector. | |
103 * | |
104 * All passes are executed on all CPUs, but only the boot CPU determines what | |
105 * features the kernel will use. | |
106 * | |
107 * Much of the worst junk in this file is for the support of processors | |
108 * that didn't really implement the cpuid instruction properly. | |
109 * | |
110 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, | |
111 * the pass numbers. Accordingly, changes to the pass code may require changes | |
112 * to the accessor code. | |
113 */ | |
114 | |
115 uint_t x86_feature = 0; | |
116 uint_t x86_vendor = X86_VENDOR_IntelClone; | |
117 uint_t x86_type = X86_TYPE_OTHER; | |
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118 uint_t x86_clflush_size = 0; |
0 | 119 |
120 uint_t pentiumpro_bug4046376; | |
121 uint_t pentiumpro_bug4064495; | |
122 | |
123 uint_t enable486; | |
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124 /* |
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125 * This is set to platform type Solaris is running on. |
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126 */ |
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127 static int platform_type = -1; |
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128 |
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129 #if !defined(__xpv) |
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130 /* |
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131 * Variable to patch if hypervisor platform detection needs to be |
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132 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0). |
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133 */ |
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134 int enable_platform_detection = 1; |
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135 #endif |
0 | 136 |
137 /* | |
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138 * monitor/mwait info. |
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139 * |
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140 * size_actual and buf_actual are the real address and size allocated to get |
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141 * proper mwait_buf alignement. buf_actual and size_actual should be passed |
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142 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use |
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143 * processor cache-line alignment, but this is not guarantied in the furture. |
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144 */ |
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145 struct mwait_info { |
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146 size_t mon_min; /* min size to avoid missed wakeups */ |
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147 size_t mon_max; /* size to avoid false wakeups */ |
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148 size_t size_actual; /* size actually allocated */ |
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149 void *buf_actual; /* memory actually allocated */ |
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150 uint32_t support; /* processor support of monitor/mwait */ |
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151 }; |
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152 |
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153 /* |
0 | 154 * These constants determine how many of the elements of the |
155 * cpuid we cache in the cpuid_info data structure; the | |
156 * remaining elements are accessible via the cpuid instruction. | |
157 */ | |
158 | |
159 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ | |
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160 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */ |
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161 |
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162 /* |
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163 * Some terminology needs to be explained: |
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164 * - Socket: Something that can be plugged into a motherboard. |
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165 * - Package: Same as socket |
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166 * - Chip: Same as socket. Note that AMD's documentation uses term "chip" |
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167 * differently: there, chip is the same as processor node (below) |
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168 * - Processor node: Some AMD processors have more than one |
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169 * "subprocessor" embedded in a package. These subprocessors (nodes) |
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170 * are fully-functional processors themselves with cores, caches, |
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171 * memory controllers, PCI configuration spaces. They are connected |
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172 * inside the package with Hypertransport links. On single-node |
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173 * processors, processor node is equivalent to chip/socket/package. |
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174 */ |
0 | 175 |
176 struct cpuid_info { | |
177 uint_t cpi_pass; /* last pass completed */ | |
178 /* | |
179 * standard function information | |
180 */ | |
181 uint_t cpi_maxeax; /* fn 0: %eax */ | |
182 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ | |
183 uint_t cpi_vendor; /* enum of cpi_vendorstr */ | |
184 | |
185 uint_t cpi_family; /* fn 1: extended family */ | |
186 uint_t cpi_model; /* fn 1: extended model */ | |
187 uint_t cpi_step; /* fn 1: stepping */ | |
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188 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */ |
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189 /* AMD: package/socket # */ |
0 | 190 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ |
191 int cpi_clogid; /* fn 1: %ebx: thread # */ | |
1228 | 192 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ |
0 | 193 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ |
194 uint_t cpi_ncache; /* fn 2: number of elements */ | |
4606 | 195 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ |
196 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ | |
197 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ | |
198 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ | |
1228 | 199 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ |
0 | 200 /* |
201 * extended function information | |
202 */ | |
203 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ | |
204 char cpi_brandstr[49]; /* fn 0x8000000[234] */ | |
205 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ | |
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206 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ |
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207 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */ |
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208 |
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209 id_t cpi_coreid; /* same coreid => strands share core */ |
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210 int cpi_pkgcoreid; /* core number within single package */ |
1228 | 211 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ |
212 /* Intel: fn 4: %eax[31-26] */ | |
0 | 213 /* |
214 * supported feature information | |
215 */ | |
3446 | 216 uint32_t cpi_support[5]; |
0 | 217 #define STD_EDX_FEATURES 0 |
218 #define AMD_EDX_FEATURES 1 | |
219 #define TM_EDX_FEATURES 2 | |
220 #define STD_ECX_FEATURES 3 | |
3446 | 221 #define AMD_ECX_FEATURES 4 |
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222 /* |
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223 * Synthesized information, where known. |
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224 */ |
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225 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ |
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226 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ |
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227 uint32_t cpi_socket; /* Chip package/socket type */ |
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228 |
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229 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ |
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230 uint32_t cpi_apicid; |
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231 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */ |
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232 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */ |
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233 /* Intel: 1 */ |
0 | 234 }; |
235 | |
236 | |
237 static struct cpuid_info cpuid_info0; | |
238 | |
239 /* | |
240 * These bit fields are defined by the Intel Application Note AP-485 | |
241 * "Intel Processor Identification and the CPUID Instruction" | |
242 */ | |
243 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) | |
244 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) | |
245 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) | |
246 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) | |
247 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) | |
248 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) | |
249 | |
250 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) | |
251 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) | |
252 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) | |
253 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) | |
254 | |
255 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) | |
256 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) | |
257 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) | |
258 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) | |
259 | |
260 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ | |
261 #define CPI_XMAXEAX_MAX 0x80000100 | |
4606 | 262 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ |
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263 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ |
4606 | 264 |
265 /* | |
266 * Function 4 (Deterministic Cache Parameters) macros | |
267 * Defined by Intel Application Note AP-485 | |
268 */ | |
269 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) | |
270 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) | |
271 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) | |
272 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) | |
273 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) | |
274 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) | |
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275 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) |
4606 | 276 |
277 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) | |
278 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) | |
279 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) | |
280 | |
281 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) | |
282 | |
283 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) | |
284 | |
0 | 285 |
286 /* | |
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287 * A couple of shorthand macros to identify "later" P6-family chips |
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288 * like the Pentium M and Core. First, the "older" P6-based stuff |
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289 * (loosely defined as "pre-Pentium-4"): |
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290 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon |
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291 */ |
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292 |
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293 #define IS_LEGACY_P6(cpi) ( \ |
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294 cpi->cpi_family == 6 && \ |
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295 (cpi->cpi_model == 1 || \ |
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296 cpi->cpi_model == 3 || \ |
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297 cpi->cpi_model == 5 || \ |
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298 cpi->cpi_model == 6 || \ |
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299 cpi->cpi_model == 7 || \ |
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300 cpi->cpi_model == 8 || \ |
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301 cpi->cpi_model == 0xA || \ |
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302 cpi->cpi_model == 0xB) \ |
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303 ) |
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304 |
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305 /* A "new F6" is everything with family 6 that's not the above */ |
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306 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) |
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307 |
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308 /* Extended family/model support */ |
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309 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ |
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310 cpi->cpi_family >= 0xf) |
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311 |
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312 /* |
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313 * Info for monitor/mwait idle loop. |
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314 * |
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315 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's |
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316 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November |
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317 * 2006. |
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318 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual |
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319 * Documentation Updates" #33633, Rev 2.05, December 2006. |
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320 */ |
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321 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ |
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322 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ |
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323 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ |
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324 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) |
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325 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) |
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326 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) |
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327 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) |
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328 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) |
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329 /* |
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330 * Number of sub-cstates for a given c-state. |
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331 */ |
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332 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ |
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333 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) |
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334 |
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335 /* |
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336 * Functions we consune from cpuid_subr.c; don't publish these in a header |
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337 * file to try and keep people using the expected cpuid_* interfaces. |
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338 */ |
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339 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); |
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340 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); |
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341 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); |
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342 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); |
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343 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); |
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344 |
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345 /* |
3446 | 346 * Apply up various platform-dependent restrictions where the |
347 * underlying platform restrictions mean the CPU can be marked | |
348 * as less capable than its cpuid instruction would imply. | |
349 */ | |
5084 | 350 #if defined(__xpv) |
351 static void | |
352 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) | |
353 { | |
354 switch (eax) { | |
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355 case 1: { |
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356 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? |
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357 0 : CPUID_INTC_EDX_MCA; |
5084 | 358 cp->cp_edx &= |
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359 ~(mcamask | |
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360 CPUID_INTC_EDX_PSE | |
5084 | 361 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | |
362 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | | |
363 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | | |
364 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
365 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); | |
366 break; | |
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367 } |
5084 | 368 |
369 case 0x80000001: | |
370 cp->cp_edx &= | |
371 ~(CPUID_AMD_EDX_PSE | | |
372 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | | |
373 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | | |
374 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | | |
375 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
376 CPUID_AMD_EDX_TSCP); | |
377 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; | |
378 break; | |
379 default: | |
380 break; | |
381 } | |
382 | |
383 switch (vendor) { | |
384 case X86_VENDOR_Intel: | |
385 switch (eax) { | |
386 case 4: | |
387 /* | |
388 * Zero out the (ncores-per-chip - 1) field | |
389 */ | |
390 cp->cp_eax &= 0x03fffffff; | |
391 break; | |
392 default: | |
393 break; | |
394 } | |
395 break; | |
396 case X86_VENDOR_AMD: | |
397 switch (eax) { | |
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398 |
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399 case 0x80000001: |
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400 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; |
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401 break; |
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402 |
5084 | 403 case 0x80000008: |
404 /* | |
405 * Zero out the (ncores-per-chip - 1) field | |
406 */ | |
407 cp->cp_ecx &= 0xffffff00; | |
408 break; | |
409 default: | |
410 break; | |
411 } | |
412 break; | |
413 default: | |
414 break; | |
415 } | |
416 } | |
417 #else | |
3446 | 418 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ |
5084 | 419 #endif |
3446 | 420 |
421 /* | |
0 | 422 * Some undocumented ways of patching the results of the cpuid |
423 * instruction to permit running Solaris 10 on future cpus that | |
424 * we don't currently support. Could be set to non-zero values | |
425 * via settings in eeprom. | |
426 */ | |
427 | |
428 uint32_t cpuid_feature_ecx_include; | |
429 uint32_t cpuid_feature_ecx_exclude; | |
430 uint32_t cpuid_feature_edx_include; | |
431 uint32_t cpuid_feature_edx_exclude; | |
432 | |
3446 | 433 void |
434 cpuid_alloc_space(cpu_t *cpu) | |
435 { | |
436 /* | |
437 * By convention, cpu0 is the boot cpu, which is set up | |
438 * before memory allocation is available. All other cpus get | |
439 * their cpuid_info struct allocated here. | |
440 */ | |
441 ASSERT(cpu->cpu_id != 0); | |
442 cpu->cpu_m.mcpu_cpi = | |
443 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); | |
444 } | |
445 | |
446 void | |
447 cpuid_free_space(cpu_t *cpu) | |
448 { | |
4606 | 449 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
450 int i; | |
451 | |
3446 | 452 ASSERT(cpu->cpu_id != 0); |
4606 | 453 |
454 /* | |
455 * Free up any function 4 related dynamic storage | |
456 */ | |
457 for (i = 1; i < cpi->cpi_std_4_size; i++) | |
458 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); | |
459 if (cpi->cpi_std_4_size > 0) | |
460 kmem_free(cpi->cpi_std_4, | |
461 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); | |
462 | |
3446 | 463 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); |
464 } | |
465 | |
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466 #if !defined(__xpv) |
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467 |
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468 static void |
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469 determine_platform() |
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470 { |
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471 struct cpuid_regs cp; |
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472 char *xen_str; |
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473 uint32_t xen_signature[4]; |
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474 |
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475 platform_type = HW_NATIVE; |
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476 |
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477 if (!enable_platform_detection) |
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478 return; |
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479 |
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480 /* |
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481 * In a fully virtualized domain, Xen's pseudo-cpuid function |
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482 * 0x40000000 returns a string representing the Xen signature in |
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483 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid |
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484 * function. |
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485 */ |
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486 cp.cp_eax = 0x40000000; |
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487 (void) __cpuid_insn(&cp); |
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488 xen_signature[0] = cp.cp_ebx; |
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489 xen_signature[1] = cp.cp_ecx; |
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490 xen_signature[2] = cp.cp_edx; |
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491 xen_signature[3] = 0; |
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492 xen_str = (char *)xen_signature; |
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493 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) { |
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494 platform_type = HW_XEN_HVM; |
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495 } else if (vmware_platform()) { /* running under vmware hypervisor? */ |
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496 platform_type = HW_VMWARE; |
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497 } |
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498 } |
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499 |
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500 int |
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501 get_hwenv(void) |
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502 { |
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503 if (platform_type == -1) |
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504 determine_platform(); |
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505 |
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506 return (platform_type); |
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507 } |
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508 |
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509 int |
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510 is_controldom(void) |
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511 { |
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512 return (0); |
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513 } |
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514 |
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515 #else |
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516 |
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517 int |
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518 get_hwenv(void) |
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519 { |
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520 return (HW_XEN_PV); |
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521 } |
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522 |
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523 int |
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524 is_controldom(void) |
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525 { |
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526 return (DOMAIN_IS_INITDOMAIN(xen_info)); |
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527 } |
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528 |
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529 #endif /* __xpv */ |
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530 |
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531 static void |
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532 cpuid_intel_getids(cpu_t *cpu, uint_t feature) |
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533 { |
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534 uint_t i; |
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535 uint_t chipid_shift = 0; |
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536 uint_t coreid_shift = 0; |
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537 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
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538 |
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539 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) |
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540 chipid_shift++; |
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541 |
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542 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift; |
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543 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1); |
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544 |
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545 if (feature & X86_CMP) { |
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546 /* |
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547 * Multi-core (and possibly multi-threaded) |
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548 * processors. |
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549 */ |
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550 uint_t ncpu_per_core; |
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551 if (cpi->cpi_ncore_per_chip == 1) |
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552 ncpu_per_core = cpi->cpi_ncpu_per_chip; |
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553 else if (cpi->cpi_ncore_per_chip > 1) |
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554 ncpu_per_core = cpi->cpi_ncpu_per_chip / |
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555 cpi->cpi_ncore_per_chip; |
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556 /* |
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557 * 8bit APIC IDs on dual core Pentiums |
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558 * look like this: |
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559 * |
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560 * +-----------------------+------+------+ |
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561 * | Physical Package ID | MC | HT | |
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562 * +-----------------------+------+------+ |
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563 * <------- chipid --------> |
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564 * <------- coreid ---------------> |
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565 * <--- clogid --> |
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566 * <------> |
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567 * pkgcoreid |
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568 * |
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569 * Where the number of bits necessary to |
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570 * represent MC and HT fields together equals |
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571 * to the minimum number of bits necessary to |
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572 * store the value of cpi->cpi_ncpu_per_chip. |
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573 * Of those bits, the MC part uses the number |
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574 * of bits necessary to store the value of |
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575 * cpi->cpi_ncore_per_chip. |
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576 */ |
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577 for (i = 1; i < ncpu_per_core; i <<= 1) |
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578 coreid_shift++; |
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579 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift; |
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580 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; |
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581 } else if (feature & X86_HTT) { |
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582 /* |
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583 * Single-core multi-threaded processors. |
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584 */ |
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585 cpi->cpi_coreid = cpi->cpi_chipid; |
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586 cpi->cpi_pkgcoreid = 0; |
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587 } |
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588 cpi->cpi_procnodeid = cpi->cpi_chipid; |
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589 } |
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590 |
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591 static void |
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592 cpuid_amd_getids(cpu_t *cpu) |
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593 { |
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594 int i, first_half, coreidsz; |
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595 uint32_t nb_caps_reg; |
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596 uint_t node2_1; |
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597 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
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598 |
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599 /* |
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600 * AMD CMP chips currently have a single thread per core. |
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601 * |
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602 * Since no two cpus share a core we must assign a distinct coreid |
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603 * per cpu, and we do this by using the cpu_id. This scheme does not, |
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604 * however, guarantee that sibling cores of a chip will have sequential |
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605 * coreids starting at a multiple of the number of cores per chip - |
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606 * that is usually the case, but if the ACPI MADT table is presented |
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607 * in a different order then we need to perform a few more gymnastics |
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608 * for the pkgcoreid. |
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609 * |
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610 * All processors in the system have the same number of enabled |
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611 * cores. Cores within a processor are always numbered sequentially |
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612 * from 0 regardless of how many or which are disabled, and there |
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613 * is no way for operating system to discover the real core id when some |
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614 * are disabled. |
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615 */ |
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616 |
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617 cpi->cpi_coreid = cpu->cpu_id; |
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618 |
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619 if (cpi->cpi_xmaxeax >= 0x80000008) { |
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620 |
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621 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); |
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622 |
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623 /* |
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624 * In AMD parlance chip is really a node while Solaris |
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625 * sees chip as equivalent to socket/package. |
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626 */ |
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627 cpi->cpi_ncore_per_chip = |
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628 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; |
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629 if (coreidsz == 0) { |
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630 /* Use legacy method */ |
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631 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1) |
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632 coreidsz++; |
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633 if (coreidsz == 0) |
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634 coreidsz = 1; |
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635 } |
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636 } else { |
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637 /* Assume single-core part */ |
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638 cpi->cpi_ncore_per_chip = 1; |
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639 } |
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640 |
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641 cpi->cpi_clogid = cpi->cpi_pkgcoreid = |
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642 cpi->cpi_apicid & ((1<<coreidsz) - 1); |
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643 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip; |
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644 |
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645 /* Get nodeID */ |
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646 if (cpi->cpi_family == 0xf) { |
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647 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; |
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648 cpi->cpi_chipid = cpi->cpi_procnodeid; |
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649 } else if (cpi->cpi_family == 0x10) { |
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650 /* |
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651 * See if we are a multi-node processor. |
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652 * All processors in the system have the same number of nodes |
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653 */ |
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654 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8); |
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655 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) { |
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656 /* Single-node */ |
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657 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5, |
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658 coreidsz); |
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659 cpi->cpi_chipid = cpi->cpi_procnodeid; |
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660 } else { |
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661 |
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662 /* |
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663 * Multi-node revision D (2 nodes per package |
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664 * are supported) |
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665 */ |
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666 cpi->cpi_procnodes_per_pkg = 2; |
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667 |
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668 first_half = (cpi->cpi_pkgcoreid <= |
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669 (cpi->cpi_ncore_per_chip/2 - 1)); |
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670 |
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671 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) { |
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672 /* We are BSP */ |
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|
673 cpi->cpi_procnodeid = (first_half ? 0 : 1); |
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674 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; |
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changeset
|
675 } else { |
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diff
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|
676 |
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6843035 Need support for Magny-Cours processors
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diff
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|
677 /* We are AP */ |
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diff
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|
678 /* NodeId[2:1] bits to use for reading F3xe8 */ |
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diff
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679 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1; |
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diff
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|
680 |
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diff
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|
681 nb_caps_reg = |
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diff
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|
682 pci_getl_func(0, 24 + node2_1, 3, 0xe8); |
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683 |
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|
684 /* |
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diff
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|
685 * Check IntNodeNum bit (31:30, but bit 31 is |
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diff
changeset
|
686 * always 0 on dual-node processors) |
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diff
changeset
|
687 */ |
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diff
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|
688 if (BITX(nb_caps_reg, 30, 30) == 0) |
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|
689 cpi->cpi_procnodeid = node2_1 + |
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diff
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|
690 !first_half; |
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diff
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691 else |
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6843035 Need support for Magny-Cours processors
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692 cpi->cpi_procnodeid = node2_1 + |
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diff
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693 first_half; |
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diff
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|
694 |
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diff
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695 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; |
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696 } |
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697 } |
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|
698 } else if (cpi->cpi_family >= 0x11) { |
2ecbb0a4d189
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diff
changeset
|
699 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; |
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6843035 Need support for Magny-Cours processors
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parents:
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diff
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|
700 cpi->cpi_chipid = cpi->cpi_procnodeid; |
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parents:
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701 } else { |
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702 cpi->cpi_procnodeid = 0; |
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diff
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|
703 cpi->cpi_chipid = cpi->cpi_procnodeid; |
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704 } |
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|
705 } |
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6843035 Need support for Magny-Cours processors
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diff
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|
706 |
0 | 707 uint_t |
708 cpuid_pass1(cpu_t *cpu) | |
709 { | |
710 uint32_t mask_ecx, mask_edx; | |
711 uint_t feature = X86_CPUID; | |
712 struct cpuid_info *cpi; | |
1228 | 713 struct cpuid_regs *cp; |
0 | 714 int xcpuid; |
5084 | 715 #if !defined(__xpv) |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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parents:
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diff
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|
716 extern int idle_cpu_prefer_mwait; |
5084 | 717 #endif |
3446 | 718 |
9482
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
719 |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
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diff
changeset
|
720 #if !defined(__xpv) |
42f3d60af7ca
6770233 New model ID for Istanbul processor
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parents:
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diff
changeset
|
721 determine_platform(); |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
722 #endif |
0 | 723 /* |
3446 | 724 * Space statically allocated for cpu0, ensure pointer is set |
0 | 725 */ |
726 if (cpu->cpu_id == 0) | |
3446 | 727 cpu->cpu_m.mcpu_cpi = &cpuid_info0; |
728 cpi = cpu->cpu_m.mcpu_cpi; | |
729 ASSERT(cpi != NULL); | |
0 | 730 cp = &cpi->cpi_std[0]; |
1228 | 731 cp->cp_eax = 0; |
732 cpi->cpi_maxeax = __cpuid_insn(cp); | |
0 | 733 { |
734 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; | |
735 *iptr++ = cp->cp_ebx; | |
736 *iptr++ = cp->cp_edx; | |
737 *iptr++ = cp->cp_ecx; | |
738 *(char *)&cpi->cpi_vendorstr[12] = '\0'; | |
739 } | |
740 | |
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
741 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); |
0 | 742 x86_vendor = cpi->cpi_vendor; /* for compatibility */ |
743 | |
744 /* | |
745 * Limit the range in case of weird hardware | |
746 */ | |
747 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) | |
748 cpi->cpi_maxeax = CPI_MAXEAX_MAX; | |
749 if (cpi->cpi_maxeax < 1) | |
750 goto pass1_done; | |
751 | |
752 cp = &cpi->cpi_std[1]; | |
1228 | 753 cp->cp_eax = 1; |
754 (void) __cpuid_insn(cp); | |
0 | 755 |
756 /* | |
757 * Extract identifying constants for easy access. | |
758 */ | |
759 cpi->cpi_model = CPI_MODEL(cpi); | |
760 cpi->cpi_family = CPI_FAMILY(cpi); | |
761 | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
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parents:
1727
diff
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|
762 if (cpi->cpi_family == 0xf) |
0 | 763 cpi->cpi_family += CPI_FAMILY_XTD(cpi); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
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parents:
1727
diff
changeset
|
764 |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
765 /* |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
766 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
767 * Intel, and presumably everyone else, uses model == 0xf, as |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
768 * one would expect (max value means possible overflow). Sigh. |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
769 */ |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
770 |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
771 switch (cpi->cpi_vendor) { |
4855
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
772 case X86_VENDOR_Intel: |
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
773 if (IS_EXTENDED_MODEL_INTEL(cpi)) |
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
774 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
4858
08409e2eed12
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint)
ksadhukh
parents:
4855
diff
changeset
|
775 break; |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
776 case X86_VENDOR_AMD: |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
777 if (CPI_FAMILY(cpi) == 0xf) |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
778 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
779 break; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
780 default: |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
781 if (cpi->cpi_model == 0xf) |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
782 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
783 break; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
784 } |
0 | 785 |
786 cpi->cpi_step = CPI_STEP(cpi); | |
787 cpi->cpi_brandid = CPI_BRANDID(cpi); | |
788 | |
789 /* | |
790 * *default* assumptions: | |
791 * - believe %edx feature word | |
792 * - ignore %ecx feature word | |
793 * - 32-bit virtual and physical addressing | |
794 */ | |
795 mask_edx = 0xffffffff; | |
796 mask_ecx = 0; | |
797 | |
798 cpi->cpi_pabits = cpi->cpi_vabits = 32; | |
799 | |
800 switch (cpi->cpi_vendor) { | |
801 case X86_VENDOR_Intel: | |
802 if (cpi->cpi_family == 5) | |
803 x86_type = X86_TYPE_P5; | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
804 else if (IS_LEGACY_P6(cpi)) { |
0 | 805 x86_type = X86_TYPE_P6; |
806 pentiumpro_bug4046376 = 1; | |
807 pentiumpro_bug4064495 = 1; | |
808 /* | |
809 * Clear the SEP bit when it was set erroneously | |
810 */ | |
811 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) | |
812 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
813 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { |
0 | 814 x86_type = X86_TYPE_P4; |
815 /* | |
816 * We don't currently depend on any of the %ecx | |
817 * features until Prescott, so we'll only check | |
818 * this from P4 onwards. We might want to revisit | |
819 * that idea later. | |
820 */ | |
821 mask_ecx = 0xffffffff; | |
822 } else if (cpi->cpi_family > 0xf) | |
823 mask_ecx = 0xffffffff; | |
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
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parents:
4628
diff
changeset
|
824 /* |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
825 * We don't support MONITOR/MWAIT if leaf 5 is not available |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
826 * to obtain the monitor linesize. |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
827 */ |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
828 if (cpi->cpi_maxeax < 5) |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
829 mask_ecx &= ~CPUID_INTC_ECX_MON; |
0 | 830 break; |
831 case X86_VENDOR_IntelClone: | |
832 default: | |
833 break; | |
834 case X86_VENDOR_AMD: | |
835 #if defined(OPTERON_ERRATUM_108) | |
836 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { | |
837 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; | |
838 cpi->cpi_model = 0xc; | |
839 } else | |
840 #endif | |
841 if (cpi->cpi_family == 5) { | |
842 /* | |
843 * AMD K5 and K6 | |
844 * | |
845 * These CPUs have an incomplete implementation | |
846 * of MCA/MCE which we mask away. | |
847 */ | |
1228 | 848 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); |
849 | |
850 /* | |
851 * Model 0 uses the wrong (APIC) bit | |
852 * to indicate PGE. Fix it here. | |
853 */ | |
0 | 854 if (cpi->cpi_model == 0) { |
855 if (cp->cp_edx & 0x200) { | |
856 cp->cp_edx &= ~0x200; | |
857 cp->cp_edx |= CPUID_INTC_EDX_PGE; | |
858 } | |
1228 | 859 } |
860 | |
861 /* | |
862 * Early models had problems w/ MMX; disable. | |
863 */ | |
864 if (cpi->cpi_model < 6) | |
865 mask_edx &= ~CPUID_INTC_EDX_MMX; | |
866 } | |
867 | |
868 /* | |
869 * For newer families, SSE3 and CX16, at least, are valid; | |
870 * enable all | |
871 */ | |
872 if (cpi->cpi_family >= 0xf) | |
771
1c25a2120ec0
6327969 cpuid sse3 feature bit not noted on any AMD processor
dmick
parents:
359
diff
changeset
|
873 mask_ecx = 0xffffffff; |
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
874 /* |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
875 * We don't support MONITOR/MWAIT if leaf 5 is not available |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
876 * to obtain the monitor linesize. |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
877 */ |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
878 if (cpi->cpi_maxeax < 5) |
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
879 mask_ecx &= ~CPUID_INTC_ECX_MON; |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
880 |
5084 | 881 #if !defined(__xpv) |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
882 /* |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
883 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
884 * processors. AMD does not intend MWAIT to be used in the cpu |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
885 * idle loop on current and future processors. 10h and future |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
886 * AMD processors use more power in MWAIT than HLT. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
887 * Pre-family-10h Opterons do not have the MWAIT instruction. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
888 */ |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
889 idle_cpu_prefer_mwait = 0; |
5084 | 890 #endif |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
891 |
0 | 892 break; |
893 case X86_VENDOR_TM: | |
894 /* | |
895 * workaround the NT workaround in CMS 4.1 | |
896 */ | |
897 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && | |
898 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) | |
899 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
900 break; | |
901 case X86_VENDOR_Centaur: | |
902 /* | |
903 * workaround the NT workarounds again | |
904 */ | |
905 if (cpi->cpi_family == 6) | |
906 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
907 break; | |
908 case X86_VENDOR_Cyrix: | |
909 /* | |
910 * We rely heavily on the probing in locore | |
911 * to actually figure out what parts, if any, | |
912 * of the Cyrix cpuid instruction to believe. | |
913 */ | |
914 switch (x86_type) { | |
915 case X86_TYPE_CYRIX_486: | |
916 mask_edx = 0; | |
917 break; | |
918 case X86_TYPE_CYRIX_6x86: | |
919 mask_edx = 0; | |
920 break; | |
921 case X86_TYPE_CYRIX_6x86L: | |
922 mask_edx = | |
923 CPUID_INTC_EDX_DE | | |
924 CPUID_INTC_EDX_CX8; | |
925 break; | |
926 case X86_TYPE_CYRIX_6x86MX: | |
927 mask_edx = | |
928 CPUID_INTC_EDX_DE | | |
929 CPUID_INTC_EDX_MSR | | |
930 CPUID_INTC_EDX_CX8 | | |
931 CPUID_INTC_EDX_PGE | | |
932 CPUID_INTC_EDX_CMOV | | |
933 CPUID_INTC_EDX_MMX; | |
934 break; | |
935 case X86_TYPE_CYRIX_GXm: | |
936 mask_edx = | |
937 CPUID_INTC_EDX_MSR | | |
938 CPUID_INTC_EDX_CX8 | | |
939 CPUID_INTC_EDX_CMOV | | |
940 CPUID_INTC_EDX_MMX; | |
941 break; | |
942 case X86_TYPE_CYRIX_MediaGX: | |
943 break; | |
944 case X86_TYPE_CYRIX_MII: | |
945 case X86_TYPE_VIA_CYRIX_III: | |
946 mask_edx = | |
947 CPUID_INTC_EDX_DE | | |
948 CPUID_INTC_EDX_TSC | | |
949 CPUID_INTC_EDX_MSR | | |
950 CPUID_INTC_EDX_CX8 | | |
951 CPUID_INTC_EDX_PGE | | |
952 CPUID_INTC_EDX_CMOV | | |
953 CPUID_INTC_EDX_MMX; | |
954 break; | |
955 default: | |
956 break; | |
957 } | |
958 break; | |
959 } | |
960 | |
5084 | 961 #if defined(__xpv) |
962 /* | |
963 * Do not support MONITOR/MWAIT under a hypervisor | |
964 */ | |
965 mask_ecx &= ~CPUID_INTC_ECX_MON; | |
966 #endif /* __xpv */ | |
967 | |
0 | 968 /* |
969 * Now we've figured out the masks that determine | |
970 * which bits we choose to believe, apply the masks | |
971 * to the feature words, then map the kernel's view | |
972 * of these feature words into its feature word. | |
973 */ | |
974 cp->cp_edx &= mask_edx; | |
975 cp->cp_ecx &= mask_ecx; | |
976 | |
977 /* | |
3446 | 978 * apply any platform restrictions (we don't call this |
979 * immediately after __cpuid_insn here, because we need the | |
980 * workarounds applied above first) | |
0 | 981 */ |
3446 | 982 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); |
0 | 983 |
3446 | 984 /* |
985 * fold in overrides from the "eeprom" mechanism | |
986 */ | |
0 | 987 cp->cp_edx |= cpuid_feature_edx_include; |
988 cp->cp_edx &= ~cpuid_feature_edx_exclude; | |
989 | |
990 cp->cp_ecx |= cpuid_feature_ecx_include; | |
991 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; | |
992 | |
993 if (cp->cp_edx & CPUID_INTC_EDX_PSE) | |
994 feature |= X86_LARGEPAGE; | |
995 if (cp->cp_edx & CPUID_INTC_EDX_TSC) | |
996 feature |= X86_TSC; | |
997 if (cp->cp_edx & CPUID_INTC_EDX_MSR) | |
998 feature |= X86_MSR; | |
999 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) | |
1000 feature |= X86_MTRR; | |
1001 if (cp->cp_edx & CPUID_INTC_EDX_PGE) | |
1002 feature |= X86_PGE; | |
1003 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) | |
1004 feature |= X86_CMOV; | |
1005 if (cp->cp_edx & CPUID_INTC_EDX_MMX) | |
1006 feature |= X86_MMX; | |
1007 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && | |
1008 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) | |
1009 feature |= X86_MCA; | |
1010 if (cp->cp_edx & CPUID_INTC_EDX_PAE) | |
1011 feature |= X86_PAE; | |
1012 if (cp->cp_edx & CPUID_INTC_EDX_CX8) | |
1013 feature |= X86_CX8; | |
1014 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) | |
1015 feature |= X86_CX16; | |
1016 if (cp->cp_edx & CPUID_INTC_EDX_PAT) | |
1017 feature |= X86_PAT; | |
1018 if (cp->cp_edx & CPUID_INTC_EDX_SEP) | |
1019 feature |= X86_SEP; | |
1020 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { | |
1021 /* | |
1022 * In our implementation, fxsave/fxrstor | |
1023 * are prerequisites before we'll even | |
1024 * try and do SSE things. | |
1025 */ | |
1026 if (cp->cp_edx & CPUID_INTC_EDX_SSE) | |
1027 feature |= X86_SSE; | |
1028 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) | |
1029 feature |= X86_SSE2; | |
1030 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) | |
1031 feature |= X86_SSE3; | |
5269
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1032 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
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1033 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) |
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1034 feature |= X86_SSSE3; |
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1035 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) |
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1036 feature |= X86_SSE4_1; |
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1037 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) |
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1038 feature |= X86_SSE4_2; |
9370
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1039 if (cp->cp_ecx & CPUID_INTC_ECX_AES) |
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6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
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1040 feature |= X86_AES; |
5269
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1041 } |
0 | 1042 } |
1043 if (cp->cp_edx & CPUID_INTC_EDX_DE) | |
3446 | 1044 feature |= X86_DE; |
7716
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1045 #if !defined(__xpv) |
4481
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1046 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { |
7716
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1047 |
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1048 /* |
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1049 * We require the CLFLUSH instruction for erratum workaround |
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1050 * to use MONITOR/MWAIT. |
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1051 */ |
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1052 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
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1053 cpi->cpi_mwait.support |= MWAIT_SUPPORT; |
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1054 feature |= X86_MWAIT; |
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1055 } else { |
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1056 extern int idle_cpu_assert_cflush_monitor; |
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1057 |
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1058 /* |
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1059 * All processors we are aware of which have |
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1060 * MONITOR/MWAIT also have CLFLUSH. |
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1061 */ |
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1062 if (idle_cpu_assert_cflush_monitor) { |
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1063 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && |
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1064 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); |
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1065 } |
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1066 } |
4481
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1067 } |
7716
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1068 #endif /* __xpv */ |
0 | 1069 |
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1070 /* |
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1071 * Only need it first time, rest of the cpus would follow suite. |
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1072 * we only capture this for the bootcpu. |
7de800909a06
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1073 */ |
7de800909a06
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1074 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
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1075 feature |= X86_CLFSH; |
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1076 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); |
7de800909a06
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1077 } |
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1078 |
0 | 1079 if (feature & X86_PAE) |
1080 cpi->cpi_pabits = 36; | |
1081 | |
1082 /* | |
1083 * Hyperthreading configuration is slightly tricky on Intel | |
1084 * and pure clones, and even trickier on AMD. | |
1085 * | |
1086 * (AMD chose to set the HTT bit on their CMP processors, | |
1087 * even though they're not actually hyperthreaded. Thus it | |
1088 * takes a bit more work to figure out what's really going | |
3446 | 1089 * on ... see the handling of the CMP_LGCY bit below) |
0 | 1090 */ |
1091 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { | |
1092 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); | |
1093 if (cpi->cpi_ncpu_per_chip > 1) | |
1094 feature |= X86_HTT; | |
1228 | 1095 } else { |
1096 cpi->cpi_ncpu_per_chip = 1; | |
0 | 1097 } |
1098 | |
1099 /* | |
1100 * Work on the "extended" feature information, doing | |
1101 * some basic initialization for cpuid_pass2() | |
1102 */ | |
1103 xcpuid = 0; | |
1104 switch (cpi->cpi_vendor) { | |
1105 case X86_VENDOR_Intel: | |
1975
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1106 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) |
0 | 1107 xcpuid++; |
1108 break; | |
1109 case X86_VENDOR_AMD: | |
1110 if (cpi->cpi_family > 5 || | |
1111 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
1112 xcpuid++; | |
1113 break; | |
1114 case X86_VENDOR_Cyrix: | |
1115 /* | |
1116 * Only these Cyrix CPUs are -known- to support | |
1117 * extended cpuid operations. | |
1118 */ | |
1119 if (x86_type == X86_TYPE_VIA_CYRIX_III || | |
1120 x86_type == X86_TYPE_CYRIX_GXm) | |
1121 xcpuid++; | |
1122 break; | |
1123 case X86_VENDOR_Centaur: | |
1124 case X86_VENDOR_TM: | |
1125 default: | |
1126 xcpuid++; | |
1127 break; | |
1128 } | |
1129 | |
1130 if (xcpuid) { | |
1131 cp = &cpi->cpi_extd[0]; | |
1228 | 1132 cp->cp_eax = 0x80000000; |
1133 cpi->cpi_xmaxeax = __cpuid_insn(cp); | |
0 | 1134 } |
1135 | |
1136 if (cpi->cpi_xmaxeax & 0x80000000) { | |
1137 | |
1138 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) | |
1139 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; | |
1140 | |
1141 switch (cpi->cpi_vendor) { | |
1142 case X86_VENDOR_Intel: | |
1143 case X86_VENDOR_AMD: | |
1144 if (cpi->cpi_xmaxeax < 0x80000001) | |
1145 break; | |
1146 cp = &cpi->cpi_extd[1]; | |
1228 | 1147 cp->cp_eax = 0x80000001; |
1148 (void) __cpuid_insn(cp); | |
3446 | 1149 |
0 | 1150 if (cpi->cpi_vendor == X86_VENDOR_AMD && |
1151 cpi->cpi_family == 5 && | |
1152 cpi->cpi_model == 6 && | |
1153 cpi->cpi_step == 6) { | |
1154 /* | |
1155 * K6 model 6 uses bit 10 to indicate SYSC | |
1156 * Later models use bit 11. Fix it here. | |
1157 */ | |
1158 if (cp->cp_edx & 0x400) { | |
1159 cp->cp_edx &= ~0x400; | |
1160 cp->cp_edx |= CPUID_AMD_EDX_SYSC; | |
1161 } | |
1162 } | |
1163 | |
3446 | 1164 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); |
1165 | |
0 | 1166 /* |
1167 * Compute the additions to the kernel's feature word. | |
1168 */ | |
1169 if (cp->cp_edx & CPUID_AMD_EDX_NX) | |
1170 feature |= X86_NX; | |
1171 | |
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1172 /* |
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1173 * Regardless whether or not we boot 64-bit, |
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1174 * we should have a way to identify whether |
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1175 * the CPU is capable of running 64-bit. |
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1176 */ |
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1177 if (cp->cp_edx & CPUID_AMD_EDX_LM) |
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1178 feature |= X86_64; |
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1179 |
5349
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1180 #if defined(__amd64) |
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1181 /* 1 GB large page - enable only for 64 bit kernel */ |
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1182 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) |
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1183 feature |= X86_1GPG; |
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1184 #endif |
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1185 |
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
1186 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
1187 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
1188 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
1189 feature |= X86_SSE4A; |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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diff
changeset
|
1190 |
0 | 1191 /* |
3446 | 1192 * If both the HTT and CMP_LGCY bits are set, |
1228 | 1193 * then we're not actually HyperThreaded. Read |
1194 * "AMD CPUID Specification" for more details. | |
0 | 1195 */ |
1196 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
1228 | 1197 (feature & X86_HTT) && |
3446 | 1198 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { |
0 | 1199 feature &= ~X86_HTT; |
1228 | 1200 feature |= X86_CMP; |
1201 } | |
3446 | 1202 #if defined(__amd64) |
0 | 1203 /* |
1204 * It's really tricky to support syscall/sysret in | |
1205 * the i386 kernel; we rely on sysenter/sysexit | |
1206 * instead. In the amd64 kernel, things are -way- | |
1207 * better. | |
1208 */ | |
1209 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) | |
1210 feature |= X86_ASYSC; | |
1211 | |
1212 /* | |
1213 * While we're thinking about system calls, note | |
1214 * that AMD processors don't support sysenter | |
1215 * in long mode at all, so don't try to program them. | |
1216 */ | |
1217 if (x86_vendor == X86_VENDOR_AMD) | |
1218 feature &= ~X86_SEP; | |
1219 #endif | |
6657 | 1220 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) |
3446 | 1221 feature |= X86_TSCP; |
0 | 1222 break; |
1223 default: | |
1224 break; | |
1225 } | |
1226 | |
1228 | 1227 /* |
1228 * Get CPUID data about processor cores and hyperthreads. | |
1229 */ | |
0 | 1230 switch (cpi->cpi_vendor) { |
1231 case X86_VENDOR_Intel: | |
1228 | 1232 if (cpi->cpi_maxeax >= 4) { |
1233 cp = &cpi->cpi_std[4]; | |
1234 cp->cp_eax = 4; | |
1235 cp->cp_ecx = 0; | |
1236 (void) __cpuid_insn(cp); | |
3446 | 1237 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); |
1228 | 1238 } |
1239 /*FALLTHROUGH*/ | |
0 | 1240 case X86_VENDOR_AMD: |
1241 if (cpi->cpi_xmaxeax < 0x80000008) | |
1242 break; | |
1243 cp = &cpi->cpi_extd[8]; | |
1228 | 1244 cp->cp_eax = 0x80000008; |
1245 (void) __cpuid_insn(cp); | |
3446 | 1246 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); |
1247 | |
0 | 1248 /* |
1249 * Virtual and physical address limits from | |
1250 * cpuid override previously guessed values. | |
1251 */ | |
1252 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); | |
1253 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); | |
1254 break; | |
1255 default: | |
1256 break; | |
1257 } | |
1228 | 1258 |
4606 | 1259 /* |
1260 * Derive the number of cores per chip | |
1261 */ | |
1228 | 1262 switch (cpi->cpi_vendor) { |
1263 case X86_VENDOR_Intel: | |
1264 if (cpi->cpi_maxeax < 4) { | |
1265 cpi->cpi_ncore_per_chip = 1; | |
1266 break; | |
1267 } else { | |
1268 cpi->cpi_ncore_per_chip = | |
1269 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; | |
1270 } | |
1271 break; | |
1272 case X86_VENDOR_AMD: | |
1273 if (cpi->cpi_xmaxeax < 0x80000008) { | |
1274 cpi->cpi_ncore_per_chip = 1; | |
1275 break; | |
1276 } else { | |
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
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diff
changeset
|
1277 /* |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
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diff
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|
1278 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
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diff
changeset
|
1279 * 1 less than the number of physical cores on |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1280 * the chip. In family 0x10 this value can |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
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diff
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|
1281 * be affected by "downcoring" - it reflects |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
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diff
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|
1282 * 1 less than the number of cores actually |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
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diff
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|
1283 * enabled on this node. |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
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diff
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|
1284 */ |
1228 | 1285 cpi->cpi_ncore_per_chip = |
1286 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; | |
1287 } | |
1288 break; | |
1289 default: | |
1290 cpi->cpi_ncore_per_chip = 1; | |
1291 break; | |
1292 } | |
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
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8418
diff
changeset
|
1293 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
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diff
changeset
|
1294 /* |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1295 * Get CPUID data about TSC Invariance in Deep C-State. |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1296 */ |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1297 switch (cpi->cpi_vendor) { |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1298 case X86_VENDOR_Intel: |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1299 if (cpi->cpi_maxeax >= 7) { |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1300 cp = &cpi->cpi_extd[7]; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1301 cp->cp_eax = 0x80000007; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
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parents:
8418
diff
changeset
|
1302 cp->cp_ecx = 0; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1303 (void) __cpuid_insn(cp); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1304 } |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1305 break; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1306 default: |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1307 break; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1308 } |
5284 | 1309 } else { |
1310 cpi->cpi_ncore_per_chip = 1; | |
0 | 1311 } |
1312 | |
1228 | 1313 /* |
1314 * If more than one core, then this processor is CMP. | |
1315 */ | |
1316 if (cpi->cpi_ncore_per_chip > 1) | |
1317 feature |= X86_CMP; | |
3446 | 1318 |
1228 | 1319 /* |
1320 * If the number of cores is the same as the number | |
1321 * of CPUs, then we cannot have HyperThreading. | |
1322 */ | |
1323 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) | |
1324 feature &= ~X86_HTT; | |
1325 | |
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1326 cpi->cpi_apicid = CPI_APIC_ID(cpi); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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diff
changeset
|
1327 cpi->cpi_procnodes_per_pkg = 1; |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1328 |
0 | 1329 if ((feature & (X86_HTT | X86_CMP)) == 0) { |
1228 | 1330 /* |
1331 * Single-core single-threaded processors. | |
1332 */ | |
0 | 1333 cpi->cpi_chipid = -1; |
1334 cpi->cpi_clogid = 0; | |
1228 | 1335 cpi->cpi_coreid = cpu->cpu_id; |
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
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5741
diff
changeset
|
1336 cpi->cpi_pkgcoreid = 0; |
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1337 if (cpi->cpi_vendor == X86_VENDOR_AMD) |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1338 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1339 else |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1340 cpi->cpi_procnodeid = cpi->cpi_chipid; |
0 | 1341 } else if (cpi->cpi_ncpu_per_chip > 1) { |
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1342 if (cpi->cpi_vendor == X86_VENDOR_Intel) |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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10175
diff
changeset
|
1343 cpuid_intel_getids(cpu, feature); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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10175
diff
changeset
|
1344 else if (cpi->cpi_vendor == X86_VENDOR_AMD) |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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10175
diff
changeset
|
1345 cpuid_amd_getids(cpu); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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10175
diff
changeset
|
1346 else { |
1228 | 1347 /* |
1348 * All other processors are currently | |
1349 * assumed to have single cores. | |
1350 */ | |
1351 cpi->cpi_coreid = cpi->cpi_chipid; | |
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
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5741
diff
changeset
|
1352 cpi->cpi_pkgcoreid = 0; |
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
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10175
diff
changeset
|
1353 cpi->cpi_procnodeid = cpi->cpi_chipid; |
1228 | 1354 } |
0 | 1355 } |
1356 | |
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1357 /* |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1358 * Synthesize chip "revision" and socket type |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1359 */ |
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1360 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, |
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1361 cpi->cpi_model, cpi->cpi_step); |
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1362 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, |
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1363 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); |
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1364 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, |
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1365 cpi->cpi_model, cpi->cpi_step); |
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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2584
diff
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|
1366 |
0 | 1367 pass1_done: |
1368 cpi->cpi_pass = 1; | |
1369 return (feature); | |
1370 } | |
1371 | |
1372 /* | |
1373 * Make copies of the cpuid table entries we depend on, in | |
1374 * part for ease of parsing now, in part so that we have only | |
1375 * one place to correct any of it, in part for ease of | |
1376 * later export to userland, and in part so we can look at | |
1377 * this stuff in a crash dump. | |
1378 */ | |
1379 | |
1380 /*ARGSUSED*/ | |
1381 void | |
1382 cpuid_pass2(cpu_t *cpu) | |
1383 { | |
1384 uint_t n, nmax; | |
1385 int i; | |
1228 | 1386 struct cpuid_regs *cp; |
0 | 1387 uint8_t *dp; |
1388 uint32_t *iptr; | |
1389 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
1390 | |
1391 ASSERT(cpi->cpi_pass == 1); | |
1392 | |
1393 if (cpi->cpi_maxeax < 1) | |
1394 goto pass2_done; | |
1395 | |
1396 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) | |
1397 nmax = NMAX_CPI_STD; | |
1398 /* | |
1399 * (We already handled n == 0 and n == 1 in pass 1) | |
1400 */ | |
1401 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { | |
1228 | 1402 cp->cp_eax = n; |
4606 | 1403 |
1404 /* | |
1405 * CPUID function 4 expects %ecx to be initialized | |
1406 * with an index which indicates which cache to return | |
1407 * information about. The OS is expected to call function 4 | |
1408 * with %ecx set to 0, 1, 2, ... until it returns with | |
1409 * EAX[4:0] set to 0, which indicates there are no more | |
1410 * caches. | |
1411 * | |
1412 * Here, populate cpi_std[4] with the information returned by | |
1413 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() | |
1414 * when dynamic memory allocation becomes available. | |
1415 * | |
1416 * Note: we need to explicitly initialize %ecx here, since | |
1417 * function 4 may have been previously invoked. | |
1418 */ | |
1419 if (n == 4) | |
1420 cp->cp_ecx = 0; | |
1421 | |
1228 | 1422 (void) __cpuid_insn(cp); |
3446 | 1423 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); |
0 | 1424 switch (n) { |
1425 case 2: | |
1426 /* | |
1427 * "the lower 8 bits of the %eax register | |
1428 * contain a value that identifies the number | |
1429 * of times the cpuid [instruction] has to be | |
1430 * executed to obtain a complete image of the | |
1431 * processor's caching systems." | |
1432 * | |
1433 * How *do* they make this stuff up? | |
1434 */ | |
1435 cpi->cpi_ncache = sizeof (*cp) * | |
1436 BITX(cp->cp_eax, 7, 0); | |
1437 if (cpi->cpi_ncache == 0) | |
1438 break; | |
1439 cpi->cpi_ncache--; /* skip count byte */ | |
1440 | |
1441 /* | |
1442 * Well, for now, rather than attempt to implement | |
1443 * this slightly dubious algorithm, we just look | |
1444 * at the first 15 .. | |
1445 */ | |
1446 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) | |
1447 cpi->cpi_ncache = sizeof (*cp) - 1; | |
1448 | |
1449 dp = cpi->cpi_cacheinfo; | |
1450 if (BITX(cp->cp_eax, 31, 31) == 0) { | |
1451 uint8_t *p = (void *)&cp->cp_eax; | |
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
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5870
diff
changeset
|
1452 for (i = 1; i < 4; i++) |
0 | 1453 if (p[i] != 0) |
1454 *dp++ = p[i]; | |
1455 } | |
1456 if (BITX(cp->cp_ebx, 31, 31) == 0) { | |
1457 uint8_t *p = (void *)&cp->cp_ebx; | |
1458 for (i = 0; i < 4; i++) | |
1459 if (p[i] != 0) | |
1460 *dp++ = p[i]; | |
1461 } | |
1462 if (BITX(cp->cp_ecx, 31, 31) == 0) { | |
1463 uint8_t *p = (void *)&cp->cp_ecx; | |
1464 for (i = 0; i < 4; i++) | |
1465 if (p[i] != 0) | |
1466 *dp++ = p[i]; | |
1467 } | |
1468 if (BITX(cp->cp_edx, 31, 31) == 0) { | |
1469 uint8_t *p = (void *)&cp->cp_edx; | |
1470 for (i = 0; i < 4; i++) | |
1471 if (p[i] != 0) | |
1472 *dp++ = p[i]; | |
1473 } | |
1474 break; | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
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4265
diff
changeset
|
1475 |
0 | 1476 case 3: /* Processor serial number, if PSN supported */ |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1477 break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
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4265
diff
changeset
|
1478 |
0 | 1479 case 4: /* Deterministic cache parameters */ |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1480 break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1481 |
0 | 1482 case 5: /* Monitor/Mwait parameters */ |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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4858
diff
changeset
|
1483 { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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4858
diff
changeset
|
1484 size_t mwait_size; |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
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4265
diff
changeset
|
1485 |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
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|
1486 /* |
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6495392 use monitor/mwait for halting idle CPUs where supported
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diff
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|
1487 * check cpi_mwait.support which was set in cpuid_pass1 |
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6495392 use monitor/mwait for halting idle CPUs where supported
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diff
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|
1488 */ |
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6495392 use monitor/mwait for halting idle CPUs where supported
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diff
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|
1489 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) |
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6495392 use monitor/mwait for halting idle CPUs where supported
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diff
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|
1490 break; |
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diff
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|
1491 |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1492 /* |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
changeset
|
1493 * Protect ourself from insane mwait line size. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1494 * Workaround for incomplete hardware emulator(s). |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
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|
1495 */ |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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diff
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|
1496 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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diff
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|
1497 if (mwait_size < sizeof (uint32_t) || |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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diff
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|
1498 !ISP2(mwait_size)) { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1499 #if DEBUG |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1500 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " |
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
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|
1501 "size %ld", cpu->cpu_id, (long)mwait_size); |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1502 #endif |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1503 break; |
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6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1504 } |
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6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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diff
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|
1505 |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
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diff
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|
1506 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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diff
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|
1507 cpi->cpi_mwait.mon_max = mwait_size; |
4481
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6495392 use monitor/mwait for halting idle CPUs where supported
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|
1508 if (MWAIT_EXTENSION(cpi)) { |
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6495392 use monitor/mwait for halting idle CPUs where supported
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|
1509 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; |
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6495392 use monitor/mwait for halting idle CPUs where supported
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|
1510 if (MWAIT_INT_ENABLE(cpi)) |
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|
1511 cpi->cpi_mwait.support |= |
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|
1512 MWAIT_ECX_INT_ENABLE; |
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6495392 use monitor/mwait for halting idle CPUs where supported
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|
1513 } |
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6495392 use monitor/mwait for halting idle CPUs where supported
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|
1514 break; |
5045
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6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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|
1515 } |
0 | 1516 default: |
1517 break; | |
1518 } | |
1519 } | |
1520 | |
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1521 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { |
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
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|
1522 struct cpuid_regs regs; |
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
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|
1523 |
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
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diff
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|
1524 cp = ®s; |
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1525 cp->cp_eax = 0xB; |
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
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diff
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|
1526 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; |
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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|
1527 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1528 (void) __cpuid_insn(cp); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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diff
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|
1529 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1530 /* |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1531 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
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|
1532 * indicates that the extended topology enumeration leaf is |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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diff
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|
1533 * available. |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1534 */ |
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6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1535 if (cp->cp_ebx) { |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1536 uint32_t x2apic_id; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1537 uint_t coreid_shift = 0; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1538 uint_t ncpu_per_core = 1; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1539 uint_t chipid_shift = 0; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1540 uint_t ncpu_per_chip = 1; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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|
1541 uint_t i; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1542 uint_t level; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1543 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1544 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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diff
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|
1545 cp->cp_eax = 0xB; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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diff
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|
1546 cp->cp_ecx = i; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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diff
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|
1547 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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parents:
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diff
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|
1548 (void) __cpuid_insn(cp); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1549 level = CPI_CPU_LEVEL_TYPE(cp); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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6964
diff
changeset
|
1550 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1551 if (level == 1) { |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
changeset
|
1552 x2apic_id = cp->cp_edx; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
changeset
|
1553 coreid_shift = BITX(cp->cp_eax, 4, 0); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1554 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
changeset
|
1555 } else if (level == 2) { |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1556 x2apic_id = cp->cp_edx; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1557 chipid_shift = BITX(cp->cp_eax, 4, 0); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1558 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1559 } |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1560 } |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1561 |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1562 cpi->cpi_apicid = x2apic_id; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1563 cpi->cpi_ncpu_per_chip = ncpu_per_chip; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1564 cpi->cpi_ncore_per_chip = ncpu_per_chip / |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1565 ncpu_per_core; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1566 cpi->cpi_chipid = x2apic_id >> chipid_shift; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1567 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
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6964
diff
changeset
|
1568 cpi->cpi_coreid = x2apic_id >> coreid_shift; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
changeset
|
1569 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
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diff
changeset
|
1570 } |
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1571 |
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1572 /* Make cp NULL so that we don't stumble on others */ |
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
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|
1573 cp = NULL; |
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1574 } |
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
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diff
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|
1575 |
0 | 1576 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) |
1577 goto pass2_done; | |
1578 | |
1579 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) | |
1580 nmax = NMAX_CPI_EXTD; | |
1581 /* | |
1582 * Copy the extended properties, fixing them as we go. | |
1583 * (We already handled n == 0 and n == 1 in pass 1) | |
1584 */ | |
1585 iptr = (void *)cpi->cpi_brandstr; | |
1586 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { | |
1228 | 1587 cp->cp_eax = 0x80000000 + n; |
1588 (void) __cpuid_insn(cp); | |
3446 | 1589 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); |
0 | 1590 switch (n) { |
1591 case 2: | |
1592 case 3: | |
1593 case 4: | |
1594 /* | |
1595 * Extract the brand string | |
1596 */ | |
1597 *iptr++ = cp->cp_eax; | |
1598 *iptr++ = cp->cp_ebx; | |
1599 *iptr++ = cp->cp_ecx; | |
1600 *iptr++ = cp->cp_edx; | |
1601 break; | |
1602 case 5: | |
1603 switch (cpi->cpi_vendor) { | |
1604 case X86_VENDOR_AMD: | |
1605 /* | |
1606 * The Athlon and Duron were the first | |
1607 * parts to report the sizes of the | |
1608 * TLB for large pages. Before then, | |
1609 * we don't trust the data. | |
1610 */ | |
1611 if (cpi->cpi_family < 6 || | |
1612 (cpi->cpi_family == 6 && | |
1613 cpi->cpi_model < 1)) | |
1614 cp->cp_eax = 0; | |
1615 break; | |
1616 default: | |
1617 break; | |
1618 } | |
1619 break; | |
1620 case 6: | |
1621 switch (cpi->cpi_vendor) { | |
1622 case X86_VENDOR_AMD: | |
1623 /* | |
1624 * The Athlon and Duron were the first | |
1625 * AMD parts with L2 TLB's. | |
1626 * Before then, don't trust the data. | |
1627 */ | |
1628 if (cpi->cpi_family < 6 || | |
1629 cpi->cpi_family == 6 && | |
1630 cpi->cpi_model < 1) | |
1631 cp->cp_eax = cp->cp_ebx = 0; | |
1632 /* | |
1633 * AMD Duron rev A0 reports L2 | |
1634 * cache size incorrectly as 1K | |
1635 * when it is really 64K | |
1636 */ | |
1637 if (cpi->cpi_family == 6 && | |
1638 cpi->cpi_model == 3 && | |
1639 cpi->cpi_step == 0) { | |
1640 cp->cp_ecx &= 0xffff; | |
1641 cp->cp_ecx |= 0x400000; | |
1642 } | |
1643 break; | |
1644 case X86_VENDOR_Cyrix: /* VIA C3 */ | |
1645 /* | |
1646 * VIA C3 processors are a bit messed | |
1647 * up w.r.t. encoding cache sizes in %ecx | |
1648 */ | |
1649 if (cpi->cpi_family != 6) | |
1650 break; | |
1651 /* | |
1652 * model 7 and 8 were incorrectly encoded | |
1653 * | |
1654 * xxx is model 8 really broken? | |
1655 */ | |
1656 if (cpi->cpi_model == 7 || | |
1657 cpi->cpi_model == 8) | |
1658 cp->cp_ecx = | |
1659 BITX(cp->cp_ecx, 31, 24) << 16 | | |
1660 BITX(cp->cp_ecx, 23, 16) << 12 | | |
1661 BITX(cp->cp_ecx, 15, 8) << 8 | | |
1662 BITX(cp->cp_ecx, 7, 0); | |
1663 /* | |
1664 * model 9 stepping 1 has wrong associativity | |
1665 */ | |
1666 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) | |
1667 cp->cp_ecx |= 8 << 12; | |
1668 break; | |
1669 case X86_VENDOR_Intel: | |
1670 /* | |
1671 * Extended L2 Cache features function. | |
1672 * First appeared on Prescott. | |
1673 */ | |
1674 default: | |
1675 break; | |
1676 } | |
1677 break; | |
1678 default: | |
1679 break; | |
1680 } | |
1681 } | |
1682 | |
1683 pass2_done: | |
1684 cpi->cpi_pass = 2; | |
1685 } | |
1686 | |
1687 static const char * | |
1688 intel_cpubrand(const struct cpuid_info *cpi) | |
1689 { | |
1690 int i; | |
1691 | |
1692 if ((x86_feature & X86_CPUID) == 0 || | |
1693 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
1694 return ("i486"); | |
1695 | |
1696 switch (cpi->cpi_family) { | |
1697 case 5: | |
1698 return ("Intel Pentium(r)"); | |
1699 case 6: | |
1700 switch (cpi->cpi_model) { | |
1701 uint_t celeron, xeon; | |
1228 | 1702 const struct cpuid_regs *cp; |
0 | 1703 case 0: |
1704 case 1: | |
1705 case 2: | |
1706 return ("Intel Pentium(r) Pro"); | |
1707 case 3: | |
1708 case 4: | |
1709 return ("Intel Pentium(r) II"); | |
1710 case 6: | |
1711 return ("Intel Celeron(r)"); | |
1712 case 5: | |
1713 case 7: | |
1714 celeron = xeon = 0; | |
1715 cp = &cpi->cpi_std[2]; /* cache info */ | |
1716 | |
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
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diff
changeset
|
1717 for (i = 1; i < 4; i++) { |
0 | 1718 uint_t tmp; |
1719 | |
1720 tmp = (cp->cp_eax >> (8 * i)) & 0xff; | |
1721 if (tmp == 0x40) | |
1722 celeron++; | |
1723 if (tmp >= 0x44 && tmp <= 0x45) | |
1724 xeon++; | |
1725 } | |
1726 | |
1727 for (i = 0; i < 2; i++) { | |
1728 uint_t tmp; | |
1729 | |
1730 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; | |
1731 if (tmp == 0x40) | |
1732 celeron++; | |
1733 else if (tmp >= 0x44 && tmp <= 0x45) | |
1734 xeon++; | |
1735 } | |
1736 | |
1737 for (i = 0; i < 4; i++) { | |
1738 uint_t tmp; | |
1739 | |
1740 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; | |
1741 if (tmp == 0x40) | |
1742 celeron++; | |
1743 else if (tmp >= 0x44 && tmp <= 0x45) | |
1744 xeon++; | |
1745 } | |
1746 | |
1747 for (i = 0; i < 4; i++) { | |
1748 uint_t tmp; | |
1749 | |
1750 tmp = (cp->cp_edx >> (8 * i)) & 0xff; | |
1751 if (tmp == 0x40) | |
1752 celeron++; | |
1753 else if (tmp >= 0x44 && tmp <= 0x45) | |
1754 xeon++; | |
1755 } | |
1756 | |
1757 if (celeron) | |
1758 return ("Intel Celeron(r)"); | |
1759 if (xeon) | |
1760 return (cpi->cpi_model == 5 ? | |
1761 "Intel Pentium(r) II Xeon(tm)" : | |
1762 "Intel Pentium(r) III Xeon(tm)"); | |
1763 return (cpi->cpi_model == 5 ? | |
1764 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : | |
1765 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); | |
1766 default: | |
1767 break; | |
1768 } | |
1769 default: | |
1770 break; | |
1771 } | |
1772 | |
1975
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1773 /* BrandID is present if the field is nonzero */ |
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1774 if (cpi->cpi_brandid != 0) { |
0 | 1775 static const struct { |
1776 uint_t bt_bid; | |
1777 const char *bt_str; | |
1778 } brand_tbl[] = { | |
1779 { 0x1, "Intel(r) Celeron(r)" }, | |
1780 { 0x2, "Intel(r) Pentium(r) III" }, | |
1781 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, | |
1782 { 0x4, "Intel(r) Pentium(r) III" }, | |
1783 { 0x6, "Mobile Intel(r) Pentium(r) III" }, | |
1784 { 0x7, "Mobile Intel(r) Celeron(r)" }, | |
1785 { 0x8, "Intel(r) Pentium(r) 4" }, | |
1786 { 0x9, "Intel(r) Pentium(r) 4" }, | |
1787 { 0xa, "Intel(r) Celeron(r)" }, | |
1788 { 0xb, "Intel(r) Xeon(tm)" }, | |
1789 { 0xc, "Intel(r) Xeon(tm) MP" }, | |
1790 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, | |
1975
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1791 { 0xf, "Mobile Intel(r) Celeron(r)" }, |
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1792 { 0x11, "Mobile Genuine Intel(r)" }, |
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1793 { 0x12, "Intel(r) Celeron(r) M" }, |
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1794 { 0x13, "Mobile Intel(r) Celeron(r)" }, |
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1795 { 0x14, "Intel(r) Celeron(r)" }, |
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1796 { 0x15, "Mobile Genuine Intel(r)" }, |
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1797 { 0x16, "Intel(r) Pentium(r) M" }, |
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1798 { 0x17, "Mobile Intel(r) Celeron(r)" } |
0 | 1799 }; |
1800 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); | |
1801 uint_t sgn; | |
1802 | |
1803 sgn = (cpi->cpi_family << 8) | | |
1804 (cpi->cpi_model << 4) | cpi->cpi_step; | |
1805 | |
1806 for (i = 0; i < btblmax; i++) | |
1807 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) | |
1808 break; | |
1809 if (i < btblmax) { | |
1810 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) | |
1811 return ("Intel(r) Celeron(r)"); | |
1812 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) | |
1813 return ("Intel(r) Xeon(tm) MP"); | |
1814 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) | |
1815 return ("Intel(r) Xeon(tm)"); | |
1816 return (brand_tbl[i].bt_str); | |
1817 } | |
1818 } | |
1819 | |
1820 return (NULL); | |
1821 } | |
1822 | |
1823 static const char * | |
1824 amd_cpubrand(const struct cpuid_info *cpi) | |
1825 { | |
1826 if ((x86_feature & X86_CPUID) == 0 || | |
1827 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) | |
1828 return ("i486 compatible"); | |
1829 | |
1830 switch (cpi->cpi_family) { | |
1831 case 5: | |
1832 switch (cpi->cpi_model) { | |
1833 case 0: | |
1834 case 1: | |
1835 case 2: | |
1836 case 3: | |
1837 case 4: | |
1838 case 5: | |
1839 return ("AMD-K5(r)"); | |
1840 case 6: | |
1841 case 7: | |
1842 return ("AMD-K6(r)"); | |
1843 case 8: | |
1844 return ("AMD-K6(r)-2"); | |
1845 case 9: | |
1846 return ("AMD-K6(r)-III"); | |
1847 default: | |
1848 return ("AMD (family 5)"); | |
1849 } | |
1850 case 6: | |
1851 switch (cpi->cpi_model) { | |
1852 case 1: | |
1853 return ("AMD-K7(tm)"); | |
1854 case 0: | |
1855 case 2: | |
1856 case 4: | |
1857 return ("AMD Athlon(tm)"); | |
1858 case 3: | |
1859 case 7: | |
1860 return ("AMD Duron(tm)"); | |
1861 case 6: | |
1862 case 8: | |
1863 case 10: | |
1864 /* | |
1865 * Use the L2 cache size to distinguish | |
1866 */ | |
1867 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? | |
1868 "AMD Athlon(tm)" : "AMD Duron(tm)"); | |
1869 default: | |
1870 return ("AMD (family 6)"); | |
1871 } | |
1872 default: | |
1873 break; | |
1874 } | |
1875 | |
1876 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && | |
1877 cpi->cpi_brandid != 0) { | |
1878 switch (BITX(cpi->cpi_brandid, 7, 5)) { | |
1879 case 3: | |
1880 return ("AMD Opteron(tm) UP 1xx"); | |
1881 case 4: | |
1882 return ("AMD Opteron(tm) DP 2xx"); | |
1883 case 5: | |
1884 return ("AMD Opteron(tm) MP 8xx"); | |
1885 default: | |
1886 return ("AMD Opteron(tm)"); | |
1887 } | |
1888 } | |
1889 | |
1890 return (NULL); | |
1891 } | |
1892 | |
1893 static const char * | |
1894 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) | |
1895 { | |
1896 if ((x86_feature & X86_CPUID) == 0 || | |
1897 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || | |
1898 type == X86_TYPE_CYRIX_486) | |
1899 return ("i486 compatible"); | |
1900 | |
1901 switch (type) { | |
1902 case X86_TYPE_CYRIX_6x86: | |
1903 return ("Cyrix 6x86"); | |
1904 case X86_TYPE_CYRIX_6x86L: | |
1905 return ("Cyrix 6x86L"); | |
1906 case X86_TYPE_CYRIX_6x86MX: | |
1907 return ("Cyrix 6x86MX"); | |
1908 case X86_TYPE_CYRIX_GXm: | |
1909 return ("Cyrix GXm"); | |
1910 case X86_TYPE_CYRIX_MediaGX: | |
1911 return ("Cyrix MediaGX"); | |
1912 case X86_TYPE_CYRIX_MII: | |
1913 return ("Cyrix M2"); | |
1914 case X86_TYPE_VIA_CYRIX_III: | |
1915 return ("VIA Cyrix M3"); | |
1916 default: | |
1917 /* | |
1918 * Have another wild guess .. | |
1919 */ | |
1920 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) | |
1921 return ("Cyrix 5x86"); | |
1922 else if (cpi->cpi_family == 5) { | |
1923 switch (cpi->cpi_model) { | |
1924 case 2: | |
1925 return ("Cyrix 6x86"); /* Cyrix M1 */ | |
1926 case 4: | |
1927 return ("Cyrix MediaGX"); | |
1928 default: | |
1929 break; | |
1930 } | |
1931 } else if (cpi->cpi_family == 6) { | |
1932 switch (cpi->cpi_model) { | |
1933 case 0: | |
1934 return ("Cyrix 6x86MX"); /* Cyrix M2? */ | |
1935 case 5: | |
1936 case 6: | |
1937 case 7: | |
1938 case 8: | |
1939 case 9: | |
1940 return ("VIA C3"); | |
1941 default: | |
1942 break; | |
1943 } | |
1944 } | |
1945 break; | |
1946 } | |
1947 return (NULL); | |
1948 } | |
1949 | |
1950 /* | |
1951 * This only gets called in the case that the CPU extended | |
1952 * feature brand string (0x80000002, 0x80000003, 0x80000004) | |
1953 * aren't available, or contain null bytes for some reason. | |
1954 */ | |
1955 static void | |
1956 fabricate_brandstr(struct cpuid_info *cpi) | |
1957 { | |
1958 const char *brand = NULL; | |
1959 | |
1960 switch (cpi->cpi_vendor) { | |
1961 case X86_VENDOR_Intel: | |
1962 brand = intel_cpubrand(cpi); | |
1963 break; | |
1964 case X86_VENDOR_AMD: | |
1965 brand = amd_cpubrand(cpi); | |
1966 break; | |
1967 case X86_VENDOR_Cyrix: | |
1968 brand = cyrix_cpubrand(cpi, x86_type); | |
1969 break; | |
1970 case X86_VENDOR_NexGen: | |
1971 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
1972 brand = "NexGen Nx586"; | |
1973 break; | |
1974 case X86_VENDOR_Centaur: | |
1975 if (cpi->cpi_family == 5) | |
1976 switch (cpi->cpi_model) { | |
1977 case 4: | |
1978 brand = "Centaur C6"; | |
1979 break; | |
1980 case 8: | |
1981 brand = "Centaur C2"; | |
1982 break; | |
1983 case 9: | |
1984 brand = "Centaur C3"; | |
1985 break; | |
1986 default: | |
1987 break; | |
1988 } | |
1989 break; | |
1990 case X86_VENDOR_Rise: | |
1991 if (cpi->cpi_family == 5 && | |
1992 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) | |
1993 brand = "Rise mP6"; | |
1994 break; | |
1995 case X86_VENDOR_SiS: | |
1996 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
1997 brand = "SiS 55x"; | |
1998 break; | |
1999 case X86_VENDOR_TM: | |
2000 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) | |
2001 brand = "Transmeta Crusoe TM3x00 or TM5x00"; | |
2002 break; | |
2003 case X86_VENDOR_NSC: | |
2004 case X86_VENDOR_UMC: | |
2005 default: | |
2006 break; | |
2007 } | |
2008 if (brand) { | |
2009 (void) strcpy((char *)cpi->cpi_brandstr, brand); | |
2010 return; | |
2011 } | |
2012 | |
2013 /* | |
2014 * If all else fails ... | |
2015 */ | |
2016 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), | |
2017 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, | |
2018 cpi->cpi_model, cpi->cpi_step); | |
2019 } | |
2020 | |
2021 /* | |
2022 * This routine is called just after kernel memory allocation | |
2023 * becomes available on cpu0, and as part of mp_startup() on | |
2024 * the other cpus. | |
2025 * | |
4606 | 2026 * Fixup the brand string, and collect any information from cpuid |
2027 * that requires dynamicically allocated storage to represent. | |
0 | 2028 */ |
2029 /*ARGSUSED*/ | |
2030 void | |
2031 cpuid_pass3(cpu_t *cpu) | |
2032 { | |
4606 | 2033 int i, max, shft, level, size; |
2034 struct cpuid_regs regs; | |
2035 struct cpuid_regs *cp; | |
0 | 2036 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
2037 | |
2038 ASSERT(cpi->cpi_pass == 2); | |
2039 | |
4606 | 2040 /* |
2041 * Function 4: Deterministic cache parameters | |
2042 * | |
2043 * Take this opportunity to detect the number of threads | |
2044 * sharing the last level cache, and construct a corresponding | |
2045 * cache id. The respective cpuid_info members are initialized | |
2046 * to the default case of "no last level cache sharing". | |
2047 */ | |
2048 cpi->cpi_ncpu_shr_last_cache = 1; | |
2049 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; | |
2050 | |
2051 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { | |
2052 | |
2053 /* | |
2054 * Find the # of elements (size) returned by fn 4, and along | |
2055 * the way detect last level cache sharing details. | |
2056 */ | |
2057 bzero(®s, sizeof (regs)); | |
2058 cp = ®s; | |
2059 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { | |
2060 cp->cp_eax = 4; | |
2061 cp->cp_ecx = i; | |
2062 | |
2063 (void) __cpuid_insn(cp); | |
2064 | |
2065 if (CPI_CACHE_TYPE(cp) == 0) | |
2066 break; | |
2067 level = CPI_CACHE_LVL(cp); | |
2068 if (level > max) { | |
2069 max = level; | |
2070 cpi->cpi_ncpu_shr_last_cache = | |
2071 CPI_NTHR_SHR_CACHE(cp) + 1; | |
2072 } | |
2073 } | |
2074 cpi->cpi_std_4_size = size = i; | |
2075 | |
2076 /* | |
2077 * Allocate the cpi_std_4 array. The first element | |
2078 * references the regs for fn 4, %ecx == 0, which | |
2079 * cpuid_pass2() stashed in cpi->cpi_std[4]. | |
2080 */ | |
2081 if (size > 0) { | |
2082 cpi->cpi_std_4 = | |
2083 kmem_alloc(size * sizeof (cp), KM_SLEEP); | |
2084 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; | |
2085 | |
2086 /* | |
2087 * Allocate storage to hold the additional regs | |
2088 * for function 4, %ecx == 1 .. cpi_std_4_size. | |
2089 * | |
2090 * The regs for fn 4, %ecx == 0 has already | |
2091 * been allocated as indicated above. | |
2092 */ | |
2093 for (i = 1; i < size; i++) { | |
2094 cp = cpi->cpi_std_4[i] = | |
2095 kmem_zalloc(sizeof (regs), KM_SLEEP); | |
2096 cp->cp_eax = 4; | |
2097 cp->cp_ecx = i; | |
2098 | |
2099 (void) __cpuid_insn(cp); | |
2100 } | |
2101 } | |
2102 /* | |
2103 * Determine the number of bits needed to represent | |
2104 * the number of CPUs sharing the last level cache. | |
2105 * | |
2106 * Shift off that number of bits from the APIC id to | |
2107 * derive the cache id. | |
2108 */ | |
2109 shft = 0; | |
2110 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) | |
2111 shft++; | |
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2112 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; |
0 | 2113 } |
2114 | |
2115 /* | |
4606 | 2116 * Now fixup the brand string |
0 | 2117 */ |
4606 | 2118 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { |
2119 fabricate_brandstr(cpi); | |
2120 } else { | |
0 | 2121 |
2122 /* | |
4606 | 2123 * If we successfully extracted a brand string from the cpuid |
2124 * instruction, clean it up by removing leading spaces and | |
2125 * similar junk. | |
0 | 2126 */ |
4606 | 2127 if (cpi->cpi_brandstr[0]) { |
2128 size_t maxlen = sizeof (cpi->cpi_brandstr); | |
2129 char *src, *dst; | |
2130 | |
2131 dst = src = (char *)cpi->cpi_brandstr; | |
2132 src[maxlen - 1] = '\0'; | |
2133 /* | |
2134 * strip leading spaces | |
2135 */ | |
2136 while (*src == ' ') | |
2137 src++; | |
2138 /* | |
2139 * Remove any 'Genuine' or "Authentic" prefixes | |
2140 */ | |
2141 if (strncmp(src, "Genuine ", 8) == 0) | |
2142 src += 8; | |
2143 if (strncmp(src, "Authentic ", 10) == 0) | |
2144 src += 10; | |
2145 | |
2146 /* | |
2147 * Now do an in-place copy. | |
2148 * Map (R) to (r) and (TM) to (tm). | |
2149 * The era of teletypes is long gone, and there's | |
2150 * -really- no need to shout. | |
2151 */ | |
2152 while (*src != '\0') { | |
2153 if (src[0] == '(') { | |
2154 if (strncmp(src + 1, "R)", 2) == 0) { | |
2155 (void) strncpy(dst, "(r)", 3); | |
2156 src += 3; | |
2157 dst += 3; | |
2158 continue; | |
2159 } | |
2160 if (strncmp(src + 1, "TM)", 3) == 0) { | |
2161 (void) strncpy(dst, "(tm)", 4); | |
2162 src += 4; | |
2163 dst += 4; | |
2164 continue; | |
2165 } | |
0 | 2166 } |
4606 | 2167 *dst++ = *src++; |
0 | 2168 } |
4606 | 2169 *dst = '\0'; |
2170 | |
2171 /* | |
2172 * Finally, remove any trailing spaces | |
2173 */ | |
2174 while (--dst > cpi->cpi_brandstr) | |
2175 if (*dst == ' ') | |
2176 *dst = '\0'; | |
2177 else | |
2178 break; | |
2179 } else | |
2180 fabricate_brandstr(cpi); | |
2181 } | |
0 | 2182 cpi->cpi_pass = 3; |
2183 } | |
2184 | |
2185 /* | |
2186 * This routine is called out of bind_hwcap() much later in the life | |
2187 * of the kernel (post_startup()). The job of this routine is to resolve | |
2188 * the hardware feature support and kernel support for those features into | |
2189 * what we're actually going to tell applications via the aux vector. | |
2190 */ | |
2191 uint_t | |
2192 cpuid_pass4(cpu_t *cpu) | |
2193 { | |
2194 struct cpuid_info *cpi; | |
2195 uint_t hwcap_flags = 0; | |
2196 | |
2197 if (cpu == NULL) | |
2198 cpu = CPU; | |
2199 cpi = cpu->cpu_m.mcpu_cpi; | |
2200 | |
2201 ASSERT(cpi->cpi_pass == 3); | |
2202 | |
2203 if (cpi->cpi_maxeax >= 1) { | |
2204 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; | |
2205 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; | |
2206 | |
2207 *edx = CPI_FEATURES_EDX(cpi); | |
2208 *ecx = CPI_FEATURES_ECX(cpi); | |
2209 | |
2210 /* | |
2211 * [these require explicit kernel support] | |
2212 */ | |
2213 if ((x86_feature & X86_SEP) == 0) | |
2214 *edx &= ~CPUID_INTC_EDX_SEP; | |
2215 | |
2216 if ((x86_feature & X86_SSE) == 0) | |
2217 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); | |
2218 if ((x86_feature & X86_SSE2) == 0) | |
2219 *edx &= ~CPUID_INTC_EDX_SSE2; | |
2220 | |
2221 if ((x86_feature & X86_HTT) == 0) | |
2222 *edx &= ~CPUID_INTC_EDX_HTT; | |
2223 | |
2224 if ((x86_feature & X86_SSE3) == 0) | |
2225 *ecx &= ~CPUID_INTC_ECX_SSE3; | |
2226 | |
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2227 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
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2228 if ((x86_feature & X86_SSSE3) == 0) |
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2229 *ecx &= ~CPUID_INTC_ECX_SSSE3; |
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2230 if ((x86_feature & X86_SSE4_1) == 0) |
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2231 *ecx &= ~CPUID_INTC_ECX_SSE4_1; |
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2232 if ((x86_feature & X86_SSE4_2) == 0) |
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2233 *ecx &= ~CPUID_INTC_ECX_SSE4_2; |
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2234 if ((x86_feature & X86_AES) == 0) |
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|
2235 *ecx &= ~CPUID_INTC_ECX_AES; |
5269
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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diff
changeset
|
2236 } |
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
2237 |
0 | 2238 /* |
2239 * [no explicit support required beyond x87 fp context] | |
2240 */ | |
2241 if (!fpu_exists) | |
2242 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); | |
2243 | |
2244 /* | |
2245 * Now map the supported feature vector to things that we | |
2246 * think userland will care about. | |
2247 */ | |
2248 if (*edx & CPUID_INTC_EDX_SEP) | |
2249 hwcap_flags |= AV_386_SEP; | |
2250 if (*edx & CPUID_INTC_EDX_SSE) | |
2251 hwcap_flags |= AV_386_FXSR | AV_386_SSE; | |
2252 if (*edx & CPUID_INTC_EDX_SSE2) | |
2253 hwcap_flags |= AV_386_SSE2; | |
2254 if (*ecx & CPUID_INTC_ECX_SSE3) | |
2255 hwcap_flags |= AV_386_SSE3; | |
5269
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
2256 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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diff
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|
2257 if (*ecx & CPUID_INTC_ECX_SSSE3) |
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
2258 hwcap_flags |= AV_386_SSSE3; |
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
2259 if (*ecx & CPUID_INTC_ECX_SSE4_1) |
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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|
2260 hwcap_flags |= AV_386_SSE4_1; |
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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diff
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|
2261 if (*ecx & CPUID_INTC_ECX_SSE4_2) |
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6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
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5254
diff
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|
2262 hwcap_flags |= AV_386_SSE4_2; |
8418
a4853cd72a21
6719310 Expose availability of MOVBE instruction
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
8377
diff
changeset
|
2263 if (*ecx & CPUID_INTC_ECX_MOVBE) |
a4853cd72a21
6719310 Expose availability of MOVBE instruction
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
8377
diff
changeset
|
2264 hwcap_flags |= AV_386_MOVBE; |
9370
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2265 if (*ecx & CPUID_INTC_ECX_AES) |
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2266 hwcap_flags |= AV_386_AES; |
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
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9283
diff
changeset
|
2267 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) |
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
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9283
diff
changeset
|
2268 hwcap_flags |= AV_386_PCLMULQDQ; |
5269
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|
2269 } |
4628
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6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
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|
2270 if (*ecx & CPUID_INTC_ECX_POPCNT) |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2271 hwcap_flags |= AV_386_POPCNT; |
0 | 2272 if (*edx & CPUID_INTC_EDX_FPU) |
2273 hwcap_flags |= AV_386_FPU; | |
2274 if (*edx & CPUID_INTC_EDX_MMX) | |
2275 hwcap_flags |= AV_386_MMX; | |
2276 | |
2277 if (*edx & CPUID_INTC_EDX_TSC) | |
2278 hwcap_flags |= AV_386_TSC; | |
2279 if (*edx & CPUID_INTC_EDX_CX8) | |
2280 hwcap_flags |= AV_386_CX8; | |
2281 if (*edx & CPUID_INTC_EDX_CMOV) | |
2282 hwcap_flags |= AV_386_CMOV; | |
2283 if (*ecx & CPUID_INTC_ECX_MON) | |
2284 hwcap_flags |= AV_386_MON; | |
2285 if (*ecx & CPUID_INTC_ECX_CX16) | |
2286 hwcap_flags |= AV_386_CX16; | |
2287 } | |
2288 | |
1228 | 2289 if (x86_feature & X86_HTT) |
0 | 2290 hwcap_flags |= AV_386_PAUSE; |
2291 | |
2292 if (cpi->cpi_xmaxeax < 0x80000001) | |
2293 goto pass4_done; | |
2294 | |
2295 switch (cpi->cpi_vendor) { | |
1228 | 2296 struct cpuid_regs cp; |
3446 | 2297 uint32_t *edx, *ecx; |
0 | 2298 |
3446 | 2299 case X86_VENDOR_Intel: |
2300 /* | |
2301 * Seems like Intel duplicated what we necessary | |
2302 * here to make the initial crop of 64-bit OS's work. | |
2303 * Hopefully, those are the only "extended" bits | |
2304 * they'll add. | |
2305 */ | |
2306 /*FALLTHROUGH*/ | |
2307 | |
0 | 2308 case X86_VENDOR_AMD: |
2309 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; | |
3446 | 2310 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; |
0 | 2311 |
2312 *edx = CPI_FEATURES_XTD_EDX(cpi); | |
3446 | 2313 *ecx = CPI_FEATURES_XTD_ECX(cpi); |
2314 | |
2315 /* | |
2316 * [these features require explicit kernel support] | |
2317 */ | |
2318 switch (cpi->cpi_vendor) { | |
2319 case X86_VENDOR_Intel: | |
6657 | 2320 if ((x86_feature & X86_TSCP) == 0) |
2321 *edx &= ~CPUID_AMD_EDX_TSCP; | |
3446 | 2322 break; |
2323 | |
2324 case X86_VENDOR_AMD: | |
2325 if ((x86_feature & X86_TSCP) == 0) | |
2326 *edx &= ~CPUID_AMD_EDX_TSCP; | |
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2327 if ((x86_feature & X86_SSE4A) == 0) |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2328 *ecx &= ~CPUID_AMD_ECX_SSE4A; |
3446 | 2329 break; |
2330 | |
2331 default: | |
2332 break; | |
2333 } | |
0 | 2334 |
2335 /* | |
2336 * [no explicit support required beyond | |
2337 * x87 fp context and exception handlers] | |
2338 */ | |
2339 if (!fpu_exists) | |
2340 *edx &= ~(CPUID_AMD_EDX_MMXamd | | |
2341 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); | |
2342 | |
2343 if ((x86_feature & X86_NX) == 0) | |
2344 *edx &= ~CPUID_AMD_EDX_NX; | |
3446 | 2345 #if !defined(__amd64) |
0 | 2346 *edx &= ~CPUID_AMD_EDX_LM; |
2347 #endif | |
2348 /* | |
2349 * Now map the supported feature vector to | |
2350 * things that we think userland will care about. | |
2351 */ | |
3446 | 2352 #if defined(__amd64) |
0 | 2353 if (*edx & CPUID_AMD_EDX_SYSC) |
2354 hwcap_flags |= AV_386_AMD_SYSC; | |
3446 | 2355 #endif |
0 | 2356 if (*edx & CPUID_AMD_EDX_MMXamd) |
2357 hwcap_flags |= AV_386_AMD_MMX; | |
2358 if (*edx & CPUID_AMD_EDX_3DNow) | |
2359 hwcap_flags |= AV_386_AMD_3DNow; | |
2360 if (*edx & CPUID_AMD_EDX_3DNowx) | |
2361 hwcap_flags |= AV_386_AMD_3DNowx; | |
3446 | 2362 |
2363 switch (cpi->cpi_vendor) { | |
2364 case X86_VENDOR_AMD: | |
2365 if (*edx & CPUID_AMD_EDX_TSCP) | |
2366 hwcap_flags |= AV_386_TSCP; | |
2367 if (*ecx & CPUID_AMD_ECX_AHF64) | |
2368 hwcap_flags |= AV_386_AHF; | |
4628
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6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
2369 if (*ecx & CPUID_AMD_ECX_SSE4A) |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2370 hwcap_flags |= AV_386_AMD_SSE4A; |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
2371 if (*ecx & CPUID_AMD_ECX_LZCNT) |
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
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4606
diff
changeset
|
2372 hwcap_flags |= AV_386_AMD_LZCNT; |
3446 | 2373 break; |
2374 | |
2375 case X86_VENDOR_Intel: | |
6657 | 2376 if (*edx & CPUID_AMD_EDX_TSCP) |
2377 hwcap_flags |= AV_386_TSCP; | |
3446 | 2378 /* |
2379 * Aarrgh. | |
2380 * Intel uses a different bit in the same word. | |
2381 */ | |
2382 if (*ecx & CPUID_INTC_ECX_AHF64) | |
2383 hwcap_flags |= AV_386_AHF; | |
2384 break; | |
2385 | |
2386 default: | |
2387 break; | |
2388 } | |
0 | 2389 break; |
2390 | |
2391 case X86_VENDOR_TM: | |
1228 | 2392 cp.cp_eax = 0x80860001; |
2393 (void) __cpuid_insn(&cp); | |
2394 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; | |
0 | 2395 break; |
2396 | |
2397 default: | |
2398 break; | |
2399 } | |
2400 | |
2401 pass4_done: | |
2402 cpi->cpi_pass = 4; | |
2403 return (hwcap_flags); | |
2404 } | |
2405 | |
2406 | |
2407 /* | |
2408 * Simulate the cpuid instruction using the data we previously | |
2409 * captured about this CPU. We try our best to return the truth | |
2410 * about the hardware, independently of kernel support. | |
2411 */ | |
2412 uint32_t | |
1228 | 2413 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) |
0 | 2414 { |
2415 struct cpuid_info *cpi; | |
1228 | 2416 struct cpuid_regs *xcp; |
0 | 2417 |
2418 if (cpu == NULL) | |
2419 cpu = CPU; | |
2420 cpi = cpu->cpu_m.mcpu_cpi; | |
2421 | |
2422 ASSERT(cpuid_checkpass(cpu, 3)); | |
2423 | |
2424 /* | |
2425 * CPUID data is cached in two separate places: cpi_std for standard | |
2426 * CPUID functions, and cpi_extd for extended CPUID functions. | |
2427 */ | |
1228 | 2428 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) |
2429 xcp = &cpi->cpi_std[cp->cp_eax]; | |
2430 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && | |
2431 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) | |
2432 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; | |
0 | 2433 else |
2434 /* | |
2435 * The caller is asking for data from an input parameter which | |
2436 * the kernel has not cached. In this case we go fetch from | |
2437 * the hardware and return the data directly to the user. | |
2438 */ | |
1228 | 2439 return (__cpuid_insn(cp)); |
2440 | |
2441 cp->cp_eax = xcp->cp_eax; | |
2442 cp->cp_ebx = xcp->cp_ebx; | |
2443 cp->cp_ecx = xcp->cp_ecx; | |
2444 cp->cp_edx = xcp->cp_edx; | |
0 | 2445 return (cp->cp_eax); |
2446 } | |
2447 | |
2448 int | |
2449 cpuid_checkpass(cpu_t *cpu, int pass) | |
2450 { | |
2451 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && | |
2452 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); | |
2453 } | |
2454 | |
2455 int | |
2456 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) | |
2457 { | |
2458 ASSERT(cpuid_checkpass(cpu, 3)); | |
2459 | |
2460 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); | |
2461 } | |
2462 | |
2463 int | |
1228 | 2464 cpuid_is_cmt(cpu_t *cpu) |
0 | 2465 { |
2466 if (cpu == NULL) | |
2467 cpu = CPU; | |
2468 | |
2469 ASSERT(cpuid_checkpass(cpu, 1)); | |
2470 | |
2471 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); | |
2472 } | |
2473 | |
2474 /* | |
2475 * AMD and Intel both implement the 64-bit variant of the syscall | |
2476 * instruction (syscallq), so if there's -any- support for syscall, | |
2477 * cpuid currently says "yes, we support this". | |
2478 * | |
2479 * However, Intel decided to -not- implement the 32-bit variant of the | |
2480 * syscall instruction, so we provide a predicate to allow our caller | |
2481 * to test that subtlety here. | |
5084 | 2482 * |
2483 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, | |
2484 * even in the case where the hardware would in fact support it. | |
0 | 2485 */ |
2486 /*ARGSUSED*/ | |
2487 int | |
2488 cpuid_syscall32_insn(cpu_t *cpu) | |
2489 { | |
2490 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); | |
2491 | |
5084 | 2492 #if !defined(__xpv) |
3446 | 2493 if (cpu == NULL) |
2494 cpu = CPU; | |
2495 | |
2496 /*CSTYLED*/ | |
2497 { | |
2498 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
2499 | |
2500 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
2501 cpi->cpi_xmaxeax >= 0x80000001 && | |
2502 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) | |
2503 return (1); | |
2504 } | |
5084 | 2505 #endif |
0 | 2506 return (0); |
2507 } | |
2508 | |
2509 int | |
2510 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) | |
2511 { | |
2512 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
2513 | |
2514 static const char fmt[] = | |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2515 "x86 (%s %X family %d model %d step %d clock %d MHz)"; |
0 | 2516 static const char fmt_ht[] = |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2517 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; |
0 | 2518 |
2519 ASSERT(cpuid_checkpass(cpu, 1)); | |
2520 | |
1228 | 2521 if (cpuid_is_cmt(cpu)) |
0 | 2522 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2523 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2524 cpi->cpi_family, cpi->cpi_model, |
0 | 2525 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
2526 return (snprintf(s, n, fmt, | |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2527 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2528 cpi->cpi_family, cpi->cpi_model, |
0 | 2529 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
2530 } | |
2531 | |
2532 const char * | |
2533 cpuid_getvendorstr(cpu_t *cpu) | |
2534 { | |
2535 ASSERT(cpuid_checkpass(cpu, 1)); | |
2536 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); | |
2537 } | |
2538 | |
2539 uint_t | |
2540 cpuid_getvendor(cpu_t *cpu) | |
2541 { | |
2542 ASSERT(cpuid_checkpass(cpu, 1)); | |
2543 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); | |
2544 } | |
2545 | |
2546 uint_t | |
2547 cpuid_getfamily(cpu_t *cpu) | |
2548 { | |
2549 ASSERT(cpuid_checkpass(cpu, 1)); | |
2550 return (cpu->cpu_m.mcpu_cpi->cpi_family); | |
2551 } | |
2552 | |
2553 uint_t | |
2554 cpuid_getmodel(cpu_t *cpu) | |
2555 { | |
2556 ASSERT(cpuid_checkpass(cpu, 1)); | |
2557 return (cpu->cpu_m.mcpu_cpi->cpi_model); | |
2558 } | |
2559 | |
2560 uint_t | |
2561 cpuid_get_ncpu_per_chip(cpu_t *cpu) | |
2562 { | |
2563 ASSERT(cpuid_checkpass(cpu, 1)); | |
2564 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); | |
2565 } | |
2566 | |
2567 uint_t | |
1228 | 2568 cpuid_get_ncore_per_chip(cpu_t *cpu) |
2569 { | |
2570 ASSERT(cpuid_checkpass(cpu, 1)); | |
2571 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); | |
2572 } | |
2573 | |
2574 uint_t | |
4606 | 2575 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) |
2576 { | |
2577 ASSERT(cpuid_checkpass(cpu, 2)); | |
2578 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); | |
2579 } | |
2580 | |
2581 id_t | |
2582 cpuid_get_last_lvl_cacheid(cpu_t *cpu) | |
2583 { | |
2584 ASSERT(cpuid_checkpass(cpu, 2)); | |
2585 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); | |
2586 } | |
2587 | |
2588 uint_t | |
0 | 2589 cpuid_getstep(cpu_t *cpu) |
2590 { | |
2591 ASSERT(cpuid_checkpass(cpu, 1)); | |
2592 return (cpu->cpu_m.mcpu_cpi->cpi_step); | |
2593 } | |
2594 | |
4581 | 2595 uint_t |
2596 cpuid_getsig(struct cpu *cpu) | |
2597 { | |
2598 ASSERT(cpuid_checkpass(cpu, 1)); | |
2599 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); | |
2600 } | |
2601 | |
2869
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diff
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|
2602 uint32_t |
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2584
diff
changeset
|
2603 cpuid_getchiprev(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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2584
diff
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|
2604 { |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2605 ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2606 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
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2584
diff
changeset
|
2607 } |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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2584
diff
changeset
|
2608 |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
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2584
diff
changeset
|
2609 const char * |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2610 cpuid_getchiprevstr(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
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2584
diff
changeset
|
2611 { |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
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parents:
2584
diff
changeset
|
2612 ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2613 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2614 } |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2615 |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2616 uint32_t |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2617 cpuid_getsockettype(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2618 { |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2619 ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2620 return (cpu->cpu_m.mcpu_cpi->cpi_socket); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2621 } |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2622 |
9482
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2623 const char * |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2624 cpuid_getsocketstr(cpu_t *cpu) |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2625 { |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2626 static const char *socketstr = NULL; |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2627 struct cpuid_info *cpi; |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2628 |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2629 ASSERT(cpuid_checkpass(cpu, 1)); |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2630 cpi = cpu->cpu_m.mcpu_cpi; |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2631 |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2632 /* Assume that socket types are the same across the system */ |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2633 if (socketstr == NULL) |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2634 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2635 cpi->cpi_model, cpi->cpi_step); |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2636 |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2637 |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2638 return (socketstr); |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2639 } |
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2640 |
3434 | 2641 int |
2642 cpuid_get_chipid(cpu_t *cpu) | |
0 | 2643 { |
2644 ASSERT(cpuid_checkpass(cpu, 1)); | |
2645 | |
1228 | 2646 if (cpuid_is_cmt(cpu)) |
0 | 2647 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); |
2648 return (cpu->cpu_id); | |
2649 } | |
2650 | |
1228 | 2651 id_t |
3434 | 2652 cpuid_get_coreid(cpu_t *cpu) |
1228 | 2653 { |
2654 ASSERT(cpuid_checkpass(cpu, 1)); | |
2655 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); | |
2656 } | |
2657 | |
0 | 2658 int |
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2659 cpuid_get_pkgcoreid(cpu_t *cpu) |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2660 { |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2661 ASSERT(cpuid_checkpass(cpu, 1)); |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2662 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2663 } |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2664 |
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2665 int |
3434 | 2666 cpuid_get_clogid(cpu_t *cpu) |
0 | 2667 { |
2668 ASSERT(cpuid_checkpass(cpu, 1)); | |
2669 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); | |
2670 } | |
2671 | |
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2672 uint_t |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2673 cpuid_get_procnodeid(cpu_t *cpu) |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2674 { |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2675 ASSERT(cpuid_checkpass(cpu, 1)); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2676 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2677 } |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2678 |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2679 uint_t |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2680 cpuid_get_procnodes_per_pkg(cpu_t *cpu) |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2681 { |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2682 ASSERT(cpuid_checkpass(cpu, 1)); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2683 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg); |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2684 } |
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2685 |
10080
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2686 /*ARGSUSED*/ |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2687 int |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2688 cpuid_have_cr8access(cpu_t *cpu) |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2689 { |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2690 #if defined(__amd64) |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2691 return (1); |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2692 #else |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2693 struct cpuid_info *cpi; |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2694 |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2695 ASSERT(cpu != NULL); |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2696 cpi = cpu->cpu_m.mcpu_cpi; |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2697 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2698 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2699 return (1); |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2700 return (0); |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2701 #endif |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2702 } |
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
2703 |
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2704 uint32_t |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2705 cpuid_get_apicid(cpu_t *cpu) |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2706 { |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2707 ASSERT(cpuid_checkpass(cpu, 1)); |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2708 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2709 return (UINT32_MAX); |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2710 } else { |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2711 return (cpu->cpu_m.mcpu_cpi->cpi_apicid); |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2712 } |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2713 } |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
2714 |
0 | 2715 void |
2716 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) | |
2717 { | |
2718 struct cpuid_info *cpi; | |
2719 | |
2720 if (cpu == NULL) | |
2721 cpu = CPU; | |
2722 cpi = cpu->cpu_m.mcpu_cpi; | |
2723 | |
2724 ASSERT(cpuid_checkpass(cpu, 1)); | |
2725 | |
2726 if (pabits) | |
2727 *pabits = cpi->cpi_pabits; | |
2728 if (vabits) | |
2729 *vabits = cpi->cpi_vabits; | |
2730 } | |
2731 | |
2732 /* | |
2733 * Returns the number of data TLB entries for a corresponding | |
2734 * pagesize. If it can't be computed, or isn't known, the | |
2735 * routine returns zero. If you ask about an architecturally | |
2736 * impossible pagesize, the routine will panic (so that the | |
2737 * hat implementor knows that things are inconsistent.) | |
2738 */ | |
2739 uint_t | |
2740 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) | |
2741 { | |
2742 struct cpuid_info *cpi; | |
2743 uint_t dtlb_nent = 0; | |
2744 | |
2745 if (cpu == NULL) | |
2746 cpu = CPU; | |
2747 cpi = cpu->cpu_m.mcpu_cpi; | |
2748 | |
2749 ASSERT(cpuid_checkpass(cpu, 1)); | |
2750 | |
2751 /* | |
2752 * Check the L2 TLB info | |
2753 */ | |
2754 if (cpi->cpi_xmaxeax >= 0x80000006) { | |
1228 | 2755 struct cpuid_regs *cp = &cpi->cpi_extd[6]; |
0 | 2756 |
2757 switch (pagesize) { | |
2758 | |
2759 case 4 * 1024: | |
2760 /* | |
2761 * All zero in the top 16 bits of the register | |
2762 * indicates a unified TLB. Size is in low 16 bits. | |
2763 */ | |
2764 if ((cp->cp_ebx & 0xffff0000) == 0) | |
2765 dtlb_nent = cp->cp_ebx & 0x0000ffff; | |
2766 else | |
2767 dtlb_nent = BITX(cp->cp_ebx, 27, 16); | |
2768 break; | |
2769 | |
2770 case 2 * 1024 * 1024: | |
2771 if ((cp->cp_eax & 0xffff0000) == 0) | |
2772 dtlb_nent = cp->cp_eax & 0x0000ffff; | |
2773 else | |
2774 dtlb_nent = BITX(cp->cp_eax, 27, 16); | |
2775 break; | |
2776 | |
2777 default: | |
2778 panic("unknown L2 pagesize"); | |
2779 /*NOTREACHED*/ | |
2780 } | |
2781 } | |
2782 | |
2783 if (dtlb_nent != 0) | |
2784 return (dtlb_nent); | |
2785 | |
2786 /* | |
2787 * No L2 TLB support for this size, try L1. | |
2788 */ | |
2789 if (cpi->cpi_xmaxeax >= 0x80000005) { | |
1228 | 2790 struct cpuid_regs *cp = &cpi->cpi_extd[5]; |
0 | 2791 |
2792 switch (pagesize) { | |
2793 case 4 * 1024: | |
2794 dtlb_nent = BITX(cp->cp_ebx, 23, 16); | |
2795 break; | |
2796 case 2 * 1024 * 1024: | |
2797 dtlb_nent = BITX(cp->cp_eax, 23, 16); | |
2798 break; | |
2799 default: | |
2800 panic("unknown L1 d-TLB pagesize"); | |
2801 /*NOTREACHED*/ | |
2802 } | |
2803 } | |
2804 | |
2805 return (dtlb_nent); | |
2806 } | |
2807 | |
2808 /* | |
2809 * Return 0 if the erratum is not present or not applicable, positive | |
2810 * if it is, and negative if the status of the erratum is unknown. | |
2811 * | |
2812 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) | |
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
2813 * Processors" #25759, Rev 3.57, August 2005 |
0 | 2814 */ |
2815 int | |
2816 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) | |
2817 { | |
2818 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
1228 | 2819 uint_t eax; |
0 | 2820 |
2584
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2821 /* |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2822 * Bail out if this CPU isn't an AMD CPU, or if it's |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2823 * a legacy (32-bit) AMD CPU. |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2824 */ |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2825 if (cpi->cpi_vendor != X86_VENDOR_AMD || |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2826 cpi->cpi_family == 4 || cpi->cpi_family == 5 || |
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2827 cpi->cpi_family == 6) |
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2828 |
0 | 2829 return (0); |
2830 | |
2831 eax = cpi->cpi_std[1].cp_eax; | |
2832 | |
2833 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) | |
2834 #define SH_B3(eax) (eax == 0xf51) | |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2835 #define B(eax) (SH_B0(eax) || SH_B3(eax)) |
0 | 2836 |
2837 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) | |
2838 | |
2839 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) | |
2840 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) | |
2841 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) | |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2842 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) |
0 | 2843 |
2844 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) | |
2845 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) | |
2846 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) | |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2847 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) |
0 | 2848 |
2849 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) | |
2850 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ | |
2851 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) | |
2852 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) | |
2853 #define BH_E4(eax) (eax == 0x20fb1) | |
2854 #define SH_E5(eax) (eax == 0x20f42) | |
2855 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) | |
2856 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) | |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2857 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2858 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2859 DH_E6(eax) || JH_E6(eax)) |
0 | 2860 |
6691
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6671130 Shanghai provides better TLB management for 1GB pages
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parents:
6671
diff
changeset
|
2861 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
2862 #define DR_B0(eax) (eax == 0x100f20) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
6671
diff
changeset
|
2863 #define DR_B1(eax) (eax == 0x100f21) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
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diff
changeset
|
2864 #define DR_BA(eax) (eax == 0x100f2a) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2865 #define DR_B2(eax) (eax == 0x100f22) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
2866 #define DR_B3(eax) (eax == 0x100f23) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
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diff
changeset
|
2867 #define RB_C0(eax) (eax == 0x100f40) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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6671
diff
changeset
|
2868 |
0 | 2869 switch (erratum) { |
2870 case 1: | |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2871 return (cpi->cpi_family < 0x10); |
0 | 2872 case 51: /* what does the asterisk mean? */ |
2873 return (B(eax) || SH_C0(eax) || CG(eax)); | |
2874 case 52: | |
2875 return (B(eax)); | |
2876 case 57: | |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
6671
diff
changeset
|
2877 return (cpi->cpi_family <= 0x11); |
0 | 2878 case 58: |
2879 return (B(eax)); | |
2880 case 60: | |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
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diff
changeset
|
2881 return (cpi->cpi_family <= 0x11); |
0 | 2882 case 61: |
2883 case 62: | |
2884 case 63: | |
2885 case 64: | |
2886 case 65: | |
2887 case 66: | |
2888 case 68: | |
2889 case 69: | |
2890 case 70: | |
2891 case 71: | |
2892 return (B(eax)); | |
2893 case 72: | |
2894 return (SH_B0(eax)); | |
2895 case 74: | |
2896 return (B(eax)); | |
2897 case 75: | |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2898 return (cpi->cpi_family < 0x10); |
0 | 2899 case 76: |
2900 return (B(eax)); | |
2901 case 77: | |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
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diff
changeset
|
2902 return (cpi->cpi_family <= 0x11); |
0 | 2903 case 78: |
2904 return (B(eax) || SH_C0(eax)); | |
2905 case 79: | |
2906 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
2907 case 80: | |
2908 case 81: | |
2909 case 82: | |
2910 return (B(eax)); | |
2911 case 83: | |
2912 return (B(eax) || SH_C0(eax) || CG(eax)); | |
2913 case 85: | |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2914 return (cpi->cpi_family < 0x10); |
0 | 2915 case 86: |
2916 return (SH_C0(eax) || CG(eax)); | |
2917 case 88: | |
2918 #if !defined(__amd64) | |
2919 return (0); | |
2920 #else | |
2921 return (B(eax) || SH_C0(eax)); | |
2922 #endif | |
2923 case 89: | |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2924 return (cpi->cpi_family < 0x10); |
0 | 2925 case 90: |
2926 return (B(eax) || SH_C0(eax) || CG(eax)); | |
2927 case 91: | |
2928 case 92: | |
2929 return (B(eax) || SH_C0(eax)); | |
2930 case 93: | |
2931 return (SH_C0(eax)); | |
2932 case 94: | |
2933 return (B(eax) || SH_C0(eax) || CG(eax)); | |
2934 case 95: | |
2935 #if !defined(__amd64) | |
2936 return (0); | |
2937 #else | |
2938 return (B(eax) || SH_C0(eax)); | |
2939 #endif | |
2940 case 96: | |
2941 return (B(eax) || SH_C0(eax) || CG(eax)); | |
2942 case 97: | |
2943 case 98: | |
2944 return (SH_C0(eax) || CG(eax)); | |
2945 case 99: | |
2946 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
2947 case 100: | |
2948 return (B(eax) || SH_C0(eax)); | |
2949 case 101: | |
2950 case 103: | |
2951 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
2952 case 104: | |
2953 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
2954 case 105: | |
2955 case 106: | |
2956 case 107: | |
2957 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
2958 case 108: | |
2959 return (DH_CG(eax)); | |
2960 case 109: | |
2961 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
2962 case 110: | |
2963 return (D0(eax) || EX(eax)); | |
2964 case 111: | |
2965 return (CG(eax)); | |
2966 case 112: | |
2967 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
2968 case 113: | |
2969 return (eax == 0x20fc0); | |
2970 case 114: | |
2971 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
2972 case 115: | |
2973 return (SH_E0(eax) || JH_E1(eax)); | |
2974 case 116: | |
2975 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
2976 case 117: | |
2977 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
2978 case 118: | |
2979 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || | |
2980 JH_E6(eax)); | |
2981 case 121: | |
2982 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
2983 case 122: | |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
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diff
changeset
|
2984 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); |
0 | 2985 case 123: |
2986 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); | |
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
2987 case 131: |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2988 return (cpi->cpi_family < 0x10); |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2989 case 6336786: |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2990 /* |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2991 * Test for AdvPowerMgmtInfo.TscPStateInvariant |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2992 * if this is a K8 family or newer processor |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2993 */ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2994 if (CPI_FAMILY(cpi) == 0xf) { |
1228 | 2995 struct cpuid_regs regs; |
2996 regs.cp_eax = 0x80000007; | |
2997 (void) __cpuid_insn(®s); | |
2998 return (!(regs.cp_edx & 0x100)); | |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2999 } |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3000 return (0); |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3001 case 6323525: |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3002 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3003 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3004 |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3005 case 6671130: |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3006 /* |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3007 * check for processors (pre-Shanghai) that do not provide |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3008 * optimal management of 1gb ptes in its tlb. |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
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diff
changeset
|
3009 */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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6671
diff
changeset
|
3010 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3011 |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3012 case 298: |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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parents:
6671
diff
changeset
|
3013 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3014 DR_B2(eax) || RB_C0(eax)); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3015 |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3016 default: |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3017 return (-1); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3018 |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3019 } |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3020 } |
f8848c7acc9e
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diff
changeset
|
3021 |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3022 /* |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3023 * Determine if specified erratum is present via OSVW (OS Visible Workaround). |
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diff
changeset
|
3024 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3025 */ |
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diff
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|
3026 int |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3027 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3028 { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3029 struct cpuid_info *cpi; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3030 uint_t osvwid; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3031 static int osvwfeature = -1; |
f8848c7acc9e
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|
3032 uint64_t osvwlength; |
f8848c7acc9e
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changeset
|
3033 |
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|
3034 |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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|
3035 cpi = cpu->cpu_m.mcpu_cpi; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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|
3036 |
f8848c7acc9e
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changeset
|
3037 /* confirm OSVW supported */ |
f8848c7acc9e
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changeset
|
3038 if (osvwfeature == -1) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3039 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3040 } else { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3041 /* assert that osvw feature setting is consistent on all cpus */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3042 ASSERT(osvwfeature == |
f8848c7acc9e
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changeset
|
3043 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3044 } |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3045 if (!osvwfeature) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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diff
changeset
|
3046 return (-1); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3047 |
f8848c7acc9e
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changeset
|
3048 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; |
f8848c7acc9e
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|
3049 |
f8848c7acc9e
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changeset
|
3050 switch (erratum) { |
f8848c7acc9e
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diff
changeset
|
3051 case 298: /* osvwid is 0 */ |
f8848c7acc9e
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changeset
|
3052 osvwid = 0; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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changeset
|
3053 if (osvwlength <= (uint64_t)osvwid) { |
f8848c7acc9e
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changeset
|
3054 /* osvwid 0 is unknown */ |
f8848c7acc9e
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changeset
|
3055 return (-1); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
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|
3056 } |
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|
3057 |
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|
3058 /* |
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|
3059 * Check the OSVW STATUS MSR to determine the state |
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|
3060 * of the erratum where: |
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|
3061 * 0 - fixed by HW |
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3062 * 1 - BIOS has applied the workaround when BIOS |
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|
3063 * workaround is available. (Or for other errata, |
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|
3064 * OS workaround is required.) |
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|
3065 * For a value of 1, caller will confirm that the |
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|
3066 * erratum 298 workaround has indeed been applied by BIOS. |
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|
3067 * |
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3068 * A 1 may be set in cpus that have a HW fix |
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|
3069 * in a mixed cpu system. Regarding erratum 298: |
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|
3070 * In a multiprocessor platform, the workaround above |
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3071 * should be applied to all processors regardless of |
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|
3072 * silicon revision when an affected processor is |
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|
3073 * present. |
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|
3074 */ |
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|
3075 |
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|
3076 return (rdmsr(MSR_AMD_OSVW_STATUS + |
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|
3077 (osvwid / OSVW_ID_CNT_PER_MSR)) & |
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|
3078 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); |
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|
3079 |
0 | 3080 default: |
3081 return (-1); | |
3082 } | |
3083 } | |
3084 | |
3085 static const char assoc_str[] = "associativity"; | |
3086 static const char line_str[] = "line-size"; | |
3087 static const char size_str[] = "size"; | |
3088 | |
3089 static void | |
3090 add_cache_prop(dev_info_t *devi, const char *label, const char *type, | |
3091 uint32_t val) | |
3092 { | |
3093 char buf[128]; | |
3094 | |
3095 /* | |
3096 * ndi_prop_update_int() is used because it is desirable for | |
3097 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. | |
3098 */ | |
3099 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) | |
3100 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); | |
3101 } | |
3102 | |
3103 /* | |
3104 * Intel-style cache/tlb description | |
3105 * | |
3106 * Standard cpuid level 2 gives a randomly ordered | |
3107 * selection of tags that index into a table that describes | |
3108 * cache and tlb properties. | |
3109 */ | |
3110 | |
3111 static const char l1_icache_str[] = "l1-icache"; | |
3112 static const char l1_dcache_str[] = "l1-dcache"; | |
3113 static const char l2_cache_str[] = "l2-cache"; | |
3446 | 3114 static const char l3_cache_str[] = "l3-cache"; |
0 | 3115 static const char itlb4k_str[] = "itlb-4K"; |
3116 static const char dtlb4k_str[] = "dtlb-4K"; | |
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3117 static const char itlb2M_str[] = "itlb-2M"; |
0 | 3118 static const char itlb4M_str[] = "itlb-4M"; |
3119 static const char dtlb4M_str[] = "dtlb-4M"; | |
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3120 static const char dtlb24_str[] = "dtlb0-2M-4M"; |
0 | 3121 static const char itlb424_str[] = "itlb-4K-2M-4M"; |
6334
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3122 static const char itlb24_str[] = "itlb-2M-4M"; |
0 | 3123 static const char dtlb44_str[] = "dtlb-4K-4M"; |
3124 static const char sl1_dcache_str[] = "sectored-l1-dcache"; | |
3125 static const char sl2_cache_str[] = "sectored-l2-cache"; | |
3126 static const char itrace_str[] = "itrace-cache"; | |
3127 static const char sl3_cache_str[] = "sectored-l3-cache"; | |
6334
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3128 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; |
0 | 3129 |
3130 static const struct cachetab { | |
3131 uint8_t ct_code; | |
3132 uint8_t ct_assoc; | |
3133 uint16_t ct_line_size; | |
3134 size_t ct_size; | |
3135 const char *ct_label; | |
3136 } intel_ctab[] = { | |
6964
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3137 /* |
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|
3138 * maintain descending order! |
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|
3139 * |
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|
3140 * Codes ignored - Reason |
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|
3141 * ---------------------- |
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|
3142 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache |
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|
3143 * f0H/f1H - Currently we do not interpret prefetch size by design |
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|
3144 */ |
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3145 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, |
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3146 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, |
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3147 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, |
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3148 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, |
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|
3149 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, |
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3150 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, |
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3151 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, |
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3152 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, |
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3153 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, |
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3154 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, |
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3155 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, |
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3156 { 0xd0, 4, 64, 512*1024, l3_cache_str}, |
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3157 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, |
6964
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|
3158 { 0xc0, 4, 0, 8, dtlb44_str }, |
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|
3159 { 0xba, 4, 0, 64, dtlb4k_str }, |
3446 | 3160 { 0xb4, 4, 0, 256, dtlb4k_str }, |
0 | 3161 { 0xb3, 4, 0, 128, dtlb4k_str }, |
6334
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|
3162 { 0xb2, 4, 0, 64, itlb4k_str }, |
0 | 3163 { 0xb0, 4, 0, 128, itlb4k_str }, |
3164 { 0x87, 8, 64, 1024*1024, l2_cache_str}, | |
3165 { 0x86, 4, 64, 512*1024, l2_cache_str}, | |
3166 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, | |
3167 { 0x84, 8, 32, 1024*1024, l2_cache_str}, | |
3168 { 0x83, 8, 32, 512*1024, l2_cache_str}, | |
3169 { 0x82, 8, 32, 256*1024, l2_cache_str}, | |
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|
3170 { 0x80, 8, 64, 512*1024, l2_cache_str}, |
0 | 3171 { 0x7f, 2, 64, 512*1024, l2_cache_str}, |
3172 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, | |
3173 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, | |
3174 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, | |
3175 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, | |
3176 { 0x79, 8, 64, 128*1024, sl2_cache_str}, | |
3177 { 0x78, 8, 64, 1024*1024, l2_cache_str}, | |
3446 | 3178 { 0x73, 8, 0, 64*1024, itrace_str}, |
0 | 3179 { 0x72, 8, 0, 32*1024, itrace_str}, |
3180 { 0x71, 8, 0, 16*1024, itrace_str}, | |
3181 { 0x70, 8, 0, 12*1024, itrace_str}, | |
3182 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, | |
3183 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, | |
3184 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, | |
3185 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, | |
3186 { 0x5d, 0, 0, 256, dtlb44_str}, | |
3187 { 0x5c, 0, 0, 128, dtlb44_str}, | |
3188 { 0x5b, 0, 0, 64, dtlb44_str}, | |
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3189 { 0x5a, 4, 0, 32, dtlb24_str}, |
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|
3190 { 0x59, 0, 0, 16, dtlb4k_str}, |
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|
3191 { 0x57, 4, 0, 16, dtlb4k_str}, |
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|
3192 { 0x56, 4, 0, 16, dtlb4M_str}, |
6334
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3193 { 0x55, 0, 0, 7, itlb24_str}, |
0 | 3194 { 0x52, 0, 0, 256, itlb424_str}, |
3195 { 0x51, 0, 0, 128, itlb424_str}, | |
3196 { 0x50, 0, 0, 64, itlb424_str}, | |
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|
3197 { 0x4f, 0, 0, 32, itlb4k_str}, |
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|
3198 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, |
3446 | 3199 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, |
3200 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, | |
3201 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, | |
3202 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, | |
3203 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, | |
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|
3204 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, |
3446 | 3205 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, |
3206 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, | |
0 | 3207 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, |
3208 { 0x44, 4, 32, 1024*1024, l2_cache_str}, | |
3209 { 0x43, 4, 32, 512*1024, l2_cache_str}, | |
3210 { 0x42, 4, 32, 256*1024, l2_cache_str}, | |
3211 { 0x41, 4, 32, 128*1024, l2_cache_str}, | |
3446 | 3212 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, |
3213 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, | |
0 | 3214 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, |
3215 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, | |
3446 | 3216 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, |
0 | 3217 { 0x39, 4, 64, 128*1024, sl2_cache_str}, |
3218 { 0x30, 8, 64, 32*1024, l1_icache_str}, | |
3219 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, | |
3220 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, | |
3221 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, | |
3222 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, | |
3223 { 0x22, 4, 64, 512*1024, sl3_cache_str}, | |
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3224 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, |
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3225 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, |
0 | 3226 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, |
3446 | 3227 { 0x0b, 4, 0, 4, itlb4M_str}, |
0 | 3228 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, |
3229 { 0x08, 4, 32, 16*1024, l1_icache_str}, | |
3230 { 0x06, 4, 32, 8*1024, l1_icache_str}, | |
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3231 { 0x05, 4, 0, 32, dtlb4M_str}, |
0 | 3232 { 0x04, 4, 0, 8, dtlb4M_str}, |
3233 { 0x03, 4, 0, 64, dtlb4k_str}, | |
3234 { 0x02, 4, 0, 2, itlb4M_str}, | |
3235 { 0x01, 4, 0, 32, itlb4k_str}, | |
3236 { 0 } | |
3237 }; | |
3238 | |
3239 static const struct cachetab cyrix_ctab[] = { | |
3240 { 0x70, 4, 0, 32, "tlb-4K" }, | |
3241 { 0x80, 4, 16, 16*1024, "l1-cache" }, | |
3242 { 0 } | |
3243 }; | |
3244 | |
3245 /* | |
3246 * Search a cache table for a matching entry | |
3247 */ | |
3248 static const struct cachetab * | |
3249 find_cacheent(const struct cachetab *ct, uint_t code) | |
3250 { | |
3251 if (code != 0) { | |
3252 for (; ct->ct_code != 0; ct++) | |
3253 if (ct->ct_code <= code) | |
3254 break; | |
3255 if (ct->ct_code == code) | |
3256 return (ct); | |
3257 } | |
3258 return (NULL); | |
3259 } | |
3260 | |
3261 /* | |
5438
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3262 * Populate cachetab entry with L2 or L3 cache-information using |
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3263 * cpuid function 4. This function is called from intel_walk_cacheinfo() |
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3264 * when descriptor 0x49 is encountered. It returns 0 if no such cache |
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3265 * information is found. |
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3266 */ |
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3267 static int |
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3268 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) |
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3269 { |
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3270 uint32_t level, i; |
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3271 int ret = 0; |
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3272 |
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|
3273 for (i = 0; i < cpi->cpi_std_4_size; i++) { |
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3274 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); |
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|
3275 |
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|
3276 if (level == 2 || level == 3) { |
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|
3277 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; |
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|
3278 ct->ct_line_size = |
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|
3279 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; |
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3280 ct->ct_size = ct->ct_assoc * |
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3281 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * |
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|
3282 ct->ct_line_size * |
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|
3283 (cpi->cpi_std_4[i]->cp_ecx + 1); |
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|
3284 |
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|
3285 if (level == 2) { |
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|
3286 ct->ct_label = l2_cache_str; |
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|
3287 } else if (level == 3) { |
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3288 ct->ct_label = l3_cache_str; |
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|
3289 } |
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|
3290 ret = 1; |
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|
3291 } |
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|
3292 } |
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|
3293 |
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|
3294 return (ret); |
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|
3295 } |
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|
3296 |
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|
3297 /* |
0 | 3298 * Walk the cacheinfo descriptor, applying 'func' to every valid element |
3299 * The walk is terminated if the walker returns non-zero. | |
3300 */ | |
3301 static void | |
3302 intel_walk_cacheinfo(struct cpuid_info *cpi, | |
3303 void *arg, int (*func)(void *, const struct cachetab *)) | |
3304 { | |
3305 const struct cachetab *ct; | |
6964
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|
3306 struct cachetab des_49_ct, des_b1_ct; |
0 | 3307 uint8_t *dp; |
3308 int i; | |
3309 | |
3310 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
3311 return; | |
4797
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|
3312 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { |
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|
3313 /* |
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6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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|
3314 * For overloaded descriptor 0x49 we use cpuid function 4 |
5438
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|
3315 * if supported by the current processor, to create |
4797
2ebe22df4dfc
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|
3316 * cache information. |
6964
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diff
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|
3317 * For overloaded descriptor 0xb1 we use X86_PAE flag |
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diff
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|
3318 * to disambiguate the cache information. |
4797
2ebe22df4dfc
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|
3319 */ |
5438
41d8edfa90d7
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|
3320 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && |
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|
3321 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { |
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|
3322 ct = &des_49_ct; |
6964
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diff
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|
3323 } else if (*dp == 0xb1) { |
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diff
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|
3324 des_b1_ct.ct_code = 0xb1; |
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|
3325 des_b1_ct.ct_assoc = 4; |
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|
3326 des_b1_ct.ct_line_size = 0; |
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|
3327 if (x86_feature & X86_PAE) { |
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|
3328 des_b1_ct.ct_size = 8; |
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|
3329 des_b1_ct.ct_label = itlb2M_str; |
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diff
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|
3330 } else { |
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diff
changeset
|
3331 des_b1_ct.ct_size = 4; |
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|
3332 des_b1_ct.ct_label = itlb4M_str; |
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diff
changeset
|
3333 } |
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diff
changeset
|
3334 ct = &des_b1_ct; |
5438
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6603986 Installing a Linux zone on an Intel blade causes a panic
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diff
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|
3335 } else { |
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6603986 Installing a Linux zone on an Intel blade causes a panic
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|
3336 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { |
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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diff
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|
3337 continue; |
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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5349
diff
changeset
|
3338 } |
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
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diff
changeset
|
3339 } |
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6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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diff
changeset
|
3340 |
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
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diff
changeset
|
3341 if (func(arg, ct) != 0) { |
41d8edfa90d7
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diff
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|
3342 break; |
0 | 3343 } |
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
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diff
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|
3344 } |
0 | 3345 } |
3346 | |
3347 /* | |
3348 * (Like the Intel one, except for Cyrix CPUs) | |
3349 */ | |
3350 static void | |
3351 cyrix_walk_cacheinfo(struct cpuid_info *cpi, | |
3352 void *arg, int (*func)(void *, const struct cachetab *)) | |
3353 { | |
3354 const struct cachetab *ct; | |
3355 uint8_t *dp; | |
3356 int i; | |
3357 | |
3358 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
3359 return; | |
3360 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { | |
3361 /* | |
3362 * Search Cyrix-specific descriptor table first .. | |
3363 */ | |
3364 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { | |
3365 if (func(arg, ct) != 0) | |
3366 break; | |
3367 continue; | |
3368 } | |
3369 /* | |
3370 * .. else fall back to the Intel one | |
3371 */ | |
3372 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { | |
3373 if (func(arg, ct) != 0) | |
3374 break; | |
3375 continue; | |
3376 } | |
3377 } | |
3378 } | |
3379 | |
3380 /* | |
3381 * A cacheinfo walker that adds associativity, line-size, and size properties | |
3382 * to the devinfo node it is passed as an argument. | |
3383 */ | |
3384 static int | |
3385 add_cacheent_props(void *arg, const struct cachetab *ct) | |
3386 { | |
3387 dev_info_t *devi = arg; | |
3388 | |
3389 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); | |
3390 if (ct->ct_line_size != 0) | |
3391 add_cache_prop(devi, ct->ct_label, line_str, | |
3392 ct->ct_line_size); | |
3393 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); | |
3394 return (0); | |
3395 } | |
3396 | |
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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diff
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|
3397 |
0 | 3398 static const char fully_assoc[] = "fully-associative?"; |
3399 | |
3400 /* | |
3401 * AMD style cache/tlb description | |
3402 * | |
3403 * Extended functions 5 and 6 directly describe properties of | |
3404 * tlbs and various cache levels. | |
3405 */ | |
3406 static void | |
3407 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
3408 { | |
3409 switch (assoc) { | |
3410 case 0: /* reserved; ignore */ | |
3411 break; | |
3412 default: | |
3413 add_cache_prop(devi, label, assoc_str, assoc); | |
3414 break; | |
3415 case 0xff: | |
3416 add_cache_prop(devi, label, fully_assoc, 1); | |
3417 break; | |
3418 } | |
3419 } | |
3420 | |
3421 static void | |
3422 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
3423 { | |
3424 if (size == 0) | |
3425 return; | |
3426 add_cache_prop(devi, label, size_str, size); | |
3427 add_amd_assoc(devi, label, assoc); | |
3428 } | |
3429 | |
3430 static void | |
3431 add_amd_cache(dev_info_t *devi, const char *label, | |
3432 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
3433 { | |
3434 if (size == 0 || line_size == 0) | |
3435 return; | |
3436 add_amd_assoc(devi, label, assoc); | |
3437 /* | |
3438 * Most AMD parts have a sectored cache. Multiple cache lines are | |
3439 * associated with each tag. A sector consists of all cache lines | |
3440 * associated with a tag. For example, the AMD K6-III has a sector | |
3441 * size of 2 cache lines per tag. | |
3442 */ | |
3443 if (lines_per_tag != 0) | |
3444 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
3445 add_cache_prop(devi, label, line_str, line_size); | |
3446 add_cache_prop(devi, label, size_str, size * 1024); | |
3447 } | |
3448 | |
3449 static void | |
3450 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
3451 { | |
3452 switch (assoc) { | |
3453 case 0: /* off */ | |
3454 break; | |
3455 case 1: | |
3456 case 2: | |
3457 case 4: | |
3458 add_cache_prop(devi, label, assoc_str, assoc); | |
3459 break; | |
3460 case 6: | |
3461 add_cache_prop(devi, label, assoc_str, 8); | |
3462 break; | |
3463 case 8: | |
3464 add_cache_prop(devi, label, assoc_str, 16); | |
3465 break; | |
3466 case 0xf: | |
3467 add_cache_prop(devi, label, fully_assoc, 1); | |
3468 break; | |
3469 default: /* reserved; ignore */ | |
3470 break; | |
3471 } | |
3472 } | |
3473 | |
3474 static void | |
3475 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
3476 { | |
3477 if (size == 0 || assoc == 0) | |
3478 return; | |
3479 add_amd_l2_assoc(devi, label, assoc); | |
3480 add_cache_prop(devi, label, size_str, size); | |
3481 } | |
3482 | |
3483 static void | |
3484 add_amd_l2_cache(dev_info_t *devi, const char *label, | |
3485 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
3486 { | |
3487 if (size == 0 || assoc == 0 || line_size == 0) | |
3488 return; | |
3489 add_amd_l2_assoc(devi, label, assoc); | |
3490 if (lines_per_tag != 0) | |
3491 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
3492 add_cache_prop(devi, label, line_str, line_size); | |
3493 add_cache_prop(devi, label, size_str, size * 1024); | |
3494 } | |
3495 | |
3496 static void | |
3497 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) | |
3498 { | |
1228 | 3499 struct cpuid_regs *cp; |
0 | 3500 |
3501 if (cpi->cpi_xmaxeax < 0x80000005) | |
3502 return; | |
3503 cp = &cpi->cpi_extd[5]; | |
3504 | |
3505 /* | |
3506 * 4M/2M L1 TLB configuration | |
3507 * | |
3508 * We report the size for 2M pages because AMD uses two | |
3509 * TLB entries for one 4M page. | |
3510 */ | |
3511 add_amd_tlb(devi, "dtlb-2M", | |
3512 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); | |
3513 add_amd_tlb(devi, "itlb-2M", | |
3514 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); | |
3515 | |
3516 /* | |
3517 * 4K L1 TLB configuration | |
3518 */ | |
3519 | |
3520 switch (cpi->cpi_vendor) { | |
3521 uint_t nentries; | |
3522 case X86_VENDOR_TM: | |
3523 if (cpi->cpi_family >= 5) { | |
3524 /* | |
3525 * Crusoe processors have 256 TLB entries, but | |
3526 * cpuid data format constrains them to only | |
3527 * reporting 255 of them. | |
3528 */ | |
3529 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) | |
3530 nentries = 256; | |
3531 /* | |
3532 * Crusoe processors also have a unified TLB | |
3533 */ | |
3534 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), | |
3535 nentries); | |
3536 break; | |
3537 } | |
3538 /*FALLTHROUGH*/ | |
3539 default: | |
3540 add_amd_tlb(devi, itlb4k_str, | |
3541 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); | |
3542 add_amd_tlb(devi, dtlb4k_str, | |
3543 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); | |
3544 break; | |
3545 } | |
3546 | |
3547 /* | |
3548 * data L1 cache configuration | |
3549 */ | |
3550 | |
3551 add_amd_cache(devi, l1_dcache_str, | |
3552 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), | |
3553 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); | |
3554 | |
3555 /* | |
3556 * code L1 cache configuration | |
3557 */ | |
3558 | |
3559 add_amd_cache(devi, l1_icache_str, | |
3560 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), | |
3561 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); | |
3562 | |
3563 if (cpi->cpi_xmaxeax < 0x80000006) | |
3564 return; | |
3565 cp = &cpi->cpi_extd[6]; | |
3566 | |
3567 /* Check for a unified L2 TLB for large pages */ | |
3568 | |
3569 if (BITX(cp->cp_eax, 31, 16) == 0) | |
3570 add_amd_l2_tlb(devi, "l2-tlb-2M", | |
3571 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
3572 else { | |
3573 add_amd_l2_tlb(devi, "l2-dtlb-2M", | |
3574 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
3575 add_amd_l2_tlb(devi, "l2-itlb-2M", | |
3576 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
3577 } | |
3578 | |
3579 /* Check for a unified L2 TLB for 4K pages */ | |
3580 | |
3581 if (BITX(cp->cp_ebx, 31, 16) == 0) { | |
3582 add_amd_l2_tlb(devi, "l2-tlb-4K", | |
3583 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
3584 } else { | |
3585 add_amd_l2_tlb(devi, "l2-dtlb-4K", | |
3586 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
3587 add_amd_l2_tlb(devi, "l2-itlb-4K", | |
3588 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
3589 } | |
3590 | |
3591 add_amd_l2_cache(devi, l2_cache_str, | |
3592 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), | |
3593 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); | |
3594 } | |
3595 | |
3596 /* | |
3597 * There are two basic ways that the x86 world describes it cache | |
3598 * and tlb architecture - Intel's way and AMD's way. | |
3599 * | |
3600 * Return which flavor of cache architecture we should use | |
3601 */ | |
3602 static int | |
3603 x86_which_cacheinfo(struct cpuid_info *cpi) | |
3604 { | |
3605 switch (cpi->cpi_vendor) { | |
3606 case X86_VENDOR_Intel: | |
3607 if (cpi->cpi_maxeax >= 2) | |
3608 return (X86_VENDOR_Intel); | |
3609 break; | |
3610 case X86_VENDOR_AMD: | |
3611 /* | |
3612 * The K5 model 1 was the first part from AMD that reported | |
3613 * cache sizes via extended cpuid functions. | |
3614 */ | |
3615 if (cpi->cpi_family > 5 || | |
3616 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
3617 return (X86_VENDOR_AMD); | |
3618 break; | |
3619 case X86_VENDOR_TM: | |
3620 if (cpi->cpi_family >= 5) | |
3621 return (X86_VENDOR_AMD); | |
3622 /*FALLTHROUGH*/ | |
3623 default: | |
3624 /* | |
3625 * If they have extended CPU data for 0x80000005 | |
3626 * then we assume they have AMD-format cache | |
3627 * information. | |
3628 * | |
3629 * If not, and the vendor happens to be Cyrix, | |
3630 * then try our-Cyrix specific handler. | |
3631 * | |
3632 * If we're not Cyrix, then assume we're using Intel's | |
3633 * table-driven format instead. | |
3634 */ | |
3635 if (cpi->cpi_xmaxeax >= 0x80000005) | |
3636 return (X86_VENDOR_AMD); | |
3637 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) | |
3638 return (X86_VENDOR_Cyrix); | |
3639 else if (cpi->cpi_maxeax >= 2) | |
3640 return (X86_VENDOR_Intel); | |
3641 break; | |
3642 } | |
3643 return (-1); | |
3644 } | |
3645 | |
3646 void | |
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3647 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, |
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3648 struct cpuid_info *cpi) |
0 | 3649 { |
3650 dev_info_t *cpu_devi; | |
3651 int create; | |
3652 | |
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3653 cpu_devi = (dev_info_t *)dip; |
0 | 3654 |
3655 /* device_type */ | |
3656 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
3657 "device_type", "cpu"); | |
3658 | |
3659 /* reg */ | |
3660 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3661 "reg", cpu_id); | |
3662 | |
3663 /* cpu-mhz, and clock-frequency */ | |
3664 if (cpu_freq > 0) { | |
3665 long long mul; | |
3666 | |
3667 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3668 "cpu-mhz", cpu_freq); | |
3669 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) | |
3670 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3671 "clock-frequency", (int)mul); | |
3672 } | |
3673 | |
3674 if ((x86_feature & X86_CPUID) == 0) { | |
3675 return; | |
3676 } | |
3677 | |
3678 /* vendor-id */ | |
3679 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3680 "vendor-id", cpi->cpi_vendorstr); |
0 | 3681 |
3682 if (cpi->cpi_maxeax == 0) { | |
3683 return; | |
3684 } | |
3685 | |
3686 /* | |
3687 * family, model, and step | |
3688 */ | |
3689 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3690 "family", CPI_FAMILY(cpi)); |
0 | 3691 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3692 "cpu-model", CPI_MODEL(cpi)); |
0 | 3693 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3694 "stepping-id", CPI_STEP(cpi)); |
0 | 3695 |
3696 /* type */ | |
3697 switch (cpi->cpi_vendor) { | |
3698 case X86_VENDOR_Intel: | |
3699 create = 1; | |
3700 break; | |
3701 default: | |
3702 create = 0; | |
3703 break; | |
3704 } | |
3705 if (create) | |
3706 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3707 "type", CPI_TYPE(cpi)); |
0 | 3708 |
3709 /* ext-family */ | |
3710 switch (cpi->cpi_vendor) { | |
3711 case X86_VENDOR_Intel: | |
3712 case X86_VENDOR_AMD: | |
3713 create = cpi->cpi_family >= 0xf; | |
3714 break; | |
3715 default: | |
3716 create = 0; | |
3717 break; | |
3718 } | |
3719 if (create) | |
3720 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3721 "ext-family", CPI_FAMILY_XTD(cpi)); | |
3722 | |
3723 /* ext-model */ | |
3724 switch (cpi->cpi_vendor) { | |
3725 case X86_VENDOR_Intel: | |
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
3726 create = IS_EXTENDED_MODEL_INTEL(cpi); |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
3727 break; |
0 | 3728 case X86_VENDOR_AMD: |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3729 create = CPI_FAMILY(cpi) == 0xf; |
0 | 3730 break; |
3731 default: | |
3732 create = 0; | |
3733 break; | |
3734 } | |
3735 if (create) | |
3736 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3737 "ext-model", CPI_MODEL_XTD(cpi)); |
0 | 3738 |
3739 /* generation */ | |
3740 switch (cpi->cpi_vendor) { | |
3741 case X86_VENDOR_AMD: | |
3742 /* | |
3743 * AMD K5 model 1 was the first part to support this | |
3744 */ | |
3745 create = cpi->cpi_xmaxeax >= 0x80000001; | |
3746 break; | |
3747 default: | |
3748 create = 0; | |
3749 break; | |
3750 } | |
3751 if (create) | |
3752 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3753 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); | |
3754 | |
3755 /* brand-id */ | |
3756 switch (cpi->cpi_vendor) { | |
3757 case X86_VENDOR_Intel: | |
3758 /* | |
3759 * brand id first appeared on Pentium III Xeon model 8, | |
3760 * and Celeron model 8 processors and Opteron | |
3761 */ | |
3762 create = cpi->cpi_family > 6 || | |
3763 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); | |
3764 break; | |
3765 case X86_VENDOR_AMD: | |
3766 create = cpi->cpi_family >= 0xf; | |
3767 break; | |
3768 default: | |
3769 create = 0; | |
3770 break; | |
3771 } | |
3772 if (create && cpi->cpi_brandid != 0) { | |
3773 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3774 "brand-id", cpi->cpi_brandid); | |
3775 } | |
3776 | |
3777 /* chunks, and apic-id */ | |
3778 switch (cpi->cpi_vendor) { | |
3779 /* | |
3780 * first available on Pentium IV and Opteron (K8) | |
3781 */ | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3782 case X86_VENDOR_Intel: |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3783 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3784 break; |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3785 case X86_VENDOR_AMD: |
0 | 3786 create = cpi->cpi_family >= 0xf; |
3787 break; | |
3788 default: | |
3789 create = 0; | |
3790 break; | |
3791 } | |
3792 if (create) { | |
3793 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3794 "chunks", CPI_CHUNKS(cpi)); |
0 | 3795 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
3796 "apic-id", cpi->cpi_apicid); |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3797 if (cpi->cpi_chipid >= 0) { |
0 | 3798 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
3799 "chip#", cpi->cpi_chipid); | |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3800 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3801 "clog#", cpi->cpi_clogid); |
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3802 } |
0 | 3803 } |
3804 | |
3805 /* cpuid-features */ | |
3806 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3807 "cpuid-features", CPI_FEATURES_EDX(cpi)); | |
3808 | |
3809 | |
3810 /* cpuid-features-ecx */ | |
3811 switch (cpi->cpi_vendor) { | |
3812 case X86_VENDOR_Intel: | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3813 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
0 | 3814 break; |
3815 default: | |
3816 create = 0; | |
3817 break; | |
3818 } | |
3819 if (create) | |
3820 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
3821 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); | |
3822 | |
3823 /* ext-cpuid-features */ | |
3824 switch (cpi->cpi_vendor) { | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3825 case X86_VENDOR_Intel: |
0 | 3826 case X86_VENDOR_AMD: |
3827 case X86_VENDOR_Cyrix: | |
3828 case X86_VENDOR_TM: | |
3829 case X86_VENDOR_Centaur: | |
3830 create = cpi->cpi_xmaxeax >= 0x80000001; | |
3831 break; | |
3832 default: | |
3833 create = 0; | |
3834 break; | |
3835 } | |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3836 if (create) { |
0 | 3837 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3838 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3839 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3840 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3841 } |
0 | 3842 |
3843 /* | |
3844 * Brand String first appeared in Intel Pentium IV, AMD K5 | |
3845 * model 1, and Cyrix GXm. On earlier models we try and | |
3846 * simulate something similar .. so this string should always | |
3847 * same -something- about the processor, however lame. | |
3848 */ | |
3849 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
3850 "brand-string", cpi->cpi_brandstr); | |
3851 | |
3852 /* | |
3853 * Finally, cache and tlb information | |
3854 */ | |
3855 switch (x86_which_cacheinfo(cpi)) { | |
3856 case X86_VENDOR_Intel: | |
3857 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
3858 break; | |
3859 case X86_VENDOR_Cyrix: | |
3860 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
3861 break; | |
3862 case X86_VENDOR_AMD: | |
3863 amd_cache_info(cpi, cpu_devi); | |
3864 break; | |
3865 default: | |
3866 break; | |
3867 } | |
3868 } | |
3869 | |
3870 struct l2info { | |
3871 int *l2i_csz; | |
3872 int *l2i_lsz; | |
3873 int *l2i_assoc; | |
3874 int l2i_ret; | |
3875 }; | |
3876 | |
3877 /* | |
3878 * A cacheinfo walker that fetches the size, line-size and associativity | |
3879 * of the L2 cache | |
3880 */ | |
3881 static int | |
3882 intel_l2cinfo(void *arg, const struct cachetab *ct) | |
3883 { | |
3884 struct l2info *l2i = arg; | |
3885 int *ip; | |
3886 | |
3887 if (ct->ct_label != l2_cache_str && | |
3888 ct->ct_label != sl2_cache_str) | |
3889 return (0); /* not an L2 -- keep walking */ | |
3890 | |
3891 if ((ip = l2i->l2i_csz) != NULL) | |
3892 *ip = ct->ct_size; | |
3893 if ((ip = l2i->l2i_lsz) != NULL) | |
3894 *ip = ct->ct_line_size; | |
3895 if ((ip = l2i->l2i_assoc) != NULL) | |
3896 *ip = ct->ct_assoc; | |
3897 l2i->l2i_ret = ct->ct_size; | |
3898 return (1); /* was an L2 -- terminate walk */ | |
3899 } | |
3900 | |
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3901 /* |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3902 * AMD L2/L3 Cache and TLB Associativity Field Definition: |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3903 * |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3904 * Unlike the associativity for the L1 cache and tlb where the 8 bit |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3905 * value is the associativity, the associativity for the L2 cache and |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3906 * tlb is encoded in the following table. The 4 bit L2 value serves as |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3907 * an index into the amd_afd[] array to determine the associativity. |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3908 * -1 is undefined. 0 is fully associative. |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3909 */ |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3910 |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3911 static int amd_afd[] = |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3912 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3913 |
0 | 3914 static void |
3915 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) | |
3916 { | |
1228 | 3917 struct cpuid_regs *cp; |
0 | 3918 uint_t size, assoc; |
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3919 int i; |
0 | 3920 int *ip; |
3921 | |
3922 if (cpi->cpi_xmaxeax < 0x80000006) | |
3923 return; | |
3924 cp = &cpi->cpi_extd[6]; | |
3925 | |
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3926 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && |
0 | 3927 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { |
3928 uint_t cachesz = size * 1024; | |
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3929 assoc = amd_afd[i]; |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3930 |
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
3931 ASSERT(assoc != -1); |
0 | 3932 |
3933 if ((ip = l2i->l2i_csz) != NULL) | |
3934 *ip = cachesz; | |
3935 if ((ip = l2i->l2i_lsz) != NULL) | |
3936 *ip = BITX(cp->cp_ecx, 7, 0); | |
3937 if ((ip = l2i->l2i_assoc) != NULL) | |
3938 *ip = assoc; | |
3939 l2i->l2i_ret = cachesz; | |
3940 } | |
3941 } | |
3942 | |
3943 int | |
3944 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) | |
3945 { | |
3946 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
3947 struct l2info __l2info, *l2i = &__l2info; | |
3948 | |
3949 l2i->l2i_csz = csz; | |
3950 l2i->l2i_lsz = lsz; | |
3951 l2i->l2i_assoc = assoc; | |
3952 l2i->l2i_ret = -1; | |
3953 | |
3954 switch (x86_which_cacheinfo(cpi)) { | |
3955 case X86_VENDOR_Intel: | |
3956 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
3957 break; | |
3958 case X86_VENDOR_Cyrix: | |
3959 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
3960 break; | |
3961 case X86_VENDOR_AMD: | |
3962 amd_l2cacheinfo(cpi, l2i); | |
3963 break; | |
3964 default: | |
3965 break; | |
3966 } | |
3967 return (l2i->l2i_ret); | |
3968 } | |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3969 |
5084 | 3970 #if !defined(__xpv) |
3971 | |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3972 uint32_t * |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3973 cpuid_mwait_alloc(cpu_t *cpu) |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3974 { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3975 uint32_t *ret; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3976 size_t mwait_size; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3977 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3978 ASSERT(cpuid_checkpass(cpu, 2)); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3979 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3980 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3981 if (mwait_size == 0) |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3982 return (NULL); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3983 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3984 /* |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3985 * kmem_alloc() returns cache line size aligned data for mwait_size |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3986 * allocations. mwait_size is currently cache line sized. Neither |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3987 * of these implementation details are guarantied to be true in the |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3988 * future. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3989 * |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3990 * First try allocating mwait_size as kmem_alloc() currently returns |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3991 * correctly aligned memory. If kmem_alloc() does not return |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3992 * mwait_size aligned memory, then use mwait_size ROUNDUP. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3993 * |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3994 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3995 * decide to free this memory. |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3996 */ |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3997 ret = kmem_zalloc(mwait_size, KM_SLEEP); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3998 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
3999 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4000 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4001 *ret = MWAIT_RUNNING; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4002 return (ret); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4003 } else { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4004 kmem_free(ret, mwait_size); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4005 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4006 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4007 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4008 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4009 *ret = MWAIT_RUNNING; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4010 return (ret); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4011 } |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4012 } |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4013 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4014 void |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4015 cpuid_mwait_free(cpu_t *cpu) |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4016 { |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4017 ASSERT(cpuid_checkpass(cpu, 2)); |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4018 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4019 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4020 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4021 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4022 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4023 } |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4024 |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4025 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4026 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4027 } |
5084 | 4028 |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4029 void |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4030 patch_tsc_read(int flag) |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4031 { |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4032 size_t cnt; |
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
4033 |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4034 switch (flag) { |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4035 case X86_NO_TSC: |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4036 cnt = &_no_rdtsc_end - &_no_rdtsc_start; |
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4037 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4038 break; |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4039 case X86_HAVE_TSCP: |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4040 cnt = &_tscp_end - &_tscp_start; |
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4041 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4042 break; |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4043 case X86_TSC_MFENCE: |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4044 cnt = &_tsc_mfence_end - &_tsc_mfence_start; |
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4045 (void) memcpy((void *)tsc_read, |
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4046 (void *)&_tsc_mfence_start, cnt); |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4047 break; |
6642
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4048 case X86_TSC_LFENCE: |
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4049 cnt = &_tsc_lfence_end - &_tsc_lfence_start; |
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4050 (void) memcpy((void *)tsc_read, |
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4051 (void *)&_tsc_lfence_start, cnt); |
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4052 break; |
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4053 default: |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4054 break; |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4055 } |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4056 } |
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4057 |
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4058 int |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4059 cpuid_deep_cstates_supported(void) |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4060 { |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4061 struct cpuid_info *cpi; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4062 struct cpuid_regs regs; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4063 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4064 ASSERT(cpuid_checkpass(CPU, 1)); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4065 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4066 cpi = CPU->cpu_m.mcpu_cpi; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4067 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4068 if (!(x86_feature & X86_CPUID)) |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4069 return (0); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4070 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4071 switch (cpi->cpi_vendor) { |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4072 case X86_VENDOR_Intel: |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4073 if (cpi->cpi_xmaxeax < 0x80000007) |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4074 return (0); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4075 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4076 /* |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4077 * TSC run at a constant rate in all ACPI C-states? |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4078 */ |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4079 regs.cp_eax = 0x80000007; |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4080 (void) __cpuid_insn(®s); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4081 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4082 |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4083 default: |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4084 return (0); |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4085 } |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4086 } |
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4087 |
8930
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4088 #endif /* !__xpv */ |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4089 |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4090 void |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4091 post_startup_cpu_fixups(void) |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4092 { |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4093 #ifndef __xpv |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4094 /* |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4095 * Some AMD processors support C1E state. Entering this state will |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4096 * cause the local APIC timer to stop, which we can't deal with at |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4097 * this time. |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4098 */ |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4099 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4100 on_trap_data_t otd; |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4101 uint64_t reg; |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4102 |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4103 if (!on_trap(&otd, OT_DATA_ACCESS)) { |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4104 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4105 /* Disable C1E state if it is enabled by BIOS */ |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4106 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4107 AMD_ACTONCMPHALT_MASK) { |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4108 reg &= ~(AMD_ACTONCMPHALT_MASK << |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4109 AMD_ACTONCMPHALT_SHIFT); |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4110 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4111 } |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4112 } |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4113 no_trap(); |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4114 } |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4115 #endif /* !__xpv */ |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4116 } |
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4117 |
9283
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4118 /* |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4119 * Starting with the Westmere processor the local |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4120 * APIC timer will continue running in all C-states, |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4121 * including the deepest C-states. |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4122 */ |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4123 int |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4124 cpuid_arat_supported(void) |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4125 { |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4126 struct cpuid_info *cpi; |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4127 struct cpuid_regs regs; |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4128 |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4129 ASSERT(cpuid_checkpass(CPU, 1)); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4130 ASSERT(x86_feature & X86_CPUID); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4131 |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4132 cpi = CPU->cpu_m.mcpu_cpi; |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4133 |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4134 switch (cpi->cpi_vendor) { |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4135 case X86_VENDOR_Intel: |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4136 /* |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4137 * Always-running Local APIC Timer is |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4138 * indicated by CPUID.6.EAX[2]. |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4139 */ |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4140 if (cpi->cpi_maxeax >= 6) { |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4141 regs.cp_eax = 6; |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4142 (void) cpuid_insn(NULL, ®s); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4143 return (regs.cp_eax & CPUID_CSTATE_ARAT); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4144 } else { |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4145 return (0); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4146 } |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4147 default: |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4148 return (0); |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4149 } |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4150 } |
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4151 |
10992
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4152 /* |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4153 * Check support for Intel ENERGY_PERF_BIAS feature |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4154 */ |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4155 int |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4156 cpuid_iepb_supported(struct cpu *cp) |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4157 { |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4158 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi; |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4159 struct cpuid_regs regs; |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4160 |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4161 ASSERT(cpuid_checkpass(cp, 1)); |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4162 |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4163 if (!(x86_feature & X86_CPUID) || !(x86_feature & X86_MSR)) { |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4164 return (0); |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4165 } |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4166 |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4167 /* |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4168 * Intel ENERGY_PERF_BIAS MSR is indicated by |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4169 * capability bit CPUID.6.ECX.3 |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4170 */ |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4171 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6)) |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4172 return (0); |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4173 |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4174 regs.cp_eax = 0x6; |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4175 (void) cpuid_insn(NULL, ®s); |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4176 return (regs.cp_ecx & CPUID_EPB_SUPPORT); |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4177 } |
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4178 |
8377
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4179 #if defined(__amd64) && !defined(__xpv) |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4180 /* |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4181 * Patch in versions of bcopy for high performance Intel Nhm processors |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4182 * and later... |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4183 */ |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4184 void |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4185 patch_memops(uint_t vendor) |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4186 { |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4187 size_t cnt, i; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4188 caddr_t to, from; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4189 |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4190 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4191 cnt = &bcopy_patch_end - &bcopy_patch_start; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4192 to = &bcopy_ck_size; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4193 from = &bcopy_patch_start; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4194 for (i = 0; i < cnt; i++) { |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4195 *to++ = *from++; |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4196 } |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4197 } |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4198 } |
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4199 #endif /* __amd64 && !__xpv */ |