illumos/illumos-gate: usr/src/uts/i86pc/os/cpuid.c annotate

annotate usr/src/uts/i86pc/os/cpuid.c @ 11389:dd00b884e84f

6764832 Provide user-level processor groups observability 6831680 cputrack(1) leaves its victim with unneeded cpc context 6901343 cpc context flag updates are not always atomic 6908152 Dormant thread CPC context affects cpu CPC consumers

author	Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
date	Tue, 22 Dec 2009 21:52:00 -0800
parents	3aa288b66f8e
children	5b917481ad11

rev	line source
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2 * CDDL HEADER START
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4 * The contents of this file are subject to the terms of the
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	5 * Common Development and Distribution License (the "License").
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	6 * You may not use this file except in compliance with the License.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	7 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	9 * or http://www.opensolaris.org/os/licensing.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	10 * See the License for the specific language governing permissions
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	11 * and limitations under the License.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	12 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	13 * When distributing Covered Code, include this CDDL HEADER in each
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	15 * If applicable, add the following below this CDDL HEADER, with the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	16 * fields enclosed by brackets "[]" replaced with your own identifying
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	17 * information: Portions Copyright [yyyy] [name of copyright owner]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	18 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	19 * CDDL HEADER END
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	20 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	21 /*
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	23 * Use is subject to license terms.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	24 */
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	25 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	26 * Copyright (c) 2009, Intel Corporation.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	27 * All rights reserved.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	28 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	29 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	30 * Portions Copyright 2009 Advanced Micro Devices, Inc.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	31 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	32
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	33 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	34 * Various routines to handle identification
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	35 * and classification of x86 processors.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	36 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	37
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	38 #include <sys/types.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	39 #include <sys/archsystm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	40 #include <sys/x86_archext.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	41 #include <sys/kmem.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	42 #include <sys/systm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	43 #include <sys/cmn_err.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	44 #include <sys/sunddi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	45 #include <sys/sunndi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	46 #include <sys/cpuvar.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	47 #include <sys/processor.h>
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	48 #include <sys/sysmacros.h>
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	49 #include <sys/pg.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	50 #include <sys/fp.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	51 #include <sys/controlregs.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	52 #include <sys/auxv_386.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	53 #include <sys/bitmap.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	54 #include <sys/memnode.h>
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	55 #include <sys/pci_cfgspace.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	56
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	57 #ifdef __xpv
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	58 #include <sys/hypervisor.h>
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	59 #else
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	60 #include <sys/ontrap.h>
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	61 #endif
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	62
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	63 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	64 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	65 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	66 * them accordingly. For most modern processors, feature detection occurs here
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	67 * in pass 1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	68 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	69 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	70 * for the boot CPU and does the basic analysis that the early kernel needs.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	71 * x86_feature is set based on the return value of cpuid_pass1() of the boot
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	72 * CPU.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	73 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	74 * Pass 1 includes:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	75 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	76 * o Determining vendor/model/family/stepping and setting x86_type and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	77 * x86_vendor accordingly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	78 * o Processing the feature flags returned by the cpuid instruction while
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	79 * applying any workarounds or tricks for the specific processor.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	80 * o Mapping the feature flags into Solaris feature bits (X86_*).
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	81 * o Processing extended feature flags if supported by the processor,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	82 * again while applying specific processor knowledge.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	83 * o Determining the CMT characteristics of the system.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	84 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	85 * Pass 1 is done on non-boot CPUs during their initialization and the results
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	86 * are used only as a meager attempt at ensuring that all processors within the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	87 * system support the same features.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	88 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	89 * Pass 2 of cpuid feature analysis happens just at the beginning
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	90 * of startup(). It just copies in and corrects the remainder
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	91 * of the cpuid data we depend on: standard cpuid functions that we didn't
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	92 * need for pass1 feature analysis, and extended cpuid functions beyond the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	93 * simple feature processing done in pass1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	94 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	95 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	96 * particular kernel memory allocation has been made available. It creates a
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	97 * readable brand string based on the data collected in the first two passes.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	98 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	99 * Pass 4 of cpuid analysis is invoked after post_startup() when all
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	100 * the support infrastructure for various hardware features has been
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	101 * initialized. It determines which processor features will be reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	102 * to userland via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	103 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	104 * All passes are executed on all CPUs, but only the boot CPU determines what
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	105 * features the kernel will use.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	106 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	107 * Much of the worst junk in this file is for the support of processors
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	108 * that didn't really implement the cpuid instruction properly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	109 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	110 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	111 * the pass numbers. Accordingly, changes to the pass code may require changes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	112 * to the accessor code.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	113 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	114
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	115 uint_t x86_feature = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	116 uint_t x86_vendor = X86_VENDOR_IntelClone;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	117 uint_t x86_type = X86_TYPE_OTHER;
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	118 uint_t x86_clflush_size = 0;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	119
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	120 uint_t pentiumpro_bug4046376;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	121 uint_t pentiumpro_bug4064495;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	122
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	123 uint_t enable486;
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	124 /*
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	125 * This is set to platform type Solaris is running on.
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	126 */
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	127 static int platform_type = -1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	128
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	129 #if !defined(__xpv)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	130 /*
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	131 * Variable to patch if hypervisor platform detection needs to be
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	132 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	133 */
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	134 int enable_platform_detection = 1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	135 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	136
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	137 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	138 * monitor/mwait info.
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	139 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	140 * size_actual and buf_actual are the real address and size allocated to get
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	141 * proper mwait_buf alignement. buf_actual and size_actual should be passed
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	142 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	143 * processor cache-line alignment, but this is not guarantied in the furture.
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	144 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	145 struct mwait_info {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	146 size_t mon_min; /* min size to avoid missed wakeups */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	147 size_t mon_max; /* size to avoid false wakeups */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	148 size_t size_actual; /* size actually allocated */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	149 void buf_actual; / memory actually allocated */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	150 uint32_t support; /* processor support of monitor/mwait */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	151 };
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	152
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	153 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	154 * These constants determine how many of the elements of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	155 * cpuid we cache in the cpuid_info data structure; the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	156 * remaining elements are accessible via the cpuid instruction.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	157 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	158
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	159 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	160 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	161
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	162 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	163 * Some terminology needs to be explained:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	164 * - Socket: Something that can be plugged into a motherboard.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	165 * - Package: Same as socket
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	166 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	167 * differently: there, chip is the same as processor node (below)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	168 * - Processor node: Some AMD processors have more than one
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	169 * "subprocessor" embedded in a package. These subprocessors (nodes)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	170 * are fully-functional processors themselves with cores, caches,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	171 * memory controllers, PCI configuration spaces. They are connected
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	172 * inside the package with Hypertransport links. On single-node
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	173 * processors, processor node is equivalent to chip/socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	174 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	175
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	176 struct cpuid_info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	177 uint_t cpi_pass; /* last pass completed */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	178 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	179 * standard function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	180 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	181 uint_t cpi_maxeax; /* fn 0: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	182 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	183 uint_t cpi_vendor; /* enum of cpi_vendorstr */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	184
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	185 uint_t cpi_family; /* fn 1: extended family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	186 uint_t cpi_model; /* fn 1: extended model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	187 uint_t cpi_step; /* fn 1: stepping */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	188 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	189 /* AMD: package/socket # */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	190 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	191 int cpi_clogid; /* fn 1: %ebx: thread # */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	192 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	193 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	194 uint_t cpi_ncache; /* fn 2: number of elements */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	195 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	196 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	197 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	198 struct cpuid_regs *cpi_std_4; / fn 4: %ecx == 0 .. fn4_size */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	199 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	200 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	201 * extended function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	202 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	203 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	204 char cpi_brandstr[49]; /* fn 0x8000000[234] */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	205 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	206 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	207 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	208
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	209 id_t cpi_coreid; /* same coreid => strands share core */
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	210 int cpi_pkgcoreid; /* core number within single package */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	211 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	212 /* Intel: fn 4: %eax[31-26] */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	213 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	214 * supported feature information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	215 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	216 uint32_t cpi_support[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	217 #define STD_EDX_FEATURES 0
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	218 #define AMD_EDX_FEATURES 1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	219 #define TM_EDX_FEATURES 2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	220 #define STD_ECX_FEATURES 3
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	221 #define AMD_ECX_FEATURES 4
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	222 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	223 * Synthesized information, where known.
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	224 */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	225 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	226 const char cpi_chiprevstr; / May be NULL if chiprev unknown */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	227 uint32_t cpi_socket; /* Chip package/socket type */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	228
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	229 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	230 uint32_t cpi_apicid;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	231 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	232 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	233 /* Intel: 1 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	234 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	235
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	236
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	237 static struct cpuid_info cpuid_info0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	238
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	239 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	240 * These bit fields are defined by the Intel Application Note AP-485
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	241 * "Intel Processor Identification and the CPUID Instruction"
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	242 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	243 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	244 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	245 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	246 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	247 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	248 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	249
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	250 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	251 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	252 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	253 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	254
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	255 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	256 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	257 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	258 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	259
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	260 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	261 #define CPI_XMAXEAX_MAX 0x80000100
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	262 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	263 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	264
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	265 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	266 * Function 4 (Deterministic Cache Parameters) macros
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	267 * Defined by Intel Application Note AP-485
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	268 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	269 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	270 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	271 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	272 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	273 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	274 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	275 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	276
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	277 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	278 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	279 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	280
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	281 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	282
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	283 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	284
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	285
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	286 /*
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	287 * A couple of shorthand macros to identify "later" P6-family chips
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	288 * like the Pentium M and Core. First, the "older" P6-based stuff
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	289 * (loosely defined as "pre-Pentium-4"):
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	290 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	291 */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	292
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	293 #define IS_LEGACY_P6(cpi) ( \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	294 cpi->cpi_family == 6 && \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	295 (cpi->cpi_model == 1 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	296 cpi->cpi_model == 3 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	297 cpi->cpi_model == 5 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	298 cpi->cpi_model == 6 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	299 cpi->cpi_model == 7 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	300 cpi->cpi_model == 8 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	301 cpi->cpi_model == 0xA \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	302 cpi->cpi_model == 0xB) \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	303 )
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	304
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	305 /* A "new F6" is everything with family 6 that's not the above */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	306 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	307
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	308 /* Extended family/model support */
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	309 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 \|\| \
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	310 cpi->cpi_family >= 0xf)
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	311
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	312 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	313 * Info for monitor/mwait idle loop.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	314 *
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	315 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	316 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	317 * 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	318 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	319 * Documentation Updates" #33633, Rev 2.05, December 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	320 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	321 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	322 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	323 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	324 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	325 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	326 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	327 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	328 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	329 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	330 * Number of sub-cstates for a given c-state.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	331 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	332 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	333 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	334
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	335 /*
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	336 * Functions we consune from cpuid_subr.c; don't publish these in a header
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	337 * file to try and keep people using the expected cpuid_* interfaces.
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	338 */
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	339 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	340 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	341 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	342 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	343 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	344
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	345 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	346 * Apply up various platform-dependent restrictions where the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	347 * underlying platform restrictions mean the CPU can be marked
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	348 * as less capable than its cpuid instruction would imply.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	349 */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	350 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	351 static void
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	352 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	353 {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	354 switch (eax) {
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	355 case 1: {
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	356 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	357 0 : CPUID_INTC_EDX_MCA;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	358 cp->cp_edx &=
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	359 ~(mcamask \|
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	360 CPUID_INTC_EDX_PSE \|
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	361 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	362 CPUID_INTC_EDX_SEP \| CPUID_INTC_EDX_MTRR \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	363 CPUID_INTC_EDX_PGE \| CPUID_INTC_EDX_PAT \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	364 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	365 CPUID_INTC_EDX_PSE36 \| CPUID_INTC_EDX_HTT);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	366 break;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	367 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	368
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	369 case 0x80000001:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	370 cp->cp_edx &=
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	371 ~(CPUID_AMD_EDX_PSE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	372 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	373 CPUID_AMD_EDX_MTRR \| CPUID_AMD_EDX_PGE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	374 CPUID_AMD_EDX_PAT \| CPUID_AMD_EDX_PSE36 \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	375 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	376 CPUID_AMD_EDX_TSCP);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	377 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	378 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	379 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	380 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	381 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	382
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	383 switch (vendor) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	384 case X86_VENDOR_Intel:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	385 switch (eax) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	386 case 4:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	387 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	388 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	389 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	390 cp->cp_eax &= 0x03fffffff;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	391 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	392 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	393 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	394 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	395 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	396 case X86_VENDOR_AMD:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	397 switch (eax) {
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	398
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	399 case 0x80000001:
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	400 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	401 break;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	402
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	403 case 0x80000008:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	404 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	405 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	406 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	407 cp->cp_ecx &= 0xffffff00;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	408 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	409 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	410 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	411 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	412 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	413 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	414 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	415 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	416 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	417 #else
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	418 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	419 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	420
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	421 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	422 * Some undocumented ways of patching the results of the cpuid
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	423 * instruction to permit running Solaris 10 on future cpus that
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	424 * we don't currently support. Could be set to non-zero values
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	425 * via settings in eeprom.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	426 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	427
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	428 uint32_t cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	429 uint32_t cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	430 uint32_t cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	431 uint32_t cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	432
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	433 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	434 cpuid_alloc_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	435 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	436 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	437 * By convention, cpu0 is the boot cpu, which is set up
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	438 * before memory allocation is available. All other cpus get
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	439 * their cpuid_info struct allocated here.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	440 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	441 ASSERT(cpu->cpu_id != 0);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	442 cpu->cpu_m.mcpu_cpi =
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	443 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	444 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	445
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	446 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	447 cpuid_free_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	448 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	449 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	450 int i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	451
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	452 ASSERT(cpu->cpu_id != 0);
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	453
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	454 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	455 * Free up any function 4 related dynamic storage
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	456 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	457 for (i = 1; i < cpi->cpi_std_4_size; i++)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	458 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	459 if (cpi->cpi_std_4_size > 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	460 kmem_free(cpi->cpi_std_4,
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	461 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	462
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	463 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi));
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	464 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	465
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	466 #if !defined(__xpv)
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	467
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	468 static void
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	469 determine_platform()
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	470 {
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	471 struct cpuid_regs cp;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	472 char *xen_str;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	473 uint32_t xen_signature[4];
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	474
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	475 platform_type = HW_NATIVE;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	476
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	477 if (!enable_platform_detection)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	478 return;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	479
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	480 /*
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	481 * In a fully virtualized domain, Xen's pseudo-cpuid function
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	482 * 0x40000000 returns a string representing the Xen signature in
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	483 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	484 * function.
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	485 */
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	486 cp.cp_eax = 0x40000000;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	487 (void) __cpuid_insn(&cp);
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	488 xen_signature[0] = cp.cp_ebx;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	489 xen_signature[1] = cp.cp_ecx;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	490 xen_signature[2] = cp.cp_edx;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	491 xen_signature[3] = 0;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	492 xen_str = (char *)xen_signature;
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	493 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	494 platform_type = HW_XEN_HVM;
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	495 } else if (vmware_platform()) { /* running under vmware hypervisor? */
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	496 platform_type = HW_VMWARE;
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	497 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	498 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	499
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	500 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	501 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	502 {
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	503 if (platform_type == -1)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	504 determine_platform();
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	505
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	506 return (platform_type);
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	507 }
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	508
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	509 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	510 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	511 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	512 return (0);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	513 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	514
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	515 #else
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	516
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	517 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	518 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	519 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	520 return (HW_XEN_PV);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	521 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	522
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	523 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	524 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	525 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	526 return (DOMAIN_IS_INITDOMAIN(xen_info));
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	527 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	528
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	529 #endif /* __xpv */
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	530
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	531 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	532 cpuid_intel_getids(cpu_t *cpu, uint_t feature)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	533 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	534 uint_t i;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	535 uint_t chipid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	536 uint_t coreid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	537 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	538
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	539 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	540 chipid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	541
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	542 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	543 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	544
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	545 if (feature & X86_CMP) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	546 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	547 * Multi-core (and possibly multi-threaded)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	548 * processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	549 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	550 uint_t ncpu_per_core;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	551 if (cpi->cpi_ncore_per_chip == 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	552 ncpu_per_core = cpi->cpi_ncpu_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	553 else if (cpi->cpi_ncore_per_chip > 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	554 ncpu_per_core = cpi->cpi_ncpu_per_chip /
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	555 cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	556 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	557 * 8bit APIC IDs on dual core Pentiums
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	558 * look like this:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	559 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	560 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	561 * \| Physical Package ID \| MC \| HT \|
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	562 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	563 * <------- chipid -------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	564 * <------- coreid --------------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	565 * <--- clogid -->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	566 * <------>
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	567 * pkgcoreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	568 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	569 * Where the number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	570 * represent MC and HT fields together equals
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	571 * to the minimum number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	572 * store the value of cpi->cpi_ncpu_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	573 * Of those bits, the MC part uses the number
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	574 * of bits necessary to store the value of
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	575 * cpi->cpi_ncore_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	576 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	577 for (i = 1; i < ncpu_per_core; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	578 coreid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	579 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	580 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	581 } else if (feature & X86_HTT) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	582 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	583 * Single-core multi-threaded processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	584 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	585 cpi->cpi_coreid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	586 cpi->cpi_pkgcoreid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	587 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	588 cpi->cpi_procnodeid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	589 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	590
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	591 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	592 cpuid_amd_getids(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	593 {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	594 int i, first_half, coreidsz;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	595 uint32_t nb_caps_reg;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	596 uint_t node2_1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	597 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	598
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	599 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	600 * AMD CMP chips currently have a single thread per core.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	601 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	602 * Since no two cpus share a core we must assign a distinct coreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	603 * per cpu, and we do this by using the cpu_id. This scheme does not,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	604 * however, guarantee that sibling cores of a chip will have sequential
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	605 * coreids starting at a multiple of the number of cores per chip -
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	606 * that is usually the case, but if the ACPI MADT table is presented
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	607 * in a different order then we need to perform a few more gymnastics
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	608 * for the pkgcoreid.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	609 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	610 * All processors in the system have the same number of enabled
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	611 * cores. Cores within a processor are always numbered sequentially
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	612 * from 0 regardless of how many or which are disabled, and there
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	613 * is no way for operating system to discover the real core id when some
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	614 * are disabled.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	615 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	616
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	617 cpi->cpi_coreid = cpu->cpu_id;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	618
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	619 if (cpi->cpi_xmaxeax >= 0x80000008) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	620
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	621 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	622
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	623 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	624 * In AMD parlance chip is really a node while Solaris
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	625 * sees chip as equivalent to socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	626 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	627 cpi->cpi_ncore_per_chip =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	628 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	629 if (coreidsz == 0) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	630 /* Use legacy method */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	631 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	632 coreidsz++;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	633 if (coreidsz == 0)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	634 coreidsz = 1;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	635 }
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	636 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	637 /* Assume single-core part */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	638 cpi->cpi_ncore_per_chip = 1;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	639 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	640
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	641 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	642 cpi->cpi_apicid & ((1<<coreidsz) - 1);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	643 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	644
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	645 /* Get nodeID */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	646 if (cpi->cpi_family == 0xf) {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	647 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	648 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	649 } else if (cpi->cpi_family == 0x10) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	650 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	651 * See if we are a multi-node processor.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	652 * All processors in the system have the same number of nodes
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	653 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	654 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	655 if ((cpi->cpi_model < 8) \|\| BITX(nb_caps_reg, 29, 29) == 0) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	656 /* Single-node */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	657 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	658 coreidsz);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	659 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	660 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	661
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	662 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	663 * Multi-node revision D (2 nodes per package
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	664 * are supported)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	665 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	666 cpi->cpi_procnodes_per_pkg = 2;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	667
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	668 first_half = (cpi->cpi_pkgcoreid <=
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	669 (cpi->cpi_ncore_per_chip/2 - 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	670
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	671 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	672 /* We are BSP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	673 cpi->cpi_procnodeid = (first_half ? 0 : 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	674 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	675 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	676
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	677 /* We are AP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	678 /* NodeId[2:1] bits to use for reading F3xe8 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	679 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	680
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	681 nb_caps_reg =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	682 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	683
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	684 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	685 * Check IntNodeNum bit (31:30, but bit 31 is
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	686 * always 0 on dual-node processors)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	687 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	688 if (BITX(nb_caps_reg, 30, 30) == 0)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	689 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	690 !first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	691 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	692 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	693 first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	694
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	695 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	696 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	697 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	698 } else if (cpi->cpi_family >= 0x11) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	699 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	700 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	701 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	702 cpi->cpi_procnodeid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	703 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	704 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	705 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	706
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	707 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	708 cpuid_pass1(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	709 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	710 uint32_t mask_ecx, mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	711 uint_t feature = X86_CPUID;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	712 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	713 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	714 int xcpuid;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	715 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	716 extern int idle_cpu_prefer_mwait;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	717 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	718
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	719
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	720 #if !defined(__xpv)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	721 determine_platform();
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	722 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	723 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	724 * Space statically allocated for cpu0, ensure pointer is set
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	725 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	726 if (cpu->cpu_id == 0)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	727 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	728 cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	729 ASSERT(cpi != NULL);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	730 cp = &cpi->cpi_std[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	731 cp->cp_eax = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	732 cpi->cpi_maxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	733 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	734 uint32_t iptr = (uint32_t )cpi->cpi_vendorstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	735 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	736 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	737 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	738 (char )&cpi->cpi_vendorstr[12] = '\0';
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	739 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	740
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	741 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	742 x86_vendor = cpi->cpi_vendor; /* for compatibility */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	743
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	744 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	745 * Limit the range in case of weird hardware
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	746 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	747 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	748 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	749 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	750 goto pass1_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	751
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	752 cp = &cpi->cpi_std[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	753 cp->cp_eax = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	754 (void) __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	755
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	756 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	757 * Extract identifying constants for easy access.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	758 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	759 cpi->cpi_model = CPI_MODEL(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	760 cpi->cpi_family = CPI_FAMILY(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	761
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	762 if (cpi->cpi_family == 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	763 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	764
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	765 /*
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	766 * Beware: AMD uses "extended model" iff base FAMILY == 0xf.
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	767 * Intel, and presumably everyone else, uses model == 0xf, as
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	768 * one would expect (max value means possible overflow). Sigh.
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	769 */
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	770
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	771 switch (cpi->cpi_vendor) {
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	772 case X86_VENDOR_Intel:
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	773 if (IS_EXTENDED_MODEL_INTEL(cpi))
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	774 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
4858 08409e2eed12 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint) ksadhukh parents: 4855 diff changeset	775 break;
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	776 case X86_VENDOR_AMD:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	777 if (CPI_FAMILY(cpi) == 0xf)
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	778 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	779 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	780 default:
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	781 if (cpi->cpi_model == 0xf)
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	782 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	783 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	784 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	785
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	786 cpi->cpi_step = CPI_STEP(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	787 cpi->cpi_brandid = CPI_BRANDID(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	788
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	789 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	790 * default assumptions:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	791 * - believe %edx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	792 * - ignore %ecx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	793 * - 32-bit virtual and physical addressing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	794 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	795 mask_edx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	796 mask_ecx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	797
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	798 cpi->cpi_pabits = cpi->cpi_vabits = 32;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	799
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	800 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	801 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	802 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	803 x86_type = X86_TYPE_P5;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	804 else if (IS_LEGACY_P6(cpi)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	805 x86_type = X86_TYPE_P6;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	806 pentiumpro_bug4046376 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	807 pentiumpro_bug4064495 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	808 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	809 * Clear the SEP bit when it was set erroneously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	810 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	811 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	812 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	813 } else if (IS_NEW_F6(cpi) \|\| cpi->cpi_family == 0xf) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	814 x86_type = X86_TYPE_P4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	815 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	816 * We don't currently depend on any of the %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	817 * features until Prescott, so we'll only check
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	818 * this from P4 onwards. We might want to revisit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	819 * that idea later.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	820 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	821 mask_ecx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	822 } else if (cpi->cpi_family > 0xf)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	823 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	824 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	825 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	826 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	827 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	828 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	829 mask_ecx &= ~CPUID_INTC_ECX_MON;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	830 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	831 case X86_VENDOR_IntelClone:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	832 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	833 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	834 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	835 #if defined(OPTERON_ERRATUM_108)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	836 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	837 cp->cp_eax = (0xf0f & cp->cp_eax) \| 0xc0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	838 cpi->cpi_model = 0xc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	839 } else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	840 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	841 if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	842 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	843 * AMD K5 and K6
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	844 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	845 * These CPUs have an incomplete implementation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	846 * of MCA/MCE which we mask away.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	847 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	848 mask_edx &= ~(CPUID_INTC_EDX_MCE \| CPUID_INTC_EDX_MCA);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	849
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	850 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	851 * Model 0 uses the wrong (APIC) bit
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	852 * to indicate PGE. Fix it here.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	853 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	854 if (cpi->cpi_model == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	855 if (cp->cp_edx & 0x200) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	856 cp->cp_edx &= ~0x200;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	857 cp->cp_edx \|= CPUID_INTC_EDX_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	858 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	859 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	860
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	861 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	862 * Early models had problems w/ MMX; disable.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	863 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	864 if (cpi->cpi_model < 6)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	865 mask_edx &= ~CPUID_INTC_EDX_MMX;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	866 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	867
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	868 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	869 * For newer families, SSE3 and CX16, at least, are valid;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	870 * enable all
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	871 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	872 if (cpi->cpi_family >= 0xf)
771 1c25a2120ec0 6327969 cpuid sse3 feature bit not noted on any AMD processor dmick parents: 359 diff changeset	873 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	874 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	875 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	876 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	877 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	878 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	879 mask_ecx &= ~CPUID_INTC_ECX_MON;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	880
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	881 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	882 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	883 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	884 * processors. AMD does not intend MWAIT to be used in the cpu
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	885 * idle loop on current and future processors. 10h and future
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	886 * AMD processors use more power in MWAIT than HLT.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	887 * Pre-family-10h Opterons do not have the MWAIT instruction.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	888 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	889 idle_cpu_prefer_mwait = 0;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	890 #endif
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	891
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	892 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	893 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	894 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	895 * workaround the NT workaround in CMS 4.1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	896 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	897 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	898 (cpi->cpi_step == 2 \|\| cpi->cpi_step == 3))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	899 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	900 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	901 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	902 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	903 * workaround the NT workarounds again
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	904 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	905 if (cpi->cpi_family == 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	906 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	907 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	908 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	909 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	910 * We rely heavily on the probing in locore
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	911 * to actually figure out what parts, if any,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	912 * of the Cyrix cpuid instruction to believe.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	913 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	914 switch (x86_type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	915 case X86_TYPE_CYRIX_486:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	916 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	917 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	918 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	919 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	920 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	921 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	922 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	923 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	924 CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	925 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	926 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	927 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	928 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	929 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	930 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	931 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	932 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	933 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	934 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	935 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	936 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	937 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	938 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	939 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	940 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	941 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	942 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	943 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	944 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	945 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	946 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	947 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	948 CPUID_INTC_EDX_TSC \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	949 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	950 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	951 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	952 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	953 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	954 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	955 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	956 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	957 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	958 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	959 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	960
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	961 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	962 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	963 * Do not support MONITOR/MWAIT under a hypervisor
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	964 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	965 mask_ecx &= ~CPUID_INTC_ECX_MON;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	966 #endif /* __xpv */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	967
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	968 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	969 * Now we've figured out the masks that determine
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	970 * which bits we choose to believe, apply the masks
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	971 * to the feature words, then map the kernel's view
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	972 * of these feature words into its feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	973 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	974 cp->cp_edx &= mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	975 cp->cp_ecx &= mask_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	976
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	977 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	978 * apply any platform restrictions (we don't call this
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	979 * immediately after __cpuid_insn here, because we need the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	980 * workarounds applied above first)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	981 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	982 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	983
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	984 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	985 * fold in overrides from the "eeprom" mechanism
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	986 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	987 cp->cp_edx \|= cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	988 cp->cp_edx &= ~cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	989
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	990 cp->cp_ecx \|= cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	991 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	992
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	993 if (cp->cp_edx & CPUID_INTC_EDX_PSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	994 feature \|= X86_LARGEPAGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	995 if (cp->cp_edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	996 feature \|= X86_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	997 if (cp->cp_edx & CPUID_INTC_EDX_MSR)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	998 feature \|= X86_MSR;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	999 if (cp->cp_edx & CPUID_INTC_EDX_MTRR)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1000 feature \|= X86_MTRR;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1001 if (cp->cp_edx & CPUID_INTC_EDX_PGE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1002 feature \|= X86_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1003 if (cp->cp_edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1004 feature \|= X86_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1005 if (cp->cp_edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1006 feature \|= X86_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1007 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1008 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1009 feature \|= X86_MCA;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1010 if (cp->cp_edx & CPUID_INTC_EDX_PAE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1011 feature \|= X86_PAE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1012 if (cp->cp_edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1013 feature \|= X86_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1014 if (cp->cp_ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1015 feature \|= X86_CX16;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1016 if (cp->cp_edx & CPUID_INTC_EDX_PAT)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1017 feature \|= X86_PAT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1018 if (cp->cp_edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1019 feature \|= X86_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1020 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1021 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1022 * In our implementation, fxsave/fxrstor
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1023 * are prerequisites before we'll even
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1024 * try and do SSE things.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1025 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1026 if (cp->cp_edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1027 feature \|= X86_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1028 if (cp->cp_edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1029 feature \|= X86_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1030 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1031 feature \|= X86_SSE3;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1032 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1033 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1034 feature \|= X86_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1035 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1036 feature \|= X86_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1037 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1038 feature \|= X86_SSE4_2;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	1039 if (cp->cp_ecx & CPUID_INTC_ECX_AES)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	1040 feature \|= X86_AES;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1041 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1042 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1043 if (cp->cp_edx & CPUID_INTC_EDX_DE)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1044 feature \|= X86_DE;
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1045 #if !defined(__xpv)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1046 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1047
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1048 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1049 * We require the CLFLUSH instruction for erratum workaround
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1050 * to use MONITOR/MWAIT.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1051 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1052 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1053 cpi->cpi_mwait.support \|= MWAIT_SUPPORT;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1054 feature \|= X86_MWAIT;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1055 } else {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1056 extern int idle_cpu_assert_cflush_monitor;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1057
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1058 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1059 * All processors we are aware of which have
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1060 * MONITOR/MWAIT also have CLFLUSH.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1061 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1062 if (idle_cpu_assert_cflush_monitor) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1063 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1064 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1065 }
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1066 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1067 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1068 #endif /* __xpv */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1069
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1070 /*
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1071 * Only need it first time, rest of the cpus would follow suite.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1072 * we only capture this for the bootcpu.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1073 */
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1074 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1075 feature \|= X86_CLFSH;
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1076 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1077 }
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1078
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1079 if (feature & X86_PAE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1080 cpi->cpi_pabits = 36;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1081
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1082 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1083 * Hyperthreading configuration is slightly tricky on Intel
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1084 * and pure clones, and even trickier on AMD.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1085 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1086 * (AMD chose to set the HTT bit on their CMP processors,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1087 * even though they're not actually hyperthreaded. Thus it
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1088 * takes a bit more work to figure out what's really going
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1089 * on ... see the handling of the CMP_LGCY bit below)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1090 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1091 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1092 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1093 if (cpi->cpi_ncpu_per_chip > 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1094 feature \|= X86_HTT;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1095 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1096 cpi->cpi_ncpu_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1097 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1098
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1099 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1100 * Work on the "extended" feature information, doing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1101 * some basic initialization for cpuid_pass2()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1102 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1103 xcpuid = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1104 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1105 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1106 if (IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1107 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1108 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1109 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1110 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1111 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1112 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1113 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1114 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1115 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1116 * Only these Cyrix CPUs are -known- to support
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1117 * extended cpuid operations.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1118 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1119 if (x86_type == X86_TYPE_VIA_CYRIX_III \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1120 x86_type == X86_TYPE_CYRIX_GXm)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1121 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1122 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1123 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1124 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1125 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1126 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1127 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1128 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1129
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1130 if (xcpuid) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1131 cp = &cpi->cpi_extd[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1132 cp->cp_eax = 0x80000000;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1133 cpi->cpi_xmaxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1134 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1135
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1136 if (cpi->cpi_xmaxeax & 0x80000000) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1137
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1138 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1139 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1140
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1141 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1142 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1143 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1144 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1145 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1146 cp = &cpi->cpi_extd[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1147 cp->cp_eax = 0x80000001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1148 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1149
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1150 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1151 cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1152 cpi->cpi_model == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1153 cpi->cpi_step == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1154 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1155 * K6 model 6 uses bit 10 to indicate SYSC
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1156 * Later models use bit 11. Fix it here.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1157 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1158 if (cp->cp_edx & 0x400) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1159 cp->cp_edx &= ~0x400;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1160 cp->cp_edx \|= CPUID_AMD_EDX_SYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1161 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1162 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1163
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1164 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1165
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1166 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1167 * Compute the additions to the kernel's feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1168 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1169 if (cp->cp_edx & CPUID_AMD_EDX_NX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1170 feature \|= X86_NX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1171
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1172 /*
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1173 * Regardless whether or not we boot 64-bit,
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1174 * we should have a way to identify whether
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1175 * the CPU is capable of running 64-bit.
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1176 */
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1177 if (cp->cp_edx & CPUID_AMD_EDX_LM)
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1178 feature \|= X86_64;
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1179
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1180 #if defined(__amd64)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1181 /* 1 GB large page - enable only for 64 bit kernel */
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1182 if (cp->cp_edx & CPUID_AMD_EDX_1GPG)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1183 feature \|= X86_1GPG;
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1184 #endif
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1185
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1186 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1187 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1188 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A))
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1189 feature \|= X86_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1190
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1191 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1192 * If both the HTT and CMP_LGCY bits are set,
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1193 * then we're not actually HyperThreaded. Read
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1194 * "AMD CPUID Specification" for more details.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1195 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1196 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1197 (feature & X86_HTT) &&
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1198 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1199 feature &= ~X86_HTT;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1200 feature \|= X86_CMP;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1201 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1202 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1203 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1204 * It's really tricky to support syscall/sysret in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1205 * the i386 kernel; we rely on sysenter/sysexit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1206 * instead. In the amd64 kernel, things are -way-
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1207 * better.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1208 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1209 if (cp->cp_edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1210 feature \|= X86_ASYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1211
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1212 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1213 * While we're thinking about system calls, note
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1214 * that AMD processors don't support sysenter
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1215 * in long mode at all, so don't try to program them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1216 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1217 if (x86_vendor == X86_VENDOR_AMD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1218 feature &= ~X86_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1219 #endif
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	1220 if (cp->cp_edx & CPUID_AMD_EDX_TSCP)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1221 feature \|= X86_TSCP;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1222 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1223 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1224 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1225 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1226
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1227 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1228 * Get CPUID data about processor cores and hyperthreads.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1229 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1230 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1231 case X86_VENDOR_Intel:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1232 if (cpi->cpi_maxeax >= 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1233 cp = &cpi->cpi_std[4];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1234 cp->cp_eax = 4;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1235 cp->cp_ecx = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1236 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1237 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1238 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1239 /FALLTHROUGH/
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1240 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1241 if (cpi->cpi_xmaxeax < 0x80000008)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1242 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1243 cp = &cpi->cpi_extd[8];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1244 cp->cp_eax = 0x80000008;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1245 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1246 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1247
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1248 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1249 * Virtual and physical address limits from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1250 * cpuid override previously guessed values.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1251 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1252 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1253 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1254 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1255 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1256 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1257 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1258
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1259 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1260 * Derive the number of cores per chip
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1261 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1262 switch (cpi->cpi_vendor) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1263 case X86_VENDOR_Intel:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1264 if (cpi->cpi_maxeax < 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1265 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1266 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1267 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1268 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1269 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1270 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1271 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1272 case X86_VENDOR_AMD:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1273 if (cpi->cpi_xmaxeax < 0x80000008) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1274 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1275 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1276 } else {
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1277 /*
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1278 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1279 * 1 less than the number of physical cores on
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1280 * the chip. In family 0x10 this value can
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1281 * be affected by "downcoring" - it reflects
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1282 * 1 less than the number of cores actually
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1283 * enabled on this node.
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1284 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1285 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1286 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1287 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1288 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1289 default:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1290 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1291 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1292 }
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1293
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1294 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1295 * Get CPUID data about TSC Invariance in Deep C-State.
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1296 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1297 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1298 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1299 if (cpi->cpi_maxeax >= 7) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1300 cp = &cpi->cpi_extd[7];
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1301 cp->cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1302 cp->cp_ecx = 0;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1303 (void) __cpuid_insn(cp);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1304 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1305 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1306 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1307 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1308 }
5284 2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1309 } else {
2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1310 cpi->cpi_ncore_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1311 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1312
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1313 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1314 * If more than one core, then this processor is CMP.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1315 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1316 if (cpi->cpi_ncore_per_chip > 1)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1317 feature \|= X86_CMP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1318
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1319 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1320 * If the number of cores is the same as the number
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1321 * of CPUs, then we cannot have HyperThreading.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1322 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1323 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1324 feature &= ~X86_HTT;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1325
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1326 cpi->cpi_apicid = CPI_APIC_ID(cpi);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1327 cpi->cpi_procnodes_per_pkg = 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1328
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1329 if ((feature & (X86_HTT \| X86_CMP)) == 0) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1330 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1331 * Single-core single-threaded processors.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1332 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1333 cpi->cpi_chipid = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1334 cpi->cpi_clogid = 0;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1335 cpi->cpi_coreid = cpu->cpu_id;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1336 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1337 if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1338 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1339 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1340 cpi->cpi_procnodeid = cpi->cpi_chipid;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1341 } else if (cpi->cpi_ncpu_per_chip > 1) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1342 if (cpi->cpi_vendor == X86_VENDOR_Intel)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1343 cpuid_intel_getids(cpu, feature);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1344 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1345 cpuid_amd_getids(cpu);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1346 else {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1347 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1348 * All other processors are currently
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1349 * assumed to have single cores.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1350 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1351 cpi->cpi_coreid = cpi->cpi_chipid;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1352 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1353 cpi->cpi_procnodeid = cpi->cpi_chipid;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1354 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1355 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1356
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1357 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1358 * Synthesize chip "revision" and socket type
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1359 */
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1360 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1361 cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1362 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1363 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1364 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1365 cpi->cpi_model, cpi->cpi_step);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1366
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1367 pass1_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1368 cpi->cpi_pass = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1369 return (feature);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1370 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1371
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1372 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1373 * Make copies of the cpuid table entries we depend on, in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1374 * part for ease of parsing now, in part so that we have only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1375 * one place to correct any of it, in part for ease of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1376 * later export to userland, and in part so we can look at
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1377 * this stuff in a crash dump.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1378 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1379
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1380 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1381 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1382 cpuid_pass2(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1383 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1384 uint_t n, nmax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1385 int i;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1386 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1387 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1388 uint32_t *iptr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1389 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1390
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1391 ASSERT(cpi->cpi_pass == 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1392
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1393 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1394 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1395
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1396 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1397 nmax = NMAX_CPI_STD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1398 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1399 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1400 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1401 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1402 cp->cp_eax = n;
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1403
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1404 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1405 * CPUID function 4 expects %ecx to be initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1406 * with an index which indicates which cache to return
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1407 * information about. The OS is expected to call function 4
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1408 * with %ecx set to 0, 1, 2, ... until it returns with
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1409 * EAX[4:0] set to 0, which indicates there are no more
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1410 * caches.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1411 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1412 * Here, populate cpi_std[4] with the information returned by
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1413 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1414 * when dynamic memory allocation becomes available.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1415 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1416 * Note: we need to explicitly initialize %ecx here, since
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1417 * function 4 may have been previously invoked.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1418 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1419 if (n == 4)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1420 cp->cp_ecx = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1421
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1422 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1423 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1424 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1425 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1426 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1427 * "the lower 8 bits of the %eax register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1428 * contain a value that identifies the number
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1429 * of times the cpuid [instruction] has to be
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1430 * executed to obtain a complete image of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1431 * processor's caching systems."
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1432 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1433 * How do they make this stuff up?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1434 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1435 cpi->cpi_ncache = sizeof (cp)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1436 BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1437 if (cpi->cpi_ncache == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1438 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1439 cpi->cpi_ncache--; /* skip count byte */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1440
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1441 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1442 * Well, for now, rather than attempt to implement
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1443 * this slightly dubious algorithm, we just look
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1444 * at the first 15 ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1445 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1446 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1447 cpi->cpi_ncache = sizeof (*cp) - 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1448
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1449 dp = cpi->cpi_cacheinfo;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1450 if (BITX(cp->cp_eax, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1451 uint8_t p = (void )&cp->cp_eax;
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1452 for (i = 1; i < 4; i++)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1453 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1454 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1455 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1456 if (BITX(cp->cp_ebx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1457 uint8_t p = (void )&cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1458 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1459 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1460 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1461 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1462 if (BITX(cp->cp_ecx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1463 uint8_t p = (void )&cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1464 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1465 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1466 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1467 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1468 if (BITX(cp->cp_edx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1469 uint8_t p = (void )&cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1470 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1471 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1472 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1473 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1474 break;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1475
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1476 case 3: /* Processor serial number, if PSN supported */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1477 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1478
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1479 case 4: /* Deterministic cache parameters */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1480 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1481
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1482 case 5: /* Monitor/Mwait parameters */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1483 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1484 size_t mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1485
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1486 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1487 * check cpi_mwait.support which was set in cpuid_pass1
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1488 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1489 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1490 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1491
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1492 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1493 * Protect ourself from insane mwait line size.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1494 * Workaround for incomplete hardware emulator(s).
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1495 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1496 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1497 if (mwait_size < sizeof (uint32_t) \|\|
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1498 !ISP2(mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1499 #if DEBUG
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1500 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1501 "size %ld", cpu->cpu_id, (long)mwait_size);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1502 #endif
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1503 break;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1504 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1505
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1506 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1507 cpi->cpi_mwait.mon_max = mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1508 if (MWAIT_EXTENSION(cpi)) {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1509 cpi->cpi_mwait.support \|= MWAIT_EXTENSIONS;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1510 if (MWAIT_INT_ENABLE(cpi))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1511 cpi->cpi_mwait.support \|=
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1512 MWAIT_ECX_INT_ENABLE;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1513 }
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1514 break;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1515 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1516 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1517 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1518 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1519 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1520
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1521 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1522 struct cpuid_regs regs;
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1523
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1524 cp = &regs;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1525 cp->cp_eax = 0xB;
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1526 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1527
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1528 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1529
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1530 /*
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1531 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1532 * indicates that the extended topology enumeration leaf is
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1533 * available.
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1534 */
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1535 if (cp->cp_ebx) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1536 uint32_t x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1537 uint_t coreid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1538 uint_t ncpu_per_core = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1539 uint_t chipid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1540 uint_t ncpu_per_chip = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1541 uint_t i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1542 uint_t level;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1543
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1544 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1545 cp->cp_eax = 0xB;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1546 cp->cp_ecx = i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1547
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1548 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1549 level = CPI_CPU_LEVEL_TYPE(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1550
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1551 if (level == 1) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1552 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1553 coreid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1554 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1555 } else if (level == 2) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1556 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1557 chipid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1558 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1559 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1560 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1561
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1562 cpi->cpi_apicid = x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1563 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1564 cpi->cpi_ncore_per_chip = ncpu_per_chip /
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1565 ncpu_per_core;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1566 cpi->cpi_chipid = x2apic_id >> chipid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1567 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1568 cpi->cpi_coreid = x2apic_id >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1569 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1570 }
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1571
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1572 /* Make cp NULL so that we don't stumble on others */
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1573 cp = NULL;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1574 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1575
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1576 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1577 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1578
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1579 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1580 nmax = NMAX_CPI_EXTD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1581 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1582 * Copy the extended properties, fixing them as we go.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1583 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1584 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1585 iptr = (void *)cpi->cpi_brandstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1586 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1587 cp->cp_eax = 0x80000000 + n;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1588 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1589 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1590 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1591 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1592 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1593 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1594 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1595 * Extract the brand string
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1596 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1597 *iptr++ = cp->cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1598 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1599 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1600 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1601 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1602 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1603 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1604 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1605 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1606 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1607 * parts to report the sizes of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1608 * TLB for large pages. Before then,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1609 * we don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1610 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1611 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1612 (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1613 cpi->cpi_model < 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1614 cp->cp_eax = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1615 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1616 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1617 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1618 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1619 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1620 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1621 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1622 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1623 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1624 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1625 * AMD parts with L2 TLB's.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1626 * Before then, don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1627 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1628 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1629 cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1630 cpi->cpi_model < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1631 cp->cp_eax = cp->cp_ebx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1632 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1633 * AMD Duron rev A0 reports L2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1634 * cache size incorrectly as 1K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1635 * when it is really 64K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1636 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1637 if (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1638 cpi->cpi_model == 3 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1639 cpi->cpi_step == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1640 cp->cp_ecx &= 0xffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1641 cp->cp_ecx \|= 0x400000;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1642 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1643 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1644 case X86_VENDOR_Cyrix: /* VIA C3 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1645 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1646 * VIA C3 processors are a bit messed
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1647 * up w.r.t. encoding cache sizes in %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1648 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1649 if (cpi->cpi_family != 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1650 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1651 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1652 * model 7 and 8 were incorrectly encoded
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1653 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1654 * xxx is model 8 really broken?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1655 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1656 if (cpi->cpi_model == 7 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1657 cpi->cpi_model == 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1658 cp->cp_ecx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1659 BITX(cp->cp_ecx, 31, 24) << 16 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1660 BITX(cp->cp_ecx, 23, 16) << 12 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1661 BITX(cp->cp_ecx, 15, 8) << 8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1662 BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1663 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1664 * model 9 stepping 1 has wrong associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1665 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1666 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1667 cp->cp_ecx \|= 8 << 12;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1668 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1669 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1670 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1671 * Extended L2 Cache features function.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1672 * First appeared on Prescott.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1673 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1674 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1675 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1676 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1677 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1678 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1679 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1680 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1681 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1682
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1683 pass2_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1684 cpi->cpi_pass = 2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1685 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1686
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1687 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1688 intel_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1689 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1690 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1691
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1692 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1693 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1694 return ("i486");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1695
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1696 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1697 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1698 return ("Intel Pentium(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1699 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1700 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1701 uint_t celeron, xeon;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1702 const struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1703 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1704 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1705 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1706 return ("Intel Pentium(r) Pro");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1707 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1708 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1709 return ("Intel Pentium(r) II");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1710 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1711 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1712 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1713 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1714 celeron = xeon = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1715 cp = &cpi->cpi_std[2]; /* cache info */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1716
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1717 for (i = 1; i < 4; i++) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1718 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1719
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1720 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1721 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1722 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1723 if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1724 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1725 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1726
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1727 for (i = 0; i < 2; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1728 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1729
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1730 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1731 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1732 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1733 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1734 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1735 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1736
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1737 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1738 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1739
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1740 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1741 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1742 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1743 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1744 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1745 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1746
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1747 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1748 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1749
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1750 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1751 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1752 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1753 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1754 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1755 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1756
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1757 if (celeron)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1758 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1759 if (xeon)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1760 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1761 "Intel Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1762 "Intel Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1763 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1764 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1765 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1766 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1767 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1768 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1769 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1770 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1771 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1772
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1773 /* BrandID is present if the field is nonzero */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1774 if (cpi->cpi_brandid != 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1775 static const struct {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1776 uint_t bt_bid;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1777 const char *bt_str;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1778 } brand_tbl[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1779 { 0x1, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1780 { 0x2, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1781 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1782 { 0x4, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1783 { 0x6, "Mobile Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1784 { 0x7, "Mobile Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1785 { 0x8, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1786 { 0x9, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1787 { 0xa, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1788 { 0xb, "Intel(r) Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1789 { 0xc, "Intel(r) Xeon(tm) MP" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1790 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1791 { 0xf, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1792 { 0x11, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1793 { 0x12, "Intel(r) Celeron(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1794 { 0x13, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1795 { 0x14, "Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1796 { 0x15, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1797 { 0x16, "Intel(r) Pentium(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1798 { 0x17, "Mobile Intel(r) Celeron(r)" }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1799 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1800 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1801 uint_t sgn;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1802
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1803 sgn = (cpi->cpi_family << 8) \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1804 (cpi->cpi_model << 4) \| cpi->cpi_step;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1805
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1806 for (i = 0; i < btblmax; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1807 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1808 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1809 if (i < btblmax) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1810 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1811 return ("Intel(r) Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1812 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1813 return ("Intel(r) Xeon(tm) MP");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1814 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1815 return ("Intel(r) Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1816 return (brand_tbl[i].bt_str);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1817 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1818 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1819
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1820 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1821 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1822
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1823 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1824 amd_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1825 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1826 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1827 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1828 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1829
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1830 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1831 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1832 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1833 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1834 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1835 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1836 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1837 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1838 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1839 return ("AMD-K5(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1840 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1841 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1842 return ("AMD-K6(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1843 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1844 return ("AMD-K6(r)-2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1845 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1846 return ("AMD-K6(r)-III");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1847 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1848 return ("AMD (family 5)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1849 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1850 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1851 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1852 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1853 return ("AMD-K7(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1854 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1855 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1856 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1857 return ("AMD Athlon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1858 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1859 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1860 return ("AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1861 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1862 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1863 case 10:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1864 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1865 * Use the L2 cache size to distinguish
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1866 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1867 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1868 "AMD Athlon(tm)" : "AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1869 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1870 return ("AMD (family 6)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1871 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1872 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1873 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1874 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1875
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1876 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1877 cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1878 switch (BITX(cpi->cpi_brandid, 7, 5)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1879 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1880 return ("AMD Opteron(tm) UP 1xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1881 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1882 return ("AMD Opteron(tm) DP 2xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1883 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1884 return ("AMD Opteron(tm) MP 8xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1885 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1886 return ("AMD Opteron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1887 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1888 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1889
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1890 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1891 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1892
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1893 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1894 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1895 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1896 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1897 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1898 type == X86_TYPE_CYRIX_486)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1899 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1900
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1901 switch (type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1902 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1903 return ("Cyrix 6x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1904 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1905 return ("Cyrix 6x86L");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1906 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1907 return ("Cyrix 6x86MX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1908 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1909 return ("Cyrix GXm");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1910 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1911 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1912 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1913 return ("Cyrix M2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1914 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1915 return ("VIA Cyrix M3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1916 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1917 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1918 * Have another wild guess ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1919 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1920 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1921 return ("Cyrix 5x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1922 else if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1923 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1924 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1925 return ("Cyrix 6x86"); /* Cyrix M1 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1926 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1927 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1928 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1929 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1930 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1931 } else if (cpi->cpi_family == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1932 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1933 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1934 return ("Cyrix 6x86MX"); /* Cyrix M2? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1935 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1936 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1937 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1938 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1939 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1940 return ("VIA C3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1941 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1942 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1943 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1944 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1945 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1946 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1947 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1948 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1949
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1950 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1951 * This only gets called in the case that the CPU extended
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1952 * feature brand string (0x80000002, 0x80000003, 0x80000004)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1953 * aren't available, or contain null bytes for some reason.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1954 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1955 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1956 fabricate_brandstr(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1957 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1958 const char *brand = NULL;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1959
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1960 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1961 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1962 brand = intel_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1963 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1964 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1965 brand = amd_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1966 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1967 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1968 brand = cyrix_cpubrand(cpi, x86_type);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1969 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1970 case X86_VENDOR_NexGen:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1971 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1972 brand = "NexGen Nx586";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1973 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1974 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1975 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1976 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1977 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1978 brand = "Centaur C6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1979 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1980 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1981 brand = "Centaur C2";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1982 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1983 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1984 brand = "Centaur C3";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1985 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1986 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1987 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1988 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1989 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1990 case X86_VENDOR_Rise:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1991 if (cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1992 (cpi->cpi_model == 0 \|\| cpi->cpi_model == 2))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1993 brand = "Rise mP6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1994 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1995 case X86_VENDOR_SiS:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1996 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1997 brand = "SiS 55x";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1998 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1999 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2000 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2001 brand = "Transmeta Crusoe TM3x00 or TM5x00";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2002 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2003 case X86_VENDOR_NSC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2004 case X86_VENDOR_UMC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2005 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2006 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2007 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2008 if (brand) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2009 (void) strcpy((char *)cpi->cpi_brandstr, brand);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2010 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2011 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2012
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2013 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2014 * If all else fails ...
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2015 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2016 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2017 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2018 cpi->cpi_model, cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2019 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2020
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2021 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2022 * This routine is called just after kernel memory allocation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2023 * becomes available on cpu0, and as part of mp_startup() on
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2024 * the other cpus.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2025 *
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2026 * Fixup the brand string, and collect any information from cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2027 * that requires dynamicically allocated storage to represent.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2028 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2029 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2030 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2031 cpuid_pass3(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2032 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2033 int i, max, shft, level, size;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2034 struct cpuid_regs regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2035 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2036 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2037
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2038 ASSERT(cpi->cpi_pass == 2);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2039
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2040 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2041 * Function 4: Deterministic cache parameters
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2042 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2043 * Take this opportunity to detect the number of threads
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2044 * sharing the last level cache, and construct a corresponding
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2045 * cache id. The respective cpuid_info members are initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2046 * to the default case of "no last level cache sharing".
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2047 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2048 cpi->cpi_ncpu_shr_last_cache = 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2049 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2050
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2051 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2052
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2053 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2054 * Find the # of elements (size) returned by fn 4, and along
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2055 * the way detect last level cache sharing details.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2056 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2057 bzero(&regs, sizeof (regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2058 cp = &regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2059 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2060 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2061 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2062
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2063 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2064
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2065 if (CPI_CACHE_TYPE(cp) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2066 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2067 level = CPI_CACHE_LVL(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2068 if (level > max) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2069 max = level;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2070 cpi->cpi_ncpu_shr_last_cache =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2071 CPI_NTHR_SHR_CACHE(cp) + 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2072 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2073 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2074 cpi->cpi_std_4_size = size = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2075
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2076 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2077 * Allocate the cpi_std_4 array. The first element
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2078 * references the regs for fn 4, %ecx == 0, which
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2079 * cpuid_pass2() stashed in cpi->cpi_std[4].
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2080 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2081 if (size > 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2082 cpi->cpi_std_4 =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2083 kmem_alloc(size * sizeof (cp), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2084 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2085
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2086 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2087 * Allocate storage to hold the additional regs
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2088 * for function 4, %ecx == 1 .. cpi_std_4_size.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2089 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2090 * The regs for fn 4, %ecx == 0 has already
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2091 * been allocated as indicated above.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2092 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2093 for (i = 1; i < size; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2094 cp = cpi->cpi_std_4[i] =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2095 kmem_zalloc(sizeof (regs), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2096 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2097 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2098
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2099 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2100 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2101 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2102 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2103 * Determine the number of bits needed to represent
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2104 * the number of CPUs sharing the last level cache.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2105 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2106 * Shift off that number of bits from the APIC id to
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2107 * derive the cache id.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2108 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2109 shft = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2110 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2111 shft++;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	2112 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2113 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2114
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2115 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2116 * Now fixup the brand string
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2117 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2118 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2119 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2120 } else {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2121
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2122 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2123 * If we successfully extracted a brand string from the cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2124 * instruction, clean it up by removing leading spaces and
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2125 * similar junk.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2126 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2127 if (cpi->cpi_brandstr[0]) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2128 size_t maxlen = sizeof (cpi->cpi_brandstr);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2129 char src, dst;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2130
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2131 dst = src = (char *)cpi->cpi_brandstr;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2132 src[maxlen - 1] = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2133 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2134 * strip leading spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2135 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2136 while (*src == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2137 src++;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2138 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2139 * Remove any 'Genuine' or "Authentic" prefixes
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2140 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2141 if (strncmp(src, "Genuine ", 8) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2142 src += 8;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2143 if (strncmp(src, "Authentic ", 10) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2144 src += 10;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2145
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2146 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2147 * Now do an in-place copy.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2148 * Map (R) to (r) and (TM) to (tm).
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2149 * The era of teletypes is long gone, and there's
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2150 * -really- no need to shout.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2151 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2152 while (*src != '\0') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2153 if (src[0] == '(') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2154 if (strncmp(src + 1, "R)", 2) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2155 (void) strncpy(dst, "(r)", 3);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2156 src += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2157 dst += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2158 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2159 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2160 if (strncmp(src + 1, "TM)", 3) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2161 (void) strncpy(dst, "(tm)", 4);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2162 src += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2163 dst += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2164 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2165 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2166 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2167 dst++ = src++;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2168 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2169 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2170
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2171 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2172 * Finally, remove any trailing spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2173 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2174 while (--dst > cpi->cpi_brandstr)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2175 if (*dst == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2176 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2177 else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2178 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2179 } else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2180 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2181 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2182 cpi->cpi_pass = 3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2183 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2184
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2185 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2186 * This routine is called out of bind_hwcap() much later in the life
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2187 * of the kernel (post_startup()). The job of this routine is to resolve
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2188 * the hardware feature support and kernel support for those features into
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2189 * what we're actually going to tell applications via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2190 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2191 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2192 cpuid_pass4(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2193 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2194 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2195 uint_t hwcap_flags = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2196
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2197 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2198 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2199 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2200
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2201 ASSERT(cpi->cpi_pass == 3);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2202
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2203 if (cpi->cpi_maxeax >= 1) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2204 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2205 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2206
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2207 *edx = CPI_FEATURES_EDX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2208 *ecx = CPI_FEATURES_ECX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2209
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2210 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2211 * [these require explicit kernel support]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2212 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2213 if ((x86_feature & X86_SEP) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2214 *edx &= ~CPUID_INTC_EDX_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2215
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2216 if ((x86_feature & X86_SSE) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2217 *edx &= ~(CPUID_INTC_EDX_FXSR\|CPUID_INTC_EDX_SSE);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2218 if ((x86_feature & X86_SSE2) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2219 *edx &= ~CPUID_INTC_EDX_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2220
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2221 if ((x86_feature & X86_HTT) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2222 *edx &= ~CPUID_INTC_EDX_HTT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2223
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2224 if ((x86_feature & X86_SSE3) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2225 *ecx &= ~CPUID_INTC_ECX_SSE3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2226
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2227 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2228 if ((x86_feature & X86_SSSE3) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2229 *ecx &= ~CPUID_INTC_ECX_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2230 if ((x86_feature & X86_SSE4_1) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2231 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2232 if ((x86_feature & X86_SSE4_2) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2233 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2234 if ((x86_feature & X86_AES) == 0)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2235 *ecx &= ~CPUID_INTC_ECX_AES;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2236 }
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2237
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2238 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2239 * [no explicit support required beyond x87 fp context]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2240 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2241 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2242 *edx &= ~(CPUID_INTC_EDX_FPU \| CPUID_INTC_EDX_MMX);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2243
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2244 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2245 * Now map the supported feature vector to things that we
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2246 * think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2247 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2248 if (*edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2249 hwcap_flags \|= AV_386_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2250 if (*edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2251 hwcap_flags \|= AV_386_FXSR \| AV_386_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2252 if (*edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2253 hwcap_flags \|= AV_386_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2254 if (*ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2255 hwcap_flags \|= AV_386_SSE3;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2256 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2257 if (*ecx & CPUID_INTC_ECX_SSSE3)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2258 hwcap_flags \|= AV_386_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2259 if (*ecx & CPUID_INTC_ECX_SSE4_1)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2260 hwcap_flags \|= AV_386_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2261 if (*ecx & CPUID_INTC_ECX_SSE4_2)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2262 hwcap_flags \|= AV_386_SSE4_2;
8418 a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2263 if (*ecx & CPUID_INTC_ECX_MOVBE)
a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2264 hwcap_flags \|= AV_386_MOVBE;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2265 if (*ecx & CPUID_INTC_ECX_AES)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2266 hwcap_flags \|= AV_386_AES;
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2267 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2268 hwcap_flags \|= AV_386_PCLMULQDQ;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2269 }
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2270 if (*ecx & CPUID_INTC_ECX_POPCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2271 hwcap_flags \|= AV_386_POPCNT;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2272 if (*edx & CPUID_INTC_EDX_FPU)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2273 hwcap_flags \|= AV_386_FPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2274 if (*edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2275 hwcap_flags \|= AV_386_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2276
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2277 if (*edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2278 hwcap_flags \|= AV_386_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2279 if (*edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2280 hwcap_flags \|= AV_386_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2281 if (*edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2282 hwcap_flags \|= AV_386_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2283 if (*ecx & CPUID_INTC_ECX_MON)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2284 hwcap_flags \|= AV_386_MON;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2285 if (*ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2286 hwcap_flags \|= AV_386_CX16;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2287 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2288
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2289 if (x86_feature & X86_HTT)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2290 hwcap_flags \|= AV_386_PAUSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2291
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2292 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2293 goto pass4_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2294
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2295 switch (cpi->cpi_vendor) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2296 struct cpuid_regs cp;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2297 uint32_t edx, ecx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2298
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2299 case X86_VENDOR_Intel:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2300 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2301 * Seems like Intel duplicated what we necessary
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2302 * here to make the initial crop of 64-bit OS's work.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2303 * Hopefully, those are the only "extended" bits
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2304 * they'll add.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2305 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2306 /FALLTHROUGH/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2307
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2308 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2309 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2310 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2311
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2312 *edx = CPI_FEATURES_XTD_EDX(cpi);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2313 *ecx = CPI_FEATURES_XTD_ECX(cpi);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2314
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2315 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2316 * [these features require explicit kernel support]
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2317 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2318 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2319 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2320 if ((x86_feature & X86_TSCP) == 0)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2321 *edx &= ~CPUID_AMD_EDX_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2322 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2323
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2324 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2325 if ((x86_feature & X86_TSCP) == 0)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2326 *edx &= ~CPUID_AMD_EDX_TSCP;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2327 if ((x86_feature & X86_SSE4A) == 0)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2328 *ecx &= ~CPUID_AMD_ECX_SSE4A;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2329 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2330
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2331 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2332 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2333 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2334
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2335 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2336 * [no explicit support required beyond
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2337 * x87 fp context and exception handlers]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2338 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2339 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2340 *edx &= ~(CPUID_AMD_EDX_MMXamd \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2341 CPUID_AMD_EDX_3DNow \| CPUID_AMD_EDX_3DNowx);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2342
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2343 if ((x86_feature & X86_NX) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2344 *edx &= ~CPUID_AMD_EDX_NX;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2345 #if !defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2346 *edx &= ~CPUID_AMD_EDX_LM;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2347 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2348 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2349 * Now map the supported feature vector to
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2350 * things that we think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2351 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2352 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2353 if (*edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2354 hwcap_flags \|= AV_386_AMD_SYSC;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2355 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2356 if (*edx & CPUID_AMD_EDX_MMXamd)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2357 hwcap_flags \|= AV_386_AMD_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2358 if (*edx & CPUID_AMD_EDX_3DNow)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2359 hwcap_flags \|= AV_386_AMD_3DNow;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2360 if (*edx & CPUID_AMD_EDX_3DNowx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2361 hwcap_flags \|= AV_386_AMD_3DNowx;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2362
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2363 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2364 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2365 if (*edx & CPUID_AMD_EDX_TSCP)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2366 hwcap_flags \|= AV_386_TSCP;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2367 if (*ecx & CPUID_AMD_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2368 hwcap_flags \|= AV_386_AHF;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2369 if (*ecx & CPUID_AMD_ECX_SSE4A)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2370 hwcap_flags \|= AV_386_AMD_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2371 if (*ecx & CPUID_AMD_ECX_LZCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2372 hwcap_flags \|= AV_386_AMD_LZCNT;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2373 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2374
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2375 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2376 if (*edx & CPUID_AMD_EDX_TSCP)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2377 hwcap_flags \|= AV_386_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2378 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2379 * Aarrgh.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2380 * Intel uses a different bit in the same word.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2381 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2382 if (*ecx & CPUID_INTC_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2383 hwcap_flags \|= AV_386_AHF;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2384 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2385
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2386 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2387 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2388 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2389 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2390
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2391 case X86_VENDOR_TM:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2392 cp.cp_eax = 0x80860001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2393 (void) __cpuid_insn(&cp);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2394 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2395 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2396
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2397 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2398 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2399 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2400
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2401 pass4_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2402 cpi->cpi_pass = 4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2403 return (hwcap_flags);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2404 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2405
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2406
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2407 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2408 * Simulate the cpuid instruction using the data we previously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2409 * captured about this CPU. We try our best to return the truth
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2410 * about the hardware, independently of kernel support.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2411 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2412 uint32_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2413 cpuid_insn(cpu_t cpu, struct cpuid_regs cp)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2414 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2415 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2416 struct cpuid_regs *xcp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2417
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2418 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2419 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2420 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2421
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2422 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2423
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2424 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2425 * CPUID data is cached in two separate places: cpi_std for standard
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2426 * CPUID functions, and cpi_extd for extended CPUID functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2427 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2428 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2429 xcp = &cpi->cpi_std[cp->cp_eax];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2430 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2431 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2432 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2433 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2434 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2435 * The caller is asking for data from an input parameter which
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2436 * the kernel has not cached. In this case we go fetch from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2437 * the hardware and return the data directly to the user.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2438 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2439 return (__cpuid_insn(cp));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2440
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2441 cp->cp_eax = xcp->cp_eax;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2442 cp->cp_ebx = xcp->cp_ebx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2443 cp->cp_ecx = xcp->cp_ecx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2444 cp->cp_edx = xcp->cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2445 return (cp->cp_eax);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2446 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2447
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2448 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2449 cpuid_checkpass(cpu_t *cpu, int pass)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2450 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2451 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2452 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2453 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2454
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2455 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2456 cpuid_getbrandstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2457 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2458 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2459
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2460 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2461 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2462
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2463 int
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2464 cpuid_is_cmt(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2465 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2466 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2467 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2468
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2469 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2470
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2471 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2472 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2473
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2474 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2475 * AMD and Intel both implement the 64-bit variant of the syscall
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2476 * instruction (syscallq), so if there's -any- support for syscall,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2477 * cpuid currently says "yes, we support this".
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2478 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2479 * However, Intel decided to -not- implement the 32-bit variant of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2480 * syscall instruction, so we provide a predicate to allow our caller
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2481 * to test that subtlety here.
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2482 *
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2483 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2484 * even in the case where the hardware would in fact support it.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2485 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2486 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2487 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2488 cpuid_syscall32_insn(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2489 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2490 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2491
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2492 #if !defined(__xpv)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2493 if (cpu == NULL)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2494 cpu = CPU;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2495
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2496 /CSTYLED/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2497 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2498 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2499
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2500 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2501 cpi->cpi_xmaxeax >= 0x80000001 &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2502 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2503 return (1);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2504 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2505 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2506 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2507 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2508
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2509 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2510 cpuid_getidstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2511 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2512 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2513
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2514 static const char fmt[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2515 "x86 (%s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2516 static const char fmt_ht[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2517 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2518
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2519 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2520
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2521 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2522 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2523 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2524 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2525 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2526 return (snprintf(s, n, fmt,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2527 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2528 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2529 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2530 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2531
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2532 const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2533 cpuid_getvendorstr(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2534 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2535 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2536 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2537 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2538
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2539 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2540 cpuid_getvendor(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2541 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2542 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2543 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2544 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2545
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2546 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2547 cpuid_getfamily(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2548 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2549 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2550 return (cpu->cpu_m.mcpu_cpi->cpi_family);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2551 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2552
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2553 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2554 cpuid_getmodel(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2555 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2556 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2557 return (cpu->cpu_m.mcpu_cpi->cpi_model);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2558 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2559
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2560 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2561 cpuid_get_ncpu_per_chip(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2562 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2563 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2564 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2565 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2566
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2567 uint_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2568 cpuid_get_ncore_per_chip(cpu_t *cpu)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2569 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2570 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2571 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2572 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2573
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2574 uint_t
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2575 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2576 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2577 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2578 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2579 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2580
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2581 id_t
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2582 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2583 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2584 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2585 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2586 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2587
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2588 uint_t
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2589 cpuid_getstep(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2590 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2591 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2592 return (cpu->cpu_m.mcpu_cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2593 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2594
4581 b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2595 uint_t
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2596 cpuid_getsig(struct cpu *cpu)
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2597 {
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2598 ASSERT(cpuid_checkpass(cpu, 1));
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2599 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2600 }
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2601
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2602 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2603 cpuid_getchiprev(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2604 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2605 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2606 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2607 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2608
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2609 const char *
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2610 cpuid_getchiprevstr(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2611 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2612 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2613 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2614 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2615
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2616 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2617 cpuid_getsockettype(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2618 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2619 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2620 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2621 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2622
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2623 const char *
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2624 cpuid_getsocketstr(cpu_t *cpu)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2625 {
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2626 static const char *socketstr = NULL;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2627 struct cpuid_info *cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2628
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2629 ASSERT(cpuid_checkpass(cpu, 1));
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2630 cpi = cpu->cpu_m.mcpu_cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2631
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2632 /* Assume that socket types are the same across the system */
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2633 if (socketstr == NULL)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2634 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2635 cpi->cpi_model, cpi->cpi_step);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2636
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2637
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2638 return (socketstr);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2639 }
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2640
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2641 int
5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2642 cpuid_get_chipid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2643 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2644 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2645
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2646 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2647 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2648 return (cpu->cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2649 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2650
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2651 id_t
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2652 cpuid_get_coreid(cpu_t *cpu)
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2653 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2654 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2655 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2656 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2657
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2658 int
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2659 cpuid_get_pkgcoreid(cpu_t *cpu)
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2660 {
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2661 ASSERT(cpuid_checkpass(cpu, 1));
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2662 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2663 }
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2664
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2665 int
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2666 cpuid_get_clogid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2667 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2668 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2669 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2670 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2671
11389 dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2672 int
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2673 cpuid_get_cacheid(cpu_t *cpu)
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2674 {
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2675 ASSERT(cpuid_checkpass(cpu, 1));
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2676 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2677 }
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2678
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2679 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2680 cpuid_get_procnodeid(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2681 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2682 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2683 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2684 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2685
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2686 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2687 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2688 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2689 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2690 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2691 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2692
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2693 /ARGSUSED/
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2694 int
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2695 cpuid_have_cr8access(cpu_t *cpu)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2696 {
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2697 #if defined(__amd64)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2698 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2699 #else
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2700 struct cpuid_info *cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2701
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2702 ASSERT(cpu != NULL);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2703 cpi = cpu->cpu_m.mcpu_cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2704 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2705 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2706 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2707 return (0);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2708 #endif
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2709 }
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2710
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2711 uint32_t
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2712 cpuid_get_apicid(cpu_t *cpu)
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2713 {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2714 ASSERT(cpuid_checkpass(cpu, 1));
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2715 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2716 return (UINT32_MAX);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2717 } else {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2718 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2719 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2720 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2721
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2722 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2723 cpuid_get_addrsize(cpu_t cpu, uint_t pabits, uint_t *vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2724 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2725 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2726
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2727 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2728 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2729 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2730
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2731 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2732
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2733 if (pabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2734 *pabits = cpi->cpi_pabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2735 if (vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2736 *vabits = cpi->cpi_vabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2737 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2738
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2739 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2740 * Returns the number of data TLB entries for a corresponding
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2741 * pagesize. If it can't be computed, or isn't known, the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2742 * routine returns zero. If you ask about an architecturally
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2743 * impossible pagesize, the routine will panic (so that the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2744 * hat implementor knows that things are inconsistent.)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2745 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2746 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2747 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2748 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2749 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2750 uint_t dtlb_nent = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2751
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2752 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2753 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2754 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2755
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2756 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2757
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2758 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2759 * Check the L2 TLB info
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2760 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2761 if (cpi->cpi_xmaxeax >= 0x80000006) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2762 struct cpuid_regs *cp = &cpi->cpi_extd[6];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2763
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2764 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2765
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2766 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2767 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2768 * All zero in the top 16 bits of the register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2769 * indicates a unified TLB. Size is in low 16 bits.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2770 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2771 if ((cp->cp_ebx & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2772 dtlb_nent = cp->cp_ebx & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2773 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2774 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2775 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2776
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2777 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2778 if ((cp->cp_eax & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2779 dtlb_nent = cp->cp_eax & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2780 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2781 dtlb_nent = BITX(cp->cp_eax, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2782 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2783
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2784 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2785 panic("unknown L2 pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2786 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2787 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2788 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2789
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2790 if (dtlb_nent != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2791 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2792
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2793 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2794 * No L2 TLB support for this size, try L1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2795 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2796 if (cpi->cpi_xmaxeax >= 0x80000005) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2797 struct cpuid_regs *cp = &cpi->cpi_extd[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2798
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2799 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2800 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2801 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2802 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2803 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2804 dtlb_nent = BITX(cp->cp_eax, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2805 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2806 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2807 panic("unknown L1 d-TLB pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2808 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2809 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2810 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2811
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2812 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2813 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2814
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2815 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2816 * Return 0 if the erratum is not present or not applicable, positive
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2817 * if it is, and negative if the status of the erratum is unknown.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2818 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2819 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	2820 * Processors" #25759, Rev 3.57, August 2005
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2821 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2822 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2823 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2824 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2825 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2826 uint_t eax;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2827
2584 c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2828 /*
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2829 * Bail out if this CPU isn't an AMD CPU, or if it's
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2830 * a legacy (32-bit) AMD CPU.
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2831 */
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2832 if (cpi->cpi_vendor != X86_VENDOR_AMD \|\|
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2833 cpi->cpi_family == 4 \|\| cpi->cpi_family == 5 \|\|
6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2834 cpi->cpi_family == 6)
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2835
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2836 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2837
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2838 eax = cpi->cpi_std[1].cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2839
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2840 #define SH_B0(eax) (eax == 0xf40 \|\| eax == 0xf50)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2841 #define SH_B3(eax) (eax == 0xf51)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2842 #define B(eax) (SH_B0(eax) \|\| SH_B3(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2843
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2844 #define SH_C0(eax) (eax == 0xf48 \|\| eax == 0xf58)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2845
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2846 #define SH_CG(eax) (eax == 0xf4a \|\| eax == 0xf5a \|\| eax == 0xf7a)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2847 #define DH_CG(eax) (eax == 0xfc0 \|\| eax == 0xfe0 \|\| eax == 0xff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2848 #define CH_CG(eax) (eax == 0xf82 \|\| eax == 0xfb2)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2849 #define CG(eax) (SH_CG(eax) \|\| DH_CG(eax) \|\| CH_CG(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2850
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2851 #define SH_D0(eax) (eax == 0x10f40 \|\| eax == 0x10f50 \|\| eax == 0x10f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2852 #define DH_D0(eax) (eax == 0x10fc0 \|\| eax == 0x10ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2853 #define CH_D0(eax) (eax == 0x10f80 \|\| eax == 0x10fb0)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2854 #define D0(eax) (SH_D0(eax) \|\| DH_D0(eax) \|\| CH_D0(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2855
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2856 #define SH_E0(eax) (eax == 0x20f50 \|\| eax == 0x20f40 \|\| eax == 0x20f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2857 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2858 #define DH_E3(eax) (eax == 0x20fc0 \|\| eax == 0x20ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2859 #define SH_E4(eax) (eax == 0x20f51 \|\| eax == 0x20f71)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2860 #define BH_E4(eax) (eax == 0x20fb1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2861 #define SH_E5(eax) (eax == 0x20f42)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2862 #define DH_E6(eax) (eax == 0x20ff2 \|\| eax == 0x20fc2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2863 #define JH_E6(eax) (eax == 0x20f12 \|\| eax == 0x20f32)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2864 #define EX(eax) (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2865 SH_E4(eax) \|\| BH_E4(eax) \|\| SH_E5(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2866 DH_E6(eax) \|\| JH_E6(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2867
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2868 #define DR_AX(eax) (eax == 0x100f00 \|\| eax == 0x100f01 \|\| eax == 0x100f02)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2869 #define DR_B0(eax) (eax == 0x100f20)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2870 #define DR_B1(eax) (eax == 0x100f21)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2871 #define DR_BA(eax) (eax == 0x100f2a)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2872 #define DR_B2(eax) (eax == 0x100f22)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2873 #define DR_B3(eax) (eax == 0x100f23)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2874 #define RB_C0(eax) (eax == 0x100f40)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2875
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2876 switch (erratum) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2877 case 1:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2878 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2879 case 51: /* what does the asterisk mean? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2880 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2881 case 52:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2882 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2883 case 57:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2884 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2885 case 58:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2886 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2887 case 60:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2888 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2889 case 61:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2890 case 62:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2891 case 63:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2892 case 64:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2893 case 65:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2894 case 66:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2895 case 68:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2896 case 69:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2897 case 70:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2898 case 71:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2899 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2900 case 72:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2901 return (SH_B0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2902 case 74:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2903 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2904 case 75:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2905 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2906 case 76:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2907 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2908 case 77:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2909 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2910 case 78:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2911 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2912 case 79:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2913 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2914 case 80:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2915 case 81:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2916 case 82:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2917 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2918 case 83:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2919 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2920 case 85:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2921 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2922 case 86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2923 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2924 case 88:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2925 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2926 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2927 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2928 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2929 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2930 case 89:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2931 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2932 case 90:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2933 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2934 case 91:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2935 case 92:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2936 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2937 case 93:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2938 return (SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2939 case 94:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2940 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2941 case 95:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2942 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2943 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2944 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2945 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2946 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2947 case 96:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2948 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2949 case 97:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2950 case 98:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2951 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2952 case 99:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2953 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2954 case 100:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2955 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2956 case 101:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2957 case 103:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2958 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2959 case 104:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2960 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2961 case 105:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2962 case 106:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2963 case 107:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2964 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2965 case 108:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2966 return (DH_CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2967 case 109:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2968 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2969 case 110:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2970 return (D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2971 case 111:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2972 return (CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2973 case 112:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2974 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2975 case 113:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2976 return (eax == 0x20fc0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2977 case 114:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2978 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2979 case 115:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2980 return (SH_E0(eax) \|\| JH_E1(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2981 case 116:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2982 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2983 case 117:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2984 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2985 case 118:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2986 return (SH_E0(eax) \|\| JH_E1(eax) \|\| SH_E4(eax) \|\| BH_E4(eax) \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2987 JH_E6(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2988 case 121:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2989 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2990 case 122:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2991 return (cpi->cpi_family < 0x10 \|\| cpi->cpi_family == 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2992 case 123:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2993 return (JH_E1(eax) \|\| BH_E4(eax) \|\| JH_E6(eax));
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	2994 case 131:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2995 return (cpi->cpi_family < 0x10);
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	2996 case 6336786:
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	2997 /*
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	2998 * Test for AdvPowerMgmtInfo.TscPStateInvariant
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2999 * if this is a K8 family or newer processor
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3000 */
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3001 if (CPI_FAMILY(cpi) == 0xf) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3002 struct cpuid_regs regs;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3003 regs.cp_eax = 0x80000007;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3004 (void) __cpuid_insn(&regs);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3005 return (!(regs.cp_edx & 0x100));
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3006 }
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3007 return (0);
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3008 case 6323525:
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3009 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) \|
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3010 (((eax >> 4) & 0xf) \| ((eax >> 12) & 0xf0))) < 0xf40);
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3011
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3012 case 6671130:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3013 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3014 * check for processors (pre-Shanghai) that do not provide
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3015 * optimal management of 1gb ptes in its tlb.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3016 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3017 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3018
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3019 case 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3020 return (DR_AX(eax) \|\| DR_B0(eax) \|\| DR_B1(eax) \|\| DR_BA(eax) \|\|
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3021 DR_B2(eax) \|\| RB_C0(eax));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3022
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3023 default:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3024 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3025
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3026 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3027 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3028
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3029 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3030 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3031 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3032 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3033 int
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3034 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3035 {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3036 struct cpuid_info *cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3037 uint_t osvwid;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3038 static int osvwfeature = -1;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3039 uint64_t osvwlength;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3040
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3041
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3042 cpi = cpu->cpu_m.mcpu_cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3043
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3044 /* confirm OSVW supported */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3045 if (osvwfeature == -1) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3046 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3047 } else {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3048 /* assert that osvw feature setting is consistent on all cpus */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3049 ASSERT(osvwfeature ==
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3050 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3051 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3052 if (!osvwfeature)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3053 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3054
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3055 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3056
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3057 switch (erratum) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3058 case 298: /* osvwid is 0 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3059 osvwid = 0;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3060 if (osvwlength <= (uint64_t)osvwid) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3061 /* osvwid 0 is unknown */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3062 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3063 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3064
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3065 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3066 * Check the OSVW STATUS MSR to determine the state
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3067 * of the erratum where:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3068 * 0 - fixed by HW
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3069 * 1 - BIOS has applied the workaround when BIOS
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3070 * workaround is available. (Or for other errata,
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3071 * OS workaround is required.)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3072 * For a value of 1, caller will confirm that the
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3073 * erratum 298 workaround has indeed been applied by BIOS.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3074 *
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3075 * A 1 may be set in cpus that have a HW fix
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3076 * in a mixed cpu system. Regarding erratum 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3077 * In a multiprocessor platform, the workaround above
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3078 * should be applied to all processors regardless of
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3079 * silicon revision when an affected processor is
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3080 * present.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3081 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3082
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3083 return (rdmsr(MSR_AMD_OSVW_STATUS +
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3084 (osvwid / OSVW_ID_CNT_PER_MSR)) &
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3085 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3086
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3087 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3088 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3089 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3090 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3091
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3092 static const char assoc_str[] = "associativity";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3093 static const char line_str[] = "line-size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3094 static const char size_str[] = "size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3095
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3096 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3097 add_cache_prop(dev_info_t devi, const char label, const char *type,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3098 uint32_t val)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3099 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3100 char buf[128];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3101
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3102 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3103 * ndi_prop_update_int() is used because it is desirable for
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3104 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3105 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3106 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3107 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3108 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3109
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3110 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3111 * Intel-style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3112 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3113 * Standard cpuid level 2 gives a randomly ordered
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3114 * selection of tags that index into a table that describes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3115 * cache and tlb properties.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3116 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3117
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3118 static const char l1_icache_str[] = "l1-icache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3119 static const char l1_dcache_str[] = "l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3120 static const char l2_cache_str[] = "l2-cache";
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3121 static const char l3_cache_str[] = "l3-cache";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3122 static const char itlb4k_str[] = "itlb-4K";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3123 static const char dtlb4k_str[] = "dtlb-4K";
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3124 static const char itlb2M_str[] = "itlb-2M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3125 static const char itlb4M_str[] = "itlb-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3126 static const char dtlb4M_str[] = "dtlb-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3127 static const char dtlb24_str[] = "dtlb0-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3128 static const char itlb424_str[] = "itlb-4K-2M-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3129 static const char itlb24_str[] = "itlb-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3130 static const char dtlb44_str[] = "dtlb-4K-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3131 static const char sl1_dcache_str[] = "sectored-l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3132 static const char sl2_cache_str[] = "sectored-l2-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3133 static const char itrace_str[] = "itrace-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3134 static const char sl3_cache_str[] = "sectored-l3-cache";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3135 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3136
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3137 static const struct cachetab {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3138 uint8_t ct_code;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3139 uint8_t ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3140 uint16_t ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3141 size_t ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3142 const char *ct_label;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3143 } intel_ctab[] = {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3144 /*
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3145 * maintain descending order!
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3146 *
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3147 * Codes ignored - Reason
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3148 * ----------------------
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3149 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3150 * f0H/f1H - Currently we do not interpret prefetch size by design
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3151 */
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3152 { 0xe4, 16, 64, 810241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3153 { 0xe3, 16, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3154 { 0xe2, 16, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3155 { 0xde, 12, 64, 610241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3156 { 0xdd, 12, 64, 310241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3157 { 0xdc, 12, 64, ((110241024)+(512*1024)), l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3158 { 0xd8, 8, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3159 { 0xd7, 8, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3160 { 0xd6, 8, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3161 { 0xd2, 4, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3162 { 0xd1, 4, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3163 { 0xd0, 4, 64, 512*1024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3164 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3165 { 0xc0, 4, 0, 8, dtlb44_str },
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3166 { 0xba, 4, 0, 64, dtlb4k_str },
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3167 { 0xb4, 4, 0, 256, dtlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3168 { 0xb3, 4, 0, 128, dtlb4k_str },
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3169 { 0xb2, 4, 0, 64, itlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3170 { 0xb0, 4, 0, 128, itlb4k_str },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3171 { 0x87, 8, 64, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3172 { 0x86, 4, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3173 { 0x85, 8, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3174 { 0x84, 8, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3175 { 0x83, 8, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3176 { 0x82, 8, 32, 256*1024, l2_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3177 { 0x80, 8, 64, 512*1024, l2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3178 { 0x7f, 2, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3179 { 0x7d, 8, 64, 210241024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3180 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3181 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3182 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3183 { 0x79, 8, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3184 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3185 { 0x73, 8, 0, 64*1024, itrace_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3186 { 0x72, 8, 0, 32*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3187 { 0x71, 8, 0, 16*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3188 { 0x70, 8, 0, 12*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3189 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3190 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3191 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3192 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3193 { 0x5d, 0, 0, 256, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3194 { 0x5c, 0, 0, 128, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3195 { 0x5b, 0, 0, 64, dtlb44_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3196 { 0x5a, 4, 0, 32, dtlb24_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3197 { 0x59, 0, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3198 { 0x57, 4, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3199 { 0x56, 4, 0, 16, dtlb4M_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3200 { 0x55, 0, 0, 7, itlb24_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3201 { 0x52, 0, 0, 256, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3202 { 0x51, 0, 0, 128, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3203 { 0x50, 0, 0, 64, itlb424_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3204 { 0x4f, 0, 0, 32, itlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3205 { 0x4e, 24, 64, 610241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3206 { 0x4d, 16, 64, 1610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3207 { 0x4c, 12, 64, 1210241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3208 { 0x4b, 16, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3209 { 0x4a, 12, 64, 610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3210 { 0x49, 16, 64, 410241024, l3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3211 { 0x48, 12, 64, 310241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3212 { 0x47, 8, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3213 { 0x46, 4, 64, 410241024, l3_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3214 { 0x45, 4, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3215 { 0x44, 4, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3216 { 0x43, 4, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3217 { 0x42, 4, 32, 256*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3218 { 0x41, 4, 32, 128*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3219 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3220 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3221 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3222 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3223 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3224 { 0x39, 4, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3225 { 0x30, 8, 64, 32*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3226 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3227 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3228 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3229 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3230 { 0x22, 4, 64, 512*1024, sl3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3231 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3232 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3233 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3234 { 0x0b, 4, 0, 4, itlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3235 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3236 { 0x08, 4, 32, 16*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3237 { 0x06, 4, 32, 8*1024, l1_icache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3238 { 0x05, 4, 0, 32, dtlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3239 { 0x04, 4, 0, 8, dtlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3240 { 0x03, 4, 0, 64, dtlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3241 { 0x02, 4, 0, 2, itlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3242 { 0x01, 4, 0, 32, itlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3243 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3244 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3245
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3246 static const struct cachetab cyrix_ctab[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3247 { 0x70, 4, 0, 32, "tlb-4K" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3248 { 0x80, 4, 16, 16*1024, "l1-cache" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3249 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3250 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3251
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3252 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3253 * Search a cache table for a matching entry
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3254 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3255 static const struct cachetab *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3256 find_cacheent(const struct cachetab *ct, uint_t code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3257 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3258 if (code != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3259 for (; ct->ct_code != 0; ct++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3260 if (ct->ct_code <= code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3261 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3262 if (ct->ct_code == code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3263 return (ct);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3264 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3265 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3266 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3267
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3268 /*
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3269 * Populate cachetab entry with L2 or L3 cache-information using
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3270 * cpuid function 4. This function is called from intel_walk_cacheinfo()
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3271 * when descriptor 0x49 is encountered. It returns 0 if no such cache
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3272 * information is found.
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3273 */
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3274 static int
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3275 intel_cpuid_4_cache_info(struct cachetab ct, struct cpuid_info cpi)
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3276 {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3277 uint32_t level, i;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3278 int ret = 0;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3279
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3280 for (i = 0; i < cpi->cpi_std_4_size; i++) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3281 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3282
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3283 if (level == 2 \|\| level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3284 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3285 ct->ct_line_size =
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3286 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3287 ct->ct_size = ct->ct_assoc *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3288 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3289 ct->ct_line_size *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3290 (cpi->cpi_std_4[i]->cp_ecx + 1);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3291
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3292 if (level == 2) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3293 ct->ct_label = l2_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3294 } else if (level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3295 ct->ct_label = l3_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3296 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3297 ret = 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3298 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3299 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3300
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3301 return (ret);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3302 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3303
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3304 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3305 * Walk the cacheinfo descriptor, applying 'func' to every valid element
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3306 * The walk is terminated if the walker returns non-zero.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3307 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3308 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3309 intel_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3310 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3311 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3312 const struct cachetab *ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3313 struct cachetab des_49_ct, des_b1_ct;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3314 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3315 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3316
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3317 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3318 return;
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3319 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3320 /*
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3321 * For overloaded descriptor 0x49 we use cpuid function 4
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3322 * if supported by the current processor, to create
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3323 * cache information.
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3324 * For overloaded descriptor 0xb1 we use X86_PAE flag
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3325 * to disambiguate the cache information.
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3326 */
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3327 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3328 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3329 ct = &des_49_ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3330 } else if (*dp == 0xb1) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3331 des_b1_ct.ct_code = 0xb1;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3332 des_b1_ct.ct_assoc = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3333 des_b1_ct.ct_line_size = 0;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3334 if (x86_feature & X86_PAE) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3335 des_b1_ct.ct_size = 8;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3336 des_b1_ct.ct_label = itlb2M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3337 } else {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3338 des_b1_ct.ct_size = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3339 des_b1_ct.ct_label = itlb4M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3340 }
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3341 ct = &des_b1_ct;
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3342 } else {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3343 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3344 continue;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3345 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3346 }
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3347
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3348 if (func(arg, ct) != 0) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3349 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3350 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3351 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3352 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3353
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3354 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3355 * (Like the Intel one, except for Cyrix CPUs)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3356 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3357 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3358 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3359 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3360 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3361 const struct cachetab *ct;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3362 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3363 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3364
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3365 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3366 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3367 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3368 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3369 * Search Cyrix-specific descriptor table first ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3370 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3371 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3372 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3373 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3374 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3375 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3376 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3377 * .. else fall back to the Intel one
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3378 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3379 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3380 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3381 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3382 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3383 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3384 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3385 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3386
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3387 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3388 * A cacheinfo walker that adds associativity, line-size, and size properties
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3389 * to the devinfo node it is passed as an argument.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3390 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3391 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3392 add_cacheent_props(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3393 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3394 dev_info_t *devi = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3395
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3396 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3397 if (ct->ct_line_size != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3398 add_cache_prop(devi, ct->ct_label, line_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3399 ct->ct_line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3400 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3401 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3402 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3403
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3404
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3405 static const char fully_assoc[] = "fully-associative?";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3406
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3407 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3408 * AMD style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3409 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3410 * Extended functions 5 and 6 directly describe properties of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3411 * tlbs and various cache levels.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3412 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3413 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3414 add_amd_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3415 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3416 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3417 case 0: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3418 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3419 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3420 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3421 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3422 case 0xff:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3423 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3424 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3425 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3426 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3427
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3428 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3429 add_amd_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3430 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3431 if (size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3432 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3433 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3434 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3435 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3436
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3437 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3438 add_amd_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3439 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3440 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3441 if (size == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3442 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3443 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3444 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3445 * Most AMD parts have a sectored cache. Multiple cache lines are
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3446 * associated with each tag. A sector consists of all cache lines
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3447 * associated with a tag. For example, the AMD K6-III has a sector
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3448 * size of 2 cache lines per tag.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3449 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3450 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3451 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3452 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3453 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3454 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3455
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3456 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3457 add_amd_l2_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3458 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3459 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3460 case 0: /* off */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3461 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3462 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3463 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3464 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3465 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3466 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3467 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3468 add_cache_prop(devi, label, assoc_str, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3469 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3470 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3471 add_cache_prop(devi, label, assoc_str, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3472 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3473 case 0xf:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3474 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3475 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3476 default: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3477 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3478 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3479 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3480
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3481 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3482 add_amd_l2_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3483 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3484 if (size == 0 \|\| assoc == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3485 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3486 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3487 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3488 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3489
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3490 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3491 add_amd_l2_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3492 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3493 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3494 if (size == 0 \|\| assoc == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3495 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3496 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3497 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3498 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3499 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3500 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3501 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3502
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3503 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3504 amd_cache_info(struct cpuid_info cpi, dev_info_t devi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3505 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3506 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3507
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3508 if (cpi->cpi_xmaxeax < 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3509 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3510 cp = &cpi->cpi_extd[5];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3511
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3512 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3513 * 4M/2M L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3514 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3515 * We report the size for 2M pages because AMD uses two
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3516 * TLB entries for one 4M page.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3517 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3518 add_amd_tlb(devi, "dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3519 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3520 add_amd_tlb(devi, "itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3521 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3522
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3523 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3524 * 4K L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3525 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3526
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3527 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3528 uint_t nentries;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3529 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3530 if (cpi->cpi_family >= 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3531 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3532 * Crusoe processors have 256 TLB entries, but
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3533 * cpuid data format constrains them to only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3534 * reporting 255 of them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3535 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3536 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3537 nentries = 256;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3538 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3539 * Crusoe processors also have a unified TLB
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3540 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3541 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3542 nentries);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3543 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3544 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3545 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3546 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3547 add_amd_tlb(devi, itlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3548 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3549 add_amd_tlb(devi, dtlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3550 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3551 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3552 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3553
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3554 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3555 * data L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3556 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3557
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3558 add_amd_cache(devi, l1_dcache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3559 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3560 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3561
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3562 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3563 * code L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3564 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3565
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3566 add_amd_cache(devi, l1_icache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3567 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3568 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3569
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3570 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3571 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3572 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3573
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3574 /* Check for a unified L2 TLB for large pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3575
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3576 if (BITX(cp->cp_eax, 31, 16) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3577 add_amd_l2_tlb(devi, "l2-tlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3578 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3579 else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3580 add_amd_l2_tlb(devi, "l2-dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3581 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3582 add_amd_l2_tlb(devi, "l2-itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3583 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3584 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3585
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3586 /* Check for a unified L2 TLB for 4K pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3587
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3588 if (BITX(cp->cp_ebx, 31, 16) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3589 add_amd_l2_tlb(devi, "l2-tlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3590 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3591 } else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3592 add_amd_l2_tlb(devi, "l2-dtlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3593 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3594 add_amd_l2_tlb(devi, "l2-itlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3595 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3596 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3597
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3598 add_amd_l2_cache(devi, l2_cache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3599 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3600 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3601 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3602
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3603 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3604 * There are two basic ways that the x86 world describes it cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3605 * and tlb architecture - Intel's way and AMD's way.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3606 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3607 * Return which flavor of cache architecture we should use
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3608 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3609 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3610 x86_which_cacheinfo(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3611 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3612 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3613 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3614 if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3615 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3616 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3617 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3618 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3619 * The K5 model 1 was the first part from AMD that reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3620 * cache sizes via extended cpuid functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3621 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3622 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3623 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3624 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3625 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3626 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3627 if (cpi->cpi_family >= 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3628 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3629 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3630 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3631 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3632 * If they have extended CPU data for 0x80000005
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3633 * then we assume they have AMD-format cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3634 * information.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3635 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3636 * If not, and the vendor happens to be Cyrix,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3637 * then try our-Cyrix specific handler.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3638 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3639 * If we're not Cyrix, then assume we're using Intel's
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3640 * table-driven format instead.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3641 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3642 if (cpi->cpi_xmaxeax >= 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3643 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3644 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3645 return (X86_VENDOR_Cyrix);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3646 else if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3647 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3648 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3649 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3650 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3651 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3652
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3653 void
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3654 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3655 struct cpuid_info *cpi)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3656 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3657 dev_info_t *cpu_devi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3658 int create;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3659
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3660 cpu_devi = (dev_info_t *)dip;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3661
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3662 /* device_type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3663 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3664 "device_type", "cpu");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3665
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3666 /* reg */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3667 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3668 "reg", cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3669
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3670 /* cpu-mhz, and clock-frequency */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3671 if (cpu_freq > 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3672 long long mul;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3673
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3674 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3675 "cpu-mhz", cpu_freq);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3676 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3677 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3678 "clock-frequency", (int)mul);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3679 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3680
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3681 if ((x86_feature & X86_CPUID) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3682 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3683 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3684
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3685 /* vendor-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3686 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3687 "vendor-id", cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3688
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3689 if (cpi->cpi_maxeax == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3690 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3691 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3692
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3693 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3694 * family, model, and step
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3695 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3696 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3697 "family", CPI_FAMILY(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3698 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3699 "cpu-model", CPI_MODEL(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3700 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3701 "stepping-id", CPI_STEP(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3702
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3703 /* type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3704 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3705 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3706 create = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3707 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3708 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3709 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3710 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3711 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3712 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3713 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3714 "type", CPI_TYPE(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3715
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3716 /* ext-family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3717 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3718 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3719 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3720 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3721 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3722 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3723 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3724 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3725 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3726 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3727 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3728 "ext-family", CPI_FAMILY_XTD(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3729
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3730 /* ext-model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3731 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3732 case X86_VENDOR_Intel:
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	3733 create = IS_EXTENDED_MODEL_INTEL(cpi);
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	3734 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3735 case X86_VENDOR_AMD:
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3736 create = CPI_FAMILY(cpi) == 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3737 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3738 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3739 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3740 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3741 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3742 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3743 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3744 "ext-model", CPI_MODEL_XTD(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3745
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3746 /* generation */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3747 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3748 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3749 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3750 * AMD K5 model 1 was the first part to support this
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3751 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3752 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3753 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3754 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3755 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3756 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3757 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3758 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3759 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3760 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3761
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3762 /* brand-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3763 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3764 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3765 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3766 * brand id first appeared on Pentium III Xeon model 8,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3767 * and Celeron model 8 processors and Opteron
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3768 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3769 create = cpi->cpi_family > 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3770 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3771 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3772 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3773 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3774 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3775 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3776 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3777 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3778 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3779 if (create && cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3780 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3781 "brand-id", cpi->cpi_brandid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3782 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3783
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3784 /* chunks, and apic-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3785 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3786 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3787 * first available on Pentium IV and Opteron (K8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3788 */
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3789 case X86_VENDOR_Intel:
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3790 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3791 break;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3792 case X86_VENDOR_AMD:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3793 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3794 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3795 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3796 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3797 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3798 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3799 if (create) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3800 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3801 "chunks", CPI_CHUNKS(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3802 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	3803 "apic-id", cpi->cpi_apicid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3804 if (cpi->cpi_chipid >= 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3805 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3806 "chip#", cpi->cpi_chipid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3807 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3808 "clog#", cpi->cpi_clogid);
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3809 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3810 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3811
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3812 /* cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3813 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3814 "cpuid-features", CPI_FEATURES_EDX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3815
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3816
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3817 /* cpuid-features-ecx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3818 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3819 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3820 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3821 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3822 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3823 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3824 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3825 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3826 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3827 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3828 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3829
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3830 /* ext-cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3831 switch (cpi->cpi_vendor) {
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3832 case X86_VENDOR_Intel:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3833 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3834 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3835 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3836 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3837 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3838 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3839 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3840 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3841 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3842 }
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3843 if (create) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3844 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3845 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3846 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3847 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3848 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3849
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3850 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3851 * Brand String first appeared in Intel Pentium IV, AMD K5
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3852 * model 1, and Cyrix GXm. On earlier models we try and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3853 * simulate something similar .. so this string should always
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3854 * same -something- about the processor, however lame.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3855 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3856 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3857 "brand-string", cpi->cpi_brandstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3858
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3859 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3860 * Finally, cache and tlb information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3861 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3862 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3863 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3864 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3865 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3866 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3867 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3868 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3869 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3870 amd_cache_info(cpi, cpu_devi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3871 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3872 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3873 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3874 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3875 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3876
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3877 struct l2info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3878 int *l2i_csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3879 int *l2i_lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3880 int *l2i_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3881 int l2i_ret;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3882 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3883
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3884 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3885 * A cacheinfo walker that fetches the size, line-size and associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3886 * of the L2 cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3887 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3888 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3889 intel_l2cinfo(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3890 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3891 struct l2info *l2i = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3892 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3893
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3894 if (ct->ct_label != l2_cache_str &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3895 ct->ct_label != sl2_cache_str)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3896 return (0); /* not an L2 -- keep walking */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3897
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3898 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3899 *ip = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3900 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3901 *ip = ct->ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3902 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3903 *ip = ct->ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3904 l2i->l2i_ret = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3905 return (1); /* was an L2 -- terminate walk */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3906 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3907
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3908 /*
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3909 * AMD L2/L3 Cache and TLB Associativity Field Definition:
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3910 *
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3911 * Unlike the associativity for the L1 cache and tlb where the 8 bit
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3912 * value is the associativity, the associativity for the L2 cache and
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3913 * tlb is encoded in the following table. The 4 bit L2 value serves as
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3914 * an index into the amd_afd[] array to determine the associativity.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3915 * -1 is undefined. 0 is fully associative.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3916 */
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3917
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3918 static int amd_afd[] =
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3919 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3920
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3921 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3922 amd_l2cacheinfo(struct cpuid_info cpi, struct l2info l2i)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3923 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3924 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3925 uint_t size, assoc;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3926 int i;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3927 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3928
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3929 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3930 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3931 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3932
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3933 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3934 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3935 uint_t cachesz = size * 1024;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3936 assoc = amd_afd[i];
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3937
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3938 ASSERT(assoc != -1);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3939
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3940 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3941 *ip = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3942 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3943 *ip = BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3944 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3945 *ip = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3946 l2i->l2i_ret = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3947 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3948 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3949
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3950 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3951 getl2cacheinfo(cpu_t cpu, int csz, int lsz, int assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3952 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3953 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3954 struct l2info __l2info, *l2i = &__l2info;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3955
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3956 l2i->l2i_csz = csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3957 l2i->l2i_lsz = lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3958 l2i->l2i_assoc = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3959 l2i->l2i_ret = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3960
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3961 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3962 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3963 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3964 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3965 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3966 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3967 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3968 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3969 amd_l2cacheinfo(cpi, l2i);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3970 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3971 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3972 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3973 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3974 return (l2i->l2i_ret);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3975 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3976
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	3977 #if !defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	3978
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3979 uint32_t *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3980 cpuid_mwait_alloc(cpu_t *cpu)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3981 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3982 uint32_t *ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3983 size_t mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3984
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3985 ASSERT(cpuid_checkpass(cpu, 2));
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3986
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3987 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3988 if (mwait_size == 0)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3989 return (NULL);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3990
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3991 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3992 * kmem_alloc() returns cache line size aligned data for mwait_size
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3993 * allocations. mwait_size is currently cache line sized. Neither
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3994 * of these implementation details are guarantied to be true in the
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3995 * future.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3996 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3997 * First try allocating mwait_size as kmem_alloc() currently returns
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3998 * correctly aligned memory. If kmem_alloc() does not return
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3999 * mwait_size aligned memory, then use mwait_size ROUNDUP.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4000 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4001 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4002 * decide to free this memory.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4003 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4004 ret = kmem_zalloc(mwait_size, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4005 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4006 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4007 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4008 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4009 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4010 } else {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4011 kmem_free(ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4012 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4013 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4014 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4015 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4016 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4017 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4018 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4019 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4020
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4021 void
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4022 cpuid_mwait_free(cpu_t *cpu)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4023 {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4024 ASSERT(cpuid_checkpass(cpu, 2));
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4025
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4026 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4027 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4028 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4029 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4030 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4031
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4032 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4033 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4034 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4035
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4036 void
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4037 patch_tsc_read(int flag)
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4038 {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4039 size_t cnt;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	4040
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4041 switch (flag) {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4042 case X86_NO_TSC:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4043 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4044 (void) memcpy((void )tsc_read, (void )&_no_rdtsc_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4045 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4046 case X86_HAVE_TSCP:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4047 cnt = &_tscp_end - &_tscp_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4048 (void) memcpy((void )tsc_read, (void )&_tscp_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4049 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4050 case X86_TSC_MFENCE:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4051 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4052 (void) memcpy((void *)tsc_read,
fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4053 (void *)&_tsc_mfence_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4054 break;
6642 c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4055 case X86_TSC_LFENCE:
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4056 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4057 (void) memcpy((void *)tsc_read,
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4058 (void *)&_tsc_lfence_start, cnt);
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4059 break;
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4060 default:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4061 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4062 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4063 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4064
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4065 int
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4066 cpuid_deep_cstates_supported(void)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4067 {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4068 struct cpuid_info *cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4069 struct cpuid_regs regs;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4070
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4071 ASSERT(cpuid_checkpass(CPU, 1));
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4072
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4073 cpi = CPU->cpu_m.mcpu_cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4074
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4075 if (!(x86_feature & X86_CPUID))
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4076 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4077
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4078 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4079 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4080 if (cpi->cpi_xmaxeax < 0x80000007)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4081 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4082
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4083 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4084 * TSC run at a constant rate in all ACPI C-states?
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4085 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4086 regs.cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4087 (void) __cpuid_insn(&regs);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4088 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4089
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4090 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4091 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4092 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4093 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4094
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4095 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4096
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4097 void
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4098 post_startup_cpu_fixups(void)
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4099 {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4100 #ifndef __xpv
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4101 /*
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4102 * Some AMD processors support C1E state. Entering this state will
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4103 * cause the local APIC timer to stop, which we can't deal with at
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4104 * this time.
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4105 */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4106 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4107 on_trap_data_t otd;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4108 uint64_t reg;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4109
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4110 if (!on_trap(&otd, OT_DATA_ACCESS)) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4111 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4112 /* Disable C1E state if it is enabled by BIOS */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4113 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4114 AMD_ACTONCMPHALT_MASK) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4115 reg &= ~(AMD_ACTONCMPHALT_MASK <<
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4116 AMD_ACTONCMPHALT_SHIFT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4117 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4118 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4119 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4120 no_trap();
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4121 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4122 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4123 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4124
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4125 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4126 * Starting with the Westmere processor the local
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4127 * APIC timer will continue running in all C-states,
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4128 * including the deepest C-states.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4129 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4130 int
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4131 cpuid_arat_supported(void)
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4132 {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4133 struct cpuid_info *cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4134 struct cpuid_regs regs;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4135
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4136 ASSERT(cpuid_checkpass(CPU, 1));
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4137 ASSERT(x86_feature & X86_CPUID);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4138
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4139 cpi = CPU->cpu_m.mcpu_cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4140
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4141 switch (cpi->cpi_vendor) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4142 case X86_VENDOR_Intel:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4143 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4144 * Always-running Local APIC Timer is
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4145 * indicated by CPUID.6.EAX[2].
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4146 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4147 if (cpi->cpi_maxeax >= 6) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4148 regs.cp_eax = 6;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4149 (void) cpuid_insn(NULL, &regs);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4150 return (regs.cp_eax & CPUID_CSTATE_ARAT);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4151 } else {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4152 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4153 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4154 default:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4155 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4156 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4157 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4158
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4159 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4160 * Check support for Intel ENERGY_PERF_BIAS feature
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4161 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4162 int
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4163 cpuid_iepb_supported(struct cpu *cp)
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4164 {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4165 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4166 struct cpuid_regs regs;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4167
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4168 ASSERT(cpuid_checkpass(cp, 1));
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4169
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4170 if (!(x86_feature & X86_CPUID) \|\| !(x86_feature & X86_MSR)) {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4171 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4172 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4173
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4174 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4175 * Intel ENERGY_PERF_BIAS MSR is indicated by
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4176 * capability bit CPUID.6.ECX.3
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4177 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4178 if ((cpi->cpi_vendor != X86_VENDOR_Intel) \|\| (cpi->cpi_maxeax < 6))
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4179 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4180
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4181 regs.cp_eax = 0x6;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4182 (void) cpuid_insn(NULL, &regs);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4183 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4184 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4185
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4186 #if defined(__amd64) && !defined(__xpv)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4187 /*
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4188 * Patch in versions of bcopy for high performance Intel Nhm processors
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4189 * and later...
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4190 */
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4191 void
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4192 patch_memops(uint_t vendor)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4193 {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4194 size_t cnt, i;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4195 caddr_t to, from;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4196
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4197 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4198 cnt = &bcopy_patch_end - &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4199 to = &bcopy_ck_size;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4200 from = &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4201 for (i = 0; i < cnt; i++) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4202 to++ = from++;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4203 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4204 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4205 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4206 #endif /* __amd64 && !__xpv */

Mercurial > illumos > illumos-gate

annotate usr/src/uts/i86pc/os/cpuid.c @ 11389:dd00b884e84f