illumos/illumos-gate: usr/src/uts/i86pc/os/cpuid.c annotate

annotate usr/src/uts/i86pc/os/cpuid.c @ 12726:8f2fba7fcf9c

6957730 cpuid_amd_getids() uses uninitialized variable coreidsz 6957751 nb_fini() leaks memory 6957783 nb_dev_reinit() leaks memory 6957795 Use-after-free in fm_nvlist_create()

author	Jakub Jermar <Jakub.Jermar@Sun.COM>
date	Tue, 29 Jun 2010 16:03:17 +0200
parents	52117d41c06e
children	fca99d9e3f2f

rev	line source
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2 * CDDL HEADER START
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4 * The contents of this file are subject to the terms of the
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	5 * Common Development and Distribution License (the "License").
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	6 * You may not use this file except in compliance with the License.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	7 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	9 * or http://www.opensolaris.org/os/licensing.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	10 * See the License for the specific language governing permissions
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	11 * and limitations under the License.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	12 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	13 * When distributing Covered Code, include this CDDL HEADER in each
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	15 * If applicable, add the following below this CDDL HEADER, with the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	16 * fields enclosed by brackets "[]" replaced with your own identifying
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	17 * information: Portions Copyright [yyyy] [name of copyright owner]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	18 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	19 * CDDL HEADER END
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	20 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	21 /*
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	23 */
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	24 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	25 * Copyright (c) 2009, Intel Corporation.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	26 * All rights reserved.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	27 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	28 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	29 * Portions Copyright 2009 Advanced Micro Devices, Inc.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	30 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	31
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	32 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	33 * Various routines to handle identification
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	34 * and classification of x86 processors.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	35 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	36
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	37 #include <sys/types.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	38 #include <sys/archsystm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	39 #include <sys/x86_archext.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	40 #include <sys/kmem.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	41 #include <sys/systm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	42 #include <sys/cmn_err.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	43 #include <sys/sunddi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	44 #include <sys/sunndi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	45 #include <sys/cpuvar.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	46 #include <sys/processor.h>
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	47 #include <sys/sysmacros.h>
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	48 #include <sys/pg.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	49 #include <sys/fp.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	50 #include <sys/controlregs.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	51 #include <sys/auxv_386.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	52 #include <sys/bitmap.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	53 #include <sys/memnode.h>
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	54 #include <sys/pci_cfgspace.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	55
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	56 #ifdef __xpv
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	57 #include <sys/hypervisor.h>
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	58 #else
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	59 #include <sys/ontrap.h>
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	60 #endif
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	61
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	62 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	63 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	64 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	65 * them accordingly. For most modern processors, feature detection occurs here
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	66 * in pass 1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	67 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	68 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	69 * for the boot CPU and does the basic analysis that the early kernel needs.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	70 * x86_feature is set based on the return value of cpuid_pass1() of the boot
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	71 * CPU.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	72 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	73 * Pass 1 includes:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	74 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	75 * o Determining vendor/model/family/stepping and setting x86_type and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	76 * x86_vendor accordingly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	77 * o Processing the feature flags returned by the cpuid instruction while
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	78 * applying any workarounds or tricks for the specific processor.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	79 * o Mapping the feature flags into Solaris feature bits (X86_*).
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	80 * o Processing extended feature flags if supported by the processor,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	81 * again while applying specific processor knowledge.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	82 * o Determining the CMT characteristics of the system.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	83 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	84 * Pass 1 is done on non-boot CPUs during their initialization and the results
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	85 * are used only as a meager attempt at ensuring that all processors within the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	86 * system support the same features.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	87 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	88 * Pass 2 of cpuid feature analysis happens just at the beginning
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	89 * of startup(). It just copies in and corrects the remainder
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	90 * of the cpuid data we depend on: standard cpuid functions that we didn't
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	91 * need for pass1 feature analysis, and extended cpuid functions beyond the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	92 * simple feature processing done in pass1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	93 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	94 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	95 * particular kernel memory allocation has been made available. It creates a
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	96 * readable brand string based on the data collected in the first two passes.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	97 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	98 * Pass 4 of cpuid analysis is invoked after post_startup() when all
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	99 * the support infrastructure for various hardware features has been
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	100 * initialized. It determines which processor features will be reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	101 * to userland via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	102 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	103 * All passes are executed on all CPUs, but only the boot CPU determines what
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	104 * features the kernel will use.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	105 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	106 * Much of the worst junk in this file is for the support of processors
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	107 * that didn't really implement the cpuid instruction properly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	108 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	109 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	110 * the pass numbers. Accordingly, changes to the pass code may require changes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	111 * to the accessor code.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	112 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	113
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	114 uint_t x86_feature = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	115 uint_t x86_vendor = X86_VENDOR_IntelClone;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	116 uint_t x86_type = X86_TYPE_OTHER;
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	117 uint_t x86_clflush_size = 0;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	118
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	119 uint_t pentiumpro_bug4046376;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	120 uint_t pentiumpro_bug4064495;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	121
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	122 uint_t enable486;
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	123 /*
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	124 * This is set to platform type Solaris is running on.
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	125 */
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	126 static int platform_type = -1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	127
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	128 #if !defined(__xpv)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	129 /*
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	130 * Variable to patch if hypervisor platform detection needs to be
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	131 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	132 */
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	133 int enable_platform_detection = 1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	134 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	135
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	136 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	137 * monitor/mwait info.
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	138 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	139 * size_actual and buf_actual are the real address and size allocated to get
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	140 * proper mwait_buf alignement. buf_actual and size_actual should be passed
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	141 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	142 * processor cache-line alignment, but this is not guarantied in the furture.
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	143 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	144 struct mwait_info {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	145 size_t mon_min; /* min size to avoid missed wakeups */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	146 size_t mon_max; /* size to avoid false wakeups */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	147 size_t size_actual; /* size actually allocated */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	148 void buf_actual; / memory actually allocated */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	149 uint32_t support; /* processor support of monitor/mwait */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	150 };
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	151
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	152 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	153 * These constants determine how many of the elements of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	154 * cpuid we cache in the cpuid_info data structure; the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	155 * remaining elements are accessible via the cpuid instruction.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	156 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	157
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	158 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	159 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	160
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	161 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	162 * Some terminology needs to be explained:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	163 * - Socket: Something that can be plugged into a motherboard.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	164 * - Package: Same as socket
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	165 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	166 * differently: there, chip is the same as processor node (below)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	167 * - Processor node: Some AMD processors have more than one
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	168 * "subprocessor" embedded in a package. These subprocessors (nodes)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	169 * are fully-functional processors themselves with cores, caches,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	170 * memory controllers, PCI configuration spaces. They are connected
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	171 * inside the package with Hypertransport links. On single-node
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	172 * processors, processor node is equivalent to chip/socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	173 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	174
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	175 struct cpuid_info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	176 uint_t cpi_pass; /* last pass completed */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	177 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	178 * standard function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	179 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	180 uint_t cpi_maxeax; /* fn 0: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	181 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	182 uint_t cpi_vendor; /* enum of cpi_vendorstr */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	183
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	184 uint_t cpi_family; /* fn 1: extended family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	185 uint_t cpi_model; /* fn 1: extended model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	186 uint_t cpi_step; /* fn 1: stepping */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	187 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	188 /* AMD: package/socket # */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	189 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	190 int cpi_clogid; /* fn 1: %ebx: thread # */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	191 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	192 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	193 uint_t cpi_ncache; /* fn 2: number of elements */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	194 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	195 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	196 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	197 struct cpuid_regs *cpi_std_4; / fn 4: %ecx == 0 .. fn4_size */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	198 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	199 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	200 * extended function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	201 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	202 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	203 char cpi_brandstr[49]; /* fn 0x8000000[234] */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	204 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	205 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	206 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	207
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	208 id_t cpi_coreid; /* same coreid => strands share core */
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	209 int cpi_pkgcoreid; /* core number within single package */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	210 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	211 /* Intel: fn 4: %eax[31-26] */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	212 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	213 * supported feature information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	214 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	215 uint32_t cpi_support[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	216 #define STD_EDX_FEATURES 0
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	217 #define AMD_EDX_FEATURES 1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	218 #define TM_EDX_FEATURES 2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	219 #define STD_ECX_FEATURES 3
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	220 #define AMD_ECX_FEATURES 4
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	221 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	222 * Synthesized information, where known.
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	223 */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	224 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	225 const char cpi_chiprevstr; / May be NULL if chiprev unknown */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	226 uint32_t cpi_socket; /* Chip package/socket type */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	227
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	228 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	229 uint32_t cpi_apicid;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	230 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	231 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	232 /* Intel: 1 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	233 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	234
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	235
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	236 static struct cpuid_info cpuid_info0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	237
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	238 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	239 * These bit fields are defined by the Intel Application Note AP-485
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	240 * "Intel Processor Identification and the CPUID Instruction"
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	241 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	242 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	243 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	244 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	245 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	246 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	247 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	248
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	249 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	250 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	251 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	252 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	253
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	254 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	255 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	256 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	257 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	258
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	259 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	260 #define CPI_XMAXEAX_MAX 0x80000100
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	261 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	262 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	263
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	264 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	265 * Function 4 (Deterministic Cache Parameters) macros
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	266 * Defined by Intel Application Note AP-485
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	267 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	268 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	269 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	270 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	271 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	272 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	273 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	274 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	275
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	276 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	277 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	278 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	279
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	280 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	281
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	282 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	283
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	284
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	285 /*
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	286 * A couple of shorthand macros to identify "later" P6-family chips
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	287 * like the Pentium M and Core. First, the "older" P6-based stuff
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	288 * (loosely defined as "pre-Pentium-4"):
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	289 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	290 */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	291
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	292 #define IS_LEGACY_P6(cpi) ( \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	293 cpi->cpi_family == 6 && \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	294 (cpi->cpi_model == 1 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	295 cpi->cpi_model == 3 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	296 cpi->cpi_model == 5 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	297 cpi->cpi_model == 6 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	298 cpi->cpi_model == 7 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	299 cpi->cpi_model == 8 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	300 cpi->cpi_model == 0xA \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	301 cpi->cpi_model == 0xB) \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	302 )
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	303
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	304 /* A "new F6" is everything with family 6 that's not the above */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	305 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	306
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	307 /* Extended family/model support */
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	308 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 \|\| \
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	309 cpi->cpi_family >= 0xf)
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	310
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	311 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	312 * Info for monitor/mwait idle loop.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	313 *
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	314 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	315 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	316 * 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	317 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	318 * Documentation Updates" #33633, Rev 2.05, December 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	319 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	320 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	321 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	322 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	323 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	324 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	325 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	326 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	327 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	328 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	329 * Number of sub-cstates for a given c-state.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	330 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	331 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	332 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	333
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	334 /*
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	335 * Functions we consune from cpuid_subr.c; don't publish these in a header
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	336 * file to try and keep people using the expected cpuid_* interfaces.
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	337 */
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	338 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	339 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	340 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	341 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	342 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	343
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	344 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	345 * Apply up various platform-dependent restrictions where the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	346 * underlying platform restrictions mean the CPU can be marked
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	347 * as less capable than its cpuid instruction would imply.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	348 */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	349 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	350 static void
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	351 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	352 {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	353 switch (eax) {
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	354 case 1: {
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	355 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	356 0 : CPUID_INTC_EDX_MCA;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	357 cp->cp_edx &=
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	358 ~(mcamask \|
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	359 CPUID_INTC_EDX_PSE \|
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	360 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	361 CPUID_INTC_EDX_SEP \| CPUID_INTC_EDX_MTRR \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	362 CPUID_INTC_EDX_PGE \| CPUID_INTC_EDX_PAT \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	363 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	364 CPUID_INTC_EDX_PSE36 \| CPUID_INTC_EDX_HTT);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	365 break;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	366 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	367
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	368 case 0x80000001:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	369 cp->cp_edx &=
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	370 ~(CPUID_AMD_EDX_PSE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	371 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	372 CPUID_AMD_EDX_MTRR \| CPUID_AMD_EDX_PGE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	373 CPUID_AMD_EDX_PAT \| CPUID_AMD_EDX_PSE36 \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	374 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	375 CPUID_AMD_EDX_TSCP);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	376 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	377 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	378 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	379 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	380 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	381
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	382 switch (vendor) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	383 case X86_VENDOR_Intel:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	384 switch (eax) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	385 case 4:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	386 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	387 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	388 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	389 cp->cp_eax &= 0x03fffffff;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	390 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	391 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	392 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	393 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	394 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	395 case X86_VENDOR_AMD:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	396 switch (eax) {
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	397
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	398 case 0x80000001:
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	399 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	400 break;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	401
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	402 case 0x80000008:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	403 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	404 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	405 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	406 cp->cp_ecx &= 0xffffff00;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	407 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	408 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	409 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	410 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	411 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	412 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	413 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	414 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	415 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	416 #else
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	417 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	418 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	419
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	420 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	421 * Some undocumented ways of patching the results of the cpuid
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	422 * instruction to permit running Solaris 10 on future cpus that
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	423 * we don't currently support. Could be set to non-zero values
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	424 * via settings in eeprom.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	425 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	426
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	427 uint32_t cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	428 uint32_t cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	429 uint32_t cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	430 uint32_t cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	431
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	432 /*
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	433 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	434 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	435 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	436 cpuid_alloc_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	437 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	438 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	439 * By convention, cpu0 is the boot cpu, which is set up
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	440 * before memory allocation is available. All other cpus get
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	441 * their cpuid_info struct allocated here.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	442 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	443 ASSERT(cpu->cpu_id != 0);
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	444 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	445 cpu->cpu_m.mcpu_cpi =
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	446 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	447 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	448
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	449 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	450 cpuid_free_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	451 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	452 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	453 int i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	454
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	455 ASSERT(cpi != NULL);
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	456 ASSERT(cpi != &cpuid_info0);
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	457
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	458 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	459 * Free up any function 4 related dynamic storage
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	460 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	461 for (i = 1; i < cpi->cpi_std_4_size; i++)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	462 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	463 if (cpi->cpi_std_4_size > 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	464 kmem_free(cpi->cpi_std_4,
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	465 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	466
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	467 kmem_free(cpi, sizeof (*cpi));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	468 cpu->cpu_m.mcpu_cpi = NULL;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	469 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	470
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	471 #if !defined(__xpv)
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	472
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	473 static void
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	474 determine_platform()
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	475 {
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	476 struct cpuid_regs cp;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	477 char *xen_str;
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	478 uint32_t xen_signature[4], base;
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	479
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	480 platform_type = HW_NATIVE;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	481
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	482 if (!enable_platform_detection)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	483 return;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	484
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	485 /*
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	486 * In a fully virtualized domain, Xen's pseudo-cpuid function
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	487 * returns a string representing the Xen signature in %ebx, %ecx,
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	488 * and %edx. %eax contains the maximum supported cpuid function.
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	489 * We need at least a (base + 2) leaf value to do what we want
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	490 * to do. Try different base values, since the hypervisor might
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	491 * use a different one depending on whether hyper-v emulation
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	492 * is switched on by default or not.
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	493 */
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	494 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	495 cp.cp_eax = base;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	496 (void) __cpuid_insn(&cp);
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	497 xen_signature[0] = cp.cp_ebx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	498 xen_signature[1] = cp.cp_ecx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	499 xen_signature[2] = cp.cp_edx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	500 xen_signature[3] = 0;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	501 xen_str = (char *)xen_signature;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	502 if (strcmp("XenVMMXenVMM", xen_str) == 0 &&
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	503 cp.cp_eax >= (base + 2)) {
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	504 platform_type = HW_XEN_HVM;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	505 return;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	506 }
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	507 }
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	508
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	509 if (vmware_platform()) /* running under vmware hypervisor? */
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	510 platform_type = HW_VMWARE;
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	511 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	512
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	513 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	514 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	515 {
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	516 if (platform_type == -1)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	517 determine_platform();
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	518
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	519 return (platform_type);
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	520 }
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	521
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	522 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	523 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	524 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	525 return (0);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	526 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	527
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	528 #else
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	529
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	530 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	531 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	532 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	533 return (HW_XEN_PV);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	534 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	535
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	536 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	537 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	538 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	539 return (DOMAIN_IS_INITDOMAIN(xen_info));
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	540 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	541
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	542 #endif /* __xpv */
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	543
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	544 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	545 cpuid_intel_getids(cpu_t *cpu, uint_t feature)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	546 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	547 uint_t i;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	548 uint_t chipid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	549 uint_t coreid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	550 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	551
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	552 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	553 chipid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	554
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	555 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	556 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	557
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	558 if (feature & X86_CMP) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	559 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	560 * Multi-core (and possibly multi-threaded)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	561 * processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	562 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	563 uint_t ncpu_per_core;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	564 if (cpi->cpi_ncore_per_chip == 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	565 ncpu_per_core = cpi->cpi_ncpu_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	566 else if (cpi->cpi_ncore_per_chip > 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	567 ncpu_per_core = cpi->cpi_ncpu_per_chip /
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	568 cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	569 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	570 * 8bit APIC IDs on dual core Pentiums
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	571 * look like this:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	572 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	573 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	574 * \| Physical Package ID \| MC \| HT \|
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	575 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	576 * <------- chipid -------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	577 * <------- coreid --------------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	578 * <--- clogid -->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	579 * <------>
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	580 * pkgcoreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	581 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	582 * Where the number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	583 * represent MC and HT fields together equals
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	584 * to the minimum number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	585 * store the value of cpi->cpi_ncpu_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	586 * Of those bits, the MC part uses the number
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	587 * of bits necessary to store the value of
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	588 * cpi->cpi_ncore_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	589 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	590 for (i = 1; i < ncpu_per_core; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	591 coreid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	592 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	593 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	594 } else if (feature & X86_HTT) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	595 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	596 * Single-core multi-threaded processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	597 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	598 cpi->cpi_coreid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	599 cpi->cpi_pkgcoreid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	600 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	601 cpi->cpi_procnodeid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	602 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	603
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	604 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	605 cpuid_amd_getids(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	606 {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	607 int i, first_half, coreidsz;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	608 uint32_t nb_caps_reg;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	609 uint_t node2_1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	610 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	611
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	612 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	613 * AMD CMP chips currently have a single thread per core.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	614 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	615 * Since no two cpus share a core we must assign a distinct coreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	616 * per cpu, and we do this by using the cpu_id. This scheme does not,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	617 * however, guarantee that sibling cores of a chip will have sequential
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	618 * coreids starting at a multiple of the number of cores per chip -
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	619 * that is usually the case, but if the ACPI MADT table is presented
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	620 * in a different order then we need to perform a few more gymnastics
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	621 * for the pkgcoreid.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	622 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	623 * All processors in the system have the same number of enabled
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	624 * cores. Cores within a processor are always numbered sequentially
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	625 * from 0 regardless of how many or which are disabled, and there
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	626 * is no way for operating system to discover the real core id when some
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	627 * are disabled.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	628 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	629
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	630 cpi->cpi_coreid = cpu->cpu_id;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	631
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	632 if (cpi->cpi_xmaxeax >= 0x80000008) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	633
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	634 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	635
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	636 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	637 * In AMD parlance chip is really a node while Solaris
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	638 * sees chip as equivalent to socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	639 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	640 cpi->cpi_ncore_per_chip =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	641 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	642 if (coreidsz == 0) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	643 /* Use legacy method */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	644 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	645 coreidsz++;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	646 if (coreidsz == 0)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	647 coreidsz = 1;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	648 }
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	649 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	650 /* Assume single-core part */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	651 cpi->cpi_ncore_per_chip = 1;
12726 8f2fba7fcf9c 6957730 cpuid_amd_getids() uses uninitialized variable coreidsz Jakub Jermar <Jakub.Jermar@Sun.COM> parents: 12261 diff changeset	652 coreidsz = 1;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	653 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	654
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	655 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	656 cpi->cpi_apicid & ((1<<coreidsz) - 1);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	657 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	658
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	659 /* Get nodeID */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	660 if (cpi->cpi_family == 0xf) {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	661 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	662 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	663 } else if (cpi->cpi_family == 0x10) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	664 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	665 * See if we are a multi-node processor.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	666 * All processors in the system have the same number of nodes
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	667 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	668 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	669 if ((cpi->cpi_model < 8) \|\| BITX(nb_caps_reg, 29, 29) == 0) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	670 /* Single-node */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	671 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	672 coreidsz);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	673 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	674 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	675
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	676 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	677 * Multi-node revision D (2 nodes per package
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	678 * are supported)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	679 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	680 cpi->cpi_procnodes_per_pkg = 2;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	681
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	682 first_half = (cpi->cpi_pkgcoreid <=
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	683 (cpi->cpi_ncore_per_chip/2 - 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	684
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	685 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	686 /* We are BSP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	687 cpi->cpi_procnodeid = (first_half ? 0 : 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	688 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	689 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	690
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	691 /* We are AP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	692 /* NodeId[2:1] bits to use for reading F3xe8 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	693 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	694
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	695 nb_caps_reg =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	696 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	697
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	698 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	699 * Check IntNodeNum bit (31:30, but bit 31 is
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	700 * always 0 on dual-node processors)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	701 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	702 if (BITX(nb_caps_reg, 30, 30) == 0)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	703 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	704 !first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	705 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	706 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	707 first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	708
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	709 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	710 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	711 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	712 } else if (cpi->cpi_family >= 0x11) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	713 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	714 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	715 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	716 cpi->cpi_procnodeid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	717 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	718 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	719 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	720
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	721 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	722 cpuid_pass1(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	723 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	724 uint32_t mask_ecx, mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	725 uint_t feature = X86_CPUID;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	726 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	727 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	728 int xcpuid;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	729 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	730 extern int idle_cpu_prefer_mwait;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	731 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	732
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	733
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	734 #if !defined(__xpv)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	735 determine_platform();
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	736 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	737 /*
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	738 * Space statically allocated for BSP, ensure pointer is set
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	739 */
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	740 if (cpu->cpu_id == 0 && cpu->cpu_m.mcpu_cpi == NULL)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	741 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	742 cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	743 ASSERT(cpi != NULL);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	744 cp = &cpi->cpi_std[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	745 cp->cp_eax = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	746 cpi->cpi_maxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	747 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	748 uint32_t iptr = (uint32_t )cpi->cpi_vendorstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	749 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	750 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	751 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	752 (char )&cpi->cpi_vendorstr[12] = '\0';
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	753 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	754
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	755 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	756 x86_vendor = cpi->cpi_vendor; /* for compatibility */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	757
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	758 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	759 * Limit the range in case of weird hardware
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	760 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	761 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	762 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	763 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	764 goto pass1_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	765
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	766 cp = &cpi->cpi_std[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	767 cp->cp_eax = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	768 (void) __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	769
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	770 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	771 * Extract identifying constants for easy access.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	772 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	773 cpi->cpi_model = CPI_MODEL(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	774 cpi->cpi_family = CPI_FAMILY(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	775
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	776 if (cpi->cpi_family == 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	777 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	778
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	779 /*
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	780 * Beware: AMD uses "extended model" iff base FAMILY == 0xf.
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	781 * Intel, and presumably everyone else, uses model == 0xf, as
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	782 * one would expect (max value means possible overflow). Sigh.
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	783 */
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	784
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	785 switch (cpi->cpi_vendor) {
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	786 case X86_VENDOR_Intel:
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	787 if (IS_EXTENDED_MODEL_INTEL(cpi))
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	788 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
4858 08409e2eed12 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint) ksadhukh parents: 4855 diff changeset	789 break;
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	790 case X86_VENDOR_AMD:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	791 if (CPI_FAMILY(cpi) == 0xf)
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	792 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	793 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	794 default:
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	795 if (cpi->cpi_model == 0xf)
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	796 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	797 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	798 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	799
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	800 cpi->cpi_step = CPI_STEP(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	801 cpi->cpi_brandid = CPI_BRANDID(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	802
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	803 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	804 * default assumptions:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	805 * - believe %edx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	806 * - ignore %ecx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	807 * - 32-bit virtual and physical addressing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	808 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	809 mask_edx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	810 mask_ecx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	811
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	812 cpi->cpi_pabits = cpi->cpi_vabits = 32;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	813
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	814 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	815 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	816 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	817 x86_type = X86_TYPE_P5;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	818 else if (IS_LEGACY_P6(cpi)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	819 x86_type = X86_TYPE_P6;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	820 pentiumpro_bug4046376 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	821 pentiumpro_bug4064495 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	822 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	823 * Clear the SEP bit when it was set erroneously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	824 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	825 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	826 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	827 } else if (IS_NEW_F6(cpi) \|\| cpi->cpi_family == 0xf) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	828 x86_type = X86_TYPE_P4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	829 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	830 * We don't currently depend on any of the %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	831 * features until Prescott, so we'll only check
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	832 * this from P4 onwards. We might want to revisit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	833 * that idea later.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	834 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	835 mask_ecx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	836 } else if (cpi->cpi_family > 0xf)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	837 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	838 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	839 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	840 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	841 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	842 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	843 mask_ecx &= ~CPUID_INTC_ECX_MON;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	844 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	845 case X86_VENDOR_IntelClone:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	846 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	847 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	848 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	849 #if defined(OPTERON_ERRATUM_108)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	850 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	851 cp->cp_eax = (0xf0f & cp->cp_eax) \| 0xc0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	852 cpi->cpi_model = 0xc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	853 } else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	854 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	855 if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	856 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	857 * AMD K5 and K6
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	858 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	859 * These CPUs have an incomplete implementation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	860 * of MCA/MCE which we mask away.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	861 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	862 mask_edx &= ~(CPUID_INTC_EDX_MCE \| CPUID_INTC_EDX_MCA);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	863
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	864 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	865 * Model 0 uses the wrong (APIC) bit
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	866 * to indicate PGE. Fix it here.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	867 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	868 if (cpi->cpi_model == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	869 if (cp->cp_edx & 0x200) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	870 cp->cp_edx &= ~0x200;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	871 cp->cp_edx \|= CPUID_INTC_EDX_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	872 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	873 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	874
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	875 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	876 * Early models had problems w/ MMX; disable.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	877 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	878 if (cpi->cpi_model < 6)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	879 mask_edx &= ~CPUID_INTC_EDX_MMX;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	880 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	881
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	882 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	883 * For newer families, SSE3 and CX16, at least, are valid;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	884 * enable all
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	885 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	886 if (cpi->cpi_family >= 0xf)
771 1c25a2120ec0 6327969 cpuid sse3 feature bit not noted on any AMD processor dmick parents: 359 diff changeset	887 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	888 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	889 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	890 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	891 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	892 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	893 mask_ecx &= ~CPUID_INTC_ECX_MON;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	894
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	895 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	896 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	897 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	898 * processors. AMD does not intend MWAIT to be used in the cpu
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	899 * idle loop on current and future processors. 10h and future
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	900 * AMD processors use more power in MWAIT than HLT.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	901 * Pre-family-10h Opterons do not have the MWAIT instruction.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	902 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	903 idle_cpu_prefer_mwait = 0;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	904 #endif
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	905
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	906 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	907 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	908 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	909 * workaround the NT workaround in CMS 4.1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	910 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	911 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	912 (cpi->cpi_step == 2 \|\| cpi->cpi_step == 3))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	913 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	914 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	915 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	916 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	917 * workaround the NT workarounds again
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	918 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	919 if (cpi->cpi_family == 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	920 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	921 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	922 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	923 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	924 * We rely heavily on the probing in locore
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	925 * to actually figure out what parts, if any,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	926 * of the Cyrix cpuid instruction to believe.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	927 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	928 switch (x86_type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	929 case X86_TYPE_CYRIX_486:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	930 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	931 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	932 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	933 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	934 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	935 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	936 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	937 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	938 CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	939 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	940 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	941 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	942 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	943 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	944 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	945 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	946 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	947 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	948 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	949 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	950 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	951 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	952 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	953 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	954 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	955 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	956 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	957 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	958 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	959 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	960 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	961 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	962 CPUID_INTC_EDX_TSC \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	963 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	964 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	965 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	966 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	967 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	968 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	969 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	970 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	971 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	972 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	973 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	974
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	975 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	976 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	977 * Do not support MONITOR/MWAIT under a hypervisor
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	978 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	979 mask_ecx &= ~CPUID_INTC_ECX_MON;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	980 #endif /* __xpv */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	981
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	982 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	983 * Now we've figured out the masks that determine
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	984 * which bits we choose to believe, apply the masks
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	985 * to the feature words, then map the kernel's view
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	986 * of these feature words into its feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	987 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	988 cp->cp_edx &= mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	989 cp->cp_ecx &= mask_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	990
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	991 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	992 * apply any platform restrictions (we don't call this
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	993 * immediately after __cpuid_insn here, because we need the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	994 * workarounds applied above first)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	995 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	996 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	997
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	998 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	999 * fold in overrides from the "eeprom" mechanism
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1000 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1001 cp->cp_edx \|= cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1002 cp->cp_edx &= ~cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1003
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1004 cp->cp_ecx \|= cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1005 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1006
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1007 if (cp->cp_edx & CPUID_INTC_EDX_PSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1008 feature \|= X86_LARGEPAGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1009 if (cp->cp_edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1010 feature \|= X86_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1011 if (cp->cp_edx & CPUID_INTC_EDX_MSR)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1012 feature \|= X86_MSR;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1013 if (cp->cp_edx & CPUID_INTC_EDX_MTRR)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1014 feature \|= X86_MTRR;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1015 if (cp->cp_edx & CPUID_INTC_EDX_PGE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1016 feature \|= X86_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1017 if (cp->cp_edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1018 feature \|= X86_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1019 if (cp->cp_edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1020 feature \|= X86_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1021 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1022 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1023 feature \|= X86_MCA;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1024 if (cp->cp_edx & CPUID_INTC_EDX_PAE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1025 feature \|= X86_PAE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1026 if (cp->cp_edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1027 feature \|= X86_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1028 if (cp->cp_ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1029 feature \|= X86_CX16;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1030 if (cp->cp_edx & CPUID_INTC_EDX_PAT)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1031 feature \|= X86_PAT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1032 if (cp->cp_edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1033 feature \|= X86_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1034 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1035 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1036 * In our implementation, fxsave/fxrstor
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1037 * are prerequisites before we'll even
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1038 * try and do SSE things.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1039 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1040 if (cp->cp_edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1041 feature \|= X86_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1042 if (cp->cp_edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1043 feature \|= X86_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1044 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1045 feature \|= X86_SSE3;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1046 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1047 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1048 feature \|= X86_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1049 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1050 feature \|= X86_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1051 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1052 feature \|= X86_SSE4_2;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	1053 if (cp->cp_ecx & CPUID_INTC_ECX_AES)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	1054 feature \|= X86_AES;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1055 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1056 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1057 if (cp->cp_edx & CPUID_INTC_EDX_DE)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1058 feature \|= X86_DE;
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1059 #if !defined(__xpv)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1060 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1061
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1062 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1063 * We require the CLFLUSH instruction for erratum workaround
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1064 * to use MONITOR/MWAIT.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1065 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1066 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1067 cpi->cpi_mwait.support \|= MWAIT_SUPPORT;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1068 feature \|= X86_MWAIT;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1069 } else {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1070 extern int idle_cpu_assert_cflush_monitor;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1071
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1072 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1073 * All processors we are aware of which have
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1074 * MONITOR/MWAIT also have CLFLUSH.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1075 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1076 if (idle_cpu_assert_cflush_monitor) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1077 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1078 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1079 }
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1080 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1081 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1082 #endif /* __xpv */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1083
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1084 /*
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1085 * Only need it first time, rest of the cpus would follow suite.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1086 * we only capture this for the bootcpu.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1087 */
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1088 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1089 feature \|= X86_CLFSH;
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1090 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1091 }
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1092
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1093 if (feature & X86_PAE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1094 cpi->cpi_pabits = 36;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1095
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1096 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1097 * Hyperthreading configuration is slightly tricky on Intel
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1098 * and pure clones, and even trickier on AMD.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1099 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1100 * (AMD chose to set the HTT bit on their CMP processors,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1101 * even though they're not actually hyperthreaded. Thus it
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1102 * takes a bit more work to figure out what's really going
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1103 * on ... see the handling of the CMP_LGCY bit below)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1104 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1105 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1106 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1107 if (cpi->cpi_ncpu_per_chip > 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1108 feature \|= X86_HTT;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1109 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1110 cpi->cpi_ncpu_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1111 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1112
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1113 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1114 * Work on the "extended" feature information, doing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1115 * some basic initialization for cpuid_pass2()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1116 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1117 xcpuid = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1118 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1119 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1120 if (IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1121 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1122 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1123 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1124 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1125 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1126 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1127 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1128 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1129 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1130 * Only these Cyrix CPUs are -known- to support
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1131 * extended cpuid operations.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1132 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1133 if (x86_type == X86_TYPE_VIA_CYRIX_III \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1134 x86_type == X86_TYPE_CYRIX_GXm)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1135 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1136 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1137 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1138 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1139 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1140 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1141 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1142 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1143
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1144 if (xcpuid) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1145 cp = &cpi->cpi_extd[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1146 cp->cp_eax = 0x80000000;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1147 cpi->cpi_xmaxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1148 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1149
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1150 if (cpi->cpi_xmaxeax & 0x80000000) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1151
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1152 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1153 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1154
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1155 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1156 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1157 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1158 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1159 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1160 cp = &cpi->cpi_extd[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1161 cp->cp_eax = 0x80000001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1162 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1163
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1164 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1165 cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1166 cpi->cpi_model == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1167 cpi->cpi_step == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1168 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1169 * K6 model 6 uses bit 10 to indicate SYSC
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1170 * Later models use bit 11. Fix it here.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1171 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1172 if (cp->cp_edx & 0x400) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1173 cp->cp_edx &= ~0x400;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1174 cp->cp_edx \|= CPUID_AMD_EDX_SYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1175 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1176 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1177
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1178 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1179
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1180 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1181 * Compute the additions to the kernel's feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1182 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1183 if (cp->cp_edx & CPUID_AMD_EDX_NX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1184 feature \|= X86_NX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1185
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1186 /*
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1187 * Regardless whether or not we boot 64-bit,
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1188 * we should have a way to identify whether
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1189 * the CPU is capable of running 64-bit.
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1190 */
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1191 if (cp->cp_edx & CPUID_AMD_EDX_LM)
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1192 feature \|= X86_64;
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1193
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1194 #if defined(__amd64)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1195 /* 1 GB large page - enable only for 64 bit kernel */
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1196 if (cp->cp_edx & CPUID_AMD_EDX_1GPG)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1197 feature \|= X86_1GPG;
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1198 #endif
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1199
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1200 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1201 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1202 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A))
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1203 feature \|= X86_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1204
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1205 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1206 * If both the HTT and CMP_LGCY bits are set,
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1207 * then we're not actually HyperThreaded. Read
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1208 * "AMD CPUID Specification" for more details.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1209 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1210 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1211 (feature & X86_HTT) &&
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1212 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1213 feature &= ~X86_HTT;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1214 feature \|= X86_CMP;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1215 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1216 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1217 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1218 * It's really tricky to support syscall/sysret in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1219 * the i386 kernel; we rely on sysenter/sysexit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1220 * instead. In the amd64 kernel, things are -way-
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1221 * better.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1222 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1223 if (cp->cp_edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1224 feature \|= X86_ASYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1225
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1226 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1227 * While we're thinking about system calls, note
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1228 * that AMD processors don't support sysenter
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1229 * in long mode at all, so don't try to program them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1230 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1231 if (x86_vendor == X86_VENDOR_AMD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1232 feature &= ~X86_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1233 #endif
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	1234 if (cp->cp_edx & CPUID_AMD_EDX_TSCP)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1235 feature \|= X86_TSCP;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1236 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1237 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1238 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1239 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1240
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1241 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1242 * Get CPUID data about processor cores and hyperthreads.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1243 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1244 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1245 case X86_VENDOR_Intel:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1246 if (cpi->cpi_maxeax >= 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1247 cp = &cpi->cpi_std[4];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1248 cp->cp_eax = 4;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1249 cp->cp_ecx = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1250 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1251 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1252 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1253 /FALLTHROUGH/
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1254 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1255 if (cpi->cpi_xmaxeax < 0x80000008)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1256 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1257 cp = &cpi->cpi_extd[8];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1258 cp->cp_eax = 0x80000008;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1259 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1260 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1261
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1262 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1263 * Virtual and physical address limits from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1264 * cpuid override previously guessed values.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1265 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1266 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1267 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1268 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1269 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1270 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1271 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1272
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1273 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1274 * Derive the number of cores per chip
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1275 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1276 switch (cpi->cpi_vendor) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1277 case X86_VENDOR_Intel:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1278 if (cpi->cpi_maxeax < 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1279 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1280 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1281 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1282 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1283 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1284 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1285 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1286 case X86_VENDOR_AMD:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1287 if (cpi->cpi_xmaxeax < 0x80000008) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1288 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1289 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1290 } else {
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1291 /*
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1292 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1293 * 1 less than the number of physical cores on
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1294 * the chip. In family 0x10 this value can
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1295 * be affected by "downcoring" - it reflects
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1296 * 1 less than the number of cores actually
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1297 * enabled on this node.
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1298 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1299 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1300 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1301 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1302 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1303 default:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1304 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1305 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1306 }
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1307
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1308 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1309 * Get CPUID data about TSC Invariance in Deep C-State.
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1310 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1311 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1312 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1313 if (cpi->cpi_maxeax >= 7) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1314 cp = &cpi->cpi_extd[7];
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1315 cp->cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1316 cp->cp_ecx = 0;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1317 (void) __cpuid_insn(cp);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1318 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1319 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1320 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1321 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1322 }
5284 2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1323 } else {
2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1324 cpi->cpi_ncore_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1325 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1326
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1327 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1328 * If more than one core, then this processor is CMP.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1329 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1330 if (cpi->cpi_ncore_per_chip > 1)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1331 feature \|= X86_CMP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1332
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1333 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1334 * If the number of cores is the same as the number
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1335 * of CPUs, then we cannot have HyperThreading.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1336 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1337 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1338 feature &= ~X86_HTT;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1339
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1340 cpi->cpi_apicid = CPI_APIC_ID(cpi);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1341 cpi->cpi_procnodes_per_pkg = 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1342
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1343 if ((feature & (X86_HTT \| X86_CMP)) == 0) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1344 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1345 * Single-core single-threaded processors.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1346 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1347 cpi->cpi_chipid = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1348 cpi->cpi_clogid = 0;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1349 cpi->cpi_coreid = cpu->cpu_id;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1350 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1351 if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1352 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1353 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1354 cpi->cpi_procnodeid = cpi->cpi_chipid;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1355 } else if (cpi->cpi_ncpu_per_chip > 1) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1356 if (cpi->cpi_vendor == X86_VENDOR_Intel)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1357 cpuid_intel_getids(cpu, feature);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1358 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1359 cpuid_amd_getids(cpu);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1360 else {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1361 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1362 * All other processors are currently
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1363 * assumed to have single cores.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1364 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1365 cpi->cpi_coreid = cpi->cpi_chipid;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1366 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1367 cpi->cpi_procnodeid = cpi->cpi_chipid;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1368 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1369 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1370
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1371 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1372 * Synthesize chip "revision" and socket type
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1373 */
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1374 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1375 cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1376 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1377 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1378 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1379 cpi->cpi_model, cpi->cpi_step);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1380
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1381 pass1_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1382 cpi->cpi_pass = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1383 return (feature);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1384 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1385
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1386 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1387 * Make copies of the cpuid table entries we depend on, in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1388 * part for ease of parsing now, in part so that we have only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1389 * one place to correct any of it, in part for ease of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1390 * later export to userland, and in part so we can look at
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1391 * this stuff in a crash dump.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1392 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1393
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1394 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1395 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1396 cpuid_pass2(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1397 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1398 uint_t n, nmax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1399 int i;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1400 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1401 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1402 uint32_t *iptr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1403 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1404
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1405 ASSERT(cpi->cpi_pass == 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1406
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1407 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1408 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1409
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1410 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1411 nmax = NMAX_CPI_STD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1412 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1413 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1414 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1415 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1416 cp->cp_eax = n;
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1417
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1418 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1419 * CPUID function 4 expects %ecx to be initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1420 * with an index which indicates which cache to return
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1421 * information about. The OS is expected to call function 4
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1422 * with %ecx set to 0, 1, 2, ... until it returns with
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1423 * EAX[4:0] set to 0, which indicates there are no more
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1424 * caches.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1425 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1426 * Here, populate cpi_std[4] with the information returned by
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1427 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1428 * when dynamic memory allocation becomes available.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1429 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1430 * Note: we need to explicitly initialize %ecx here, since
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1431 * function 4 may have been previously invoked.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1432 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1433 if (n == 4)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1434 cp->cp_ecx = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1435
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1436 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1437 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1438 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1439 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1440 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1441 * "the lower 8 bits of the %eax register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1442 * contain a value that identifies the number
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1443 * of times the cpuid [instruction] has to be
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1444 * executed to obtain a complete image of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1445 * processor's caching systems."
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1446 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1447 * How do they make this stuff up?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1448 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1449 cpi->cpi_ncache = sizeof (cp)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1450 BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1451 if (cpi->cpi_ncache == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1452 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1453 cpi->cpi_ncache--; /* skip count byte */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1454
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1455 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1456 * Well, for now, rather than attempt to implement
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1457 * this slightly dubious algorithm, we just look
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1458 * at the first 15 ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1459 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1460 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1461 cpi->cpi_ncache = sizeof (*cp) - 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1462
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1463 dp = cpi->cpi_cacheinfo;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1464 if (BITX(cp->cp_eax, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1465 uint8_t p = (void )&cp->cp_eax;
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1466 for (i = 1; i < 4; i++)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1467 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1468 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1469 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1470 if (BITX(cp->cp_ebx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1471 uint8_t p = (void )&cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1472 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1473 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1474 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1475 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1476 if (BITX(cp->cp_ecx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1477 uint8_t p = (void )&cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1478 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1479 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1480 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1481 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1482 if (BITX(cp->cp_edx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1483 uint8_t p = (void )&cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1484 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1485 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1486 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1487 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1488 break;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1489
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1490 case 3: /* Processor serial number, if PSN supported */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1491 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1492
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1493 case 4: /* Deterministic cache parameters */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1494 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1495
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1496 case 5: /* Monitor/Mwait parameters */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1497 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1498 size_t mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1499
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1500 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1501 * check cpi_mwait.support which was set in cpuid_pass1
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1502 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1503 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1504 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1505
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1506 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1507 * Protect ourself from insane mwait line size.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1508 * Workaround for incomplete hardware emulator(s).
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1509 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1510 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1511 if (mwait_size < sizeof (uint32_t) \|\|
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1512 !ISP2(mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1513 #if DEBUG
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1514 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1515 "size %ld", cpu->cpu_id, (long)mwait_size);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1516 #endif
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1517 break;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1518 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1519
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1520 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1521 cpi->cpi_mwait.mon_max = mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1522 if (MWAIT_EXTENSION(cpi)) {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1523 cpi->cpi_mwait.support \|= MWAIT_EXTENSIONS;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1524 if (MWAIT_INT_ENABLE(cpi))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1525 cpi->cpi_mwait.support \|=
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1526 MWAIT_ECX_INT_ENABLE;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1527 }
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1528 break;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1529 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1530 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1531 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1532 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1533 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1534
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1535 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1536 struct cpuid_regs regs;
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1537
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1538 cp = &regs;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1539 cp->cp_eax = 0xB;
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1540 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1541
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1542 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1543
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1544 /*
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1545 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1546 * indicates that the extended topology enumeration leaf is
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1547 * available.
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1548 */
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1549 if (cp->cp_ebx) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1550 uint32_t x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1551 uint_t coreid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1552 uint_t ncpu_per_core = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1553 uint_t chipid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1554 uint_t ncpu_per_chip = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1555 uint_t i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1556 uint_t level;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1557
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1558 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1559 cp->cp_eax = 0xB;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1560 cp->cp_ecx = i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1561
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1562 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1563 level = CPI_CPU_LEVEL_TYPE(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1564
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1565 if (level == 1) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1566 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1567 coreid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1568 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1569 } else if (level == 2) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1570 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1571 chipid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1572 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1573 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1574 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1575
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1576 cpi->cpi_apicid = x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1577 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1578 cpi->cpi_ncore_per_chip = ncpu_per_chip /
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1579 ncpu_per_core;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1580 cpi->cpi_chipid = x2apic_id >> chipid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1581 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1582 cpi->cpi_coreid = x2apic_id >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1583 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1584 }
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1585
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1586 /* Make cp NULL so that we don't stumble on others */
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1587 cp = NULL;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1588 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1589
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1590 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1591 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1592
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1593 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1594 nmax = NMAX_CPI_EXTD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1595 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1596 * Copy the extended properties, fixing them as we go.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1597 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1598 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1599 iptr = (void *)cpi->cpi_brandstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1600 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1601 cp->cp_eax = 0x80000000 + n;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1602 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1603 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1604 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1605 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1606 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1607 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1608 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1609 * Extract the brand string
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1610 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1611 *iptr++ = cp->cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1612 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1613 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1614 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1615 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1616 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1617 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1618 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1619 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1620 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1621 * parts to report the sizes of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1622 * TLB for large pages. Before then,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1623 * we don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1624 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1625 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1626 (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1627 cpi->cpi_model < 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1628 cp->cp_eax = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1629 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1630 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1631 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1632 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1633 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1634 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1635 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1636 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1637 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1638 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1639 * AMD parts with L2 TLB's.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1640 * Before then, don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1641 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1642 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1643 cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1644 cpi->cpi_model < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1645 cp->cp_eax = cp->cp_ebx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1646 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1647 * AMD Duron rev A0 reports L2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1648 * cache size incorrectly as 1K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1649 * when it is really 64K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1650 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1651 if (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1652 cpi->cpi_model == 3 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1653 cpi->cpi_step == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1654 cp->cp_ecx &= 0xffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1655 cp->cp_ecx \|= 0x400000;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1656 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1657 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1658 case X86_VENDOR_Cyrix: /* VIA C3 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1659 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1660 * VIA C3 processors are a bit messed
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1661 * up w.r.t. encoding cache sizes in %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1662 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1663 if (cpi->cpi_family != 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1664 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1665 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1666 * model 7 and 8 were incorrectly encoded
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1667 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1668 * xxx is model 8 really broken?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1669 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1670 if (cpi->cpi_model == 7 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1671 cpi->cpi_model == 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1672 cp->cp_ecx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1673 BITX(cp->cp_ecx, 31, 24) << 16 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1674 BITX(cp->cp_ecx, 23, 16) << 12 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1675 BITX(cp->cp_ecx, 15, 8) << 8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1676 BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1677 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1678 * model 9 stepping 1 has wrong associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1679 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1680 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1681 cp->cp_ecx \|= 8 << 12;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1682 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1683 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1684 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1685 * Extended L2 Cache features function.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1686 * First appeared on Prescott.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1687 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1688 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1689 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1690 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1691 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1692 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1693 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1694 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1695 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1696
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1697 pass2_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1698 cpi->cpi_pass = 2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1699 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1700
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1701 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1702 intel_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1703 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1704 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1705
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1706 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1707 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1708 return ("i486");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1709
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1710 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1711 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1712 return ("Intel Pentium(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1713 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1714 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1715 uint_t celeron, xeon;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1716 const struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1717 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1718 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1719 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1720 return ("Intel Pentium(r) Pro");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1721 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1722 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1723 return ("Intel Pentium(r) II");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1724 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1725 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1726 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1727 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1728 celeron = xeon = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1729 cp = &cpi->cpi_std[2]; /* cache info */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1730
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1731 for (i = 1; i < 4; i++) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1732 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1733
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1734 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1735 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1736 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1737 if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1738 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1739 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1740
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1741 for (i = 0; i < 2; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1742 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1743
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1744 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1745 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1746 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1747 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1748 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1749 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1750
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1751 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1752 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1753
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1754 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1755 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1756 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1757 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1758 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1759 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1760
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1761 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1762 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1763
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1764 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1765 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1766 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1767 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1768 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1769 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1770
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1771 if (celeron)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1772 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1773 if (xeon)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1774 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1775 "Intel Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1776 "Intel Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1777 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1778 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1779 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1780 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1781 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1782 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1783 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1784 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1785 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1786
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1787 /* BrandID is present if the field is nonzero */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1788 if (cpi->cpi_brandid != 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1789 static const struct {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1790 uint_t bt_bid;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1791 const char *bt_str;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1792 } brand_tbl[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1793 { 0x1, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1794 { 0x2, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1795 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1796 { 0x4, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1797 { 0x6, "Mobile Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1798 { 0x7, "Mobile Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1799 { 0x8, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1800 { 0x9, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1801 { 0xa, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1802 { 0xb, "Intel(r) Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1803 { 0xc, "Intel(r) Xeon(tm) MP" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1804 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1805 { 0xf, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1806 { 0x11, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1807 { 0x12, "Intel(r) Celeron(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1808 { 0x13, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1809 { 0x14, "Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1810 { 0x15, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1811 { 0x16, "Intel(r) Pentium(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1812 { 0x17, "Mobile Intel(r) Celeron(r)" }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1813 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1814 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1815 uint_t sgn;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1816
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1817 sgn = (cpi->cpi_family << 8) \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1818 (cpi->cpi_model << 4) \| cpi->cpi_step;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1819
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1820 for (i = 0; i < btblmax; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1821 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1822 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1823 if (i < btblmax) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1824 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1825 return ("Intel(r) Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1826 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1827 return ("Intel(r) Xeon(tm) MP");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1828 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1829 return ("Intel(r) Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1830 return (brand_tbl[i].bt_str);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1831 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1832 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1833
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1834 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1835 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1836
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1837 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1838 amd_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1839 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1840 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1841 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1842 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1843
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1844 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1845 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1846 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1847 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1848 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1849 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1850 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1851 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1852 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1853 return ("AMD-K5(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1854 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1855 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1856 return ("AMD-K6(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1857 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1858 return ("AMD-K6(r)-2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1859 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1860 return ("AMD-K6(r)-III");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1861 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1862 return ("AMD (family 5)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1863 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1864 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1865 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1866 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1867 return ("AMD-K7(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1868 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1869 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1870 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1871 return ("AMD Athlon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1872 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1873 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1874 return ("AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1875 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1876 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1877 case 10:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1878 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1879 * Use the L2 cache size to distinguish
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1880 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1881 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1882 "AMD Athlon(tm)" : "AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1883 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1884 return ("AMD (family 6)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1885 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1886 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1887 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1888 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1889
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1890 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1891 cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1892 switch (BITX(cpi->cpi_brandid, 7, 5)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1893 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1894 return ("AMD Opteron(tm) UP 1xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1895 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1896 return ("AMD Opteron(tm) DP 2xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1897 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1898 return ("AMD Opteron(tm) MP 8xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1899 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1900 return ("AMD Opteron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1901 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1902 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1903
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1904 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1905 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1906
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1907 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1908 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1909 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1910 if ((x86_feature & X86_CPUID) == 0 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1911 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1912 type == X86_TYPE_CYRIX_486)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1913 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1914
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1915 switch (type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1916 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1917 return ("Cyrix 6x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1918 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1919 return ("Cyrix 6x86L");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1920 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1921 return ("Cyrix 6x86MX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1922 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1923 return ("Cyrix GXm");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1924 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1925 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1926 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1927 return ("Cyrix M2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1928 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1929 return ("VIA Cyrix M3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1930 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1931 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1932 * Have another wild guess ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1933 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1934 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1935 return ("Cyrix 5x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1936 else if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1937 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1938 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1939 return ("Cyrix 6x86"); /* Cyrix M1 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1940 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1941 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1942 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1943 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1944 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1945 } else if (cpi->cpi_family == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1946 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1947 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1948 return ("Cyrix 6x86MX"); /* Cyrix M2? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1949 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1950 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1951 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1952 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1953 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1954 return ("VIA C3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1955 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1956 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1957 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1958 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1959 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1960 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1961 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1962 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1963
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1964 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1965 * This only gets called in the case that the CPU extended
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1966 * feature brand string (0x80000002, 0x80000003, 0x80000004)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1967 * aren't available, or contain null bytes for some reason.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1968 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1969 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1970 fabricate_brandstr(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1971 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1972 const char *brand = NULL;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1973
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1974 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1975 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1976 brand = intel_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1977 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1978 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1979 brand = amd_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1980 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1981 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1982 brand = cyrix_cpubrand(cpi, x86_type);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1983 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1984 case X86_VENDOR_NexGen:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1985 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1986 brand = "NexGen Nx586";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1987 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1988 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1989 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1990 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1991 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1992 brand = "Centaur C6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1993 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1994 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1995 brand = "Centaur C2";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1996 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1997 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1998 brand = "Centaur C3";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1999 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2000 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2001 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2002 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2003 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2004 case X86_VENDOR_Rise:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2005 if (cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2006 (cpi->cpi_model == 0 \|\| cpi->cpi_model == 2))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2007 brand = "Rise mP6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2008 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2009 case X86_VENDOR_SiS:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2010 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2011 brand = "SiS 55x";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2012 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2013 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2014 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2015 brand = "Transmeta Crusoe TM3x00 or TM5x00";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2016 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2017 case X86_VENDOR_NSC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2018 case X86_VENDOR_UMC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2019 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2020 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2021 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2022 if (brand) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2023 (void) strcpy((char *)cpi->cpi_brandstr, brand);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2024 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2025 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2026
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2027 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2028 * If all else fails ...
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2029 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2030 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2031 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2032 cpi->cpi_model, cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2033 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2034
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2035 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2036 * This routine is called just after kernel memory allocation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2037 * becomes available on cpu0, and as part of mp_startup() on
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2038 * the other cpus.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2039 *
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2040 * Fixup the brand string, and collect any information from cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2041 * that requires dynamicically allocated storage to represent.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2042 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2043 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2044 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2045 cpuid_pass3(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2046 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2047 int i, max, shft, level, size;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2048 struct cpuid_regs regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2049 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2050 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2051
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2052 ASSERT(cpi->cpi_pass == 2);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2053
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2054 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2055 * Function 4: Deterministic cache parameters
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2056 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2057 * Take this opportunity to detect the number of threads
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2058 * sharing the last level cache, and construct a corresponding
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2059 * cache id. The respective cpuid_info members are initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2060 * to the default case of "no last level cache sharing".
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2061 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2062 cpi->cpi_ncpu_shr_last_cache = 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2063 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2064
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2065 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2066
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2067 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2068 * Find the # of elements (size) returned by fn 4, and along
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2069 * the way detect last level cache sharing details.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2070 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2071 bzero(&regs, sizeof (regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2072 cp = &regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2073 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2074 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2075 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2076
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2077 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2078
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2079 if (CPI_CACHE_TYPE(cp) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2080 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2081 level = CPI_CACHE_LVL(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2082 if (level > max) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2083 max = level;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2084 cpi->cpi_ncpu_shr_last_cache =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2085 CPI_NTHR_SHR_CACHE(cp) + 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2086 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2087 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2088 cpi->cpi_std_4_size = size = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2089
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2090 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2091 * Allocate the cpi_std_4 array. The first element
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2092 * references the regs for fn 4, %ecx == 0, which
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2093 * cpuid_pass2() stashed in cpi->cpi_std[4].
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2094 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2095 if (size > 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2096 cpi->cpi_std_4 =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2097 kmem_alloc(size * sizeof (cp), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2098 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2099
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2100 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2101 * Allocate storage to hold the additional regs
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2102 * for function 4, %ecx == 1 .. cpi_std_4_size.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2103 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2104 * The regs for fn 4, %ecx == 0 has already
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2105 * been allocated as indicated above.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2106 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2107 for (i = 1; i < size; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2108 cp = cpi->cpi_std_4[i] =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2109 kmem_zalloc(sizeof (regs), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2110 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2111 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2112
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2113 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2114 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2115 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2116 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2117 * Determine the number of bits needed to represent
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2118 * the number of CPUs sharing the last level cache.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2119 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2120 * Shift off that number of bits from the APIC id to
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2121 * derive the cache id.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2122 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2123 shft = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2124 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2125 shft++;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	2126 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2127 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2128
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2129 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2130 * Now fixup the brand string
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2131 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2132 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2133 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2134 } else {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2135
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2136 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2137 * If we successfully extracted a brand string from the cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2138 * instruction, clean it up by removing leading spaces and
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2139 * similar junk.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2140 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2141 if (cpi->cpi_brandstr[0]) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2142 size_t maxlen = sizeof (cpi->cpi_brandstr);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2143 char src, dst;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2144
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2145 dst = src = (char *)cpi->cpi_brandstr;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2146 src[maxlen - 1] = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2147 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2148 * strip leading spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2149 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2150 while (*src == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2151 src++;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2152 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2153 * Remove any 'Genuine' or "Authentic" prefixes
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2154 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2155 if (strncmp(src, "Genuine ", 8) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2156 src += 8;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2157 if (strncmp(src, "Authentic ", 10) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2158 src += 10;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2159
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2160 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2161 * Now do an in-place copy.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2162 * Map (R) to (r) and (TM) to (tm).
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2163 * The era of teletypes is long gone, and there's
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2164 * -really- no need to shout.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2165 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2166 while (*src != '\0') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2167 if (src[0] == '(') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2168 if (strncmp(src + 1, "R)", 2) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2169 (void) strncpy(dst, "(r)", 3);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2170 src += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2171 dst += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2172 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2173 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2174 if (strncmp(src + 1, "TM)", 3) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2175 (void) strncpy(dst, "(tm)", 4);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2176 src += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2177 dst += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2178 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2179 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2180 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2181 dst++ = src++;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2182 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2183 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2184
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2185 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2186 * Finally, remove any trailing spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2187 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2188 while (--dst > cpi->cpi_brandstr)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2189 if (*dst == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2190 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2191 else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2192 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2193 } else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2194 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2195 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2196 cpi->cpi_pass = 3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2197 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2198
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2199 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2200 * This routine is called out of bind_hwcap() much later in the life
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2201 * of the kernel (post_startup()). The job of this routine is to resolve
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2202 * the hardware feature support and kernel support for those features into
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2203 * what we're actually going to tell applications via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2204 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2205 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2206 cpuid_pass4(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2207 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2208 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2209 uint_t hwcap_flags = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2210
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2211 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2212 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2213 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2214
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2215 ASSERT(cpi->cpi_pass == 3);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2216
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2217 if (cpi->cpi_maxeax >= 1) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2218 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2219 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2220
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2221 *edx = CPI_FEATURES_EDX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2222 *ecx = CPI_FEATURES_ECX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2223
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2224 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2225 * [these require explicit kernel support]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2226 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2227 if ((x86_feature & X86_SEP) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2228 *edx &= ~CPUID_INTC_EDX_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2229
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2230 if ((x86_feature & X86_SSE) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2231 *edx &= ~(CPUID_INTC_EDX_FXSR\|CPUID_INTC_EDX_SSE);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2232 if ((x86_feature & X86_SSE2) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2233 *edx &= ~CPUID_INTC_EDX_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2234
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2235 if ((x86_feature & X86_HTT) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2236 *edx &= ~CPUID_INTC_EDX_HTT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2237
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2238 if ((x86_feature & X86_SSE3) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2239 *ecx &= ~CPUID_INTC_ECX_SSE3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2240
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2241 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2242 if ((x86_feature & X86_SSSE3) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2243 *ecx &= ~CPUID_INTC_ECX_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2244 if ((x86_feature & X86_SSE4_1) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2245 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2246 if ((x86_feature & X86_SSE4_2) == 0)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2247 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2248 if ((x86_feature & X86_AES) == 0)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2249 *ecx &= ~CPUID_INTC_ECX_AES;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2250 }
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2251
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2252 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2253 * [no explicit support required beyond x87 fp context]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2254 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2255 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2256 *edx &= ~(CPUID_INTC_EDX_FPU \| CPUID_INTC_EDX_MMX);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2257
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2258 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2259 * Now map the supported feature vector to things that we
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2260 * think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2261 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2262 if (*edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2263 hwcap_flags \|= AV_386_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2264 if (*edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2265 hwcap_flags \|= AV_386_FXSR \| AV_386_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2266 if (*edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2267 hwcap_flags \|= AV_386_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2268 if (*ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2269 hwcap_flags \|= AV_386_SSE3;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2270 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2271 if (*ecx & CPUID_INTC_ECX_SSSE3)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2272 hwcap_flags \|= AV_386_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2273 if (*ecx & CPUID_INTC_ECX_SSE4_1)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2274 hwcap_flags \|= AV_386_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2275 if (*ecx & CPUID_INTC_ECX_SSE4_2)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2276 hwcap_flags \|= AV_386_SSE4_2;
8418 a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2277 if (*ecx & CPUID_INTC_ECX_MOVBE)
a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2278 hwcap_flags \|= AV_386_MOVBE;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2279 if (*ecx & CPUID_INTC_ECX_AES)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2280 hwcap_flags \|= AV_386_AES;
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2281 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2282 hwcap_flags \|= AV_386_PCLMULQDQ;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2283 }
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2284 if (*ecx & CPUID_INTC_ECX_POPCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2285 hwcap_flags \|= AV_386_POPCNT;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2286 if (*edx & CPUID_INTC_EDX_FPU)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2287 hwcap_flags \|= AV_386_FPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2288 if (*edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2289 hwcap_flags \|= AV_386_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2290
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2291 if (*edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2292 hwcap_flags \|= AV_386_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2293 if (*edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2294 hwcap_flags \|= AV_386_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2295 if (*edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2296 hwcap_flags \|= AV_386_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2297 if (*ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2298 hwcap_flags \|= AV_386_CX16;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2299 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2300
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2301 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2302 goto pass4_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2303
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2304 switch (cpi->cpi_vendor) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2305 struct cpuid_regs cp;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2306 uint32_t edx, ecx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2307
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2308 case X86_VENDOR_Intel:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2309 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2310 * Seems like Intel duplicated what we necessary
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2311 * here to make the initial crop of 64-bit OS's work.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2312 * Hopefully, those are the only "extended" bits
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2313 * they'll add.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2314 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2315 /FALLTHROUGH/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2316
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2317 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2318 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2319 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2320
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2321 *edx = CPI_FEATURES_XTD_EDX(cpi);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2322 *ecx = CPI_FEATURES_XTD_ECX(cpi);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2323
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2324 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2325 * [these features require explicit kernel support]
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2326 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2327 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2328 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2329 if ((x86_feature & X86_TSCP) == 0)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2330 *edx &= ~CPUID_AMD_EDX_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2331 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2332
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2333 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2334 if ((x86_feature & X86_TSCP) == 0)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2335 *edx &= ~CPUID_AMD_EDX_TSCP;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2336 if ((x86_feature & X86_SSE4A) == 0)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2337 *ecx &= ~CPUID_AMD_ECX_SSE4A;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2338 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2339
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2340 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2341 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2342 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2343
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2344 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2345 * [no explicit support required beyond
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2346 * x87 fp context and exception handlers]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2347 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2348 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2349 *edx &= ~(CPUID_AMD_EDX_MMXamd \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2350 CPUID_AMD_EDX_3DNow \| CPUID_AMD_EDX_3DNowx);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2351
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2352 if ((x86_feature & X86_NX) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2353 *edx &= ~CPUID_AMD_EDX_NX;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2354 #if !defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2355 *edx &= ~CPUID_AMD_EDX_LM;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2356 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2357 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2358 * Now map the supported feature vector to
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2359 * things that we think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2360 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2361 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2362 if (*edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2363 hwcap_flags \|= AV_386_AMD_SYSC;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2364 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2365 if (*edx & CPUID_AMD_EDX_MMXamd)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2366 hwcap_flags \|= AV_386_AMD_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2367 if (*edx & CPUID_AMD_EDX_3DNow)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2368 hwcap_flags \|= AV_386_AMD_3DNow;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2369 if (*edx & CPUID_AMD_EDX_3DNowx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2370 hwcap_flags \|= AV_386_AMD_3DNowx;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2371
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2372 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2373 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2374 if (*edx & CPUID_AMD_EDX_TSCP)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2375 hwcap_flags \|= AV_386_TSCP;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2376 if (*ecx & CPUID_AMD_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2377 hwcap_flags \|= AV_386_AHF;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2378 if (*ecx & CPUID_AMD_ECX_SSE4A)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2379 hwcap_flags \|= AV_386_AMD_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2380 if (*ecx & CPUID_AMD_ECX_LZCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2381 hwcap_flags \|= AV_386_AMD_LZCNT;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2382 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2383
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2384 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2385 if (*edx & CPUID_AMD_EDX_TSCP)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2386 hwcap_flags \|= AV_386_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2387 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2388 * Aarrgh.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2389 * Intel uses a different bit in the same word.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2390 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2391 if (*ecx & CPUID_INTC_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2392 hwcap_flags \|= AV_386_AHF;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2393 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2394
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2395 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2396 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2397 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2398 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2399
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2400 case X86_VENDOR_TM:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2401 cp.cp_eax = 0x80860001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2402 (void) __cpuid_insn(&cp);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2403 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2404 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2405
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2406 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2407 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2408 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2409
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2410 pass4_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2411 cpi->cpi_pass = 4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2412 return (hwcap_flags);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2413 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2414
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2415
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2416 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2417 * Simulate the cpuid instruction using the data we previously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2418 * captured about this CPU. We try our best to return the truth
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2419 * about the hardware, independently of kernel support.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2420 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2421 uint32_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2422 cpuid_insn(cpu_t cpu, struct cpuid_regs cp)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2423 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2424 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2425 struct cpuid_regs *xcp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2426
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2427 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2428 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2429 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2430
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2431 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2432
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2433 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2434 * CPUID data is cached in two separate places: cpi_std for standard
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2435 * CPUID functions, and cpi_extd for extended CPUID functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2436 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2437 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2438 xcp = &cpi->cpi_std[cp->cp_eax];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2439 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2440 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2441 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2442 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2443 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2444 * The caller is asking for data from an input parameter which
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2445 * the kernel has not cached. In this case we go fetch from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2446 * the hardware and return the data directly to the user.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2447 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2448 return (__cpuid_insn(cp));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2449
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2450 cp->cp_eax = xcp->cp_eax;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2451 cp->cp_ebx = xcp->cp_ebx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2452 cp->cp_ecx = xcp->cp_ecx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2453 cp->cp_edx = xcp->cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2454 return (cp->cp_eax);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2455 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2456
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2457 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2458 cpuid_checkpass(cpu_t *cpu, int pass)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2459 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2460 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2461 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2462 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2463
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2464 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2465 cpuid_getbrandstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2466 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2467 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2468
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2469 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2470 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2471
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2472 int
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2473 cpuid_is_cmt(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2474 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2475 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2476 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2477
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2478 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2479
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2480 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2481 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2482
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2483 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2484 * AMD and Intel both implement the 64-bit variant of the syscall
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2485 * instruction (syscallq), so if there's -any- support for syscall,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2486 * cpuid currently says "yes, we support this".
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2487 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2488 * However, Intel decided to -not- implement the 32-bit variant of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2489 * syscall instruction, so we provide a predicate to allow our caller
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2490 * to test that subtlety here.
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2491 *
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2492 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2493 * even in the case where the hardware would in fact support it.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2494 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2495 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2496 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2497 cpuid_syscall32_insn(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2498 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2499 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2500
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2501 #if !defined(__xpv)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2502 if (cpu == NULL)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2503 cpu = CPU;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2504
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2505 /CSTYLED/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2506 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2507 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2508
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2509 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2510 cpi->cpi_xmaxeax >= 0x80000001 &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2511 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2512 return (1);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2513 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2514 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2515 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2516 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2517
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2518 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2519 cpuid_getidstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2520 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2521 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2522
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2523 static const char fmt[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2524 "x86 (%s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2525 static const char fmt_ht[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2526 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2527
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2528 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2529
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2530 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2531 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2532 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2533 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2534 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2535 return (snprintf(s, n, fmt,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2536 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2537 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2538 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2539 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2540
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2541 const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2542 cpuid_getvendorstr(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2543 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2544 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2545 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2546 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2547
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2548 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2549 cpuid_getvendor(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2550 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2551 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2552 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2553 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2554
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2555 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2556 cpuid_getfamily(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2557 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2558 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2559 return (cpu->cpu_m.mcpu_cpi->cpi_family);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2560 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2561
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2562 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2563 cpuid_getmodel(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2564 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2565 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2566 return (cpu->cpu_m.mcpu_cpi->cpi_model);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2567 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2568
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2569 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2570 cpuid_get_ncpu_per_chip(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2571 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2572 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2573 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2574 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2575
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2576 uint_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2577 cpuid_get_ncore_per_chip(cpu_t *cpu)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2578 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2579 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2580 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2581 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2582
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2583 uint_t
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2584 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2585 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2586 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2587 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2588 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2589
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2590 id_t
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2591 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2592 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2593 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2594 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2595 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2596
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2597 uint_t
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2598 cpuid_getstep(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2599 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2600 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2601 return (cpu->cpu_m.mcpu_cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2602 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2603
4581 b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2604 uint_t
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2605 cpuid_getsig(struct cpu *cpu)
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2606 {
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2607 ASSERT(cpuid_checkpass(cpu, 1));
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2608 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2609 }
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2610
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2611 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2612 cpuid_getchiprev(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2613 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2614 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2615 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2616 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2617
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2618 const char *
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2619 cpuid_getchiprevstr(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2620 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2621 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2622 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2623 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2624
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2625 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2626 cpuid_getsockettype(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2627 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2628 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2629 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2630 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2631
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2632 const char *
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2633 cpuid_getsocketstr(cpu_t *cpu)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2634 {
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2635 static const char *socketstr = NULL;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2636 struct cpuid_info *cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2637
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2638 ASSERT(cpuid_checkpass(cpu, 1));
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2639 cpi = cpu->cpu_m.mcpu_cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2640
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2641 /* Assume that socket types are the same across the system */
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2642 if (socketstr == NULL)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2643 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2644 cpi->cpi_model, cpi->cpi_step);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2645
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2646
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2647 return (socketstr);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2648 }
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2649
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2650 int
5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2651 cpuid_get_chipid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2652 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2653 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2654
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2655 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2656 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2657 return (cpu->cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2658 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2659
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2660 id_t
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2661 cpuid_get_coreid(cpu_t *cpu)
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2662 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2663 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2664 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2665 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2666
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2667 int
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2668 cpuid_get_pkgcoreid(cpu_t *cpu)
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2669 {
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2670 ASSERT(cpuid_checkpass(cpu, 1));
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2671 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2672 }
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2673
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2674 int
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2675 cpuid_get_clogid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2676 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2677 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2678 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2679 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2680
11389 dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2681 int
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2682 cpuid_get_cacheid(cpu_t *cpu)
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2683 {
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2684 ASSERT(cpuid_checkpass(cpu, 1));
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2685 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2686 }
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2687
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2688 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2689 cpuid_get_procnodeid(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2690 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2691 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2692 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2693 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2694
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2695 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2696 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2697 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2698 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2699 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2700 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2701
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2702 /ARGSUSED/
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2703 int
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2704 cpuid_have_cr8access(cpu_t *cpu)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2705 {
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2706 #if defined(__amd64)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2707 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2708 #else
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2709 struct cpuid_info *cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2710
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2711 ASSERT(cpu != NULL);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2712 cpi = cpu->cpu_m.mcpu_cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2713 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2714 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2715 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2716 return (0);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2717 #endif
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2718 }
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2719
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2720 uint32_t
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2721 cpuid_get_apicid(cpu_t *cpu)
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2722 {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2723 ASSERT(cpuid_checkpass(cpu, 1));
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2724 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2725 return (UINT32_MAX);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2726 } else {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2727 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2728 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2729 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	2730
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2731 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2732 cpuid_get_addrsize(cpu_t cpu, uint_t pabits, uint_t *vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2733 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2734 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2735
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2736 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2737 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2738 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2739
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2740 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2741
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2742 if (pabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2743 *pabits = cpi->cpi_pabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2744 if (vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2745 *vabits = cpi->cpi_vabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2746 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2747
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2748 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2749 * Returns the number of data TLB entries for a corresponding
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2750 * pagesize. If it can't be computed, or isn't known, the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2751 * routine returns zero. If you ask about an architecturally
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2752 * impossible pagesize, the routine will panic (so that the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2753 * hat implementor knows that things are inconsistent.)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2754 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2755 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2756 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2757 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2758 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2759 uint_t dtlb_nent = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2760
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2761 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2762 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2763 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2764
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2765 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2766
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2767 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2768 * Check the L2 TLB info
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2769 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2770 if (cpi->cpi_xmaxeax >= 0x80000006) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2771 struct cpuid_regs *cp = &cpi->cpi_extd[6];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2772
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2773 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2774
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2775 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2776 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2777 * All zero in the top 16 bits of the register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2778 * indicates a unified TLB. Size is in low 16 bits.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2779 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2780 if ((cp->cp_ebx & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2781 dtlb_nent = cp->cp_ebx & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2782 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2783 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2784 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2785
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2786 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2787 if ((cp->cp_eax & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2788 dtlb_nent = cp->cp_eax & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2789 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2790 dtlb_nent = BITX(cp->cp_eax, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2791 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2792
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2793 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2794 panic("unknown L2 pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2795 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2796 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2797 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2798
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2799 if (dtlb_nent != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2800 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2801
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2802 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2803 * No L2 TLB support for this size, try L1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2804 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2805 if (cpi->cpi_xmaxeax >= 0x80000005) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2806 struct cpuid_regs *cp = &cpi->cpi_extd[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2807
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2808 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2809 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2810 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2811 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2812 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2813 dtlb_nent = BITX(cp->cp_eax, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2814 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2815 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2816 panic("unknown L1 d-TLB pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2817 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2818 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2819 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2820
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2821 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2822 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2823
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2824 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2825 * Return 0 if the erratum is not present or not applicable, positive
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2826 * if it is, and negative if the status of the erratum is unknown.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2827 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2828 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	2829 * Processors" #25759, Rev 3.57, August 2005
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2830 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2831 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2832 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2833 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2834 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2835 uint_t eax;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2836
2584 c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2837 /*
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2838 * Bail out if this CPU isn't an AMD CPU, or if it's
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2839 * a legacy (32-bit) AMD CPU.
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2840 */
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	2841 if (cpi->cpi_vendor != X86_VENDOR_AMD \|\|
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2842 cpi->cpi_family == 4 \|\| cpi->cpi_family == 5 \|\|
6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2843 cpi->cpi_family == 6)
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2844
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2845 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2846
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2847 eax = cpi->cpi_std[1].cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2848
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2849 #define SH_B0(eax) (eax == 0xf40 \|\| eax == 0xf50)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2850 #define SH_B3(eax) (eax == 0xf51)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2851 #define B(eax) (SH_B0(eax) \|\| SH_B3(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2852
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2853 #define SH_C0(eax) (eax == 0xf48 \|\| eax == 0xf58)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2854
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2855 #define SH_CG(eax) (eax == 0xf4a \|\| eax == 0xf5a \|\| eax == 0xf7a)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2856 #define DH_CG(eax) (eax == 0xfc0 \|\| eax == 0xfe0 \|\| eax == 0xff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2857 #define CH_CG(eax) (eax == 0xf82 \|\| eax == 0xfb2)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2858 #define CG(eax) (SH_CG(eax) \|\| DH_CG(eax) \|\| CH_CG(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2859
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2860 #define SH_D0(eax) (eax == 0x10f40 \|\| eax == 0x10f50 \|\| eax == 0x10f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2861 #define DH_D0(eax) (eax == 0x10fc0 \|\| eax == 0x10ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2862 #define CH_D0(eax) (eax == 0x10f80 \|\| eax == 0x10fb0)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2863 #define D0(eax) (SH_D0(eax) \|\| DH_D0(eax) \|\| CH_D0(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2864
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2865 #define SH_E0(eax) (eax == 0x20f50 \|\| eax == 0x20f40 \|\| eax == 0x20f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2866 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2867 #define DH_E3(eax) (eax == 0x20fc0 \|\| eax == 0x20ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2868 #define SH_E4(eax) (eax == 0x20f51 \|\| eax == 0x20f71)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2869 #define BH_E4(eax) (eax == 0x20fb1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2870 #define SH_E5(eax) (eax == 0x20f42)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2871 #define DH_E6(eax) (eax == 0x20ff2 \|\| eax == 0x20fc2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2872 #define JH_E6(eax) (eax == 0x20f12 \|\| eax == 0x20f32)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2873 #define EX(eax) (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2874 SH_E4(eax) \|\| BH_E4(eax) \|\| SH_E5(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	2875 DH_E6(eax) \|\| JH_E6(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2876
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2877 #define DR_AX(eax) (eax == 0x100f00 \|\| eax == 0x100f01 \|\| eax == 0x100f02)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2878 #define DR_B0(eax) (eax == 0x100f20)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2879 #define DR_B1(eax) (eax == 0x100f21)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2880 #define DR_BA(eax) (eax == 0x100f2a)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2881 #define DR_B2(eax) (eax == 0x100f22)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2882 #define DR_B3(eax) (eax == 0x100f23)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2883 #define RB_C0(eax) (eax == 0x100f40)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2884
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2885 switch (erratum) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2886 case 1:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2887 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2888 case 51: /* what does the asterisk mean? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2889 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2890 case 52:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2891 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2892 case 57:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2893 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2894 case 58:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2895 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2896 case 60:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2897 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2898 case 61:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2899 case 62:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2900 case 63:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2901 case 64:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2902 case 65:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2903 case 66:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2904 case 68:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2905 case 69:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2906 case 70:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2907 case 71:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2908 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2909 case 72:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2910 return (SH_B0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2911 case 74:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2912 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2913 case 75:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2914 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2915 case 76:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2916 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2917 case 77:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	2918 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2919 case 78:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2920 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2921 case 79:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2922 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2923 case 80:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2924 case 81:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2925 case 82:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2926 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2927 case 83:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2928 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2929 case 85:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2930 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2931 case 86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2932 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2933 case 88:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2934 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2935 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2936 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2937 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2938 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2939 case 89:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	2940 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2941 case 90:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2942 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2943 case 91:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2944 case 92:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2945 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2946 case 93:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2947 return (SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2948 case 94:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2949 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2950 case 95:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2951 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2952 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2953 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2954 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2955 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2956 case 96:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2957 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2958 case 97:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2959 case 98:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2960 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2961 case 99:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2962 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2963 case 100:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2964 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2965 case 101:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2966 case 103:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2967 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2968 case 104:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2969 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2970 case 105:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2971 case 106:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2972 case 107:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2973 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2974 case 108:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2975 return (DH_CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2976 case 109:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2977 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2978 case 110:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2979 return (D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2980 case 111:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2981 return (CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2982 case 112:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2983 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2984 case 113:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2985 return (eax == 0x20fc0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2986 case 114:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2987 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2988 case 115:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2989 return (SH_E0(eax) \|\| JH_E1(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2990 case 116:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2991 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2992 case 117:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2993 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2994 case 118:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2995 return (SH_E0(eax) \|\| JH_E1(eax) \|\| SH_E4(eax) \|\| BH_E4(eax) \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2996 JH_E6(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2997 case 121:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2998 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2999 case 122:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3000 return (cpi->cpi_family < 0x10 \|\| cpi->cpi_family == 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3001 case 123:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3002 return (JH_E1(eax) \|\| BH_E4(eax) \|\| JH_E6(eax));
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	3003 case 131:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3004 return (cpi->cpi_family < 0x10);
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3005 case 6336786:
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3006 /*
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3007 * Test for AdvPowerMgmtInfo.TscPStateInvariant
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3008 * if this is a K8 family or newer processor
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3009 */
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3010 if (CPI_FAMILY(cpi) == 0xf) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3011 struct cpuid_regs regs;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3012 regs.cp_eax = 0x80000007;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3013 (void) __cpuid_insn(&regs);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3014 return (!(regs.cp_edx & 0x100));
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3015 }
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3016 return (0);
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3017 case 6323525:
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3018 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) \|
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3019 (((eax >> 4) & 0xf) \| ((eax >> 12) & 0xf0))) < 0xf40);
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3020
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3021 case 6671130:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3022 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3023 * check for processors (pre-Shanghai) that do not provide
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3024 * optimal management of 1gb ptes in its tlb.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3025 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3026 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3027
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3028 case 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3029 return (DR_AX(eax) \|\| DR_B0(eax) \|\| DR_B1(eax) \|\| DR_BA(eax) \|\|
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3030 DR_B2(eax) \|\| RB_C0(eax));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3031
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3032 default:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3033 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3034
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3035 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3036 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3037
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3038 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3039 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3040 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3041 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3042 int
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3043 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3044 {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3045 struct cpuid_info *cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3046 uint_t osvwid;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3047 static int osvwfeature = -1;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3048 uint64_t osvwlength;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3049
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3050
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3051 cpi = cpu->cpu_m.mcpu_cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3052
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3053 /* confirm OSVW supported */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3054 if (osvwfeature == -1) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3055 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3056 } else {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3057 /* assert that osvw feature setting is consistent on all cpus */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3058 ASSERT(osvwfeature ==
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3059 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3060 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3061 if (!osvwfeature)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3062 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3063
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3064 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3065
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3066 switch (erratum) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3067 case 298: /* osvwid is 0 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3068 osvwid = 0;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3069 if (osvwlength <= (uint64_t)osvwid) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3070 /* osvwid 0 is unknown */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3071 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3072 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3073
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3074 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3075 * Check the OSVW STATUS MSR to determine the state
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3076 * of the erratum where:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3077 * 0 - fixed by HW
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3078 * 1 - BIOS has applied the workaround when BIOS
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3079 * workaround is available. (Or for other errata,
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3080 * OS workaround is required.)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3081 * For a value of 1, caller will confirm that the
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3082 * erratum 298 workaround has indeed been applied by BIOS.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3083 *
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3084 * A 1 may be set in cpus that have a HW fix
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3085 * in a mixed cpu system. Regarding erratum 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3086 * In a multiprocessor platform, the workaround above
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3087 * should be applied to all processors regardless of
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3088 * silicon revision when an affected processor is
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3089 * present.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3090 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3091
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3092 return (rdmsr(MSR_AMD_OSVW_STATUS +
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3093 (osvwid / OSVW_ID_CNT_PER_MSR)) &
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3094 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3095
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3096 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3097 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3098 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3099 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3100
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3101 static const char assoc_str[] = "associativity";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3102 static const char line_str[] = "line-size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3103 static const char size_str[] = "size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3104
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3105 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3106 add_cache_prop(dev_info_t devi, const char label, const char *type,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3107 uint32_t val)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3108 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3109 char buf[128];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3110
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3111 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3112 * ndi_prop_update_int() is used because it is desirable for
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3113 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3114 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3115 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3116 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3117 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3118
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3119 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3120 * Intel-style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3121 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3122 * Standard cpuid level 2 gives a randomly ordered
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3123 * selection of tags that index into a table that describes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3124 * cache and tlb properties.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3125 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3126
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3127 static const char l1_icache_str[] = "l1-icache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3128 static const char l1_dcache_str[] = "l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3129 static const char l2_cache_str[] = "l2-cache";
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3130 static const char l3_cache_str[] = "l3-cache";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3131 static const char itlb4k_str[] = "itlb-4K";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3132 static const char dtlb4k_str[] = "dtlb-4K";
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3133 static const char itlb2M_str[] = "itlb-2M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3134 static const char itlb4M_str[] = "itlb-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3135 static const char dtlb4M_str[] = "dtlb-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3136 static const char dtlb24_str[] = "dtlb0-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3137 static const char itlb424_str[] = "itlb-4K-2M-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3138 static const char itlb24_str[] = "itlb-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3139 static const char dtlb44_str[] = "dtlb-4K-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3140 static const char sl1_dcache_str[] = "sectored-l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3141 static const char sl2_cache_str[] = "sectored-l2-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3142 static const char itrace_str[] = "itrace-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3143 static const char sl3_cache_str[] = "sectored-l3-cache";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3144 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3145
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3146 static const struct cachetab {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3147 uint8_t ct_code;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3148 uint8_t ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3149 uint16_t ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3150 size_t ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3151 const char *ct_label;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3152 } intel_ctab[] = {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3153 /*
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3154 * maintain descending order!
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3155 *
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3156 * Codes ignored - Reason
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3157 * ----------------------
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3158 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3159 * f0H/f1H - Currently we do not interpret prefetch size by design
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3160 */
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3161 { 0xe4, 16, 64, 810241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3162 { 0xe3, 16, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3163 { 0xe2, 16, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3164 { 0xde, 12, 64, 610241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3165 { 0xdd, 12, 64, 310241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3166 { 0xdc, 12, 64, ((110241024)+(512*1024)), l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3167 { 0xd8, 8, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3168 { 0xd7, 8, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3169 { 0xd6, 8, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3170 { 0xd2, 4, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3171 { 0xd1, 4, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3172 { 0xd0, 4, 64, 512*1024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3173 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3174 { 0xc0, 4, 0, 8, dtlb44_str },
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3175 { 0xba, 4, 0, 64, dtlb4k_str },
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3176 { 0xb4, 4, 0, 256, dtlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3177 { 0xb3, 4, 0, 128, dtlb4k_str },
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3178 { 0xb2, 4, 0, 64, itlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3179 { 0xb0, 4, 0, 128, itlb4k_str },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3180 { 0x87, 8, 64, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3181 { 0x86, 4, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3182 { 0x85, 8, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3183 { 0x84, 8, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3184 { 0x83, 8, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3185 { 0x82, 8, 32, 256*1024, l2_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3186 { 0x80, 8, 64, 512*1024, l2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3187 { 0x7f, 2, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3188 { 0x7d, 8, 64, 210241024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3189 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3190 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3191 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3192 { 0x79, 8, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3193 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3194 { 0x73, 8, 0, 64*1024, itrace_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3195 { 0x72, 8, 0, 32*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3196 { 0x71, 8, 0, 16*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3197 { 0x70, 8, 0, 12*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3198 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3199 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3200 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3201 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3202 { 0x5d, 0, 0, 256, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3203 { 0x5c, 0, 0, 128, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3204 { 0x5b, 0, 0, 64, dtlb44_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3205 { 0x5a, 4, 0, 32, dtlb24_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3206 { 0x59, 0, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3207 { 0x57, 4, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3208 { 0x56, 4, 0, 16, dtlb4M_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3209 { 0x55, 0, 0, 7, itlb24_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3210 { 0x52, 0, 0, 256, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3211 { 0x51, 0, 0, 128, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3212 { 0x50, 0, 0, 64, itlb424_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3213 { 0x4f, 0, 0, 32, itlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3214 { 0x4e, 24, 64, 610241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3215 { 0x4d, 16, 64, 1610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3216 { 0x4c, 12, 64, 1210241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3217 { 0x4b, 16, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3218 { 0x4a, 12, 64, 610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3219 { 0x49, 16, 64, 410241024, l3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3220 { 0x48, 12, 64, 310241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3221 { 0x47, 8, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3222 { 0x46, 4, 64, 410241024, l3_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3223 { 0x45, 4, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3224 { 0x44, 4, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3225 { 0x43, 4, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3226 { 0x42, 4, 32, 256*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3227 { 0x41, 4, 32, 128*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3228 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3229 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3230 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3231 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3232 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3233 { 0x39, 4, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3234 { 0x30, 8, 64, 32*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3235 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3236 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3237 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3238 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3239 { 0x22, 4, 64, 512*1024, sl3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3240 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3241 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3242 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3243 { 0x0b, 4, 0, 4, itlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3244 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3245 { 0x08, 4, 32, 16*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3246 { 0x06, 4, 32, 8*1024, l1_icache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3247 { 0x05, 4, 0, 32, dtlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3248 { 0x04, 4, 0, 8, dtlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3249 { 0x03, 4, 0, 64, dtlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3250 { 0x02, 4, 0, 2, itlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3251 { 0x01, 4, 0, 32, itlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3252 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3253 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3254
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3255 static const struct cachetab cyrix_ctab[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3256 { 0x70, 4, 0, 32, "tlb-4K" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3257 { 0x80, 4, 16, 16*1024, "l1-cache" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3258 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3259 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3260
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3261 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3262 * Search a cache table for a matching entry
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3263 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3264 static const struct cachetab *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3265 find_cacheent(const struct cachetab *ct, uint_t code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3266 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3267 if (code != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3268 for (; ct->ct_code != 0; ct++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3269 if (ct->ct_code <= code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3270 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3271 if (ct->ct_code == code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3272 return (ct);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3273 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3274 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3275 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3276
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3277 /*
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3278 * Populate cachetab entry with L2 or L3 cache-information using
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3279 * cpuid function 4. This function is called from intel_walk_cacheinfo()
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3280 * when descriptor 0x49 is encountered. It returns 0 if no such cache
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3281 * information is found.
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3282 */
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3283 static int
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3284 intel_cpuid_4_cache_info(struct cachetab ct, struct cpuid_info cpi)
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3285 {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3286 uint32_t level, i;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3287 int ret = 0;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3288
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3289 for (i = 0; i < cpi->cpi_std_4_size; i++) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3290 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3291
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3292 if (level == 2 \|\| level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3293 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3294 ct->ct_line_size =
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3295 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3296 ct->ct_size = ct->ct_assoc *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3297 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3298 ct->ct_line_size *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3299 (cpi->cpi_std_4[i]->cp_ecx + 1);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3300
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3301 if (level == 2) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3302 ct->ct_label = l2_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3303 } else if (level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3304 ct->ct_label = l3_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3305 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3306 ret = 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3307 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3308 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3309
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3310 return (ret);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3311 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3312
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3313 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3314 * Walk the cacheinfo descriptor, applying 'func' to every valid element
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3315 * The walk is terminated if the walker returns non-zero.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3316 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3317 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3318 intel_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3319 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3320 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3321 const struct cachetab *ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3322 struct cachetab des_49_ct, des_b1_ct;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3323 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3324 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3325
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3326 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3327 return;
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3328 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3329 /*
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3330 * For overloaded descriptor 0x49 we use cpuid function 4
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3331 * if supported by the current processor, to create
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3332 * cache information.
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3333 * For overloaded descriptor 0xb1 we use X86_PAE flag
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3334 * to disambiguate the cache information.
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3335 */
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3336 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3337 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3338 ct = &des_49_ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3339 } else if (*dp == 0xb1) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3340 des_b1_ct.ct_code = 0xb1;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3341 des_b1_ct.ct_assoc = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3342 des_b1_ct.ct_line_size = 0;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3343 if (x86_feature & X86_PAE) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3344 des_b1_ct.ct_size = 8;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3345 des_b1_ct.ct_label = itlb2M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3346 } else {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3347 des_b1_ct.ct_size = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3348 des_b1_ct.ct_label = itlb4M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3349 }
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3350 ct = &des_b1_ct;
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3351 } else {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3352 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3353 continue;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3354 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3355 }
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3356
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3357 if (func(arg, ct) != 0) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3358 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3359 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3360 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3361 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3362
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3363 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3364 * (Like the Intel one, except for Cyrix CPUs)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3365 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3366 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3367 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3368 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3369 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3370 const struct cachetab *ct;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3371 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3372 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3373
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3374 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3375 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3376 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3377 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3378 * Search Cyrix-specific descriptor table first ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3379 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3380 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3381 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3382 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3383 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3384 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3385 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3386 * .. else fall back to the Intel one
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3387 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3388 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3389 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3390 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3391 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3392 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3393 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3394 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3395
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3396 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3397 * A cacheinfo walker that adds associativity, line-size, and size properties
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3398 * to the devinfo node it is passed as an argument.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3399 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3400 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3401 add_cacheent_props(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3402 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3403 dev_info_t *devi = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3404
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3405 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3406 if (ct->ct_line_size != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3407 add_cache_prop(devi, ct->ct_label, line_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3408 ct->ct_line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3409 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3410 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3411 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3412
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3413
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3414 static const char fully_assoc[] = "fully-associative?";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3415
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3416 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3417 * AMD style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3418 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3419 * Extended functions 5 and 6 directly describe properties of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3420 * tlbs and various cache levels.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3421 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3422 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3423 add_amd_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3424 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3425 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3426 case 0: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3427 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3428 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3429 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3430 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3431 case 0xff:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3432 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3433 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3434 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3435 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3436
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3437 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3438 add_amd_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3439 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3440 if (size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3441 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3442 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3443 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3444 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3445
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3446 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3447 add_amd_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3448 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3449 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3450 if (size == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3451 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3452 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3453 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3454 * Most AMD parts have a sectored cache. Multiple cache lines are
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3455 * associated with each tag. A sector consists of all cache lines
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3456 * associated with a tag. For example, the AMD K6-III has a sector
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3457 * size of 2 cache lines per tag.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3458 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3459 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3460 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3461 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3462 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3463 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3464
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3465 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3466 add_amd_l2_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3467 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3468 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3469 case 0: /* off */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3470 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3471 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3472 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3473 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3474 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3475 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3476 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3477 add_cache_prop(devi, label, assoc_str, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3478 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3479 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3480 add_cache_prop(devi, label, assoc_str, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3481 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3482 case 0xf:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3483 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3484 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3485 default: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3486 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3487 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3488 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3489
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3490 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3491 add_amd_l2_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3492 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3493 if (size == 0 \|\| assoc == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3494 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3495 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3496 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3497 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3498
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3499 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3500 add_amd_l2_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3501 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3502 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3503 if (size == 0 \|\| assoc == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3504 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3505 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3506 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3507 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3508 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3509 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3510 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3511
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3512 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3513 amd_cache_info(struct cpuid_info cpi, dev_info_t devi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3514 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3515 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3516
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3517 if (cpi->cpi_xmaxeax < 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3518 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3519 cp = &cpi->cpi_extd[5];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3520
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3521 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3522 * 4M/2M L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3523 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3524 * We report the size for 2M pages because AMD uses two
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3525 * TLB entries for one 4M page.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3526 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3527 add_amd_tlb(devi, "dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3528 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3529 add_amd_tlb(devi, "itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3530 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3531
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3532 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3533 * 4K L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3534 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3535
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3536 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3537 uint_t nentries;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3538 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3539 if (cpi->cpi_family >= 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3540 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3541 * Crusoe processors have 256 TLB entries, but
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3542 * cpuid data format constrains them to only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3543 * reporting 255 of them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3544 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3545 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3546 nentries = 256;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3547 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3548 * Crusoe processors also have a unified TLB
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3549 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3550 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3551 nentries);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3552 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3553 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3554 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3555 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3556 add_amd_tlb(devi, itlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3557 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3558 add_amd_tlb(devi, dtlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3559 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3560 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3561 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3562
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3563 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3564 * data L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3565 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3566
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3567 add_amd_cache(devi, l1_dcache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3568 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3569 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3570
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3571 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3572 * code L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3573 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3574
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3575 add_amd_cache(devi, l1_icache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3576 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3577 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3578
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3579 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3580 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3581 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3582
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3583 /* Check for a unified L2 TLB for large pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3584
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3585 if (BITX(cp->cp_eax, 31, 16) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3586 add_amd_l2_tlb(devi, "l2-tlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3587 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3588 else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3589 add_amd_l2_tlb(devi, "l2-dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3590 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3591 add_amd_l2_tlb(devi, "l2-itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3592 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3593 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3594
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3595 /* Check for a unified L2 TLB for 4K pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3596
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3597 if (BITX(cp->cp_ebx, 31, 16) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3598 add_amd_l2_tlb(devi, "l2-tlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3599 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3600 } else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3601 add_amd_l2_tlb(devi, "l2-dtlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3602 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3603 add_amd_l2_tlb(devi, "l2-itlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3604 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3605 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3606
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3607 add_amd_l2_cache(devi, l2_cache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3608 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3609 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3610 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3611
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3612 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3613 * There are two basic ways that the x86 world describes it cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3614 * and tlb architecture - Intel's way and AMD's way.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3615 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3616 * Return which flavor of cache architecture we should use
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3617 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3618 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3619 x86_which_cacheinfo(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3620 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3621 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3622 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3623 if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3624 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3625 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3626 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3627 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3628 * The K5 model 1 was the first part from AMD that reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3629 * cache sizes via extended cpuid functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3630 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3631 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3632 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3633 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3634 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3635 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3636 if (cpi->cpi_family >= 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3637 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3638 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3639 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3640 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3641 * If they have extended CPU data for 0x80000005
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3642 * then we assume they have AMD-format cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3643 * information.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3644 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3645 * If not, and the vendor happens to be Cyrix,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3646 * then try our-Cyrix specific handler.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3647 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3648 * If we're not Cyrix, then assume we're using Intel's
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3649 * table-driven format instead.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3650 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3651 if (cpi->cpi_xmaxeax >= 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3652 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3653 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3654 return (X86_VENDOR_Cyrix);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3655 else if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3656 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3657 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3658 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3659 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3660 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3661
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3662 void
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3663 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3664 struct cpuid_info *cpi)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3665 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3666 dev_info_t *cpu_devi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3667 int create;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3668
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3669 cpu_devi = (dev_info_t *)dip;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3670
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3671 /* device_type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3672 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3673 "device_type", "cpu");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3674
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3675 /* reg */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3676 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3677 "reg", cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3678
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3679 /* cpu-mhz, and clock-frequency */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3680 if (cpu_freq > 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3681 long long mul;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3682
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3683 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3684 "cpu-mhz", cpu_freq);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3685 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3686 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3687 "clock-frequency", (int)mul);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3688 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3689
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3690 if ((x86_feature & X86_CPUID) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3691 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3692 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3693
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3694 /* vendor-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3695 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3696 "vendor-id", cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3697
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3698 if (cpi->cpi_maxeax == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3699 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3700 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3701
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3702 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3703 * family, model, and step
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3704 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3705 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3706 "family", CPI_FAMILY(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3707 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3708 "cpu-model", CPI_MODEL(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3709 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3710 "stepping-id", CPI_STEP(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3711
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3712 /* type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3713 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3714 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3715 create = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3716 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3717 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3718 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3719 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3720 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3721 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3722 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3723 "type", CPI_TYPE(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3724
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3725 /* ext-family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3726 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3727 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3728 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3729 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3730 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3731 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3732 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3733 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3734 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3735 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3736 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3737 "ext-family", CPI_FAMILY_XTD(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3738
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3739 /* ext-model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3740 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3741 case X86_VENDOR_Intel:
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	3742 create = IS_EXTENDED_MODEL_INTEL(cpi);
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	3743 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3744 case X86_VENDOR_AMD:
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3745 create = CPI_FAMILY(cpi) == 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3746 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3747 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3748 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3749 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3750 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3751 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3752 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3753 "ext-model", CPI_MODEL_XTD(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3754
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3755 /* generation */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3756 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3757 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3758 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3759 * AMD K5 model 1 was the first part to support this
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3760 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3761 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3762 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3763 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3764 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3765 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3766 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3767 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3768 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3769 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3770
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3771 /* brand-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3772 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3773 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3774 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3775 * brand id first appeared on Pentium III Xeon model 8,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3776 * and Celeron model 8 processors and Opteron
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3777 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3778 create = cpi->cpi_family > 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3779 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3780 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3781 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3782 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3783 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3784 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3785 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3786 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3787 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3788 if (create && cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3789 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3790 "brand-id", cpi->cpi_brandid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3791 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3792
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3793 /* chunks, and apic-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3794 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3795 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3796 * first available on Pentium IV and Opteron (K8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3797 */
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3798 case X86_VENDOR_Intel:
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3799 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3800 break;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3801 case X86_VENDOR_AMD:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3802 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3803 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3804 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3805 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3806 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3807 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3808 if (create) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3809 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3810 "chunks", CPI_CHUNKS(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3811 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	3812 "apic-id", cpi->cpi_apicid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3813 if (cpi->cpi_chipid >= 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3814 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3815 "chip#", cpi->cpi_chipid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3816 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3817 "clog#", cpi->cpi_clogid);
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	3818 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3819 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3820
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3821 /* cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3822 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3823 "cpuid-features", CPI_FEATURES_EDX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3824
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3825
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3826 /* cpuid-features-ecx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3827 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3828 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3829 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3830 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3831 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3832 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3833 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3834 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3835 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3836 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3837 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3838
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3839 /* ext-cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3840 switch (cpi->cpi_vendor) {
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3841 case X86_VENDOR_Intel:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3842 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3843 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3844 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3845 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3846 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3847 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3848 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3849 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3850 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3851 }
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3852 if (create) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3853 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3854 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3855 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3856 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	3857 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3858
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3859 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3860 * Brand String first appeared in Intel Pentium IV, AMD K5
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3861 * model 1, and Cyrix GXm. On earlier models we try and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3862 * simulate something similar .. so this string should always
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3863 * same -something- about the processor, however lame.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3864 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3865 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3866 "brand-string", cpi->cpi_brandstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3867
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3868 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3869 * Finally, cache and tlb information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3870 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3871 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3872 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3873 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3874 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3875 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3876 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3877 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3878 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3879 amd_cache_info(cpi, cpu_devi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3880 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3881 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3882 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3883 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3884 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3885
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3886 struct l2info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3887 int *l2i_csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3888 int *l2i_lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3889 int *l2i_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3890 int l2i_ret;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3891 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3892
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3893 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3894 * A cacheinfo walker that fetches the size, line-size and associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3895 * of the L2 cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3896 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3897 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3898 intel_l2cinfo(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3899 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3900 struct l2info *l2i = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3901 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3902
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3903 if (ct->ct_label != l2_cache_str &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3904 ct->ct_label != sl2_cache_str)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3905 return (0); /* not an L2 -- keep walking */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3906
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3907 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3908 *ip = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3909 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3910 *ip = ct->ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3911 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3912 *ip = ct->ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3913 l2i->l2i_ret = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3914 return (1); /* was an L2 -- terminate walk */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3915 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3916
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3917 /*
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3918 * AMD L2/L3 Cache and TLB Associativity Field Definition:
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3919 *
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3920 * Unlike the associativity for the L1 cache and tlb where the 8 bit
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3921 * value is the associativity, the associativity for the L2 cache and
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3922 * tlb is encoded in the following table. The 4 bit L2 value serves as
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3923 * an index into the amd_afd[] array to determine the associativity.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3924 * -1 is undefined. 0 is fully associative.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3925 */
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3926
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3927 static int amd_afd[] =
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3928 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3929
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3930 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3931 amd_l2cacheinfo(struct cpuid_info cpi, struct l2info l2i)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3932 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3933 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3934 uint_t size, assoc;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3935 int i;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3936 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3937
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3938 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3939 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3940 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3941
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3942 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3943 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3944 uint_t cachesz = size * 1024;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3945 assoc = amd_afd[i];
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3946
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	3947 ASSERT(assoc != -1);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3948
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3949 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3950 *ip = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3951 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3952 *ip = BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3953 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3954 *ip = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3955 l2i->l2i_ret = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3956 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3957 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3958
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3959 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3960 getl2cacheinfo(cpu_t cpu, int csz, int lsz, int assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3961 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3962 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3963 struct l2info __l2info, *l2i = &__l2info;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3964
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3965 l2i->l2i_csz = csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3966 l2i->l2i_lsz = lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3967 l2i->l2i_assoc = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3968 l2i->l2i_ret = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3969
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3970 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3971 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3972 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3973 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3974 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3975 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3976 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3977 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3978 amd_l2cacheinfo(cpi, l2i);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3979 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3980 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3981 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3982 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3983 return (l2i->l2i_ret);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3984 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3985
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	3986 #if !defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	3987
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3988 uint32_t *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3989 cpuid_mwait_alloc(cpu_t *cpu)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3990 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3991 uint32_t *ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3992 size_t mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3993
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	3994 ASSERT(cpuid_checkpass(CPU, 2));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	3995
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	3996 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3997 if (mwait_size == 0)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3998 return (NULL);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	3999
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4000 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4001 * kmem_alloc() returns cache line size aligned data for mwait_size
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4002 * allocations. mwait_size is currently cache line sized. Neither
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4003 * of these implementation details are guarantied to be true in the
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4004 * future.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4005 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4006 * First try allocating mwait_size as kmem_alloc() currently returns
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4007 * correctly aligned memory. If kmem_alloc() does not return
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4008 * mwait_size aligned memory, then use mwait_size ROUNDUP.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4009 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4010 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4011 * decide to free this memory.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4012 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4013 ret = kmem_zalloc(mwait_size, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4014 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4015 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4016 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4017 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4018 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4019 } else {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4020 kmem_free(ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4021 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4022 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4023 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4024 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4025 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4026 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4027 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4028 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4029
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4030 void
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4031 cpuid_mwait_free(cpu_t *cpu)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4032 {
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4033 if (cpu->cpu_m.mcpu_cpi == NULL) {
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4034 return;
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4035 }
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4036
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4037 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4038 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4039 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4040 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4041 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4042
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4043 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4044 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4045 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4046
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4047 void
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4048 patch_tsc_read(int flag)
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4049 {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4050 size_t cnt;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	4051
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4052 switch (flag) {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4053 case X86_NO_TSC:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4054 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4055 (void) memcpy((void )tsc_read, (void )&_no_rdtsc_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4056 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4057 case X86_HAVE_TSCP:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4058 cnt = &_tscp_end - &_tscp_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4059 (void) memcpy((void )tsc_read, (void )&_tscp_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4060 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4061 case X86_TSC_MFENCE:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4062 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4063 (void) memcpy((void *)tsc_read,
fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4064 (void *)&_tsc_mfence_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4065 break;
6642 c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4066 case X86_TSC_LFENCE:
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4067 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4068 (void) memcpy((void *)tsc_read,
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4069 (void *)&_tsc_lfence_start, cnt);
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4070 break;
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4071 default:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4072 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4073 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4074 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4075
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4076 int
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4077 cpuid_deep_cstates_supported(void)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4078 {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4079 struct cpuid_info *cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4080 struct cpuid_regs regs;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4081
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4082 ASSERT(cpuid_checkpass(CPU, 1));
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4083
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4084 cpi = CPU->cpu_m.mcpu_cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4085
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4086 if (!(x86_feature & X86_CPUID))
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4087 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4088
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4089 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4090 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4091 if (cpi->cpi_xmaxeax < 0x80000007)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4092 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4093
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4094 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4095 * TSC run at a constant rate in all ACPI C-states?
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4096 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4097 regs.cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4098 (void) __cpuid_insn(&regs);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4099 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4100
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4101 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4102 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4103 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4104 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4105
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4106 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4107
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4108 void
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4109 post_startup_cpu_fixups(void)
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4110 {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4111 #ifndef __xpv
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4112 /*
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4113 * Some AMD processors support C1E state. Entering this state will
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4114 * cause the local APIC timer to stop, which we can't deal with at
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4115 * this time.
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4116 */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4117 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4118 on_trap_data_t otd;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4119 uint64_t reg;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4120
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4121 if (!on_trap(&otd, OT_DATA_ACCESS)) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4122 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4123 /* Disable C1E state if it is enabled by BIOS */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4124 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4125 AMD_ACTONCMPHALT_MASK) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4126 reg &= ~(AMD_ACTONCMPHALT_MASK <<
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4127 AMD_ACTONCMPHALT_SHIFT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4128 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4129 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4130 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4131 no_trap();
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4132 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4133 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4134 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4135
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4136 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4137 * Starting with the Westmere processor the local
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4138 * APIC timer will continue running in all C-states,
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4139 * including the deepest C-states.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4140 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4141 int
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4142 cpuid_arat_supported(void)
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4143 {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4144 struct cpuid_info *cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4145 struct cpuid_regs regs;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4146
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4147 ASSERT(cpuid_checkpass(CPU, 1));
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4148 ASSERT(x86_feature & X86_CPUID);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4149
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4150 cpi = CPU->cpu_m.mcpu_cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4151
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4152 switch (cpi->cpi_vendor) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4153 case X86_VENDOR_Intel:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4154 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4155 * Always-running Local APIC Timer is
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4156 * indicated by CPUID.6.EAX[2].
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4157 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4158 if (cpi->cpi_maxeax >= 6) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4159 regs.cp_eax = 6;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4160 (void) cpuid_insn(NULL, &regs);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4161 return (regs.cp_eax & CPUID_CSTATE_ARAT);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4162 } else {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4163 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4164 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4165 default:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4166 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4167 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4168 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4169
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4170 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4171 * Check support for Intel ENERGY_PERF_BIAS feature
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4172 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4173 int
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4174 cpuid_iepb_supported(struct cpu *cp)
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4175 {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4176 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4177 struct cpuid_regs regs;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4178
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4179 ASSERT(cpuid_checkpass(cp, 1));
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4180
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4181 if (!(x86_feature & X86_CPUID) \|\| !(x86_feature & X86_MSR)) {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4182 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4183 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4184
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4185 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4186 * Intel ENERGY_PERF_BIAS MSR is indicated by
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4187 * capability bit CPUID.6.ECX.3
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4188 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4189 if ((cpi->cpi_vendor != X86_VENDOR_Intel) \|\| (cpi->cpi_maxeax < 6))
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4190 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4191
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4192 regs.cp_eax = 0x6;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4193 (void) cpuid_insn(NULL, &regs);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4194 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4195 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4196
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4197 #if defined(__amd64) && !defined(__xpv)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4198 /*
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4199 * Patch in versions of bcopy for high performance Intel Nhm processors
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4200 * and later...
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4201 */
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4202 void
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4203 patch_memops(uint_t vendor)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4204 {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4205 size_t cnt, i;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4206 caddr_t to, from;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4207
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4208 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4209 cnt = &bcopy_patch_end - &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4210 to = &bcopy_ck_size;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4211 from = &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4212 for (i = 0; i < cnt; i++) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4213 to++ = from++;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4214 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4215 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4216 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4217 #endif /* __amd64 && !__xpv */
12261 52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4218
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4219 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4220 * This function finds the number of bits to represent the number of cores per
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4221 * chip and the number of strands per core for the Intel platforms.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4222 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4223 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4224 void
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4225 cpuid_get_ext_topo(uint_t vendor, uint_t core_nbits, uint_t strand_nbits)
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4226 {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4227 struct cpuid_regs regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4228 struct cpuid_regs *cp = &regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4229
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4230 if (vendor != X86_VENDOR_Intel) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4231 return;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4232 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4233
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4234 /* if the cpuid level is 0xB, extended topo is available. */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4235 cp->cp_eax = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4236 if (__cpuid_insn(cp) >= 0xB) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4237
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4238 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4239 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4240 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4241
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4242 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4243 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4244 * indicates that the extended topology enumeration leaf is
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4245 * available.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4246 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4247 if (cp->cp_ebx) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4248 uint_t coreid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4249 uint_t chipid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4250 uint_t i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4251 uint_t level;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4252
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4253 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4254 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4255 cp->cp_ecx = i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4256
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4257 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4258 level = CPI_CPU_LEVEL_TYPE(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4259
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4260 if (level == 1) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4261 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4262 * Thread level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4263 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4264 * to get the coreid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4265 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4266 coreid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4267 } else if (level == 2) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4268 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4269 * Core level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4270 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4271 * to get the chipid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4272 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4273 chipid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4274 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4275 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4276
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4277 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4278 *strand_nbits = coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4279 *core_nbits = chipid_shift - coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4280 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4281 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4282 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4283 }

Mercurial > illumos > illumos-gate

annotate usr/src/uts/i86pc/os/cpuid.c @ 12726:8f2fba7fcf9c