illumos/illumos-gate: usr/src/uts/i86pc/os/cpuid.c annotate

annotate usr/src/uts/i86pc/os/cpuid.c @ 13148:67d1861e02c1 onnv_147

6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset

author	Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
date	Mon, 16 Aug 2010 22:47:01 -0700
parents	8315ff49e22e
children	8640246a3548

rev	line source
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2 * CDDL HEADER START
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4 * The contents of this file are subject to the terms of the
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	5 * Common Development and Distribution License (the "License").
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	6 * You may not use this file except in compliance with the License.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	7 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	9 * or http://www.opensolaris.org/os/licensing.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	10 * See the License for the specific language governing permissions
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	11 * and limitations under the License.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	12 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	13 * When distributing Covered Code, include this CDDL HEADER in each
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	15 * If applicable, add the following below this CDDL HEADER, with the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	16 * fields enclosed by brackets "[]" replaced with your own identifying
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	17 * information: Portions Copyright [yyyy] [name of copyright owner]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	18 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	19 * CDDL HEADER END
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	20 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	21 /*
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	23 */
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	24 /*
13041 2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	25 * Copyright (c) 2010, Intel Corporation.
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	26 * All rights reserved.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	27 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	28 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	29 * Portions Copyright 2009 Advanced Micro Devices, Inc.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	30 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	31
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	32 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	33 * Various routines to handle identification
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	34 * and classification of x86 processors.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	35 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	36
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	37 #include <sys/types.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	38 #include <sys/archsystm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	39 #include <sys/x86_archext.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	40 #include <sys/kmem.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	41 #include <sys/systm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	42 #include <sys/cmn_err.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	43 #include <sys/sunddi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	44 #include <sys/sunndi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	45 #include <sys/cpuvar.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	46 #include <sys/processor.h>
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	47 #include <sys/sysmacros.h>
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	48 #include <sys/pg.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	49 #include <sys/fp.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	50 #include <sys/controlregs.h>
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	51 #include <sys/bitmap.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	52 #include <sys/auxv_386.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	53 #include <sys/memnode.h>
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	54 #include <sys/pci_cfgspace.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	55
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	56 #ifdef __xpv
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	57 #include <sys/hypervisor.h>
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	58 #else
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	59 #include <sys/ontrap.h>
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	60 #endif
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	61
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	62 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	63 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	64 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	65 * them accordingly. For most modern processors, feature detection occurs here
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	66 * in pass 1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	67 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	68 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	69 * for the boot CPU and does the basic analysis that the early kernel needs.
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	70 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	71 * CPU.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	72 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	73 * Pass 1 includes:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	74 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	75 * o Determining vendor/model/family/stepping and setting x86_type and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	76 * x86_vendor accordingly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	77 * o Processing the feature flags returned by the cpuid instruction while
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	78 * applying any workarounds or tricks for the specific processor.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	79 * o Mapping the feature flags into Solaris feature bits (X86_*).
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	80 * o Processing extended feature flags if supported by the processor,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	81 * again while applying specific processor knowledge.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	82 * o Determining the CMT characteristics of the system.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	83 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	84 * Pass 1 is done on non-boot CPUs during their initialization and the results
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	85 * are used only as a meager attempt at ensuring that all processors within the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	86 * system support the same features.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	87 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	88 * Pass 2 of cpuid feature analysis happens just at the beginning
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	89 * of startup(). It just copies in and corrects the remainder
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	90 * of the cpuid data we depend on: standard cpuid functions that we didn't
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	91 * need for pass1 feature analysis, and extended cpuid functions beyond the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	92 * simple feature processing done in pass1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	93 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	94 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	95 * particular kernel memory allocation has been made available. It creates a
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	96 * readable brand string based on the data collected in the first two passes.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	97 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	98 * Pass 4 of cpuid analysis is invoked after post_startup() when all
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	99 * the support infrastructure for various hardware features has been
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	100 * initialized. It determines which processor features will be reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	101 * to userland via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	102 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	103 * All passes are executed on all CPUs, but only the boot CPU determines what
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	104 * features the kernel will use.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	105 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	106 * Much of the worst junk in this file is for the support of processors
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	107 * that didn't really implement the cpuid instruction properly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	108 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	109 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	110 * the pass numbers. Accordingly, changes to the pass code may require changes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	111 * to the accessor code.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	112 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	113
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	114 uint_t x86_vendor = X86_VENDOR_IntelClone;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	115 uint_t x86_type = X86_TYPE_OTHER;
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	116 uint_t x86_clflush_size = 0;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	117
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	118 uint_t pentiumpro_bug4046376;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	119 uint_t pentiumpro_bug4064495;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	120
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	121 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	122
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	123 static char *x86_feature_names[NUM_X86_FEATURES] = {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	124 "lgpg",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	125 "tsc",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	126 "msr",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	127 "mtrr",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	128 "pge",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	129 "de",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	130 "cmov",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	131 "mmx",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	132 "mca",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	133 "pae",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	134 "cv8",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	135 "pat",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	136 "sep",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	137 "sse",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	138 "sse2",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	139 "htt",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	140 "asysc",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	141 "nx",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	142 "sse3",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	143 "cx16",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	144 "cmp",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	145 "tscp",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	146 "mwait",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	147 "sse4a",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	148 "cpuid",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	149 "ssse3",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	150 "sse4_1",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	151 "sse4_2",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	152 "1gpg",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	153 "clfsh",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	154 "64",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	155 "aes",
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	156 "pclmulqdq",
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	157 "xsave",
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	158 "avx" };
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	159
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	160 boolean_t
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	161 is_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	162 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	163 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	164 return (BT_TEST((ulong_t *)featureset, feature));
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	165 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	166
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	167 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	168 add_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	169 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	170 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	171 BT_SET((ulong_t *)featureset, feature);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	172 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	173
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	174 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	175 remove_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	176 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	177 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	178 BT_CLEAR((ulong_t *)featureset, feature);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	179 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	180
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	181 boolean_t
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	182 compare_x86_featureset(void setA, void setB)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	183 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	184 /*
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	185 * We assume that the unused bits of the bitmap are always zero.
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	186 */
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	187 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	188 return (B_TRUE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	189 } else {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	190 return (B_FALSE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	191 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	192 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	193
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	194 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	195 print_x86_featureset(void *featureset)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	196 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	197 uint_t i;
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	198
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	199 for (i = 0; i < NUM_X86_FEATURES; i++) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	200 if (is_x86_feature(featureset, i)) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	201 cmn_err(CE_CONT, "?x86_feature: %s\n",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	202 x86_feature_names[i]);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	203 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	204 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	205 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	206
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	207 uint_t enable486;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	208
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	209 static size_t xsave_state_size = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	210 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP \| XFEATURE_SSE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	211 boolean_t xsave_force_disable = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	212
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	213 /*
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	214 * This is set to platform type Solaris is running on.
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	215 */
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	216 static int platform_type = -1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	217
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	218 #if !defined(__xpv)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	219 /*
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	220 * Variable to patch if hypervisor platform detection needs to be
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	221 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	222 */
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	223 int enable_platform_detection = 1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	224 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	225
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	226 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	227 * monitor/mwait info.
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	228 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	229 * size_actual and buf_actual are the real address and size allocated to get
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	230 * proper mwait_buf alignement. buf_actual and size_actual should be passed
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	231 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	232 * processor cache-line alignment, but this is not guarantied in the furture.
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	233 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	234 struct mwait_info {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	235 size_t mon_min; /* min size to avoid missed wakeups */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	236 size_t mon_max; /* size to avoid false wakeups */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	237 size_t size_actual; /* size actually allocated */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	238 void buf_actual; / memory actually allocated */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	239 uint32_t support; /* processor support of monitor/mwait */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	240 };
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	241
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	242 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	243 * xsave/xrestor info.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	244 *
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	245 * This structure contains HW feature bits and size of the xsave save area.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	246 * Note: the kernel will use the maximum size required for all hardware
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	247 * features. It is not optimize for potential memory savings if features at
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	248 * the end of the save area are not enabled.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	249 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	250 struct xsave_info {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	251 uint32_t xsav_hw_features_low; /* Supported HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	252 uint32_t xsav_hw_features_high; /* Supported HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	253 size_t xsav_max_size; /* max size save area for HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	254 size_t ymm_size; /* AVX: size of ymm save area */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	255 size_t ymm_offset; /* AVX: offset for ymm save area */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	256 };
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	257
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	258
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	259 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	260 * These constants determine how many of the elements of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	261 * cpuid we cache in the cpuid_info data structure; the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	262 * remaining elements are accessible via the cpuid instruction.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	263 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	264
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	265 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	266 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	267
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	268 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	269 * Some terminology needs to be explained:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	270 * - Socket: Something that can be plugged into a motherboard.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	271 * - Package: Same as socket
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	272 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	273 * differently: there, chip is the same as processor node (below)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	274 * - Processor node: Some AMD processors have more than one
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	275 * "subprocessor" embedded in a package. These subprocessors (nodes)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	276 * are fully-functional processors themselves with cores, caches,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	277 * memory controllers, PCI configuration spaces. They are connected
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	278 * inside the package with Hypertransport links. On single-node
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	279 * processors, processor node is equivalent to chip/socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	280 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	281
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	282 struct cpuid_info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	283 uint_t cpi_pass; /* last pass completed */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	284 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	285 * standard function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	286 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	287 uint_t cpi_maxeax; /* fn 0: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	288 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	289 uint_t cpi_vendor; /* enum of cpi_vendorstr */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	290
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	291 uint_t cpi_family; /* fn 1: extended family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	292 uint_t cpi_model; /* fn 1: extended model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	293 uint_t cpi_step; /* fn 1: stepping */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	294 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	295 /* AMD: package/socket # */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	296 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	297 int cpi_clogid; /* fn 1: %ebx: thread # */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	298 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	299 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	300 uint_t cpi_ncache; /* fn 2: number of elements */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	301 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	302 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	303 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	304 struct cpuid_regs *cpi_std_4; / fn 4: %ecx == 0 .. fn4_size */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	305 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	306 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	307 * extended function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	308 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	309 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	310 char cpi_brandstr[49]; /* fn 0x8000000[234] */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	311 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	312 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	313 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	314
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	315 id_t cpi_coreid; /* same coreid => strands share core */
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	316 int cpi_pkgcoreid; /* core number within single package */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	317 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	318 /* Intel: fn 4: %eax[31-26] */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	319 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	320 * supported feature information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	321 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	322 uint32_t cpi_support[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	323 #define STD_EDX_FEATURES 0
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	324 #define AMD_EDX_FEATURES 1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	325 #define TM_EDX_FEATURES 2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	326 #define STD_ECX_FEATURES 3
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	327 #define AMD_ECX_FEATURES 4
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	328 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	329 * Synthesized information, where known.
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	330 */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	331 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	332 const char cpi_chiprevstr; / May be NULL if chiprev unknown */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	333 uint32_t cpi_socket; /* Chip package/socket type */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	334
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	335 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	336 uint32_t cpi_apicid;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	337 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	338 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	339 /* Intel: 1 */
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	340
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	341 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	342 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	343
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	344
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	345 static struct cpuid_info cpuid_info0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	346
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	347 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	348 * These bit fields are defined by the Intel Application Note AP-485
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	349 * "Intel Processor Identification and the CPUID Instruction"
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	350 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	351 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	352 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	353 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	354 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	355 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	356 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	357
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	358 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	359 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	360 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	361 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	362
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	363 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	364 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	365 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	366 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	367
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	368 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	369 #define CPI_XMAXEAX_MAX 0x80000100
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	370 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	371 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	372
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	373 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	374 * Function 4 (Deterministic Cache Parameters) macros
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	375 * Defined by Intel Application Note AP-485
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	376 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	377 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	378 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	379 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	380 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	381 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	382 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	383 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	384
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	385 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	386 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	387 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	388
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	389 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	390
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	391 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	392
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	393
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	394 /*
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	395 * A couple of shorthand macros to identify "later" P6-family chips
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	396 * like the Pentium M and Core. First, the "older" P6-based stuff
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	397 * (loosely defined as "pre-Pentium-4"):
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	398 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	399 */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	400
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	401 #define IS_LEGACY_P6(cpi) ( \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	402 cpi->cpi_family == 6 && \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	403 (cpi->cpi_model == 1 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	404 cpi->cpi_model == 3 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	405 cpi->cpi_model == 5 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	406 cpi->cpi_model == 6 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	407 cpi->cpi_model == 7 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	408 cpi->cpi_model == 8 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	409 cpi->cpi_model == 0xA \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	410 cpi->cpi_model == 0xB) \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	411 )
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	412
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	413 /* A "new F6" is everything with family 6 that's not the above */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	414 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	415
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	416 /* Extended family/model support */
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	417 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 \|\| \
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	418 cpi->cpi_family >= 0xf)
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	419
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	420 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	421 * Info for monitor/mwait idle loop.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	422 *
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	423 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	424 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	425 * 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	426 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	427 * Documentation Updates" #33633, Rev 2.05, December 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	428 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	429 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	430 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	431 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	432 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	433 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	434 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	435 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	436 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	437 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	438 * Number of sub-cstates for a given c-state.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	439 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	440 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	441 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	442
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	443 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	444 * XSAVE leaf 0xD enumeration
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	445 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	446 #define CPUID_LEAFD_2_YMM_OFFSET 576
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	447 #define CPUID_LEAFD_2_YMM_SIZE 256
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	448
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	449 /*
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	450 * Functions we consune from cpuid_subr.c; don't publish these in a header
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	451 * file to try and keep people using the expected cpuid_* interfaces.
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	452 */
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	453 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	454 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	455 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	456 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	457 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	458
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	459 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	460 * Apply up various platform-dependent restrictions where the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	461 * underlying platform restrictions mean the CPU can be marked
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	462 * as less capable than its cpuid instruction would imply.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	463 */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	464 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	465 static void
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	466 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	467 {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	468 switch (eax) {
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	469 case 1: {
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	470 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	471 0 : CPUID_INTC_EDX_MCA;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	472 cp->cp_edx &=
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	473 ~(mcamask \|
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	474 CPUID_INTC_EDX_PSE \|
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	475 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	476 CPUID_INTC_EDX_SEP \| CPUID_INTC_EDX_MTRR \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	477 CPUID_INTC_EDX_PGE \| CPUID_INTC_EDX_PAT \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	478 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	479 CPUID_INTC_EDX_PSE36 \| CPUID_INTC_EDX_HTT);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	480 break;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	481 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	482
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	483 case 0x80000001:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	484 cp->cp_edx &=
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	485 ~(CPUID_AMD_EDX_PSE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	486 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	487 CPUID_AMD_EDX_MTRR \| CPUID_AMD_EDX_PGE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	488 CPUID_AMD_EDX_PAT \| CPUID_AMD_EDX_PSE36 \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	489 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	490 CPUID_AMD_EDX_TSCP);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	491 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	492 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	493 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	494 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	495 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	496
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	497 switch (vendor) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	498 case X86_VENDOR_Intel:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	499 switch (eax) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	500 case 4:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	501 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	502 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	503 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	504 cp->cp_eax &= 0x03fffffff;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	505 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	506 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	507 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	508 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	509 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	510 case X86_VENDOR_AMD:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	511 switch (eax) {
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	512
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	513 case 0x80000001:
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	514 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	515 break;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	516
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	517 case 0x80000008:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	518 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	519 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	520 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	521 cp->cp_ecx &= 0xffffff00;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	522 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	523 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	524 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	525 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	526 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	527 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	528 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	529 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	530 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	531 #else
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	532 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	533 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	534
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	535 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	536 * Some undocumented ways of patching the results of the cpuid
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	537 * instruction to permit running Solaris 10 on future cpus that
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	538 * we don't currently support. Could be set to non-zero values
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	539 * via settings in eeprom.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	540 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	541
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	542 uint32_t cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	543 uint32_t cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	544 uint32_t cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	545 uint32_t cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	546
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	547 /*
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	548 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	549 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	550 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	551 cpuid_alloc_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	552 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	553 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	554 * By convention, cpu0 is the boot cpu, which is set up
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	555 * before memory allocation is available. All other cpus get
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	556 * their cpuid_info struct allocated here.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	557 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	558 ASSERT(cpu->cpu_id != 0);
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	559 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	560 cpu->cpu_m.mcpu_cpi =
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	561 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	562 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	563
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	564 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	565 cpuid_free_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	566 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	567 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	568 int i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	569
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	570 ASSERT(cpi != NULL);
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	571 ASSERT(cpi != &cpuid_info0);
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	572
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	573 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	574 * Free up any function 4 related dynamic storage
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	575 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	576 for (i = 1; i < cpi->cpi_std_4_size; i++)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	577 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	578 if (cpi->cpi_std_4_size > 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	579 kmem_free(cpi->cpi_std_4,
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	580 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	581
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	582 kmem_free(cpi, sizeof (*cpi));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	583 cpu->cpu_m.mcpu_cpi = NULL;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	584 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	585
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	586 #if !defined(__xpv)
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	587
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	588 static void
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	589 determine_platform()
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	590 {
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	591 struct cpuid_regs cp;
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	592 char *xen_str;
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	593 uint32_t xen_signature[4], base;
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	594
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	595 platform_type = HW_NATIVE;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	596
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	597 if (!enable_platform_detection)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	598 return;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	599
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	600 /*
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	601 * In a fully virtualized domain, Xen's pseudo-cpuid function
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	602 * returns a string representing the Xen signature in %ebx, %ecx,
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	603 * and %edx. %eax contains the maximum supported cpuid function.
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	604 * We need at least a (base + 2) leaf value to do what we want
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	605 * to do. Try different base values, since the hypervisor might
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	606 * use a different one depending on whether hyper-v emulation
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	607 * is switched on by default or not.
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	608 */
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	609 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	610 cp.cp_eax = base;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	611 (void) __cpuid_insn(&cp);
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	612 xen_signature[0] = cp.cp_ebx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	613 xen_signature[1] = cp.cp_ecx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	614 xen_signature[2] = cp.cp_edx;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	615 xen_signature[3] = 0;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	616 xen_str = (char *)xen_signature;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	617 if (strcmp("XenVMMXenVMM", xen_str) == 0 &&
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	618 cp.cp_eax >= (base + 2)) {
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	619 platform_type = HW_XEN_HVM;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	620 return;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	621 }
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	622 }
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	623
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	624 if (vmware_platform()) /* running under vmware hypervisor? */
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	625 platform_type = HW_VMWARE;
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	626 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	627
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	628 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	629 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	630 {
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	631 if (platform_type == -1)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	632 determine_platform();
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	633
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	634 return (platform_type);
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	635 }
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	636
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	637 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	638 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	639 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	640 return (0);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	641 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	642
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	643 #else
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	644
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	645 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	646 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	647 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	648 return (HW_XEN_PV);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	649 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	650
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	651 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	652 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	653 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	654 return (DOMAIN_IS_INITDOMAIN(xen_info));
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	655 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	656
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	657 #endif /* __xpv */
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	658
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	659 static void
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	660 cpuid_intel_getids(cpu_t cpu, void feature)
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	661 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	662 uint_t i;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	663 uint_t chipid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	664 uint_t coreid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	665 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	666
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	667 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	668 chipid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	669
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	670 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	671 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	672
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	673 if (is_x86_feature(feature, X86FSET_CMP)) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	674 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	675 * Multi-core (and possibly multi-threaded)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	676 * processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	677 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	678 uint_t ncpu_per_core;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	679 if (cpi->cpi_ncore_per_chip == 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	680 ncpu_per_core = cpi->cpi_ncpu_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	681 else if (cpi->cpi_ncore_per_chip > 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	682 ncpu_per_core = cpi->cpi_ncpu_per_chip /
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	683 cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	684 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	685 * 8bit APIC IDs on dual core Pentiums
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	686 * look like this:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	687 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	688 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	689 * \| Physical Package ID \| MC \| HT \|
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	690 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	691 * <------- chipid -------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	692 * <------- coreid --------------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	693 * <--- clogid -->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	694 * <------>
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	695 * pkgcoreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	696 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	697 * Where the number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	698 * represent MC and HT fields together equals
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	699 * to the minimum number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	700 * store the value of cpi->cpi_ncpu_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	701 * Of those bits, the MC part uses the number
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	702 * of bits necessary to store the value of
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	703 * cpi->cpi_ncore_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	704 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	705 for (i = 1; i < ncpu_per_core; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	706 coreid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	707 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	708 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	709 } else if (is_x86_feature(feature, X86FSET_HTT)) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	710 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	711 * Single-core multi-threaded processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	712 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	713 cpi->cpi_coreid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	714 cpi->cpi_pkgcoreid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	715 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	716 cpi->cpi_procnodeid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	717 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	718
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	719 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	720 cpuid_amd_getids(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	721 {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	722 int i, first_half, coreidsz;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	723 uint32_t nb_caps_reg;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	724 uint_t node2_1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	725 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	726
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	727 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	728 * AMD CMP chips currently have a single thread per core.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	729 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	730 * Since no two cpus share a core we must assign a distinct coreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	731 * per cpu, and we do this by using the cpu_id. This scheme does not,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	732 * however, guarantee that sibling cores of a chip will have sequential
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	733 * coreids starting at a multiple of the number of cores per chip -
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	734 * that is usually the case, but if the ACPI MADT table is presented
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	735 * in a different order then we need to perform a few more gymnastics
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	736 * for the pkgcoreid.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	737 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	738 * All processors in the system have the same number of enabled
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	739 * cores. Cores within a processor are always numbered sequentially
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	740 * from 0 regardless of how many or which are disabled, and there
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	741 * is no way for operating system to discover the real core id when some
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	742 * are disabled.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	743 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	744
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	745 cpi->cpi_coreid = cpu->cpu_id;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	746
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	747 if (cpi->cpi_xmaxeax >= 0x80000008) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	748
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	749 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	750
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	751 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	752 * In AMD parlance chip is really a node while Solaris
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	753 * sees chip as equivalent to socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	754 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	755 cpi->cpi_ncore_per_chip =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	756 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	757 if (coreidsz == 0) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	758 /* Use legacy method */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	759 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	760 coreidsz++;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	761 if (coreidsz == 0)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	762 coreidsz = 1;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	763 }
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	764 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	765 /* Assume single-core part */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	766 cpi->cpi_ncore_per_chip = 1;
12726 8f2fba7fcf9c 6957730 cpuid_amd_getids() uses uninitialized variable coreidsz Jakub Jermar <Jakub.Jermar@Sun.COM> parents: 12261 diff changeset	767 coreidsz = 1;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	768 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	769
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	770 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	771 cpi->cpi_apicid & ((1<<coreidsz) - 1);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	772 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	773
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	774 /* Get nodeID */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	775 if (cpi->cpi_family == 0xf) {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	776 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	777 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	778 } else if (cpi->cpi_family == 0x10) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	779 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	780 * See if we are a multi-node processor.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	781 * All processors in the system have the same number of nodes
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	782 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	783 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	784 if ((cpi->cpi_model < 8) \|\| BITX(nb_caps_reg, 29, 29) == 0) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	785 /* Single-node */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	786 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	787 coreidsz);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	788 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	789 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	790
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	791 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	792 * Multi-node revision D (2 nodes per package
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	793 * are supported)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	794 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	795 cpi->cpi_procnodes_per_pkg = 2;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	796
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	797 first_half = (cpi->cpi_pkgcoreid <=
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	798 (cpi->cpi_ncore_per_chip/2 - 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	799
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	800 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	801 /* We are BSP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	802 cpi->cpi_procnodeid = (first_half ? 0 : 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	803 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	804 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	805
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	806 /* We are AP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	807 /* NodeId[2:1] bits to use for reading F3xe8 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	808 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	809
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	810 nb_caps_reg =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	811 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	812
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	813 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	814 * Check IntNodeNum bit (31:30, but bit 31 is
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	815 * always 0 on dual-node processors)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	816 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	817 if (BITX(nb_caps_reg, 30, 30) == 0)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	818 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	819 !first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	820 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	821 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	822 first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	823
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	824 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	825 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	826 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	827 } else if (cpi->cpi_family >= 0x11) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	828 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	829 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	830 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	831 cpi->cpi_procnodeid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	832 cpi->cpi_chipid = cpi->cpi_procnodeid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	833 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	834 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	835
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	836 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	837 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	838 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	839 void
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	840 setup_xfem(void)
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	841 {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	842 uint64_t flags = XFEATURE_LEGACY_FP;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	843
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	844 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	845
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	846 if (is_x86_feature(x86_featureset, X86FSET_SSE))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	847 flags \|= XFEATURE_SSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	848
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	849 if (is_x86_feature(x86_featureset, X86FSET_AVX))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	850 flags \|= XFEATURE_AVX;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	851
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	852 set_xcr(XFEATURE_ENABLED_MASK, flags);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	853
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	854 xsave_bv_all = flags;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	855 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	856
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	857 void
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	858 cpuid_pass1(cpu_t cpu, uchar_t featureset)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	859 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	860 uint32_t mask_ecx, mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	861 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	862 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	863 int xcpuid;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	864 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	865 extern int idle_cpu_prefer_mwait;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	866 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	867
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	868 #if !defined(__xpv)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	869 determine_platform();
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	870 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	871 /*
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	872 * Space statically allocated for BSP, ensure pointer is set
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	873 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	874 if (cpu->cpu_id == 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	875 if (cpu->cpu_m.mcpu_cpi == NULL)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	876 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	877 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	878
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	879 add_x86_feature(featureset, X86FSET_CPUID);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	880
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	881 cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	882 ASSERT(cpi != NULL);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	883 cp = &cpi->cpi_std[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	884 cp->cp_eax = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	885 cpi->cpi_maxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	886 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	887 uint32_t iptr = (uint32_t )cpi->cpi_vendorstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	888 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	889 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	890 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	891 (char )&cpi->cpi_vendorstr[12] = '\0';
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	892 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	893
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	894 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	895 x86_vendor = cpi->cpi_vendor; /* for compatibility */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	896
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	897 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	898 * Limit the range in case of weird hardware
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	899 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	900 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	901 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	902 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	903 goto pass1_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	904
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	905 cp = &cpi->cpi_std[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	906 cp->cp_eax = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	907 (void) __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	908
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	909 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	910 * Extract identifying constants for easy access.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	911 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	912 cpi->cpi_model = CPI_MODEL(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	913 cpi->cpi_family = CPI_FAMILY(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	914
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	915 if (cpi->cpi_family == 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	916 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	917
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	918 /*
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	919 * Beware: AMD uses "extended model" iff base FAMILY == 0xf.
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	920 * Intel, and presumably everyone else, uses model == 0xf, as
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	921 * one would expect (max value means possible overflow). Sigh.
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	922 */
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	923
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	924 switch (cpi->cpi_vendor) {
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	925 case X86_VENDOR_Intel:
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	926 if (IS_EXTENDED_MODEL_INTEL(cpi))
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	927 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
4858 08409e2eed12 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint) ksadhukh parents: 4855 diff changeset	928 break;
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	929 case X86_VENDOR_AMD:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	930 if (CPI_FAMILY(cpi) == 0xf)
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	931 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	932 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	933 default:
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	934 if (cpi->cpi_model == 0xf)
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	935 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	936 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	937 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	938
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	939 cpi->cpi_step = CPI_STEP(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	940 cpi->cpi_brandid = CPI_BRANDID(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	941
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	942 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	943 * default assumptions:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	944 * - believe %edx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	945 * - ignore %ecx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	946 * - 32-bit virtual and physical addressing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	947 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	948 mask_edx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	949 mask_ecx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	950
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	951 cpi->cpi_pabits = cpi->cpi_vabits = 32;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	952
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	953 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	954 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	955 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	956 x86_type = X86_TYPE_P5;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	957 else if (IS_LEGACY_P6(cpi)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	958 x86_type = X86_TYPE_P6;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	959 pentiumpro_bug4046376 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	960 pentiumpro_bug4064495 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	961 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	962 * Clear the SEP bit when it was set erroneously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	963 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	964 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	965 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	966 } else if (IS_NEW_F6(cpi) \|\| cpi->cpi_family == 0xf) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	967 x86_type = X86_TYPE_P4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	968 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	969 * We don't currently depend on any of the %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	970 * features until Prescott, so we'll only check
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	971 * this from P4 onwards. We might want to revisit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	972 * that idea later.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	973 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	974 mask_ecx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	975 } else if (cpi->cpi_family > 0xf)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	976 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	977 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	978 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	979 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	980 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	981 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	982 mask_ecx &= ~CPUID_INTC_ECX_MON;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	983 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	984 case X86_VENDOR_IntelClone:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	985 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	986 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	987 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	988 #if defined(OPTERON_ERRATUM_108)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	989 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	990 cp->cp_eax = (0xf0f & cp->cp_eax) \| 0xc0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	991 cpi->cpi_model = 0xc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	992 } else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	993 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	994 if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	995 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	996 * AMD K5 and K6
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	997 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	998 * These CPUs have an incomplete implementation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	999 * of MCA/MCE which we mask away.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1000 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1001 mask_edx &= ~(CPUID_INTC_EDX_MCE \| CPUID_INTC_EDX_MCA);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1002
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1003 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1004 * Model 0 uses the wrong (APIC) bit
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1005 * to indicate PGE. Fix it here.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1006 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1007 if (cpi->cpi_model == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1008 if (cp->cp_edx & 0x200) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1009 cp->cp_edx &= ~0x200;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1010 cp->cp_edx \|= CPUID_INTC_EDX_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1011 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1012 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1013
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1014 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1015 * Early models had problems w/ MMX; disable.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1016 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1017 if (cpi->cpi_model < 6)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1018 mask_edx &= ~CPUID_INTC_EDX_MMX;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1019 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1020
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1021 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1022 * For newer families, SSE3 and CX16, at least, are valid;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1023 * enable all
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1024 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1025 if (cpi->cpi_family >= 0xf)
771 1c25a2120ec0 6327969 cpuid sse3 feature bit not noted on any AMD processor dmick parents: 359 diff changeset	1026 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1027 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1028 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1029 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1030 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1031 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1032 mask_ecx &= ~CPUID_INTC_ECX_MON;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1033
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1034 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1035 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1036 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1037 * processors. AMD does not intend MWAIT to be used in the cpu
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1038 * idle loop on current and future processors. 10h and future
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1039 * AMD processors use more power in MWAIT than HLT.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1040 * Pre-family-10h Opterons do not have the MWAIT instruction.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1041 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1042 idle_cpu_prefer_mwait = 0;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1043 #endif
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1044
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1045 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1046 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1047 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1048 * workaround the NT workaround in CMS 4.1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1049 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1050 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1051 (cpi->cpi_step == 2 \|\| cpi->cpi_step == 3))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1052 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1053 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1054 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1055 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1056 * workaround the NT workarounds again
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1057 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1058 if (cpi->cpi_family == 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1059 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1060 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1061 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1062 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1063 * We rely heavily on the probing in locore
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1064 * to actually figure out what parts, if any,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1065 * of the Cyrix cpuid instruction to believe.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1066 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1067 switch (x86_type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1068 case X86_TYPE_CYRIX_486:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1069 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1070 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1071 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1072 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1073 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1074 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1075 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1076 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1077 CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1078 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1079 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1080 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1081 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1082 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1083 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1084 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1085 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1086 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1087 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1088 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1089 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1090 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1091 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1092 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1093 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1094 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1095 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1096 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1097 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1098 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1099 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1100 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1101 CPUID_INTC_EDX_TSC \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1102 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1103 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1104 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1105 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1106 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1107 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1108 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1109 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1110 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1111 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1112 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1113
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1114 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1115 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1116 * Do not support MONITOR/MWAIT under a hypervisor
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1117 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1118 mask_ecx &= ~CPUID_INTC_ECX_MON;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1119 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1120 * Do not support XSAVE under a hypervisor for now
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1121 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1122 xsave_force_disable = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1123
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1124 #endif /* __xpv */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1125
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1126 if (xsave_force_disable) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1127 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1128 mask_ecx &= ~CPUID_INTC_ECX_AVX;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1129 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1130
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1131 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1132 * Now we've figured out the masks that determine
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1133 * which bits we choose to believe, apply the masks
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1134 * to the feature words, then map the kernel's view
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1135 * of these feature words into its feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1136 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1137 cp->cp_edx &= mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1138 cp->cp_ecx &= mask_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1139
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1140 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1141 * apply any platform restrictions (we don't call this
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1142 * immediately after __cpuid_insn here, because we need the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1143 * workarounds applied above first)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1144 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1145 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1146
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1147 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1148 * fold in overrides from the "eeprom" mechanism
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1149 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1150 cp->cp_edx \|= cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1151 cp->cp_edx &= ~cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1152
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1153 cp->cp_ecx \|= cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1154 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1155
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1156 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1157 add_x86_feature(featureset, X86FSET_LARGEPAGE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1158 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1159 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1160 add_x86_feature(featureset, X86FSET_TSC);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1161 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1162 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1163 add_x86_feature(featureset, X86FSET_MSR);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1164 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1165 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1166 add_x86_feature(featureset, X86FSET_MTRR);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1167 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1168 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1169 add_x86_feature(featureset, X86FSET_PGE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1170 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1171 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1172 add_x86_feature(featureset, X86FSET_CMOV);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1173 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1174 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1175 add_x86_feature(featureset, X86FSET_MMX);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1176 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1177 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1178 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1179 add_x86_feature(featureset, X86FSET_MCA);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1180 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1181 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1182 add_x86_feature(featureset, X86FSET_PAE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1183 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1184 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1185 add_x86_feature(featureset, X86FSET_CX8);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1186 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1187 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1188 add_x86_feature(featureset, X86FSET_CX16);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1189 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1190 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1191 add_x86_feature(featureset, X86FSET_PAT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1192 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1193 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1194 add_x86_feature(featureset, X86FSET_SEP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1195 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1196 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1197 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1198 * In our implementation, fxsave/fxrstor
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1199 * are prerequisites before we'll even
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1200 * try and do SSE things.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1201 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1202 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1203 add_x86_feature(featureset, X86FSET_SSE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1204 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1205 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1206 add_x86_feature(featureset, X86FSET_SSE2);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1207 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1208 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1209 add_x86_feature(featureset, X86FSET_SSE3);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1210 }
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1211 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1212 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1213 add_x86_feature(featureset, X86FSET_SSSE3);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1214 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1215 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1216 add_x86_feature(featureset, X86FSET_SSE4_1);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1217 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1218 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1219 add_x86_feature(featureset, X86FSET_SSE4_2);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1220 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1221 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1222 add_x86_feature(featureset, X86FSET_AES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1223 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1224 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1225 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1226 }
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1227
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1228 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1229 add_x86_feature(featureset, X86FSET_XSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1230 /* We only test AVX when there is XSAVE */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1231 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1232 add_x86_feature(featureset,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1233 X86FSET_AVX);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1234 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1235 }
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1236 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1237 }
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1238 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1239 add_x86_feature(featureset, X86FSET_DE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1240 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1241 #if !defined(__xpv)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1242 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1243
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1244 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1245 * We require the CLFLUSH instruction for erratum workaround
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1246 * to use MONITOR/MWAIT.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1247 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1248 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1249 cpi->cpi_mwait.support \|= MWAIT_SUPPORT;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1250 add_x86_feature(featureset, X86FSET_MWAIT);
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1251 } else {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1252 extern int idle_cpu_assert_cflush_monitor;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1253
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1254 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1255 * All processors we are aware of which have
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1256 * MONITOR/MWAIT also have CLFLUSH.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1257 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1258 if (idle_cpu_assert_cflush_monitor) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1259 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1260 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1261 }
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1262 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1263 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1264 #endif /* __xpv */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1265
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1266 /*
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1267 * Only need it first time, rest of the cpus would follow suite.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1268 * we only capture this for the bootcpu.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1269 */
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1270 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1271 add_x86_feature(featureset, X86FSET_CLFSH);
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1272 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1273 }
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1274 if (is_x86_feature(featureset, X86FSET_PAE))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1275 cpi->cpi_pabits = 36;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1276
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1277 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1278 * Hyperthreading configuration is slightly tricky on Intel
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1279 * and pure clones, and even trickier on AMD.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1280 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1281 * (AMD chose to set the HTT bit on their CMP processors,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1282 * even though they're not actually hyperthreaded. Thus it
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1283 * takes a bit more work to figure out what's really going
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1284 * on ... see the handling of the CMP_LGCY bit below)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1285 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1286 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1287 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1288 if (cpi->cpi_ncpu_per_chip > 1)
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1289 add_x86_feature(featureset, X86FSET_HTT);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1290 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1291 cpi->cpi_ncpu_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1292 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1293
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1294 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1295 * Work on the "extended" feature information, doing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1296 * some basic initialization for cpuid_pass2()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1297 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1298 xcpuid = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1299 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1300 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1301 if (IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1302 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1303 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1304 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1305 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1306 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1307 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1308 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1309 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1310 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1311 * Only these Cyrix CPUs are -known- to support
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1312 * extended cpuid operations.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1313 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1314 if (x86_type == X86_TYPE_VIA_CYRIX_III \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1315 x86_type == X86_TYPE_CYRIX_GXm)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1316 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1317 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1318 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1319 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1320 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1321 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1322 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1323 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1324
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1325 if (xcpuid) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1326 cp = &cpi->cpi_extd[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1327 cp->cp_eax = 0x80000000;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1328 cpi->cpi_xmaxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1329 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1330
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1331 if (cpi->cpi_xmaxeax & 0x80000000) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1332
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1333 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1334 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1335
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1336 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1337 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1338 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1339 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1340 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1341 cp = &cpi->cpi_extd[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1342 cp->cp_eax = 0x80000001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1343 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1344
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1345 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1346 cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1347 cpi->cpi_model == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1348 cpi->cpi_step == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1349 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1350 * K6 model 6 uses bit 10 to indicate SYSC
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1351 * Later models use bit 11. Fix it here.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1352 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1353 if (cp->cp_edx & 0x400) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1354 cp->cp_edx &= ~0x400;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1355 cp->cp_edx \|= CPUID_AMD_EDX_SYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1356 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1357 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1358
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1359 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1360
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1361 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1362 * Compute the additions to the kernel's feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1363 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1364 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1365 add_x86_feature(featureset, X86FSET_NX);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1366 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1367
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1368 /*
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1369 * Regardless whether or not we boot 64-bit,
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1370 * we should have a way to identify whether
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1371 * the CPU is capable of running 64-bit.
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1372 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1373 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1374 add_x86_feature(featureset, X86FSET_64);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1375 }
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1376
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1377 #if defined(__amd64)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1378 /* 1 GB large page - enable only for 64 bit kernel */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1379 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1380 add_x86_feature(featureset, X86FSET_1GPG);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1381 }
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1382 #endif
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1383
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1384 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1385 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1386 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1387 add_x86_feature(featureset, X86FSET_SSE4A);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1388 }
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1389
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1390 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1391 * If both the HTT and CMP_LGCY bits are set,
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1392 * then we're not actually HyperThreaded. Read
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1393 * "AMD CPUID Specification" for more details.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1394 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1395 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1396 is_x86_feature(featureset, X86FSET_HTT) &&
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1397 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1398 remove_x86_feature(featureset, X86FSET_HTT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1399 add_x86_feature(featureset, X86FSET_CMP);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1400 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1401 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1402 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1403 * It's really tricky to support syscall/sysret in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1404 * the i386 kernel; we rely on sysenter/sysexit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1405 * instead. In the amd64 kernel, things are -way-
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1406 * better.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1407 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1408 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1409 add_x86_feature(featureset, X86FSET_ASYSC);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1410 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1411
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1412 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1413 * While we're thinking about system calls, note
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1414 * that AMD processors don't support sysenter
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1415 * in long mode at all, so don't try to program them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1416 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1417 if (x86_vendor == X86_VENDOR_AMD) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1418 remove_x86_feature(featureset, X86FSET_SEP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1419 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1420 #endif
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1421 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1422 add_x86_feature(featureset, X86FSET_TSCP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1423 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1424 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1425 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1426 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1427 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1428
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1429 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1430 * Get CPUID data about processor cores and hyperthreads.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1431 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1432 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1433 case X86_VENDOR_Intel:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1434 if (cpi->cpi_maxeax >= 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1435 cp = &cpi->cpi_std[4];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1436 cp->cp_eax = 4;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1437 cp->cp_ecx = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1438 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1439 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1440 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1441 /FALLTHROUGH/
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1442 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1443 if (cpi->cpi_xmaxeax < 0x80000008)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1444 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1445 cp = &cpi->cpi_extd[8];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1446 cp->cp_eax = 0x80000008;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1447 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1448 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1449
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1450 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1451 * Virtual and physical address limits from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1452 * cpuid override previously guessed values.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1453 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1454 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1455 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1456 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1457 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1458 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1459 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1460
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1461 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1462 * Derive the number of cores per chip
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1463 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1464 switch (cpi->cpi_vendor) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1465 case X86_VENDOR_Intel:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1466 if (cpi->cpi_maxeax < 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1467 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1468 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1469 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1470 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1471 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1472 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1473 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1474 case X86_VENDOR_AMD:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1475 if (cpi->cpi_xmaxeax < 0x80000008) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1476 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1477 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1478 } else {
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1479 /*
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1480 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1481 * 1 less than the number of physical cores on
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1482 * the chip. In family 0x10 this value can
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1483 * be affected by "downcoring" - it reflects
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1484 * 1 less than the number of cores actually
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1485 * enabled on this node.
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1486 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1487 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1488 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1489 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1490 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1491 default:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1492 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1493 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1494 }
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1495
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1496 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1497 * Get CPUID data about TSC Invariance in Deep C-State.
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1498 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1499 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1500 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1501 if (cpi->cpi_maxeax >= 7) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1502 cp = &cpi->cpi_extd[7];
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1503 cp->cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1504 cp->cp_ecx = 0;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1505 (void) __cpuid_insn(cp);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1506 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1507 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1508 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1509 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1510 }
5284 2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1511 } else {
2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1512 cpi->cpi_ncore_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1513 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1514
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1515 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1516 * If more than one core, then this processor is CMP.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1517 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1518 if (cpi->cpi_ncore_per_chip > 1) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1519 add_x86_feature(featureset, X86FSET_CMP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1520 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1521
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1522 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1523 * If the number of cores is the same as the number
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1524 * of CPUs, then we cannot have HyperThreading.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1525 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1526 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1527 remove_x86_feature(featureset, X86FSET_HTT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1528 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1529
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1530 cpi->cpi_apicid = CPI_APIC_ID(cpi);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1531 cpi->cpi_procnodes_per_pkg = 1;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1532 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1533 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1534 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1535 * Single-core single-threaded processors.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1536 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1537 cpi->cpi_chipid = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1538 cpi->cpi_clogid = 0;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1539 cpi->cpi_coreid = cpu->cpu_id;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1540 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1541 if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1542 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1543 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1544 cpi->cpi_procnodeid = cpi->cpi_chipid;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1545 } else if (cpi->cpi_ncpu_per_chip > 1) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1546 if (cpi->cpi_vendor == X86_VENDOR_Intel)
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1547 cpuid_intel_getids(cpu, featureset);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1548 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1549 cpuid_amd_getids(cpu);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1550 else {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1551 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1552 * All other processors are currently
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1553 * assumed to have single cores.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1554 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1555 cpi->cpi_coreid = cpi->cpi_chipid;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1556 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1557 cpi->cpi_procnodeid = cpi->cpi_chipid;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1558 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1559 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1560
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1561 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1562 * Synthesize chip "revision" and socket type
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1563 */
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1564 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1565 cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1566 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1567 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1568 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1569 cpi->cpi_model, cpi->cpi_step);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1570
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1571 pass1_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1572 cpi->cpi_pass = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1573 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1574
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1575 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1576 * Make copies of the cpuid table entries we depend on, in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1577 * part for ease of parsing now, in part so that we have only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1578 * one place to correct any of it, in part for ease of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1579 * later export to userland, and in part so we can look at
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1580 * this stuff in a crash dump.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1581 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1582
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1583 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1584 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1585 cpuid_pass2(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1586 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1587 uint_t n, nmax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1588 int i;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1589 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1590 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1591 uint32_t *iptr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1592 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1593
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1594 ASSERT(cpi->cpi_pass == 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1595
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1596 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1597 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1598
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1599 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1600 nmax = NMAX_CPI_STD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1601 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1602 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1603 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1604 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1605 cp->cp_eax = n;
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1606
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1607 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1608 * CPUID function 4 expects %ecx to be initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1609 * with an index which indicates which cache to return
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1610 * information about. The OS is expected to call function 4
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1611 * with %ecx set to 0, 1, 2, ... until it returns with
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1612 * EAX[4:0] set to 0, which indicates there are no more
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1613 * caches.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1614 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1615 * Here, populate cpi_std[4] with the information returned by
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1616 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1617 * when dynamic memory allocation becomes available.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1618 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1619 * Note: we need to explicitly initialize %ecx here, since
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1620 * function 4 may have been previously invoked.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1621 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1622 if (n == 4)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1623 cp->cp_ecx = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1624
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1625 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1626 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1627 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1628 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1629 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1630 * "the lower 8 bits of the %eax register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1631 * contain a value that identifies the number
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1632 * of times the cpuid [instruction] has to be
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1633 * executed to obtain a complete image of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1634 * processor's caching systems."
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1635 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1636 * How do they make this stuff up?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1637 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1638 cpi->cpi_ncache = sizeof (cp)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1639 BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1640 if (cpi->cpi_ncache == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1641 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1642 cpi->cpi_ncache--; /* skip count byte */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1643
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1644 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1645 * Well, for now, rather than attempt to implement
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1646 * this slightly dubious algorithm, we just look
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1647 * at the first 15 ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1648 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1649 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1650 cpi->cpi_ncache = sizeof (*cp) - 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1651
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1652 dp = cpi->cpi_cacheinfo;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1653 if (BITX(cp->cp_eax, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1654 uint8_t p = (void )&cp->cp_eax;
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1655 for (i = 1; i < 4; i++)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1656 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1657 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1658 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1659 if (BITX(cp->cp_ebx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1660 uint8_t p = (void )&cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1661 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1662 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1663 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1664 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1665 if (BITX(cp->cp_ecx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1666 uint8_t p = (void )&cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1667 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1668 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1669 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1670 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1671 if (BITX(cp->cp_edx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1672 uint8_t p = (void )&cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1673 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1674 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1675 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1676 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1677 break;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1678
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1679 case 3: /* Processor serial number, if PSN supported */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1680 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1681
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1682 case 4: /* Deterministic cache parameters */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1683 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1684
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1685 case 5: /* Monitor/Mwait parameters */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1686 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1687 size_t mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1688
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1689 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1690 * check cpi_mwait.support which was set in cpuid_pass1
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1691 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1692 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1693 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1694
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1695 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1696 * Protect ourself from insane mwait line size.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1697 * Workaround for incomplete hardware emulator(s).
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1698 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1699 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1700 if (mwait_size < sizeof (uint32_t) \|\|
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1701 !ISP2(mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1702 #if DEBUG
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1703 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1704 "size %ld", cpu->cpu_id, (long)mwait_size);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1705 #endif
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1706 break;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1707 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1708
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1709 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1710 cpi->cpi_mwait.mon_max = mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1711 if (MWAIT_EXTENSION(cpi)) {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1712 cpi->cpi_mwait.support \|= MWAIT_EXTENSIONS;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1713 if (MWAIT_INT_ENABLE(cpi))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1714 cpi->cpi_mwait.support \|=
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1715 MWAIT_ECX_INT_ENABLE;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1716 }
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1717 break;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1718 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1719 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1720 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1721 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1722 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1723
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1724 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1725 struct cpuid_regs regs;
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1726
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1727 cp = &regs;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1728 cp->cp_eax = 0xB;
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1729 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1730
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1731 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1732
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1733 /*
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1734 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1735 * indicates that the extended topology enumeration leaf is
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1736 * available.
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1737 */
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1738 if (cp->cp_ebx) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1739 uint32_t x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1740 uint_t coreid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1741 uint_t ncpu_per_core = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1742 uint_t chipid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1743 uint_t ncpu_per_chip = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1744 uint_t i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1745 uint_t level;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1746
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1747 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1748 cp->cp_eax = 0xB;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1749 cp->cp_ecx = i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1750
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1751 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1752 level = CPI_CPU_LEVEL_TYPE(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1753
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1754 if (level == 1) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1755 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1756 coreid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1757 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1758 } else if (level == 2) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1759 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1760 chipid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1761 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1762 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1763 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1764
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1765 cpi->cpi_apicid = x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1766 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1767 cpi->cpi_ncore_per_chip = ncpu_per_chip /
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1768 ncpu_per_core;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1769 cpi->cpi_chipid = x2apic_id >> chipid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1770 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1771 cpi->cpi_coreid = x2apic_id >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1772 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1773 }
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1774
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1775 /* Make cp NULL so that we don't stumble on others */
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1776 cp = NULL;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1777 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1778
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1779 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1780 * XSAVE enumeration
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1781 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1782 if (cpi->cpi_maxeax >= 0xD && cpi->cpi_vendor == X86_VENDOR_Intel) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1783 struct cpuid_regs regs;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1784 boolean_t cpuid_d_valid = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1785
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1786 cp = &regs;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1787 cp->cp_eax = 0xD;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1788 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1789
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1790 (void) __cpuid_insn(cp);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1791
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1792 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1793 * Sanity checks for debug
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1794 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1795 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 \|\|
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1796 (cp->cp_eax & XFEATURE_SSE) == 0) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1797 cpuid_d_valid = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1798 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1799
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1800 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1801 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1802 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1803
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1804 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1805 * If the hw supports AVX, get the size and offset in the save
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1806 * area for the ymm state.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1807 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1808 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1809 cp->cp_eax = 0xD;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1810 cp->cp_ecx = 2;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1811 cp->cp_edx = cp->cp_ebx = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1812
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1813 (void) __cpuid_insn(cp);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1814
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1815 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET \|\|
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1816 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1817 cpuid_d_valid = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1818 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1819
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1820 cpi->cpi_xsave.ymm_size = cp->cp_eax;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1821 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1822 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1823
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1824 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1825 xsave_state_size = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1826 } else if (cpuid_d_valid) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1827 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1828 } else {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1829 /* Broken CPUID 0xD, probably in HVM */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1830 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1831 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1832 ", ymm_size = %d, ymm_offset = %d\n",
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1833 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1834 cpi->cpi_xsave.xsav_hw_features_high,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1835 (int)cpi->cpi_xsave.xsav_max_size,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1836 (int)cpi->cpi_xsave.ymm_size,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1837 (int)cpi->cpi_xsave.ymm_offset);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1838
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1839 if (xsave_state_size != 0) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1840 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1841 * This must be a non-boot CPU. We cannot
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1842 * continue, because boot cpu has already
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1843 * enabled XSAVE.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1844 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1845 ASSERT(cpu->cpu_id != 0);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1846 cmn_err(CE_PANIC, "cpu%d: we have already "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1847 "enabled XSAVE on boot cpu, cannot "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1848 "continue.", cpu->cpu_id);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1849 } else {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1850 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1851 * Must be from boot CPU, OK to disable XSAVE.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1852 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1853 ASSERT(cpu->cpu_id == 0);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1854 remove_x86_feature(x86_featureset,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1855 X86FSET_XSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1856 remove_x86_feature(x86_featureset, X86FSET_AVX);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1857 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_XSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1858 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_AVX;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1859 xsave_force_disable = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1860 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1861 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1862 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1863
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1864
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1865 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1866 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1867
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1868 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1869 nmax = NMAX_CPI_EXTD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1870 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1871 * Copy the extended properties, fixing them as we go.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1872 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1873 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1874 iptr = (void *)cpi->cpi_brandstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1875 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1876 cp->cp_eax = 0x80000000 + n;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1877 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1878 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1879 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1880 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1881 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1882 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1883 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1884 * Extract the brand string
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1885 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1886 *iptr++ = cp->cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1887 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1888 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1889 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1890 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1891 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1892 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1893 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1894 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1895 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1896 * parts to report the sizes of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1897 * TLB for large pages. Before then,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1898 * we don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1899 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1900 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1901 (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1902 cpi->cpi_model < 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1903 cp->cp_eax = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1904 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1905 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1906 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1907 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1908 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1909 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1910 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1911 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1912 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1913 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1914 * AMD parts with L2 TLB's.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1915 * Before then, don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1916 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1917 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1918 cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1919 cpi->cpi_model < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1920 cp->cp_eax = cp->cp_ebx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1921 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1922 * AMD Duron rev A0 reports L2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1923 * cache size incorrectly as 1K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1924 * when it is really 64K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1925 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1926 if (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1927 cpi->cpi_model == 3 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1928 cpi->cpi_step == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1929 cp->cp_ecx &= 0xffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1930 cp->cp_ecx \|= 0x400000;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1931 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1932 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1933 case X86_VENDOR_Cyrix: /* VIA C3 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1934 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1935 * VIA C3 processors are a bit messed
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1936 * up w.r.t. encoding cache sizes in %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1937 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1938 if (cpi->cpi_family != 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1939 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1940 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1941 * model 7 and 8 were incorrectly encoded
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1942 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1943 * xxx is model 8 really broken?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1944 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1945 if (cpi->cpi_model == 7 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1946 cpi->cpi_model == 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1947 cp->cp_ecx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1948 BITX(cp->cp_ecx, 31, 24) << 16 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1949 BITX(cp->cp_ecx, 23, 16) << 12 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1950 BITX(cp->cp_ecx, 15, 8) << 8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1951 BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1952 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1953 * model 9 stepping 1 has wrong associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1954 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1955 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1956 cp->cp_ecx \|= 8 << 12;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1957 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1958 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1959 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1960 * Extended L2 Cache features function.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1961 * First appeared on Prescott.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1962 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1963 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1964 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1965 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1966 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1967 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1968 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1969 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1970 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1971
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1972 pass2_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1973 cpi->cpi_pass = 2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1974 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1975
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1976 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1977 intel_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1978 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1979 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1980
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1981 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1982 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1983 return ("i486");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1984
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1985 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1986 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1987 return ("Intel Pentium(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1988 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1989 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1990 uint_t celeron, xeon;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1991 const struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1992 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1993 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1994 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1995 return ("Intel Pentium(r) Pro");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1996 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1997 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1998 return ("Intel Pentium(r) II");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1999 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2000 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2001 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2002 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2003 celeron = xeon = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2004 cp = &cpi->cpi_std[2]; /* cache info */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2005
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	2006 for (i = 1; i < 4; i++) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2007 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2008
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2009 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2010 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2011 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2012 if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2013 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2014 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2015
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2016 for (i = 0; i < 2; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2017 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2018
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2019 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2020 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2021 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2022 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2023 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2024 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2025
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2026 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2027 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2028
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2029 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2030 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2031 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2032 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2033 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2034 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2035
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2036 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2037 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2038
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2039 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2040 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2041 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2042 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2043 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2044 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2045
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2046 if (celeron)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2047 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2048 if (xeon)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2049 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2050 "Intel Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2051 "Intel Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2052 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2053 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2054 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2055 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2056 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2057 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2058 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2059 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2060 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2061
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2062 /* BrandID is present if the field is nonzero */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2063 if (cpi->cpi_brandid != 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2064 static const struct {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2065 uint_t bt_bid;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2066 const char *bt_str;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2067 } brand_tbl[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2068 { 0x1, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2069 { 0x2, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2070 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2071 { 0x4, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2072 { 0x6, "Mobile Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2073 { 0x7, "Mobile Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2074 { 0x8, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2075 { 0x9, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2076 { 0xa, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2077 { 0xb, "Intel(r) Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2078 { 0xc, "Intel(r) Xeon(tm) MP" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2079 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2080 { 0xf, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2081 { 0x11, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2082 { 0x12, "Intel(r) Celeron(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2083 { 0x13, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2084 { 0x14, "Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2085 { 0x15, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2086 { 0x16, "Intel(r) Pentium(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2087 { 0x17, "Mobile Intel(r) Celeron(r)" }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2088 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2089 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2090 uint_t sgn;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2091
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2092 sgn = (cpi->cpi_family << 8) \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2093 (cpi->cpi_model << 4) \| cpi->cpi_step;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2094
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2095 for (i = 0; i < btblmax; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2096 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2097 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2098 if (i < btblmax) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2099 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2100 return ("Intel(r) Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2101 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2102 return ("Intel(r) Xeon(tm) MP");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2103 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2104 return ("Intel(r) Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2105 return (brand_tbl[i].bt_str);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2106 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2107 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2108
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2109 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2110 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2111
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2112 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2113 amd_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2114 {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2115 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2116 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2117 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2118
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2119 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2120 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2121 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2122 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2123 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2124 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2125 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2126 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2127 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2128 return ("AMD-K5(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2129 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2130 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2131 return ("AMD-K6(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2132 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2133 return ("AMD-K6(r)-2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2134 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2135 return ("AMD-K6(r)-III");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2136 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2137 return ("AMD (family 5)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2138 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2139 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2140 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2141 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2142 return ("AMD-K7(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2143 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2144 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2145 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2146 return ("AMD Athlon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2147 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2148 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2149 return ("AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2150 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2151 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2152 case 10:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2153 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2154 * Use the L2 cache size to distinguish
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2155 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2156 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2157 "AMD Athlon(tm)" : "AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2158 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2159 return ("AMD (family 6)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2160 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2161 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2162 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2163 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2164
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2165 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2166 cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2167 switch (BITX(cpi->cpi_brandid, 7, 5)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2168 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2169 return ("AMD Opteron(tm) UP 1xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2170 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2171 return ("AMD Opteron(tm) DP 2xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2172 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2173 return ("AMD Opteron(tm) MP 8xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2174 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2175 return ("AMD Opteron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2176 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2177 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2178
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2179 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2180 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2181
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2182 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2183 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2184 {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2185 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2186 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2187 type == X86_TYPE_CYRIX_486)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2188 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2189
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2190 switch (type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2191 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2192 return ("Cyrix 6x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2193 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2194 return ("Cyrix 6x86L");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2195 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2196 return ("Cyrix 6x86MX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2197 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2198 return ("Cyrix GXm");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2199 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2200 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2201 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2202 return ("Cyrix M2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2203 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2204 return ("VIA Cyrix M3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2205 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2206 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2207 * Have another wild guess ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2208 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2209 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2210 return ("Cyrix 5x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2211 else if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2212 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2213 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2214 return ("Cyrix 6x86"); /* Cyrix M1 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2215 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2216 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2217 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2218 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2219 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2220 } else if (cpi->cpi_family == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2221 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2222 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2223 return ("Cyrix 6x86MX"); /* Cyrix M2? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2224 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2225 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2226 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2227 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2228 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2229 return ("VIA C3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2230 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2231 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2232 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2233 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2234 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2235 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2236 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2237 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2238
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2239 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2240 * This only gets called in the case that the CPU extended
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2241 * feature brand string (0x80000002, 0x80000003, 0x80000004)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2242 * aren't available, or contain null bytes for some reason.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2243 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2244 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2245 fabricate_brandstr(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2246 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2247 const char *brand = NULL;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2248
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2249 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2250 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2251 brand = intel_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2252 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2253 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2254 brand = amd_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2255 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2256 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2257 brand = cyrix_cpubrand(cpi, x86_type);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2258 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2259 case X86_VENDOR_NexGen:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2260 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2261 brand = "NexGen Nx586";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2262 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2263 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2264 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2265 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2266 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2267 brand = "Centaur C6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2268 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2269 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2270 brand = "Centaur C2";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2271 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2272 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2273 brand = "Centaur C3";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2274 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2275 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2276 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2277 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2278 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2279 case X86_VENDOR_Rise:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2280 if (cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2281 (cpi->cpi_model == 0 \|\| cpi->cpi_model == 2))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2282 brand = "Rise mP6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2283 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2284 case X86_VENDOR_SiS:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2285 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2286 brand = "SiS 55x";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2287 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2288 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2289 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2290 brand = "Transmeta Crusoe TM3x00 or TM5x00";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2291 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2292 case X86_VENDOR_NSC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2293 case X86_VENDOR_UMC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2294 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2295 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2296 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2297 if (brand) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2298 (void) strcpy((char *)cpi->cpi_brandstr, brand);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2299 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2300 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2301
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2302 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2303 * If all else fails ...
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2304 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2305 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2306 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2307 cpi->cpi_model, cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2308 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2309
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2310 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2311 * This routine is called just after kernel memory allocation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2312 * becomes available on cpu0, and as part of mp_startup() on
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2313 * the other cpus.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2314 *
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2315 * Fixup the brand string, and collect any information from cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2316 * that requires dynamicically allocated storage to represent.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2317 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2318 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2319 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2320 cpuid_pass3(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2321 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2322 int i, max, shft, level, size;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2323 struct cpuid_regs regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2324 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2325 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2326
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2327 ASSERT(cpi->cpi_pass == 2);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2328
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2329 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2330 * Function 4: Deterministic cache parameters
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2331 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2332 * Take this opportunity to detect the number of threads
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2333 * sharing the last level cache, and construct a corresponding
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2334 * cache id. The respective cpuid_info members are initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2335 * to the default case of "no last level cache sharing".
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2336 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2337 cpi->cpi_ncpu_shr_last_cache = 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2338 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2339
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2340 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2341
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2342 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2343 * Find the # of elements (size) returned by fn 4, and along
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2344 * the way detect last level cache sharing details.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2345 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2346 bzero(&regs, sizeof (regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2347 cp = &regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2348 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2349 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2350 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2351
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2352 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2353
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2354 if (CPI_CACHE_TYPE(cp) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2355 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2356 level = CPI_CACHE_LVL(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2357 if (level > max) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2358 max = level;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2359 cpi->cpi_ncpu_shr_last_cache =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2360 CPI_NTHR_SHR_CACHE(cp) + 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2361 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2362 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2363 cpi->cpi_std_4_size = size = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2364
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2365 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2366 * Allocate the cpi_std_4 array. The first element
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2367 * references the regs for fn 4, %ecx == 0, which
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2368 * cpuid_pass2() stashed in cpi->cpi_std[4].
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2369 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2370 if (size > 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2371 cpi->cpi_std_4 =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2372 kmem_alloc(size * sizeof (cp), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2373 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2374
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2375 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2376 * Allocate storage to hold the additional regs
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2377 * for function 4, %ecx == 1 .. cpi_std_4_size.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2378 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2379 * The regs for fn 4, %ecx == 0 has already
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2380 * been allocated as indicated above.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2381 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2382 for (i = 1; i < size; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2383 cp = cpi->cpi_std_4[i] =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2384 kmem_zalloc(sizeof (regs), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2385 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2386 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2387
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2388 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2389 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2390 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2391 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2392 * Determine the number of bits needed to represent
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2393 * the number of CPUs sharing the last level cache.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2394 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2395 * Shift off that number of bits from the APIC id to
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2396 * derive the cache id.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2397 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2398 shft = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2399 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2400 shft++;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	2401 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2402 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2403
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2404 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2405 * Now fixup the brand string
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2406 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2407 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2408 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2409 } else {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2410
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2411 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2412 * If we successfully extracted a brand string from the cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2413 * instruction, clean it up by removing leading spaces and
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2414 * similar junk.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2415 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2416 if (cpi->cpi_brandstr[0]) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2417 size_t maxlen = sizeof (cpi->cpi_brandstr);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2418 char src, dst;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2419
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2420 dst = src = (char *)cpi->cpi_brandstr;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2421 src[maxlen - 1] = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2422 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2423 * strip leading spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2424 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2425 while (*src == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2426 src++;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2427 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2428 * Remove any 'Genuine' or "Authentic" prefixes
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2429 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2430 if (strncmp(src, "Genuine ", 8) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2431 src += 8;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2432 if (strncmp(src, "Authentic ", 10) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2433 src += 10;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2434
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2435 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2436 * Now do an in-place copy.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2437 * Map (R) to (r) and (TM) to (tm).
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2438 * The era of teletypes is long gone, and there's
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2439 * -really- no need to shout.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2440 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2441 while (*src != '\0') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2442 if (src[0] == '(') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2443 if (strncmp(src + 1, "R)", 2) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2444 (void) strncpy(dst, "(r)", 3);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2445 src += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2446 dst += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2447 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2448 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2449 if (strncmp(src + 1, "TM)", 3) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2450 (void) strncpy(dst, "(tm)", 4);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2451 src += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2452 dst += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2453 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2454 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2455 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2456 dst++ = src++;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2457 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2458 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2459
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2460 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2461 * Finally, remove any trailing spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2462 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2463 while (--dst > cpi->cpi_brandstr)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2464 if (*dst == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2465 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2466 else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2467 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2468 } else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2469 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2470 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2471 cpi->cpi_pass = 3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2472 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2473
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2474 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2475 * This routine is called out of bind_hwcap() much later in the life
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2476 * of the kernel (post_startup()). The job of this routine is to resolve
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2477 * the hardware feature support and kernel support for those features into
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2478 * what we're actually going to tell applications via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2479 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2480 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2481 cpuid_pass4(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2482 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2483 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2484 uint_t hwcap_flags = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2485
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2486 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2487 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2488 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2489
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2490 ASSERT(cpi->cpi_pass == 3);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2491
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2492 if (cpi->cpi_maxeax >= 1) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2493 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2494 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2495
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2496 *edx = CPI_FEATURES_EDX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2497 *ecx = CPI_FEATURES_ECX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2498
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2499 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2500 * [these require explicit kernel support]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2501 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2502 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2503 *edx &= ~CPUID_INTC_EDX_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2504
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2505 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2506 *edx &= ~(CPUID_INTC_EDX_FXSR\|CPUID_INTC_EDX_SSE);
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2507 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2508 *edx &= ~CPUID_INTC_EDX_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2509
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2510 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2511 *edx &= ~CPUID_INTC_EDX_HTT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2512
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2513 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2514 *ecx &= ~CPUID_INTC_ECX_SSE3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2515
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2516 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2517 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2518 *ecx &= ~CPUID_INTC_ECX_SSSE3;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2519 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2520 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2521 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2522 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2523 if (!is_x86_feature(x86_featureset, X86FSET_AES))
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2524 *ecx &= ~CPUID_INTC_ECX_AES;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2525 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2526 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2527 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2528 *ecx &= ~(CPUID_INTC_ECX_XSAVE \|
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2529 CPUID_INTC_ECX_OSXSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2530 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2531 *ecx &= ~CPUID_INTC_ECX_AVX;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2532 }
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2533
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2534 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2535 * [no explicit support required beyond x87 fp context]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2536 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2537 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2538 *edx &= ~(CPUID_INTC_EDX_FPU \| CPUID_INTC_EDX_MMX);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2539
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2540 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2541 * Now map the supported feature vector to things that we
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2542 * think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2543 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2544 if (*edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2545 hwcap_flags \|= AV_386_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2546 if (*edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2547 hwcap_flags \|= AV_386_FXSR \| AV_386_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2548 if (*edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2549 hwcap_flags \|= AV_386_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2550 if (*ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2551 hwcap_flags \|= AV_386_SSE3;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2552 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2553 if (*ecx & CPUID_INTC_ECX_SSSE3)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2554 hwcap_flags \|= AV_386_SSSE3;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2555 if (*ecx & CPUID_INTC_ECX_SSE4_1)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2556 hwcap_flags \|= AV_386_SSE4_1;
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2557 if (*ecx & CPUID_INTC_ECX_SSE4_2)
395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2558 hwcap_flags \|= AV_386_SSE4_2;
8418 a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2559 if (*ecx & CPUID_INTC_ECX_MOVBE)
a4853cd72a21 6719310 Expose availability of MOVBE instruction Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 8377 diff changeset	2560 hwcap_flags \|= AV_386_MOVBE;
9370 5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2561 if (*ecx & CPUID_INTC_ECX_AES)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2562 hwcap_flags \|= AV_386_AES;
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2563 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
5f964d9a7826 6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9283 diff changeset	2564 hwcap_flags \|= AV_386_PCLMULQDQ;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2565 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2566 (*ecx & CPUID_INTC_ECX_OSXSAVE))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	2567 hwcap_flags \|= AV_386_XSAVE;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2568 }
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2569 if (*ecx & CPUID_INTC_ECX_POPCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2570 hwcap_flags \|= AV_386_POPCNT;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2571 if (*edx & CPUID_INTC_EDX_FPU)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2572 hwcap_flags \|= AV_386_FPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2573 if (*edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2574 hwcap_flags \|= AV_386_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2575
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2576 if (*edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2577 hwcap_flags \|= AV_386_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2578 if (*edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2579 hwcap_flags \|= AV_386_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2580 if (*edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2581 hwcap_flags \|= AV_386_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2582 if (*ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2583 hwcap_flags \|= AV_386_CX16;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2584 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2585
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2586 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2587 goto pass4_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2588
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2589 switch (cpi->cpi_vendor) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2590 struct cpuid_regs cp;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2591 uint32_t edx, ecx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2592
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2593 case X86_VENDOR_Intel:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2594 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2595 * Seems like Intel duplicated what we necessary
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2596 * here to make the initial crop of 64-bit OS's work.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2597 * Hopefully, those are the only "extended" bits
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2598 * they'll add.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2599 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2600 /FALLTHROUGH/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2601
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2602 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2603 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2604 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2605
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2606 *edx = CPI_FEATURES_XTD_EDX(cpi);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2607 *ecx = CPI_FEATURES_XTD_ECX(cpi);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2608
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2609 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2610 * [these features require explicit kernel support]
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2611 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2612 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2613 case X86_VENDOR_Intel:
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2614 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2615 *edx &= ~CPUID_AMD_EDX_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2616 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2617
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2618 case X86_VENDOR_AMD:
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2619 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2620 *edx &= ~CPUID_AMD_EDX_TSCP;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2621 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2622 *ecx &= ~CPUID_AMD_ECX_SSE4A;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2623 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2624
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2625 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2626 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2627 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2628
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2629 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2630 * [no explicit support required beyond
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2631 * x87 fp context and exception handlers]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2632 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2633 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2634 *edx &= ~(CPUID_AMD_EDX_MMXamd \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2635 CPUID_AMD_EDX_3DNow \| CPUID_AMD_EDX_3DNowx);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2636
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2637 if (!is_x86_feature(x86_featureset, X86FSET_NX))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2638 *edx &= ~CPUID_AMD_EDX_NX;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2639 #if !defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2640 *edx &= ~CPUID_AMD_EDX_LM;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2641 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2642 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2643 * Now map the supported feature vector to
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2644 * things that we think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2645 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2646 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2647 if (*edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2648 hwcap_flags \|= AV_386_AMD_SYSC;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2649 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2650 if (*edx & CPUID_AMD_EDX_MMXamd)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2651 hwcap_flags \|= AV_386_AMD_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2652 if (*edx & CPUID_AMD_EDX_3DNow)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2653 hwcap_flags \|= AV_386_AMD_3DNow;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2654 if (*edx & CPUID_AMD_EDX_3DNowx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2655 hwcap_flags \|= AV_386_AMD_3DNowx;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2656
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2657 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2658 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2659 if (*edx & CPUID_AMD_EDX_TSCP)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2660 hwcap_flags \|= AV_386_TSCP;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2661 if (*ecx & CPUID_AMD_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2662 hwcap_flags \|= AV_386_AHF;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2663 if (*ecx & CPUID_AMD_ECX_SSE4A)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2664 hwcap_flags \|= AV_386_AMD_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2665 if (*ecx & CPUID_AMD_ECX_LZCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2666 hwcap_flags \|= AV_386_AMD_LZCNT;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2667 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2668
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2669 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2670 if (*edx & CPUID_AMD_EDX_TSCP)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2671 hwcap_flags \|= AV_386_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2672 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2673 * Aarrgh.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2674 * Intel uses a different bit in the same word.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2675 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2676 if (*ecx & CPUID_INTC_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2677 hwcap_flags \|= AV_386_AHF;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2678 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2679
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2680 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2681 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2682 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2683 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2684
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2685 case X86_VENDOR_TM:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2686 cp.cp_eax = 0x80860001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2687 (void) __cpuid_insn(&cp);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2688 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2689 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2690
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2691 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2692 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2693 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2694
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2695 pass4_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2696 cpi->cpi_pass = 4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2697 return (hwcap_flags);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2698 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2699
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2700
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2701 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2702 * Simulate the cpuid instruction using the data we previously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2703 * captured about this CPU. We try our best to return the truth
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2704 * about the hardware, independently of kernel support.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2705 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2706 uint32_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2707 cpuid_insn(cpu_t cpu, struct cpuid_regs cp)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2708 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2709 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2710 struct cpuid_regs *xcp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2711
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2712 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2713 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2714 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2715
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2716 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2717
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2718 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2719 * CPUID data is cached in two separate places: cpi_std for standard
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2720 * CPUID functions, and cpi_extd for extended CPUID functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2721 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2722 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2723 xcp = &cpi->cpi_std[cp->cp_eax];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2724 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2725 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2726 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2727 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2728 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2729 * The caller is asking for data from an input parameter which
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2730 * the kernel has not cached. In this case we go fetch from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2731 * the hardware and return the data directly to the user.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2732 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2733 return (__cpuid_insn(cp));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2734
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2735 cp->cp_eax = xcp->cp_eax;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2736 cp->cp_ebx = xcp->cp_ebx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2737 cp->cp_ecx = xcp->cp_ecx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2738 cp->cp_edx = xcp->cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2739 return (cp->cp_eax);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2740 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2741
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2742 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2743 cpuid_checkpass(cpu_t *cpu, int pass)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2744 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2745 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2746 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2747 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2748
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2749 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2750 cpuid_getbrandstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2751 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2752 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2753
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2754 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2755 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2756
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2757 int
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2758 cpuid_is_cmt(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2759 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2760 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2761 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2762
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2763 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2764
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2765 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2766 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2767
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2768 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2769 * AMD and Intel both implement the 64-bit variant of the syscall
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2770 * instruction (syscallq), so if there's -any- support for syscall,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2771 * cpuid currently says "yes, we support this".
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2772 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2773 * However, Intel decided to -not- implement the 32-bit variant of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2774 * syscall instruction, so we provide a predicate to allow our caller
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2775 * to test that subtlety here.
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2776 *
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2777 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2778 * even in the case where the hardware would in fact support it.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2779 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2780 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2781 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2782 cpuid_syscall32_insn(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2783 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2784 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2785
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2786 #if !defined(__xpv)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2787 if (cpu == NULL)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2788 cpu = CPU;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2789
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2790 /CSTYLED/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2791 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2792 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2793
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2794 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2795 cpi->cpi_xmaxeax >= 0x80000001 &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2796 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2797 return (1);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2798 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2799 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2800 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2801 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2802
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2803 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2804 cpuid_getidstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2805 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2806 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2807
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2808 static const char fmt[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2809 "x86 (%s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2810 static const char fmt_ht[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2811 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2812
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2813 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2814
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2815 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2816 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2817 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2818 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2819 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2820 return (snprintf(s, n, fmt,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2821 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2822 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2823 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2824 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2825
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2826 const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2827 cpuid_getvendorstr(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2828 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2829 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2830 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2831 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2832
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2833 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2834 cpuid_getvendor(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2835 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2836 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2837 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2838 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2839
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2840 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2841 cpuid_getfamily(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2842 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2843 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2844 return (cpu->cpu_m.mcpu_cpi->cpi_family);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2845 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2846
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2847 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2848 cpuid_getmodel(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2849 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2850 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2851 return (cpu->cpu_m.mcpu_cpi->cpi_model);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2852 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2853
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2854 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2855 cpuid_get_ncpu_per_chip(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2856 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2857 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2858 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2859 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2860
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2861 uint_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2862 cpuid_get_ncore_per_chip(cpu_t *cpu)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2863 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2864 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2865 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2866 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2867
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2868 uint_t
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2869 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2870 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2871 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2872 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2873 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2874
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2875 id_t
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2876 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2877 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2878 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2879 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2880 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2881
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2882 uint_t
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2883 cpuid_getstep(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2884 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2885 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2886 return (cpu->cpu_m.mcpu_cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2887 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2888
4581 b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2889 uint_t
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2890 cpuid_getsig(struct cpu *cpu)
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2891 {
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2892 ASSERT(cpuid_checkpass(cpu, 1));
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2893 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2894 }
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	2895
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2896 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2897 cpuid_getchiprev(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2898 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2899 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2900 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2901 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2902
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2903 const char *
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2904 cpuid_getchiprevstr(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2905 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2906 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2907 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2908 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2909
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2910 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2911 cpuid_getsockettype(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2912 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2913 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2914 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2915 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	2916
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2917 const char *
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2918 cpuid_getsocketstr(cpu_t *cpu)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2919 {
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2920 static const char *socketstr = NULL;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2921 struct cpuid_info *cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2922
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2923 ASSERT(cpuid_checkpass(cpu, 1));
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2924 cpi = cpu->cpu_m.mcpu_cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2925
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2926 /* Assume that socket types are the same across the system */
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2927 if (socketstr == NULL)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2928 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2929 cpi->cpi_model, cpi->cpi_step);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2930
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2931
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2932 return (socketstr);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2933 }
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	2934
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2935 int
5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2936 cpuid_get_chipid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2937 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2938 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2939
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2940 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2941 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2942 return (cpu->cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2943 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2944
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2945 id_t
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2946 cpuid_get_coreid(cpu_t *cpu)
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2947 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2948 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2949 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2950 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2951
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2952 int
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2953 cpuid_get_pkgcoreid(cpu_t *cpu)
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2954 {
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2955 ASSERT(cpuid_checkpass(cpu, 1));
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2956 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2957 }
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2958
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	2959 int
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	2960 cpuid_get_clogid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2961 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2962 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2963 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2964 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2965
11389 dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2966 int
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2967 cpuid_get_cacheid(cpu_t *cpu)
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2968 {
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2969 ASSERT(cpuid_checkpass(cpu, 1));
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2970 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2971 }
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	2972
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2973 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2974 cpuid_get_procnodeid(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2975 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2976 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2977 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2978 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2979
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2980 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2981 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2982 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2983 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2984 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2985 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	2986
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2987 /ARGSUSED/
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2988 int
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2989 cpuid_have_cr8access(cpu_t *cpu)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2990 {
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2991 #if defined(__amd64)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2992 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2993 #else
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2994 struct cpuid_info *cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2995
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2996 ASSERT(cpu != NULL);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2997 cpi = cpu->cpu_m.mcpu_cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2998 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	2999 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3000 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3001 return (0);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3002 #endif
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3003 }
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3004
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3005 uint32_t
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3006 cpuid_get_apicid(cpu_t *cpu)
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3007 {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3008 ASSERT(cpuid_checkpass(cpu, 1));
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3009 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3010 return (UINT32_MAX);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3011 } else {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3012 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3013 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3014 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3015
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3016 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3017 cpuid_get_addrsize(cpu_t cpu, uint_t pabits, uint_t *vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3018 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3019 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3020
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3021 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3022 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3023 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3024
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3025 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3026
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3027 if (pabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3028 *pabits = cpi->cpi_pabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3029 if (vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3030 *vabits = cpi->cpi_vabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3031 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3032
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3033 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3034 * Returns the number of data TLB entries for a corresponding
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3035 * pagesize. If it can't be computed, or isn't known, the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3036 * routine returns zero. If you ask about an architecturally
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3037 * impossible pagesize, the routine will panic (so that the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3038 * hat implementor knows that things are inconsistent.)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3039 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3040 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3041 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3042 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3043 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3044 uint_t dtlb_nent = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3045
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3046 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3047 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3048 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3049
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3050 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3051
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3052 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3053 * Check the L2 TLB info
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3054 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3055 if (cpi->cpi_xmaxeax >= 0x80000006) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3056 struct cpuid_regs *cp = &cpi->cpi_extd[6];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3057
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3058 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3059
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3060 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3061 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3062 * All zero in the top 16 bits of the register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3063 * indicates a unified TLB. Size is in low 16 bits.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3064 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3065 if ((cp->cp_ebx & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3066 dtlb_nent = cp->cp_ebx & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3067 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3068 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3069 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3070
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3071 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3072 if ((cp->cp_eax & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3073 dtlb_nent = cp->cp_eax & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3074 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3075 dtlb_nent = BITX(cp->cp_eax, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3076 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3077
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3078 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3079 panic("unknown L2 pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3080 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3081 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3082 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3083
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3084 if (dtlb_nent != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3085 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3086
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3087 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3088 * No L2 TLB support for this size, try L1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3089 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3090 if (cpi->cpi_xmaxeax >= 0x80000005) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3091 struct cpuid_regs *cp = &cpi->cpi_extd[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3092
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3093 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3094 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3095 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3096 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3097 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3098 dtlb_nent = BITX(cp->cp_eax, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3099 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3100 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3101 panic("unknown L1 d-TLB pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3102 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3103 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3104 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3105
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3106 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3107 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3108
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3109 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3110 * Return 0 if the erratum is not present or not applicable, positive
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3111 * if it is, and negative if the status of the erratum is unknown.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3112 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3113 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	3114 * Processors" #25759, Rev 3.57, August 2005
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3115 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3116 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3117 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3118 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3119 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3120 uint_t eax;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3121
2584 c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3122 /*
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3123 * Bail out if this CPU isn't an AMD CPU, or if it's
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3124 * a legacy (32-bit) AMD CPU.
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3125 */
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3126 if (cpi->cpi_vendor != X86_VENDOR_AMD \|\|
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3127 cpi->cpi_family == 4 \|\| cpi->cpi_family == 5 \|\|
6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3128 cpi->cpi_family == 6)
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3129
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3130 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3131
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3132 eax = cpi->cpi_std[1].cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3133
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3134 #define SH_B0(eax) (eax == 0xf40 \|\| eax == 0xf50)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3135 #define SH_B3(eax) (eax == 0xf51)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3136 #define B(eax) (SH_B0(eax) \|\| SH_B3(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3137
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3138 #define SH_C0(eax) (eax == 0xf48 \|\| eax == 0xf58)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3139
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3140 #define SH_CG(eax) (eax == 0xf4a \|\| eax == 0xf5a \|\| eax == 0xf7a)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3141 #define DH_CG(eax) (eax == 0xfc0 \|\| eax == 0xfe0 \|\| eax == 0xff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3142 #define CH_CG(eax) (eax == 0xf82 \|\| eax == 0xfb2)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3143 #define CG(eax) (SH_CG(eax) \|\| DH_CG(eax) \|\| CH_CG(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3144
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3145 #define SH_D0(eax) (eax == 0x10f40 \|\| eax == 0x10f50 \|\| eax == 0x10f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3146 #define DH_D0(eax) (eax == 0x10fc0 \|\| eax == 0x10ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3147 #define CH_D0(eax) (eax == 0x10f80 \|\| eax == 0x10fb0)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3148 #define D0(eax) (SH_D0(eax) \|\| DH_D0(eax) \|\| CH_D0(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3149
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3150 #define SH_E0(eax) (eax == 0x20f50 \|\| eax == 0x20f40 \|\| eax == 0x20f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3151 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3152 #define DH_E3(eax) (eax == 0x20fc0 \|\| eax == 0x20ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3153 #define SH_E4(eax) (eax == 0x20f51 \|\| eax == 0x20f71)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3154 #define BH_E4(eax) (eax == 0x20fb1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3155 #define SH_E5(eax) (eax == 0x20f42)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3156 #define DH_E6(eax) (eax == 0x20ff2 \|\| eax == 0x20fc2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3157 #define JH_E6(eax) (eax == 0x20f12 \|\| eax == 0x20f32)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3158 #define EX(eax) (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3159 SH_E4(eax) \|\| BH_E4(eax) \|\| SH_E5(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3160 DH_E6(eax) \|\| JH_E6(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3161
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3162 #define DR_AX(eax) (eax == 0x100f00 \|\| eax == 0x100f01 \|\| eax == 0x100f02)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3163 #define DR_B0(eax) (eax == 0x100f20)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3164 #define DR_B1(eax) (eax == 0x100f21)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3165 #define DR_BA(eax) (eax == 0x100f2a)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3166 #define DR_B2(eax) (eax == 0x100f22)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3167 #define DR_B3(eax) (eax == 0x100f23)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3168 #define RB_C0(eax) (eax == 0x100f40)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3169
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3170 switch (erratum) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3171 case 1:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3172 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3173 case 51: /* what does the asterisk mean? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3174 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3175 case 52:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3176 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3177 case 57:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3178 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3179 case 58:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3180 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3181 case 60:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3182 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3183 case 61:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3184 case 62:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3185 case 63:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3186 case 64:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3187 case 65:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3188 case 66:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3189 case 68:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3190 case 69:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3191 case 70:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3192 case 71:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3193 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3194 case 72:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3195 return (SH_B0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3196 case 74:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3197 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3198 case 75:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3199 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3200 case 76:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3201 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3202 case 77:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3203 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3204 case 78:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3205 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3206 case 79:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3207 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3208 case 80:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3209 case 81:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3210 case 82:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3211 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3212 case 83:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3213 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3214 case 85:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3215 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3216 case 86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3217 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3218 case 88:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3219 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3220 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3221 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3222 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3223 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3224 case 89:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3225 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3226 case 90:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3227 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3228 case 91:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3229 case 92:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3230 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3231 case 93:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3232 return (SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3233 case 94:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3234 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3235 case 95:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3236 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3237 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3238 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3239 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3240 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3241 case 96:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3242 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3243 case 97:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3244 case 98:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3245 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3246 case 99:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3247 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3248 case 100:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3249 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3250 case 101:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3251 case 103:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3252 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3253 case 104:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3254 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3255 case 105:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3256 case 106:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3257 case 107:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3258 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3259 case 108:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3260 return (DH_CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3261 case 109:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3262 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3263 case 110:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3264 return (D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3265 case 111:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3266 return (CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3267 case 112:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3268 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3269 case 113:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3270 return (eax == 0x20fc0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3271 case 114:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3272 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3273 case 115:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3274 return (SH_E0(eax) \|\| JH_E1(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3275 case 116:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3276 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3277 case 117:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3278 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3279 case 118:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3280 return (SH_E0(eax) \|\| JH_E1(eax) \|\| SH_E4(eax) \|\| BH_E4(eax) \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3281 JH_E6(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3282 case 121:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3283 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3284 case 122:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3285 return (cpi->cpi_family < 0x10 \|\| cpi->cpi_family == 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3286 case 123:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3287 return (JH_E1(eax) \|\| BH_E4(eax) \|\| JH_E6(eax));
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	3288 case 131:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3289 return (cpi->cpi_family < 0x10);
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3290 case 6336786:
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3291 /*
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3292 * Test for AdvPowerMgmtInfo.TscPStateInvariant
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3293 * if this is a K8 family or newer processor
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3294 */
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3295 if (CPI_FAMILY(cpi) == 0xf) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3296 struct cpuid_regs regs;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3297 regs.cp_eax = 0x80000007;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3298 (void) __cpuid_insn(&regs);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3299 return (!(regs.cp_edx & 0x100));
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3300 }
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3301 return (0);
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3302 case 6323525:
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3303 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) \|
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3304 (((eax >> 4) & 0xf) \| ((eax >> 12) & 0xf0))) < 0xf40);
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3305
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3306 case 6671130:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3307 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3308 * check for processors (pre-Shanghai) that do not provide
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3309 * optimal management of 1gb ptes in its tlb.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3310 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3311 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3312
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3313 case 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3314 return (DR_AX(eax) \|\| DR_B0(eax) \|\| DR_B1(eax) \|\| DR_BA(eax) \|\|
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3315 DR_B2(eax) \|\| RB_C0(eax));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3316
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3317 default:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3318 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3319
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3320 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3321 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3322
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3323 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3324 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3325 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3326 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3327 int
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3328 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3329 {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3330 struct cpuid_info *cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3331 uint_t osvwid;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3332 static int osvwfeature = -1;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3333 uint64_t osvwlength;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3334
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3335
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3336 cpi = cpu->cpu_m.mcpu_cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3337
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3338 /* confirm OSVW supported */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3339 if (osvwfeature == -1) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3340 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3341 } else {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3342 /* assert that osvw feature setting is consistent on all cpus */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3343 ASSERT(osvwfeature ==
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3344 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3345 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3346 if (!osvwfeature)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3347 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3348
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3349 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3350
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3351 switch (erratum) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3352 case 298: /* osvwid is 0 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3353 osvwid = 0;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3354 if (osvwlength <= (uint64_t)osvwid) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3355 /* osvwid 0 is unknown */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3356 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3357 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3358
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3359 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3360 * Check the OSVW STATUS MSR to determine the state
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3361 * of the erratum where:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3362 * 0 - fixed by HW
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3363 * 1 - BIOS has applied the workaround when BIOS
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3364 * workaround is available. (Or for other errata,
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3365 * OS workaround is required.)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3366 * For a value of 1, caller will confirm that the
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3367 * erratum 298 workaround has indeed been applied by BIOS.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3368 *
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3369 * A 1 may be set in cpus that have a HW fix
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3370 * in a mixed cpu system. Regarding erratum 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3371 * In a multiprocessor platform, the workaround above
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3372 * should be applied to all processors regardless of
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3373 * silicon revision when an affected processor is
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3374 * present.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3375 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3376
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3377 return (rdmsr(MSR_AMD_OSVW_STATUS +
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3378 (osvwid / OSVW_ID_CNT_PER_MSR)) &
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3379 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3380
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3381 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3382 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3383 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3384 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3385
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3386 static const char assoc_str[] = "associativity";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3387 static const char line_str[] = "line-size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3388 static const char size_str[] = "size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3389
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3390 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3391 add_cache_prop(dev_info_t devi, const char label, const char *type,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3392 uint32_t val)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3393 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3394 char buf[128];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3395
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3396 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3397 * ndi_prop_update_int() is used because it is desirable for
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3398 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3399 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3400 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3401 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3402 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3403
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3404 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3405 * Intel-style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3406 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3407 * Standard cpuid level 2 gives a randomly ordered
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3408 * selection of tags that index into a table that describes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3409 * cache and tlb properties.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3410 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3411
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3412 static const char l1_icache_str[] = "l1-icache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3413 static const char l1_dcache_str[] = "l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3414 static const char l2_cache_str[] = "l2-cache";
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3415 static const char l3_cache_str[] = "l3-cache";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3416 static const char itlb4k_str[] = "itlb-4K";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3417 static const char dtlb4k_str[] = "dtlb-4K";
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3418 static const char itlb2M_str[] = "itlb-2M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3419 static const char itlb4M_str[] = "itlb-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3420 static const char dtlb4M_str[] = "dtlb-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3421 static const char dtlb24_str[] = "dtlb0-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3422 static const char itlb424_str[] = "itlb-4K-2M-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3423 static const char itlb24_str[] = "itlb-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3424 static const char dtlb44_str[] = "dtlb-4K-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3425 static const char sl1_dcache_str[] = "sectored-l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3426 static const char sl2_cache_str[] = "sectored-l2-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3427 static const char itrace_str[] = "itrace-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3428 static const char sl3_cache_str[] = "sectored-l3-cache";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3429 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3430
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3431 static const struct cachetab {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3432 uint8_t ct_code;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3433 uint8_t ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3434 uint16_t ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3435 size_t ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3436 const char *ct_label;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3437 } intel_ctab[] = {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3438 /*
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3439 * maintain descending order!
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3440 *
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3441 * Codes ignored - Reason
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3442 * ----------------------
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3443 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3444 * f0H/f1H - Currently we do not interpret prefetch size by design
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3445 */
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3446 { 0xe4, 16, 64, 810241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3447 { 0xe3, 16, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3448 { 0xe2, 16, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3449 { 0xde, 12, 64, 610241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3450 { 0xdd, 12, 64, 310241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3451 { 0xdc, 12, 64, ((110241024)+(512*1024)), l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3452 { 0xd8, 8, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3453 { 0xd7, 8, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3454 { 0xd6, 8, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3455 { 0xd2, 4, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3456 { 0xd1, 4, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3457 { 0xd0, 4, 64, 512*1024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3458 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3459 { 0xc0, 4, 0, 8, dtlb44_str },
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3460 { 0xba, 4, 0, 64, dtlb4k_str },
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3461 { 0xb4, 4, 0, 256, dtlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3462 { 0xb3, 4, 0, 128, dtlb4k_str },
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3463 { 0xb2, 4, 0, 64, itlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3464 { 0xb0, 4, 0, 128, itlb4k_str },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3465 { 0x87, 8, 64, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3466 { 0x86, 4, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3467 { 0x85, 8, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3468 { 0x84, 8, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3469 { 0x83, 8, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3470 { 0x82, 8, 32, 256*1024, l2_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3471 { 0x80, 8, 64, 512*1024, l2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3472 { 0x7f, 2, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3473 { 0x7d, 8, 64, 210241024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3474 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3475 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3476 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3477 { 0x79, 8, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3478 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3479 { 0x73, 8, 0, 64*1024, itrace_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3480 { 0x72, 8, 0, 32*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3481 { 0x71, 8, 0, 16*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3482 { 0x70, 8, 0, 12*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3483 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3484 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3485 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3486 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3487 { 0x5d, 0, 0, 256, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3488 { 0x5c, 0, 0, 128, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3489 { 0x5b, 0, 0, 64, dtlb44_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3490 { 0x5a, 4, 0, 32, dtlb24_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3491 { 0x59, 0, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3492 { 0x57, 4, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3493 { 0x56, 4, 0, 16, dtlb4M_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3494 { 0x55, 0, 0, 7, itlb24_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3495 { 0x52, 0, 0, 256, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3496 { 0x51, 0, 0, 128, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3497 { 0x50, 0, 0, 64, itlb424_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3498 { 0x4f, 0, 0, 32, itlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3499 { 0x4e, 24, 64, 610241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3500 { 0x4d, 16, 64, 1610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3501 { 0x4c, 12, 64, 1210241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3502 { 0x4b, 16, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3503 { 0x4a, 12, 64, 610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3504 { 0x49, 16, 64, 410241024, l3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3505 { 0x48, 12, 64, 310241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3506 { 0x47, 8, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3507 { 0x46, 4, 64, 410241024, l3_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3508 { 0x45, 4, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3509 { 0x44, 4, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3510 { 0x43, 4, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3511 { 0x42, 4, 32, 256*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3512 { 0x41, 4, 32, 128*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3513 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3514 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3515 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3516 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3517 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3518 { 0x39, 4, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3519 { 0x30, 8, 64, 32*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3520 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3521 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3522 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3523 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3524 { 0x22, 4, 64, 512*1024, sl3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3525 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3526 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3527 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3528 { 0x0b, 4, 0, 4, itlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3529 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3530 { 0x08, 4, 32, 16*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3531 { 0x06, 4, 32, 8*1024, l1_icache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3532 { 0x05, 4, 0, 32, dtlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3533 { 0x04, 4, 0, 8, dtlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3534 { 0x03, 4, 0, 64, dtlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3535 { 0x02, 4, 0, 2, itlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3536 { 0x01, 4, 0, 32, itlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3537 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3538 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3539
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3540 static const struct cachetab cyrix_ctab[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3541 { 0x70, 4, 0, 32, "tlb-4K" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3542 { 0x80, 4, 16, 16*1024, "l1-cache" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3543 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3544 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3545
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3546 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3547 * Search a cache table for a matching entry
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3548 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3549 static const struct cachetab *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3550 find_cacheent(const struct cachetab *ct, uint_t code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3551 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3552 if (code != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3553 for (; ct->ct_code != 0; ct++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3554 if (ct->ct_code <= code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3555 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3556 if (ct->ct_code == code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3557 return (ct);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3558 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3559 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3560 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3561
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3562 /*
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3563 * Populate cachetab entry with L2 or L3 cache-information using
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3564 * cpuid function 4. This function is called from intel_walk_cacheinfo()
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3565 * when descriptor 0x49 is encountered. It returns 0 if no such cache
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3566 * information is found.
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3567 */
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3568 static int
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3569 intel_cpuid_4_cache_info(struct cachetab ct, struct cpuid_info cpi)
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3570 {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3571 uint32_t level, i;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3572 int ret = 0;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3573
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3574 for (i = 0; i < cpi->cpi_std_4_size; i++) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3575 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3576
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3577 if (level == 2 \|\| level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3578 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3579 ct->ct_line_size =
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3580 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3581 ct->ct_size = ct->ct_assoc *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3582 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3583 ct->ct_line_size *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3584 (cpi->cpi_std_4[i]->cp_ecx + 1);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3585
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3586 if (level == 2) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3587 ct->ct_label = l2_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3588 } else if (level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3589 ct->ct_label = l3_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3590 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3591 ret = 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3592 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3593 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3594
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3595 return (ret);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3596 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3597
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3598 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3599 * Walk the cacheinfo descriptor, applying 'func' to every valid element
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3600 * The walk is terminated if the walker returns non-zero.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3601 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3602 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3603 intel_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3604 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3605 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3606 const struct cachetab *ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3607 struct cachetab des_49_ct, des_b1_ct;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3608 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3609 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3610
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3611 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3612 return;
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3613 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3614 /*
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3615 * For overloaded descriptor 0x49 we use cpuid function 4
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3616 * if supported by the current processor, to create
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3617 * cache information.
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3618 * For overloaded descriptor 0xb1 we use X86_PAE flag
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3619 * to disambiguate the cache information.
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3620 */
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3621 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3622 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3623 ct = &des_49_ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3624 } else if (*dp == 0xb1) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3625 des_b1_ct.ct_code = 0xb1;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3626 des_b1_ct.ct_assoc = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3627 des_b1_ct.ct_line_size = 0;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	3628 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3629 des_b1_ct.ct_size = 8;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3630 des_b1_ct.ct_label = itlb2M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3631 } else {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3632 des_b1_ct.ct_size = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3633 des_b1_ct.ct_label = itlb4M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3634 }
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3635 ct = &des_b1_ct;
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3636 } else {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3637 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3638 continue;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3639 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3640 }
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3641
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3642 if (func(arg, ct) != 0) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3643 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3644 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3645 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3646 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3647
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3648 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3649 * (Like the Intel one, except for Cyrix CPUs)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3650 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3651 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3652 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3653 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3654 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3655 const struct cachetab *ct;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3656 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3657 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3658
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3659 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3660 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3661 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3662 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3663 * Search Cyrix-specific descriptor table first ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3664 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3665 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3666 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3667 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3668 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3669 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3670 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3671 * .. else fall back to the Intel one
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3672 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3673 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3674 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3675 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3676 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3677 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3678 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3679 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3680
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3681 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3682 * A cacheinfo walker that adds associativity, line-size, and size properties
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3683 * to the devinfo node it is passed as an argument.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3684 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3685 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3686 add_cacheent_props(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3687 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3688 dev_info_t *devi = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3689
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3690 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3691 if (ct->ct_line_size != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3692 add_cache_prop(devi, ct->ct_label, line_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3693 ct->ct_line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3694 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3695 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3696 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3697
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3698
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3699 static const char fully_assoc[] = "fully-associative?";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3700
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3701 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3702 * AMD style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3703 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3704 * Extended functions 5 and 6 directly describe properties of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3705 * tlbs and various cache levels.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3706 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3707 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3708 add_amd_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3709 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3710 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3711 case 0: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3712 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3713 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3714 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3715 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3716 case 0xff:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3717 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3718 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3719 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3720 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3721
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3722 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3723 add_amd_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3724 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3725 if (size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3726 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3727 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3728 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3729 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3730
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3731 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3732 add_amd_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3733 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3734 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3735 if (size == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3736 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3737 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3738 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3739 * Most AMD parts have a sectored cache. Multiple cache lines are
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3740 * associated with each tag. A sector consists of all cache lines
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3741 * associated with a tag. For example, the AMD K6-III has a sector
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3742 * size of 2 cache lines per tag.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3743 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3744 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3745 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3746 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3747 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3748 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3749
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3750 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3751 add_amd_l2_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3752 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3753 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3754 case 0: /* off */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3755 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3756 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3757 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3758 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3759 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3760 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3761 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3762 add_cache_prop(devi, label, assoc_str, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3763 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3764 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3765 add_cache_prop(devi, label, assoc_str, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3766 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3767 case 0xf:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3768 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3769 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3770 default: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3771 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3772 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3773 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3774
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3775 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3776 add_amd_l2_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3777 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3778 if (size == 0 \|\| assoc == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3779 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3780 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3781 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3782 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3783
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3784 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3785 add_amd_l2_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3786 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3787 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3788 if (size == 0 \|\| assoc == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3789 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3790 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3791 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3792 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3793 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3794 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3795 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3796
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3797 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3798 amd_cache_info(struct cpuid_info cpi, dev_info_t devi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3799 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3800 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3801
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3802 if (cpi->cpi_xmaxeax < 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3803 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3804 cp = &cpi->cpi_extd[5];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3805
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3806 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3807 * 4M/2M L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3808 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3809 * We report the size for 2M pages because AMD uses two
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3810 * TLB entries for one 4M page.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3811 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3812 add_amd_tlb(devi, "dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3813 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3814 add_amd_tlb(devi, "itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3815 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3816
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3817 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3818 * 4K L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3819 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3820
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3821 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3822 uint_t nentries;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3823 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3824 if (cpi->cpi_family >= 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3825 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3826 * Crusoe processors have 256 TLB entries, but
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3827 * cpuid data format constrains them to only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3828 * reporting 255 of them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3829 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3830 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3831 nentries = 256;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3832 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3833 * Crusoe processors also have a unified TLB
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3834 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3835 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3836 nentries);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3837 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3838 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3839 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3840 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3841 add_amd_tlb(devi, itlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3842 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3843 add_amd_tlb(devi, dtlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3844 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3845 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3846 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3847
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3848 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3849 * data L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3850 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3851
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3852 add_amd_cache(devi, l1_dcache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3853 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3854 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3855
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3856 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3857 * code L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3858 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3859
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3860 add_amd_cache(devi, l1_icache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3861 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3862 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3863
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3864 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3865 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3866 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3867
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3868 /* Check for a unified L2 TLB for large pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3869
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3870 if (BITX(cp->cp_eax, 31, 16) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3871 add_amd_l2_tlb(devi, "l2-tlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3872 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3873 else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3874 add_amd_l2_tlb(devi, "l2-dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3875 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3876 add_amd_l2_tlb(devi, "l2-itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3877 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3878 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3879
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3880 /* Check for a unified L2 TLB for 4K pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3881
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3882 if (BITX(cp->cp_ebx, 31, 16) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3883 add_amd_l2_tlb(devi, "l2-tlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3884 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3885 } else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3886 add_amd_l2_tlb(devi, "l2-dtlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3887 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3888 add_amd_l2_tlb(devi, "l2-itlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3889 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3890 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3891
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3892 add_amd_l2_cache(devi, l2_cache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3893 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3894 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3895 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3896
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3897 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3898 * There are two basic ways that the x86 world describes it cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3899 * and tlb architecture - Intel's way and AMD's way.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3900 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3901 * Return which flavor of cache architecture we should use
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3902 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3903 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3904 x86_which_cacheinfo(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3905 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3906 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3907 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3908 if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3909 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3910 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3911 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3912 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3913 * The K5 model 1 was the first part from AMD that reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3914 * cache sizes via extended cpuid functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3915 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3916 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3917 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3918 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3919 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3920 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3921 if (cpi->cpi_family >= 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3922 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3923 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3924 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3925 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3926 * If they have extended CPU data for 0x80000005
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3927 * then we assume they have AMD-format cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3928 * information.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3929 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3930 * If not, and the vendor happens to be Cyrix,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3931 * then try our-Cyrix specific handler.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3932 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3933 * If we're not Cyrix, then assume we're using Intel's
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3934 * table-driven format instead.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3935 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3936 if (cpi->cpi_xmaxeax >= 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3937 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3938 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3939 return (X86_VENDOR_Cyrix);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3940 else if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3941 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3942 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3943 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3944 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3945 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3946
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3947 void
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3948 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3949 struct cpuid_info *cpi)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3950 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3951 dev_info_t *cpu_devi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3952 int create;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3953
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3954 cpu_devi = (dev_info_t *)dip;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3955
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3956 /* device_type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3957 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3958 "device_type", "cpu");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3959
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3960 /* reg */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3961 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3962 "reg", cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3963
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3964 /* cpu-mhz, and clock-frequency */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3965 if (cpu_freq > 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3966 long long mul;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3967
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3968 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3969 "cpu-mhz", cpu_freq);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3970 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3971 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3972 "clock-frequency", (int)mul);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3973 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3974
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	3975 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3976 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3977 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3978
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3979 /* vendor-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3980 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3981 "vendor-id", cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3982
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3983 if (cpi->cpi_maxeax == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3984 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3985 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3986
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3987 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3988 * family, model, and step
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3989 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3990 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3991 "family", CPI_FAMILY(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3992 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3993 "cpu-model", CPI_MODEL(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3994 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	3995 "stepping-id", CPI_STEP(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3996
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3997 /* type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3998 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3999 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4000 create = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4001 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4002 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4003 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4004 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4005 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4006 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4007 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4008 "type", CPI_TYPE(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4009
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4010 /* ext-family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4011 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4012 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4013 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4014 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4015 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4016 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4017 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4018 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4019 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4020 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4021 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4022 "ext-family", CPI_FAMILY_XTD(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4023
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4024 /* ext-model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4025 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4026 case X86_VENDOR_Intel:
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	4027 create = IS_EXTENDED_MODEL_INTEL(cpi);
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	4028 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4029 case X86_VENDOR_AMD:
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	4030 create = CPI_FAMILY(cpi) == 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4031 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4032 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4033 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4034 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4035 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4036 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4037 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4038 "ext-model", CPI_MODEL_XTD(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4039
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4040 /* generation */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4041 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4042 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4043 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4044 * AMD K5 model 1 was the first part to support this
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4045 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4046 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4047 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4048 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4049 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4050 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4051 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4052 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4053 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4054 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4055
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4056 /* brand-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4057 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4058 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4059 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4060 * brand id first appeared on Pentium III Xeon model 8,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4061 * and Celeron model 8 processors and Opteron
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4062 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4063 create = cpi->cpi_family > 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4064 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4065 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4066 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4067 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4068 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4069 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4070 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4071 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4072 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4073 if (create && cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4074 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4075 "brand-id", cpi->cpi_brandid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4076 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4077
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4078 /* chunks, and apic-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4079 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4080 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4081 * first available on Pentium IV and Opteron (K8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4082 */
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4083 case X86_VENDOR_Intel:
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4084 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4085 break;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4086 case X86_VENDOR_AMD:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4087 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4088 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4089 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4090 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4091 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4092 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4093 if (create) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4094 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4095 "chunks", CPI_CHUNKS(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4096 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	4097 "apic-id", cpi->cpi_apicid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4098 if (cpi->cpi_chipid >= 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4099 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4100 "chip#", cpi->cpi_chipid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4101 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4102 "clog#", cpi->cpi_clogid);
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4103 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4104 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4105
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4106 /* cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4107 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4108 "cpuid-features", CPI_FEATURES_EDX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4109
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4110
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4111 /* cpuid-features-ecx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4112 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4113 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4114 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4115 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4116 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4117 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4118 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4119 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4120 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4121 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4122 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4123
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4124 /* ext-cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4125 switch (cpi->cpi_vendor) {
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4126 case X86_VENDOR_Intel:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4127 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4128 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4129 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4130 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4131 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4132 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4133 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4134 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4135 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4136 }
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4137 if (create) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4138 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4139 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4140 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4141 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4142 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4143
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4144 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4145 * Brand String first appeared in Intel Pentium IV, AMD K5
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4146 * model 1, and Cyrix GXm. On earlier models we try and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4147 * simulate something similar .. so this string should always
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4148 * same -something- about the processor, however lame.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4149 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4150 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4151 "brand-string", cpi->cpi_brandstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4152
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4153 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4154 * Finally, cache and tlb information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4155 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4156 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4157 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4158 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4159 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4160 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4161 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4162 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4163 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4164 amd_cache_info(cpi, cpu_devi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4165 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4166 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4167 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4168 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4169 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4170
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4171 struct l2info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4172 int *l2i_csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4173 int *l2i_lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4174 int *l2i_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4175 int l2i_ret;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4176 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4177
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4178 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4179 * A cacheinfo walker that fetches the size, line-size and associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4180 * of the L2 cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4181 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4182 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4183 intel_l2cinfo(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4184 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4185 struct l2info *l2i = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4186 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4187
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4188 if (ct->ct_label != l2_cache_str &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4189 ct->ct_label != sl2_cache_str)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4190 return (0); /* not an L2 -- keep walking */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4191
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4192 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4193 *ip = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4194 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4195 *ip = ct->ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4196 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4197 *ip = ct->ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4198 l2i->l2i_ret = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4199 return (1); /* was an L2 -- terminate walk */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4200 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4201
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4202 /*
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4203 * AMD L2/L3 Cache and TLB Associativity Field Definition:
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4204 *
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4205 * Unlike the associativity for the L1 cache and tlb where the 8 bit
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4206 * value is the associativity, the associativity for the L2 cache and
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4207 * tlb is encoded in the following table. The 4 bit L2 value serves as
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4208 * an index into the amd_afd[] array to determine the associativity.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4209 * -1 is undefined. 0 is fully associative.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4210 */
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4211
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4212 static int amd_afd[] =
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4213 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4214
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4215 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4216 amd_l2cacheinfo(struct cpuid_info cpi, struct l2info l2i)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4217 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	4218 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4219 uint_t size, assoc;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4220 int i;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4221 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4222
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4223 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4224 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4225 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4226
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4227 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4228 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4229 uint_t cachesz = size * 1024;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4230 assoc = amd_afd[i];
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4231
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4232 ASSERT(assoc != -1);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4233
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4234 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4235 *ip = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4236 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4237 *ip = BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4238 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4239 *ip = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4240 l2i->l2i_ret = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4241 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4242 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4243
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4244 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4245 getl2cacheinfo(cpu_t cpu, int csz, int lsz, int assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4246 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4247 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4248 struct l2info __l2info, *l2i = &__l2info;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4249
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4250 l2i->l2i_csz = csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4251 l2i->l2i_lsz = lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4252 l2i->l2i_assoc = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4253 l2i->l2i_ret = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4254
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4255 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4256 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4257 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4258 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4259 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4260 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4261 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4262 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4263 amd_l2cacheinfo(cpi, l2i);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4264 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4265 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4266 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4267 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4268 return (l2i->l2i_ret);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4269 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4270
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4271 #if !defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4272
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4273 uint32_t *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4274 cpuid_mwait_alloc(cpu_t *cpu)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4275 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4276 uint32_t *ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4277 size_t mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4278
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4279 ASSERT(cpuid_checkpass(CPU, 2));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4280
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4281 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4282 if (mwait_size == 0)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4283 return (NULL);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4284
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4285 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4286 * kmem_alloc() returns cache line size aligned data for mwait_size
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4287 * allocations. mwait_size is currently cache line sized. Neither
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4288 * of these implementation details are guarantied to be true in the
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4289 * future.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4290 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4291 * First try allocating mwait_size as kmem_alloc() currently returns
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4292 * correctly aligned memory. If kmem_alloc() does not return
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4293 * mwait_size aligned memory, then use mwait_size ROUNDUP.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4294 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4295 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4296 * decide to free this memory.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4297 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4298 ret = kmem_zalloc(mwait_size, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4299 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4300 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4301 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4302 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4303 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4304 } else {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4305 kmem_free(ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4306 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4307 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4308 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4309 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4310 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4311 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4312 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4313 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4314
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4315 void
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4316 cpuid_mwait_free(cpu_t *cpu)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4317 {
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4318 if (cpu->cpu_m.mcpu_cpi == NULL) {
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4319 return;
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4320 }
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4321
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4322 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4323 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4324 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4325 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4326 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4327
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4328 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4329 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4330 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4331
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4332 void
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4333 patch_tsc_read(int flag)
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4334 {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4335 size_t cnt;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	4336
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4337 switch (flag) {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4338 case X86_NO_TSC:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4339 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4340 (void) memcpy((void )tsc_read, (void )&_no_rdtsc_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4341 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4342 case X86_HAVE_TSCP:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4343 cnt = &_tscp_end - &_tscp_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4344 (void) memcpy((void )tsc_read, (void )&_tscp_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4345 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4346 case X86_TSC_MFENCE:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4347 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4348 (void) memcpy((void *)tsc_read,
fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4349 (void *)&_tsc_mfence_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4350 break;
6642 c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4351 case X86_TSC_LFENCE:
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4352 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4353 (void) memcpy((void *)tsc_read,
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4354 (void *)&_tsc_lfence_start, cnt);
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4355 break;
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4356 default:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4357 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4358 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4359 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4360
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4361 int
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4362 cpuid_deep_cstates_supported(void)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4363 {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4364 struct cpuid_info *cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4365 struct cpuid_regs regs;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4366
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4367 ASSERT(cpuid_checkpass(CPU, 1));
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4368
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4369 cpi = CPU->cpu_m.mcpu_cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4370
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4371 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4372 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4373
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4374 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4375 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4376 if (cpi->cpi_xmaxeax < 0x80000007)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4377 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4378
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4379 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4380 * TSC run at a constant rate in all ACPI C-states?
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4381 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4382 regs.cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4383 (void) __cpuid_insn(&regs);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4384 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4385
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4386 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4387 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4388 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4389 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4390
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4391 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4392
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4393 void
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4394 post_startup_cpu_fixups(void)
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4395 {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4396 #ifndef __xpv
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4397 /*
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4398 * Some AMD processors support C1E state. Entering this state will
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4399 * cause the local APIC timer to stop, which we can't deal with at
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4400 * this time.
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4401 */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4402 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4403 on_trap_data_t otd;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4404 uint64_t reg;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4405
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4406 if (!on_trap(&otd, OT_DATA_ACCESS)) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4407 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4408 /* Disable C1E state if it is enabled by BIOS */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4409 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4410 AMD_ACTONCMPHALT_MASK) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4411 reg &= ~(AMD_ACTONCMPHALT_MASK <<
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4412 AMD_ACTONCMPHALT_SHIFT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4413 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4414 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4415 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4416 no_trap();
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4417 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4418 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4419 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4420
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4421 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4422 * Setup necessary registers to enable XSAVE feature on this processor.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4423 * This function needs to be called early enough, so that no xsave/xrstor
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4424 * ops will execute on the processor before the MSRs are properly set up.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4425 *
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4426 * Current implementation has the following assumption:
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4427 * - cpuid_pass1() is done, so that X86 features are known.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4428 * - fpu_probe() is done, so that fp_save_mech is chosen.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4429 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4430 void
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4431 xsave_setup_msr(cpu_t *cpu)
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4432 {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4433 ASSERT(fp_save_mech == FP_XSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4434 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4435
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4436 /* Enable OSXSAVE in CR4. */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4437 setcr4(getcr4() \| CR4_OSXSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4438 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4439 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4440 * correct value.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4441 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4442 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx \|= CPUID_INTC_ECX_OSXSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4443 setup_xfem();
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4444 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4445
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4446 /*
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4447 * Starting with the Westmere processor the local
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4448 * APIC timer will continue running in all C-states,
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4449 * including the deepest C-states.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4450 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4451 int
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4452 cpuid_arat_supported(void)
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4453 {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4454 struct cpuid_info *cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4455 struct cpuid_regs regs;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4456
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4457 ASSERT(cpuid_checkpass(CPU, 1));
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4458 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4459
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4460 cpi = CPU->cpu_m.mcpu_cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4461
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4462 switch (cpi->cpi_vendor) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4463 case X86_VENDOR_Intel:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4464 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4465 * Always-running Local APIC Timer is
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4466 * indicated by CPUID.6.EAX[2].
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4467 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4468 if (cpi->cpi_maxeax >= 6) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4469 regs.cp_eax = 6;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4470 (void) cpuid_insn(NULL, &regs);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4471 return (regs.cp_eax & CPUID_CSTATE_ARAT);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4472 } else {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4473 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4474 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4475 default:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4476 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4477 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4478 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4479
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4480 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4481 * Check support for Intel ENERGY_PERF_BIAS feature
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4482 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4483 int
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4484 cpuid_iepb_supported(struct cpu *cp)
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4485 {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4486 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4487 struct cpuid_regs regs;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4488
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4489 ASSERT(cpuid_checkpass(cp, 1));
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4490
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4491 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) \|\|
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4492 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4493 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4494 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4495
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4496 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4497 * Intel ENERGY_PERF_BIAS MSR is indicated by
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4498 * capability bit CPUID.6.ECX.3
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4499 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4500 if ((cpi->cpi_vendor != X86_VENDOR_Intel) \|\| (cpi->cpi_maxeax < 6))
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4501 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4502
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4503 regs.cp_eax = 0x6;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4504 (void) cpuid_insn(NULL, &regs);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4505 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4506 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4507
13041 2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4508 /*
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4509 * Check support for TSC deadline timer
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4510 *
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4511 * TSC deadline timer provides a superior software programming
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4512 * model over local APIC timer that eliminates "time drifts".
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4513 * Instead of specifying a relative time, software specifies an
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4514 * absolute time as the target at which the processor should
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4515 * generate a timer event.
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4516 */
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4517 int
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4518 cpuid_deadline_tsc_supported(void)
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4519 {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4520 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4521 struct cpuid_regs regs;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4522
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4523 ASSERT(cpuid_checkpass(CPU, 1));
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4524 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4525
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4526 switch (cpi->cpi_vendor) {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4527 case X86_VENDOR_Intel:
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4528 if (cpi->cpi_maxeax >= 1) {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4529 regs.cp_eax = 1;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4530 (void) cpuid_insn(NULL, &regs);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4531 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4532 } else {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4533 return (0);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4534 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4535 default:
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4536 return (0);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4537 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4538 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4539
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4540 #if defined(__amd64) && !defined(__xpv)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4541 /*
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4542 * Patch in versions of bcopy for high performance Intel Nhm processors
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4543 * and later...
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4544 */
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4545 void
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4546 patch_memops(uint_t vendor)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4547 {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4548 size_t cnt, i;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4549 caddr_t to, from;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4550
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4551 if ((vendor == X86_VENDOR_Intel) &&
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4552 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4553 cnt = &bcopy_patch_end - &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4554 to = &bcopy_ck_size;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4555 from = &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4556 for (i = 0; i < cnt; i++) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4557 to++ = from++;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4558 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4559 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4560 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4561 #endif /* __amd64 && !__xpv */
12261 52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4562
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4563 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4564 * This function finds the number of bits to represent the number of cores per
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4565 * chip and the number of strands per core for the Intel platforms.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4566 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4567 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4568 void
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4569 cpuid_get_ext_topo(uint_t vendor, uint_t core_nbits, uint_t strand_nbits)
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4570 {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4571 struct cpuid_regs regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4572 struct cpuid_regs *cp = &regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4573
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4574 if (vendor != X86_VENDOR_Intel) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4575 return;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4576 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4577
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4578 /* if the cpuid level is 0xB, extended topo is available. */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4579 cp->cp_eax = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4580 if (__cpuid_insn(cp) >= 0xB) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4581
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4582 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4583 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4584 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4585
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4586 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4587 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4588 * indicates that the extended topology enumeration leaf is
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4589 * available.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4590 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4591 if (cp->cp_ebx) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4592 uint_t coreid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4593 uint_t chipid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4594 uint_t i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4595 uint_t level;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4596
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4597 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4598 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4599 cp->cp_ecx = i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4600
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4601 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4602 level = CPI_CPU_LEVEL_TYPE(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4603
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4604 if (level == 1) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4605 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4606 * Thread level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4607 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4608 * to get the coreid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4609 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4610 coreid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4611 } else if (level == 2) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4612 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4613 * Core level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4614 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4615 * to get the chipid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4616 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4617 chipid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4618 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4619 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4620
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4621 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4622 *strand_nbits = coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4623 *core_nbits = chipid_shift - coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4624 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4625 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4626 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4627 }

Mercurial > illumos > illumos-gate

annotate usr/src/uts/i86pc/os/cpuid.c @ 13148:67d1861e02c1 onnv_147