Mercurial > illumos > illumos-gate
annotate usr/src/uts/i86pc/os/cpuid.c @ 13651:af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Reviewed by: Dan McDonald <danmcd@nexenta.com>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Albert Lee <trisk@nexenta.com>
Approved by: Richard Lowe <richlowe@richlowe.net>
| author | Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> |
|---|---|
| date | Thu, 29 Mar 2012 05:29:08 -0500 |
| parents | e702644ca141 |
| children | 0461a7e94e53 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * CDDL HEADER START | |
| 3 * | |
| 4 * The contents of this file are subject to the terms of the | |
|
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5 * Common Development and Distribution License (the "License"). |
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6 * You may not use this file except in compliance with the License. |
| 0 | 7 * |
| 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE | |
| 9 * or http://www.opensolaris.org/os/licensing. | |
| 10 * See the License for the specific language governing permissions | |
| 11 * and limitations under the License. | |
| 12 * | |
| 13 * When distributing Covered Code, include this CDDL HEADER in each | |
| 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. | |
| 15 * If applicable, add the following below this CDDL HEADER, with the | |
| 16 * fields enclosed by brackets "[]" replaced with your own identifying | |
| 17 * information: Portions Copyright [yyyy] [name of copyright owner] | |
| 18 * | |
| 19 * CDDL HEADER END | |
| 20 */ | |
| 21 /* | |
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22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. |
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23 * Copyright (c) 2011 by Delphix. All rights reserved. |
| 0 | 24 */ |
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25 /* |
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26 * Copyright (c) 2010, Intel Corporation. |
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27 * All rights reserved. |
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28 */ |
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29 /* |
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30 * Portions Copyright 2009 Advanced Micro Devices, Inc. |
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31 */ |
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32 /* |
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33 * Copyright (c) 2011, Joyent, Inc. All rights reserved. |
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34 */ |
| 0 | 35 /* |
| 36 * Various routines to handle identification | |
| 37 * and classification of x86 processors. | |
| 38 */ | |
| 39 | |
| 40 #include <sys/types.h> | |
| 41 #include <sys/archsystm.h> | |
| 42 #include <sys/x86_archext.h> | |
| 43 #include <sys/kmem.h> | |
| 44 #include <sys/systm.h> | |
| 45 #include <sys/cmn_err.h> | |
| 46 #include <sys/sunddi.h> | |
| 47 #include <sys/sunndi.h> | |
| 48 #include <sys/cpuvar.h> | |
| 49 #include <sys/processor.h> | |
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50 #include <sys/sysmacros.h> |
| 3434 | 51 #include <sys/pg.h> |
| 0 | 52 #include <sys/fp.h> |
| 53 #include <sys/controlregs.h> | |
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54 #include <sys/bitmap.h> |
| 0 | 55 #include <sys/auxv_386.h> |
| 56 #include <sys/memnode.h> | |
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57 #include <sys/pci_cfgspace.h> |
| 0 | 58 |
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59 #ifdef __xpv |
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60 #include <sys/hypervisor.h> |
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61 #else |
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62 #include <sys/ontrap.h> |
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63 #endif |
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64 |
| 0 | 65 /* |
| 66 * Pass 0 of cpuid feature analysis happens in locore. It contains special code | |
| 67 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with | |
| 68 * them accordingly. For most modern processors, feature detection occurs here | |
| 69 * in pass 1. | |
| 70 * | |
| 71 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() | |
| 72 * for the boot CPU and does the basic analysis that the early kernel needs. | |
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73 * x86_featureset is set based on the return value of cpuid_pass1() of the boot |
| 0 | 74 * CPU. |
| 75 * | |
| 76 * Pass 1 includes: | |
| 77 * | |
| 78 * o Determining vendor/model/family/stepping and setting x86_type and | |
| 79 * x86_vendor accordingly. | |
| 80 * o Processing the feature flags returned by the cpuid instruction while | |
| 81 * applying any workarounds or tricks for the specific processor. | |
| 82 * o Mapping the feature flags into Solaris feature bits (X86_*). | |
| 83 * o Processing extended feature flags if supported by the processor, | |
| 84 * again while applying specific processor knowledge. | |
| 85 * o Determining the CMT characteristics of the system. | |
| 86 * | |
| 87 * Pass 1 is done on non-boot CPUs during their initialization and the results | |
| 88 * are used only as a meager attempt at ensuring that all processors within the | |
| 89 * system support the same features. | |
| 90 * | |
| 91 * Pass 2 of cpuid feature analysis happens just at the beginning | |
| 92 * of startup(). It just copies in and corrects the remainder | |
| 93 * of the cpuid data we depend on: standard cpuid functions that we didn't | |
| 94 * need for pass1 feature analysis, and extended cpuid functions beyond the | |
| 95 * simple feature processing done in pass1. | |
| 96 * | |
| 97 * Pass 3 of cpuid analysis is invoked after basic kernel services; in | |
| 98 * particular kernel memory allocation has been made available. It creates a | |
| 99 * readable brand string based on the data collected in the first two passes. | |
| 100 * | |
| 101 * Pass 4 of cpuid analysis is invoked after post_startup() when all | |
| 102 * the support infrastructure for various hardware features has been | |
| 103 * initialized. It determines which processor features will be reported | |
| 104 * to userland via the aux vector. | |
| 105 * | |
| 106 * All passes are executed on all CPUs, but only the boot CPU determines what | |
| 107 * features the kernel will use. | |
| 108 * | |
| 109 * Much of the worst junk in this file is for the support of processors | |
| 110 * that didn't really implement the cpuid instruction properly. | |
| 111 * | |
| 112 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, | |
| 113 * the pass numbers. Accordingly, changes to the pass code may require changes | |
| 114 * to the accessor code. | |
| 115 */ | |
| 116 | |
| 117 uint_t x86_vendor = X86_VENDOR_IntelClone; | |
| 118 uint_t x86_type = X86_TYPE_OTHER; | |
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119 uint_t x86_clflush_size = 0; |
| 0 | 120 |
| 121 uint_t pentiumpro_bug4046376; | |
| 122 uint_t pentiumpro_bug4064495; | |
| 123 | |
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124 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; |
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125 |
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126 static char *x86_feature_names[NUM_X86_FEATURES] = { |
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127 "lgpg", |
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128 "tsc", |
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129 "msr", |
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130 "mtrr", |
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131 "pge", |
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132 "de", |
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133 "cmov", |
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134 "mmx", |
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135 "mca", |
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136 "pae", |
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137 "cv8", |
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138 "pat", |
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139 "sep", |
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140 "sse", |
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141 "sse2", |
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142 "htt", |
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143 "asysc", |
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144 "nx", |
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145 "sse3", |
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146 "cx16", |
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147 "cmp", |
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148 "tscp", |
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149 "mwait", |
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150 "sse4a", |
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151 "cpuid", |
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152 "ssse3", |
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153 "sse4_1", |
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154 "sse4_2", |
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155 "1gpg", |
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156 "clfsh", |
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157 "64", |
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158 "aes", |
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159 "pclmulqdq", |
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160 "xsave", |
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161 "avx", |
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162 "vmx", |
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163 "svm" |
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164 }; |
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165 |
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166 boolean_t |
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167 is_x86_feature(void *featureset, uint_t feature) |
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168 { |
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169 ASSERT(feature < NUM_X86_FEATURES); |
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170 return (BT_TEST((ulong_t *)featureset, feature)); |
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171 } |
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172 |
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173 void |
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174 add_x86_feature(void *featureset, uint_t feature) |
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175 { |
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176 ASSERT(feature < NUM_X86_FEATURES); |
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177 BT_SET((ulong_t *)featureset, feature); |
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178 } |
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179 |
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180 void |
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181 remove_x86_feature(void *featureset, uint_t feature) |
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182 { |
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183 ASSERT(feature < NUM_X86_FEATURES); |
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184 BT_CLEAR((ulong_t *)featureset, feature); |
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185 } |
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186 |
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187 boolean_t |
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188 compare_x86_featureset(void *setA, void *setB) |
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189 { |
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190 /* |
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191 * We assume that the unused bits of the bitmap are always zero. |
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192 */ |
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193 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) { |
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194 return (B_TRUE); |
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195 } else { |
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196 return (B_FALSE); |
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197 } |
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198 } |
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199 |
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200 void |
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201 print_x86_featureset(void *featureset) |
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202 { |
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203 uint_t i; |
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204 |
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205 for (i = 0; i < NUM_X86_FEATURES; i++) { |
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206 if (is_x86_feature(featureset, i)) { |
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207 cmn_err(CE_CONT, "?x86_feature: %s\n", |
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208 x86_feature_names[i]); |
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209 } |
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210 } |
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211 } |
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212 |
| 0 | 213 uint_t enable486; |
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214 |
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215 static size_t xsave_state_size = 0; |
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216 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE); |
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217 boolean_t xsave_force_disable = B_FALSE; |
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218 |
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219 /* |
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220 * This is set to platform type Solaris is running on. |
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221 */ |
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222 static int platform_type = -1; |
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223 |
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224 #if !defined(__xpv) |
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225 /* |
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226 * Variable to patch if hypervisor platform detection needs to be |
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227 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0). |
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228 */ |
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229 int enable_platform_detection = 1; |
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230 #endif |
| 0 | 231 |
| 232 /* | |
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233 * monitor/mwait info. |
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234 * |
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235 * size_actual and buf_actual are the real address and size allocated to get |
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236 * proper mwait_buf alignement. buf_actual and size_actual should be passed |
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237 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use |
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238 * processor cache-line alignment, but this is not guarantied in the furture. |
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239 */ |
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240 struct mwait_info { |
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241 size_t mon_min; /* min size to avoid missed wakeups */ |
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242 size_t mon_max; /* size to avoid false wakeups */ |
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243 size_t size_actual; /* size actually allocated */ |
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244 void *buf_actual; /* memory actually allocated */ |
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245 uint32_t support; /* processor support of monitor/mwait */ |
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246 }; |
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247 |
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248 /* |
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249 * xsave/xrestor info. |
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250 * |
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251 * This structure contains HW feature bits and size of the xsave save area. |
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252 * Note: the kernel will use the maximum size required for all hardware |
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253 * features. It is not optimize for potential memory savings if features at |
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254 * the end of the save area are not enabled. |
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255 */ |
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256 struct xsave_info { |
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257 uint32_t xsav_hw_features_low; /* Supported HW features */ |
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258 uint32_t xsav_hw_features_high; /* Supported HW features */ |
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259 size_t xsav_max_size; /* max size save area for HW features */ |
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260 size_t ymm_size; /* AVX: size of ymm save area */ |
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261 size_t ymm_offset; /* AVX: offset for ymm save area */ |
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262 }; |
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263 |
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264 |
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265 /* |
| 0 | 266 * These constants determine how many of the elements of the |
| 267 * cpuid we cache in the cpuid_info data structure; the | |
| 268 * remaining elements are accessible via the cpuid instruction. | |
| 269 */ | |
| 270 | |
| 271 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ | |
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272 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */ |
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273 |
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274 /* |
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275 * Some terminology needs to be explained: |
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276 * - Socket: Something that can be plugged into a motherboard. |
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277 * - Package: Same as socket |
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278 * - Chip: Same as socket. Note that AMD's documentation uses term "chip" |
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279 * differently: there, chip is the same as processor node (below) |
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280 * - Processor node: Some AMD processors have more than one |
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281 * "subprocessor" embedded in a package. These subprocessors (nodes) |
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282 * are fully-functional processors themselves with cores, caches, |
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283 * memory controllers, PCI configuration spaces. They are connected |
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284 * inside the package with Hypertransport links. On single-node |
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285 * processors, processor node is equivalent to chip/socket/package. |
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286 */ |
| 0 | 287 |
| 288 struct cpuid_info { | |
| 289 uint_t cpi_pass; /* last pass completed */ | |
| 290 /* | |
| 291 * standard function information | |
| 292 */ | |
| 293 uint_t cpi_maxeax; /* fn 0: %eax */ | |
| 294 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ | |
| 295 uint_t cpi_vendor; /* enum of cpi_vendorstr */ | |
| 296 | |
| 297 uint_t cpi_family; /* fn 1: extended family */ | |
| 298 uint_t cpi_model; /* fn 1: extended model */ | |
| 299 uint_t cpi_step; /* fn 1: stepping */ | |
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300 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */ |
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301 /* AMD: package/socket # */ |
| 0 | 302 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ |
| 303 int cpi_clogid; /* fn 1: %ebx: thread # */ | |
| 1228 | 304 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ |
| 0 | 305 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ |
| 306 uint_t cpi_ncache; /* fn 2: number of elements */ | |
| 4606 | 307 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ |
| 308 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ | |
| 309 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ | |
| 310 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ | |
| 1228 | 311 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ |
| 0 | 312 /* |
| 313 * extended function information | |
| 314 */ | |
| 315 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ | |
| 316 char cpi_brandstr[49]; /* fn 0x8000000[234] */ | |
| 317 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ | |
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318 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ |
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319 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */ |
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320 |
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321 id_t cpi_coreid; /* same coreid => strands share core */ |
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322 int cpi_pkgcoreid; /* core number within single package */ |
| 1228 | 323 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ |
| 324 /* Intel: fn 4: %eax[31-26] */ | |
| 0 | 325 /* |
| 326 * supported feature information | |
| 327 */ | |
| 3446 | 328 uint32_t cpi_support[5]; |
| 0 | 329 #define STD_EDX_FEATURES 0 |
| 330 #define AMD_EDX_FEATURES 1 | |
| 331 #define TM_EDX_FEATURES 2 | |
| 332 #define STD_ECX_FEATURES 3 | |
| 3446 | 333 #define AMD_ECX_FEATURES 4 |
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334 /* |
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335 * Synthesized information, where known. |
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336 */ |
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337 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ |
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338 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ |
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339 uint32_t cpi_socket; /* Chip package/socket type */ |
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340 |
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341 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ |
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342 uint32_t cpi_apicid; |
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343 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */ |
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344 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */ |
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345 /* Intel: 1 */ |
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346 |
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347 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */ |
| 0 | 348 }; |
| 349 | |
| 350 | |
| 351 static struct cpuid_info cpuid_info0; | |
| 352 | |
| 353 /* | |
| 354 * These bit fields are defined by the Intel Application Note AP-485 | |
| 355 * "Intel Processor Identification and the CPUID Instruction" | |
| 356 */ | |
| 357 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) | |
| 358 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) | |
| 359 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) | |
| 360 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) | |
| 361 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) | |
| 362 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) | |
| 363 | |
| 364 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) | |
| 365 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) | |
| 366 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) | |
| 367 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) | |
| 368 | |
| 369 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) | |
| 370 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) | |
| 371 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) | |
| 372 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) | |
| 373 | |
| 374 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ | |
| 375 #define CPI_XMAXEAX_MAX 0x80000100 | |
| 4606 | 376 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ |
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377 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ |
| 4606 | 378 |
| 379 /* | |
| 380 * Function 4 (Deterministic Cache Parameters) macros | |
| 381 * Defined by Intel Application Note AP-485 | |
| 382 */ | |
| 383 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) | |
| 384 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) | |
| 385 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) | |
| 386 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) | |
| 387 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) | |
| 388 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) | |
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389 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) |
| 4606 | 390 |
| 391 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) | |
| 392 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) | |
| 393 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) | |
| 394 | |
| 395 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) | |
| 396 | |
| 397 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) | |
| 398 | |
| 0 | 399 |
| 400 /* | |
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401 * A couple of shorthand macros to identify "later" P6-family chips |
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402 * like the Pentium M and Core. First, the "older" P6-based stuff |
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403 * (loosely defined as "pre-Pentium-4"): |
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404 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon |
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405 */ |
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406 |
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407 #define IS_LEGACY_P6(cpi) ( \ |
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408 cpi->cpi_family == 6 && \ |
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409 (cpi->cpi_model == 1 || \ |
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410 cpi->cpi_model == 3 || \ |
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411 cpi->cpi_model == 5 || \ |
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412 cpi->cpi_model == 6 || \ |
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413 cpi->cpi_model == 7 || \ |
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414 cpi->cpi_model == 8 || \ |
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415 cpi->cpi_model == 0xA || \ |
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416 cpi->cpi_model == 0xB) \ |
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417 ) |
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418 |
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419 /* A "new F6" is everything with family 6 that's not the above */ |
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420 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) |
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421 |
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422 /* Extended family/model support */ |
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423 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ |
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424 cpi->cpi_family >= 0xf) |
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425 |
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426 /* |
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427 * Info for monitor/mwait idle loop. |
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428 * |
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429 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's |
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430 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November |
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431 * 2006. |
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432 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual |
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433 * Documentation Updates" #33633, Rev 2.05, December 2006. |
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434 */ |
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435 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ |
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436 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ |
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437 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ |
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438 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) |
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439 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) |
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440 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) |
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441 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) |
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442 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) |
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443 /* |
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444 * Number of sub-cstates for a given c-state. |
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445 */ |
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446 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ |
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447 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) |
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448 |
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449 /* |
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450 * XSAVE leaf 0xD enumeration |
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451 */ |
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452 #define CPUID_LEAFD_2_YMM_OFFSET 576 |
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453 #define CPUID_LEAFD_2_YMM_SIZE 256 |
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454 |
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455 /* |
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456 * Functions we consune from cpuid_subr.c; don't publish these in a header |
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457 * file to try and keep people using the expected cpuid_* interfaces. |
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458 */ |
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459 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); |
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460 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); |
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461 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); |
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462 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); |
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463 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); |
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464 |
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465 /* |
| 3446 | 466 * Apply up various platform-dependent restrictions where the |
| 467 * underlying platform restrictions mean the CPU can be marked | |
| 468 * as less capable than its cpuid instruction would imply. | |
| 469 */ | |
| 5084 | 470 #if defined(__xpv) |
| 471 static void | |
| 472 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) | |
| 473 { | |
| 474 switch (eax) { | |
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475 case 1: { |
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476 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? |
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477 0 : CPUID_INTC_EDX_MCA; |
| 5084 | 478 cp->cp_edx &= |
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479 ~(mcamask | |
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480 CPUID_INTC_EDX_PSE | |
| 5084 | 481 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | |
| 482 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | | |
| 483 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | | |
| 484 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
| 485 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); | |
| 486 break; | |
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487 } |
| 5084 | 488 |
| 489 case 0x80000001: | |
| 490 cp->cp_edx &= | |
| 491 ~(CPUID_AMD_EDX_PSE | | |
| 492 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | | |
| 493 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | | |
| 494 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | | |
| 495 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | | |
| 496 CPUID_AMD_EDX_TSCP); | |
| 497 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; | |
| 498 break; | |
| 499 default: | |
| 500 break; | |
| 501 } | |
| 502 | |
| 503 switch (vendor) { | |
| 504 case X86_VENDOR_Intel: | |
| 505 switch (eax) { | |
| 506 case 4: | |
| 507 /* | |
| 508 * Zero out the (ncores-per-chip - 1) field | |
| 509 */ | |
| 510 cp->cp_eax &= 0x03fffffff; | |
| 511 break; | |
| 512 default: | |
| 513 break; | |
| 514 } | |
| 515 break; | |
| 516 case X86_VENDOR_AMD: | |
| 517 switch (eax) { | |
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518 |
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519 case 0x80000001: |
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520 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; |
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521 break; |
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522 |
| 5084 | 523 case 0x80000008: |
| 524 /* | |
| 525 * Zero out the (ncores-per-chip - 1) field | |
| 526 */ | |
| 527 cp->cp_ecx &= 0xffffff00; | |
| 528 break; | |
| 529 default: | |
| 530 break; | |
| 531 } | |
| 532 break; | |
| 533 default: | |
| 534 break; | |
| 535 } | |
| 536 } | |
| 537 #else | |
| 3446 | 538 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ |
| 5084 | 539 #endif |
| 3446 | 540 |
| 541 /* | |
| 0 | 542 * Some undocumented ways of patching the results of the cpuid |
| 543 * instruction to permit running Solaris 10 on future cpus that | |
| 544 * we don't currently support. Could be set to non-zero values | |
| 545 * via settings in eeprom. | |
| 546 */ | |
| 547 | |
| 548 uint32_t cpuid_feature_ecx_include; | |
| 549 uint32_t cpuid_feature_ecx_exclude; | |
| 550 uint32_t cpuid_feature_edx_include; | |
| 551 uint32_t cpuid_feature_edx_exclude; | |
| 552 | |
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553 /* |
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554 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs. |
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555 */ |
| 3446 | 556 void |
| 557 cpuid_alloc_space(cpu_t *cpu) | |
| 558 { | |
| 559 /* | |
| 560 * By convention, cpu0 is the boot cpu, which is set up | |
| 561 * before memory allocation is available. All other cpus get | |
| 562 * their cpuid_info struct allocated here. | |
| 563 */ | |
| 564 ASSERT(cpu->cpu_id != 0); | |
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565 ASSERT(cpu->cpu_m.mcpu_cpi == NULL); |
| 3446 | 566 cpu->cpu_m.mcpu_cpi = |
| 567 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); | |
| 568 } | |
| 569 | |
| 570 void | |
| 571 cpuid_free_space(cpu_t *cpu) | |
| 572 { | |
| 4606 | 573 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 574 int i; | |
| 575 | |
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576 ASSERT(cpi != NULL); |
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577 ASSERT(cpi != &cpuid_info0); |
| 4606 | 578 |
| 579 /* | |
| 580 * Free up any function 4 related dynamic storage | |
| 581 */ | |
| 582 for (i = 1; i < cpi->cpi_std_4_size; i++) | |
| 583 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); | |
| 584 if (cpi->cpi_std_4_size > 0) | |
| 585 kmem_free(cpi->cpi_std_4, | |
| 586 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); | |
| 587 | |
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588 kmem_free(cpi, sizeof (*cpi)); |
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589 cpu->cpu_m.mcpu_cpi = NULL; |
| 3446 | 590 } |
| 591 | |
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592 #if !defined(__xpv) |
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593 |
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594 /* |
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595 * Determine the type of the underlying platform. This is used to customize |
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596 * initialization of various subsystems (e.g. TSC). determine_platform() must |
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597 * only ever be called once to prevent two processors from seeing different |
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598 * values of platform_type, it must be called before cpuid_pass1(), the |
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599 * earliest consumer to execute. |
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600 */ |
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601 void |
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602 determine_platform(void) |
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603 { |
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604 struct cpuid_regs cp; |
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605 char *xen_str; |
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606 uint32_t xen_signature[4], base; |
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607 |
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608 ASSERT(platform_type == -1); |
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609 |
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610 platform_type = HW_NATIVE; |
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611 |
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612 if (!enable_platform_detection) |
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613 return; |
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614 |
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615 /* |
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616 * In a fully virtualized domain, Xen's pseudo-cpuid function |
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617 * returns a string representing the Xen signature in %ebx, %ecx, |
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618 * and %edx. %eax contains the maximum supported cpuid function. |
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619 * We need at least a (base + 2) leaf value to do what we want |
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620 * to do. Try different base values, since the hypervisor might |
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621 * use a different one depending on whether hyper-v emulation |
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622 * is switched on by default or not. |
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623 */ |
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624 for (base = 0x40000000; base < 0x40010000; base += 0x100) { |
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625 cp.cp_eax = base; |
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626 (void) __cpuid_insn(&cp); |
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627 xen_signature[0] = cp.cp_ebx; |
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628 xen_signature[1] = cp.cp_ecx; |
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629 xen_signature[2] = cp.cp_edx; |
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630 xen_signature[3] = 0; |
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631 xen_str = (char *)xen_signature; |
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632 if (strcmp("XenVMMXenVMM", xen_str) == 0 && |
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633 cp.cp_eax >= (base + 2)) { |
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634 platform_type = HW_XEN_HVM; |
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635 return; |
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636 } |
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637 } |
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638 |
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639 if (vmware_platform()) /* running under vmware hypervisor? */ |
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640 platform_type = HW_VMWARE; |
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641 } |
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642 |
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643 int |
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644 get_hwenv(void) |
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645 { |
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646 ASSERT(platform_type != -1); |
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647 return (platform_type); |
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648 } |
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649 |
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650 int |
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|
651 is_controldom(void) |
|
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|
652 { |
|
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|
653 return (0); |
|
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|
654 } |
|
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changeset
|
655 |
|
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|
656 #else |
|
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|
657 |
|
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|
658 int |
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|
659 get_hwenv(void) |
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|
660 { |
|
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|
661 return (HW_XEN_PV); |
|
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|
662 } |
|
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changeset
|
663 |
|
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|
664 int |
|
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|
665 is_controldom(void) |
|
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|
666 { |
|
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|
667 return (DOMAIN_IS_INITDOMAIN(xen_info)); |
|
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|
668 } |
|
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|
669 |
|
5741
58423876d513
PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains
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|
670 #endif /* __xpv */ |
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|
671 |
|
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|
672 static void |
|
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673 cpuid_intel_getids(cpu_t *cpu, void *feature) |
|
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674 { |
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675 uint_t i; |
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676 uint_t chipid_shift = 0; |
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677 uint_t coreid_shift = 0; |
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678 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
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|
679 |
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680 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) |
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681 chipid_shift++; |
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682 |
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683 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift; |
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684 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1); |
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|
685 |
|
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686 if (is_x86_feature(feature, X86FSET_CMP)) { |
|
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687 /* |
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688 * Multi-core (and possibly multi-threaded) |
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689 * processors. |
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690 */ |
|
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691 uint_t ncpu_per_core; |
|
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692 if (cpi->cpi_ncore_per_chip == 1) |
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693 ncpu_per_core = cpi->cpi_ncpu_per_chip; |
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694 else if (cpi->cpi_ncore_per_chip > 1) |
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695 ncpu_per_core = cpi->cpi_ncpu_per_chip / |
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696 cpi->cpi_ncore_per_chip; |
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|
697 /* |
|
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|
698 * 8bit APIC IDs on dual core Pentiums |
|
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|
699 * look like this: |
|
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|
700 * |
|
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|
701 * +-----------------------+------+------+ |
|
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|
702 * | Physical Package ID | MC | HT | |
|
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703 * +-----------------------+------+------+ |
|
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|
704 * <------- chipid --------> |
|
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|
705 * <------- coreid ---------------> |
|
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|
706 * <--- clogid --> |
|
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|
707 * <------> |
|
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|
708 * pkgcoreid |
|
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|
709 * |
|
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|
710 * Where the number of bits necessary to |
|
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|
711 * represent MC and HT fields together equals |
|
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|
712 * to the minimum number of bits necessary to |
|
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|
713 * store the value of cpi->cpi_ncpu_per_chip. |
|
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|
714 * Of those bits, the MC part uses the number |
|
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|
715 * of bits necessary to store the value of |
|
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|
716 * cpi->cpi_ncore_per_chip. |
|
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|
717 */ |
|
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|
718 for (i = 1; i < ncpu_per_core; i <<= 1) |
|
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|
719 coreid_shift++; |
|
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|
720 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift; |
|
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|
721 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; |
|
12838
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diff
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|
722 } else if (is_x86_feature(feature, X86FSET_HTT)) { |
|
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|
723 /* |
|
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|
724 * Single-core multi-threaded processors. |
|
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|
725 */ |
|
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changeset
|
726 cpi->cpi_coreid = cpi->cpi_chipid; |
|
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|
727 cpi->cpi_pkgcoreid = 0; |
|
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|
728 } |
|
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changeset
|
729 cpi->cpi_procnodeid = cpi->cpi_chipid; |
|
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|
730 } |
|
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diff
changeset
|
731 |
|
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|
732 static void |
|
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|
733 cpuid_amd_getids(cpu_t *cpu) |
|
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|
734 { |
|
11013
3aa288b66f8e
6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module
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diff
changeset
|
735 int i, first_half, coreidsz; |
|
10947
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changeset
|
736 uint32_t nb_caps_reg; |
|
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changeset
|
737 uint_t node2_1; |
|
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|
738 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
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|
739 |
|
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changeset
|
740 /* |
|
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changeset
|
741 * AMD CMP chips currently have a single thread per core. |
|
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|
742 * |
|
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|
743 * Since no two cpus share a core we must assign a distinct coreid |
|
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|
744 * per cpu, and we do this by using the cpu_id. This scheme does not, |
|
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|
745 * however, guarantee that sibling cores of a chip will have sequential |
|
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|
746 * coreids starting at a multiple of the number of cores per chip - |
|
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|
747 * that is usually the case, but if the ACPI MADT table is presented |
|
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changeset
|
748 * in a different order then we need to perform a few more gymnastics |
|
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changeset
|
749 * for the pkgcoreid. |
|
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changeset
|
750 * |
|
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751 * All processors in the system have the same number of enabled |
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752 * cores. Cores within a processor are always numbered sequentially |
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753 * from 0 regardless of how many or which are disabled, and there |
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754 * is no way for operating system to discover the real core id when some |
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|
755 * are disabled. |
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756 */ |
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757 |
|
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|
758 cpi->cpi_coreid = cpu->cpu_id; |
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759 |
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760 if (cpi->cpi_xmaxeax >= 0x80000008) { |
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761 |
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762 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); |
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763 |
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764 /* |
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765 * In AMD parlance chip is really a node while Solaris |
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766 * sees chip as equivalent to socket/package. |
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767 */ |
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768 cpi->cpi_ncore_per_chip = |
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769 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; |
|
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770 if (coreidsz == 0) { |
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771 /* Use legacy method */ |
|
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772 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1) |
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773 coreidsz++; |
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774 if (coreidsz == 0) |
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775 coreidsz = 1; |
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776 } |
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777 } else { |
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778 /* Assume single-core part */ |
|
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|
779 cpi->cpi_ncore_per_chip = 1; |
|
12726
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780 coreidsz = 1; |
|
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781 } |
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782 |
|
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|
783 cpi->cpi_clogid = cpi->cpi_pkgcoreid = |
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784 cpi->cpi_apicid & ((1<<coreidsz) - 1); |
|
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785 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip; |
|
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|
786 |
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787 /* Get nodeID */ |
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788 if (cpi->cpi_family == 0xf) { |
|
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789 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; |
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790 cpi->cpi_chipid = cpi->cpi_procnodeid; |
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791 } else if (cpi->cpi_family == 0x10) { |
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792 /* |
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793 * See if we are a multi-node processor. |
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794 * All processors in the system have the same number of nodes |
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795 */ |
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796 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8); |
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797 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) { |
|
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798 /* Single-node */ |
|
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799 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5, |
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|
800 coreidsz); |
|
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801 cpi->cpi_chipid = cpi->cpi_procnodeid; |
|
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802 } else { |
|
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|
803 |
|
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|
804 /* |
|
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|
805 * Multi-node revision D (2 nodes per package |
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|
806 * are supported) |
|
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|
807 */ |
|
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|
808 cpi->cpi_procnodes_per_pkg = 2; |
|
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|
809 |
|
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|
810 first_half = (cpi->cpi_pkgcoreid <= |
|
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811 (cpi->cpi_ncore_per_chip/2 - 1)); |
|
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|
812 |
|
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813 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) { |
|
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|
814 /* We are BSP */ |
|
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815 cpi->cpi_procnodeid = (first_half ? 0 : 1); |
|
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|
816 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; |
|
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817 } else { |
|
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|
818 |
|
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|
819 /* We are AP */ |
|
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|
820 /* NodeId[2:1] bits to use for reading F3xe8 */ |
|
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821 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1; |
|
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822 |
|
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823 nb_caps_reg = |
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824 pci_getl_func(0, 24 + node2_1, 3, 0xe8); |
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|
825 |
|
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|
826 /* |
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827 * Check IntNodeNum bit (31:30, but bit 31 is |
|
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828 * always 0 on dual-node processors) |
|
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|
829 */ |
|
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830 if (BITX(nb_caps_reg, 30, 30) == 0) |
|
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831 cpi->cpi_procnodeid = node2_1 + |
|
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|
832 !first_half; |
|
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833 else |
|
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834 cpi->cpi_procnodeid = node2_1 + |
|
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|
835 first_half; |
|
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|
836 |
|
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837 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; |
|
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838 } |
|
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|
839 } |
|
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|
840 } else if (cpi->cpi_family >= 0x11) { |
|
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841 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; |
|
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|
842 cpi->cpi_chipid = cpi->cpi_procnodeid; |
|
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|
843 } else { |
|
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|
844 cpi->cpi_procnodeid = 0; |
|
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Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
845 cpi->cpi_chipid = cpi->cpi_procnodeid; |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
846 } |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
847 } |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
848 |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
849 /* |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
850 * Setup XFeature_Enabled_Mask register. Required by xsave feature. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
851 */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
852 void |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
853 setup_xfem(void) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
854 { |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
855 uint64_t flags = XFEATURE_LEGACY_FP; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
856 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
857 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
858 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
859 if (is_x86_feature(x86_featureset, X86FSET_SSE)) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
860 flags |= XFEATURE_SSE; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
861 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
862 if (is_x86_feature(x86_featureset, X86FSET_AVX)) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
863 flags |= XFEATURE_AVX; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
864 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
865 set_xcr(XFEATURE_ENABLED_MASK, flags); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
866 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
867 xsave_bv_all = flags; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
868 } |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
869 |
|
13148
67d1861e02c1
6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13146
diff
changeset
|
870 void |
|
67d1861e02c1
6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13146
diff
changeset
|
871 cpuid_pass1(cpu_t *cpu, uchar_t *featureset) |
| 0 | 872 { |
| 873 uint32_t mask_ecx, mask_edx; | |
| 874 struct cpuid_info *cpi; | |
| 1228 | 875 struct cpuid_regs *cp; |
| 0 | 876 int xcpuid; |
| 5084 | 877 #if !defined(__xpv) |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
878 extern int idle_cpu_prefer_mwait; |
| 5084 | 879 #endif |
| 3446 | 880 |
| 0 | 881 /* |
|
12004
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
882 * Space statically allocated for BSP, ensure pointer is set |
| 0 | 883 */ |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
884 if (cpu->cpu_id == 0) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
885 if (cpu->cpu_m.mcpu_cpi == NULL) |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
886 cpu->cpu_m.mcpu_cpi = &cpuid_info0; |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
887 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
888 |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
889 add_x86_feature(featureset, X86FSET_CPUID); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
890 |
| 3446 | 891 cpi = cpu->cpu_m.mcpu_cpi; |
| 892 ASSERT(cpi != NULL); | |
| 0 | 893 cp = &cpi->cpi_std[0]; |
| 1228 | 894 cp->cp_eax = 0; |
| 895 cpi->cpi_maxeax = __cpuid_insn(cp); | |
| 0 | 896 { |
| 897 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; | |
| 898 *iptr++ = cp->cp_ebx; | |
| 899 *iptr++ = cp->cp_edx; | |
| 900 *iptr++ = cp->cp_ecx; | |
| 901 *(char *)&cpi->cpi_vendorstr[12] = '\0'; | |
| 902 } | |
| 903 | |
|
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
904 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); |
| 0 | 905 x86_vendor = cpi->cpi_vendor; /* for compatibility */ |
| 906 | |
| 907 /* | |
| 908 * Limit the range in case of weird hardware | |
| 909 */ | |
| 910 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) | |
| 911 cpi->cpi_maxeax = CPI_MAXEAX_MAX; | |
| 912 if (cpi->cpi_maxeax < 1) | |
| 913 goto pass1_done; | |
| 914 | |
| 915 cp = &cpi->cpi_std[1]; | |
| 1228 | 916 cp->cp_eax = 1; |
| 917 (void) __cpuid_insn(cp); | |
| 0 | 918 |
| 919 /* | |
| 920 * Extract identifying constants for easy access. | |
| 921 */ | |
| 922 cpi->cpi_model = CPI_MODEL(cpi); | |
| 923 cpi->cpi_family = CPI_FAMILY(cpi); | |
| 924 | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
925 if (cpi->cpi_family == 0xf) |
| 0 | 926 cpi->cpi_family += CPI_FAMILY_XTD(cpi); |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
927 |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
928 /* |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
929 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
930 * Intel, and presumably everyone else, uses model == 0xf, as |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
931 * one would expect (max value means possible overflow). Sigh. |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
932 */ |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
933 |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
934 switch (cpi->cpi_vendor) { |
|
4855
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
935 case X86_VENDOR_Intel: |
|
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
936 if (IS_EXTENDED_MODEL_INTEL(cpi)) |
|
3319ad80f260
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors
ksadhukh
parents:
4797
diff
changeset
|
937 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
4858
08409e2eed12
6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint)
ksadhukh
parents:
4855
diff
changeset
|
938 break; |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
939 case X86_VENDOR_AMD: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
940 if (CPI_FAMILY(cpi) == 0xf) |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
941 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
942 break; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
943 default: |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
944 if (cpi->cpi_model == 0xf) |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
945 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
946 break; |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
947 } |
| 0 | 948 |
| 949 cpi->cpi_step = CPI_STEP(cpi); | |
| 950 cpi->cpi_brandid = CPI_BRANDID(cpi); | |
| 951 | |
| 952 /* | |
| 953 * *default* assumptions: | |
| 954 * - believe %edx feature word | |
| 955 * - ignore %ecx feature word | |
| 956 * - 32-bit virtual and physical addressing | |
| 957 */ | |
| 958 mask_edx = 0xffffffff; | |
| 959 mask_ecx = 0; | |
| 960 | |
| 961 cpi->cpi_pabits = cpi->cpi_vabits = 32; | |
| 962 | |
| 963 switch (cpi->cpi_vendor) { | |
| 964 case X86_VENDOR_Intel: | |
| 965 if (cpi->cpi_family == 5) | |
| 966 x86_type = X86_TYPE_P5; | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
967 else if (IS_LEGACY_P6(cpi)) { |
| 0 | 968 x86_type = X86_TYPE_P6; |
| 969 pentiumpro_bug4046376 = 1; | |
| 970 pentiumpro_bug4064495 = 1; | |
| 971 /* | |
| 972 * Clear the SEP bit when it was set erroneously | |
| 973 */ | |
| 974 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) | |
| 975 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
976 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { |
| 0 | 977 x86_type = X86_TYPE_P4; |
| 978 /* | |
| 979 * We don't currently depend on any of the %ecx | |
| 980 * features until Prescott, so we'll only check | |
| 981 * this from P4 onwards. We might want to revisit | |
| 982 * that idea later. | |
| 983 */ | |
| 984 mask_ecx = 0xffffffff; | |
| 985 } else if (cpi->cpi_family > 0xf) | |
| 986 mask_ecx = 0xffffffff; | |
|
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
987 /* |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
988 * We don't support MONITOR/MWAIT if leaf 5 is not available |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
989 * to obtain the monitor linesize. |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
990 */ |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
991 if (cpi->cpi_maxeax < 5) |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
992 mask_ecx &= ~CPUID_INTC_ECX_MON; |
| 0 | 993 break; |
| 994 case X86_VENDOR_IntelClone: | |
| 995 default: | |
| 996 break; | |
| 997 case X86_VENDOR_AMD: | |
| 998 #if defined(OPTERON_ERRATUM_108) | |
| 999 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { | |
| 1000 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; | |
| 1001 cpi->cpi_model = 0xc; | |
| 1002 } else | |
| 1003 #endif | |
| 1004 if (cpi->cpi_family == 5) { | |
| 1005 /* | |
| 1006 * AMD K5 and K6 | |
| 1007 * | |
| 1008 * These CPUs have an incomplete implementation | |
| 1009 * of MCA/MCE which we mask away. | |
| 1010 */ | |
| 1228 | 1011 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); |
| 1012 | |
| 1013 /* | |
| 1014 * Model 0 uses the wrong (APIC) bit | |
| 1015 * to indicate PGE. Fix it here. | |
| 1016 */ | |
| 0 | 1017 if (cpi->cpi_model == 0) { |
| 1018 if (cp->cp_edx & 0x200) { | |
| 1019 cp->cp_edx &= ~0x200; | |
| 1020 cp->cp_edx |= CPUID_INTC_EDX_PGE; | |
| 1021 } | |
| 1228 | 1022 } |
| 1023 | |
| 1024 /* | |
| 1025 * Early models had problems w/ MMX; disable. | |
| 1026 */ | |
| 1027 if (cpi->cpi_model < 6) | |
| 1028 mask_edx &= ~CPUID_INTC_EDX_MMX; | |
| 1029 } | |
| 1030 | |
| 1031 /* | |
| 1032 * For newer families, SSE3 and CX16, at least, are valid; | |
| 1033 * enable all | |
| 1034 */ | |
| 1035 if (cpi->cpi_family >= 0xf) | |
|
771
1c25a2120ec0
6327969 cpuid sse3 feature bit not noted on any AMD processor
dmick
parents:
359
diff
changeset
|
1036 mask_ecx = 0xffffffff; |
|
4636
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1037 /* |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1038 * We don't support MONITOR/MWAIT if leaf 5 is not available |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1039 * to obtain the monitor linesize. |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1040 */ |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1041 if (cpi->cpi_maxeax < 5) |
|
f7779128d972
6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0
bholler
parents:
4628
diff
changeset
|
1042 mask_ecx &= ~CPUID_INTC_ECX_MON; |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1043 |
| 5084 | 1044 #if !defined(__xpv) |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1045 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1046 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1047 * processors. AMD does not intend MWAIT to be used in the cpu |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1048 * idle loop on current and future processors. 10h and future |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1049 * AMD processors use more power in MWAIT than HLT. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1050 * Pre-family-10h Opterons do not have the MWAIT instruction. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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4858
diff
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|
1051 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
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4858
diff
changeset
|
1052 idle_cpu_prefer_mwait = 0; |
| 5084 | 1053 #endif |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
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|
1054 |
| 0 | 1055 break; |
| 1056 case X86_VENDOR_TM: | |
| 1057 /* | |
| 1058 * workaround the NT workaround in CMS 4.1 | |
| 1059 */ | |
| 1060 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && | |
| 1061 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) | |
| 1062 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 1063 break; | |
| 1064 case X86_VENDOR_Centaur: | |
| 1065 /* | |
| 1066 * workaround the NT workarounds again | |
| 1067 */ | |
| 1068 if (cpi->cpi_family == 6) | |
| 1069 cp->cp_edx |= CPUID_INTC_EDX_CX8; | |
| 1070 break; | |
| 1071 case X86_VENDOR_Cyrix: | |
| 1072 /* | |
| 1073 * We rely heavily on the probing in locore | |
| 1074 * to actually figure out what parts, if any, | |
| 1075 * of the Cyrix cpuid instruction to believe. | |
| 1076 */ | |
| 1077 switch (x86_type) { | |
| 1078 case X86_TYPE_CYRIX_486: | |
| 1079 mask_edx = 0; | |
| 1080 break; | |
| 1081 case X86_TYPE_CYRIX_6x86: | |
| 1082 mask_edx = 0; | |
| 1083 break; | |
| 1084 case X86_TYPE_CYRIX_6x86L: | |
| 1085 mask_edx = | |
| 1086 CPUID_INTC_EDX_DE | | |
| 1087 CPUID_INTC_EDX_CX8; | |
| 1088 break; | |
| 1089 case X86_TYPE_CYRIX_6x86MX: | |
| 1090 mask_edx = | |
| 1091 CPUID_INTC_EDX_DE | | |
| 1092 CPUID_INTC_EDX_MSR | | |
| 1093 CPUID_INTC_EDX_CX8 | | |
| 1094 CPUID_INTC_EDX_PGE | | |
| 1095 CPUID_INTC_EDX_CMOV | | |
| 1096 CPUID_INTC_EDX_MMX; | |
| 1097 break; | |
| 1098 case X86_TYPE_CYRIX_GXm: | |
| 1099 mask_edx = | |
| 1100 CPUID_INTC_EDX_MSR | | |
| 1101 CPUID_INTC_EDX_CX8 | | |
| 1102 CPUID_INTC_EDX_CMOV | | |
| 1103 CPUID_INTC_EDX_MMX; | |
| 1104 break; | |
| 1105 case X86_TYPE_CYRIX_MediaGX: | |
| 1106 break; | |
| 1107 case X86_TYPE_CYRIX_MII: | |
| 1108 case X86_TYPE_VIA_CYRIX_III: | |
| 1109 mask_edx = | |
| 1110 CPUID_INTC_EDX_DE | | |
| 1111 CPUID_INTC_EDX_TSC | | |
| 1112 CPUID_INTC_EDX_MSR | | |
| 1113 CPUID_INTC_EDX_CX8 | | |
| 1114 CPUID_INTC_EDX_PGE | | |
| 1115 CPUID_INTC_EDX_CMOV | | |
| 1116 CPUID_INTC_EDX_MMX; | |
| 1117 break; | |
| 1118 default: | |
| 1119 break; | |
| 1120 } | |
| 1121 break; | |
| 1122 } | |
| 1123 | |
| 5084 | 1124 #if defined(__xpv) |
| 1125 /* | |
| 1126 * Do not support MONITOR/MWAIT under a hypervisor | |
| 1127 */ | |
| 1128 mask_ecx &= ~CPUID_INTC_ECX_MON; | |
|
13146
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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13041
diff
changeset
|
1129 /* |
|
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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diff
changeset
|
1130 * Do not support XSAVE under a hypervisor for now |
|
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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diff
changeset
|
1131 */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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13041
diff
changeset
|
1132 xsave_force_disable = B_TRUE; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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diff
changeset
|
1133 |
| 5084 | 1134 #endif /* __xpv */ |
| 1135 | |
|
13146
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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13041
diff
changeset
|
1136 if (xsave_force_disable) { |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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13041
diff
changeset
|
1137 mask_ecx &= ~CPUID_INTC_ECX_XSAVE; |
|
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
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changeset
|
1138 mask_ecx &= ~CPUID_INTC_ECX_AVX; |
|
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6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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changeset
|
1139 } |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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13041
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changeset
|
1140 |
| 0 | 1141 /* |
| 1142 * Now we've figured out the masks that determine | |
| 1143 * which bits we choose to believe, apply the masks | |
| 1144 * to the feature words, then map the kernel's view | |
| 1145 * of these feature words into its feature word. | |
| 1146 */ | |
| 1147 cp->cp_edx &= mask_edx; | |
| 1148 cp->cp_ecx &= mask_ecx; | |
| 1149 | |
| 1150 /* | |
| 3446 | 1151 * apply any platform restrictions (we don't call this |
| 1152 * immediately after __cpuid_insn here, because we need the | |
| 1153 * workarounds applied above first) | |
| 0 | 1154 */ |
| 3446 | 1155 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); |
| 0 | 1156 |
| 3446 | 1157 /* |
| 1158 * fold in overrides from the "eeprom" mechanism | |
| 1159 */ | |
| 0 | 1160 cp->cp_edx |= cpuid_feature_edx_include; |
| 1161 cp->cp_edx &= ~cpuid_feature_edx_exclude; | |
| 1162 | |
| 1163 cp->cp_ecx |= cpuid_feature_ecx_include; | |
| 1164 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; | |
| 1165 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1166 if (cp->cp_edx & CPUID_INTC_EDX_PSE) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1167 add_x86_feature(featureset, X86FSET_LARGEPAGE); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1168 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1169 if (cp->cp_edx & CPUID_INTC_EDX_TSC) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1170 add_x86_feature(featureset, X86FSET_TSC); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1171 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1172 if (cp->cp_edx & CPUID_INTC_EDX_MSR) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1173 add_x86_feature(featureset, X86FSET_MSR); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1174 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1175 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1176 add_x86_feature(featureset, X86FSET_MTRR); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1177 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1178 if (cp->cp_edx & CPUID_INTC_EDX_PGE) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1179 add_x86_feature(featureset, X86FSET_PGE); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1180 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1181 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1182 add_x86_feature(featureset, X86FSET_CMOV); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1183 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1184 if (cp->cp_edx & CPUID_INTC_EDX_MMX) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1185 add_x86_feature(featureset, X86FSET_MMX); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1186 } |
| 0 | 1187 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1188 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1189 add_x86_feature(featureset, X86FSET_MCA); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1190 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1191 if (cp->cp_edx & CPUID_INTC_EDX_PAE) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1192 add_x86_feature(featureset, X86FSET_PAE); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1193 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1194 if (cp->cp_edx & CPUID_INTC_EDX_CX8) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1195 add_x86_feature(featureset, X86FSET_CX8); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1196 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1197 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1198 add_x86_feature(featureset, X86FSET_CX16); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1199 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1200 if (cp->cp_edx & CPUID_INTC_EDX_PAT) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1201 add_x86_feature(featureset, X86FSET_PAT); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1202 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1203 if (cp->cp_edx & CPUID_INTC_EDX_SEP) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1204 add_x86_feature(featureset, X86FSET_SEP); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1205 } |
| 0 | 1206 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { |
| 1207 /* | |
| 1208 * In our implementation, fxsave/fxrstor | |
| 1209 * are prerequisites before we'll even | |
| 1210 * try and do SSE things. | |
| 1211 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1212 if (cp->cp_edx & CPUID_INTC_EDX_SSE) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1213 add_x86_feature(featureset, X86FSET_SSE); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1214 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
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parents:
12726
diff
changeset
|
1215 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1216 add_x86_feature(featureset, X86FSET_SSE2); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
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diff
changeset
|
1217 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
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parents:
12726
diff
changeset
|
1218 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1219 add_x86_feature(featureset, X86FSET_SSE3); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1220 } |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
1221 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1222 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1223 add_x86_feature(featureset, X86FSET_SSSE3); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
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12726
diff
changeset
|
1224 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
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parents:
12726
diff
changeset
|
1225 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1226 add_x86_feature(featureset, X86FSET_SSE4_1); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
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diff
changeset
|
1227 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1228 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1229 add_x86_feature(featureset, X86FSET_SSE4_2); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1230 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1231 if (cp->cp_ecx & CPUID_INTC_ECX_AES) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1232 add_x86_feature(featureset, X86FSET_AES); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1233 } |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1234 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1235 add_x86_feature(featureset, X86FSET_PCLMULQDQ); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1236 } |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1237 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1238 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) { |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1239 add_x86_feature(featureset, X86FSET_XSAVE); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1240 /* We only test AVX when there is XSAVE */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1241 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) { |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1242 add_x86_feature(featureset, |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1243 X86FSET_AVX); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1244 } |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
1245 } |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
1246 } |
| 0 | 1247 } |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1248 if (cp->cp_edx & CPUID_INTC_EDX_DE) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1249 add_x86_feature(featureset, X86FSET_DE); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1250 } |
|
7716
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1251 #if !defined(__xpv) |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1252 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { |
|
7716
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1253 |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1254 /* |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1255 * We require the CLFLUSH instruction for erratum workaround |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1256 * to use MONITOR/MWAIT. |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1257 */ |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1258 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1259 cpi->cpi_mwait.support |= MWAIT_SUPPORT; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1260 add_x86_feature(featureset, X86FSET_MWAIT); |
|
7716
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1261 } else { |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1262 extern int idle_cpu_assert_cflush_monitor; |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1263 |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1264 /* |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1265 * All processors we are aware of which have |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1266 * MONITOR/MWAIT also have CLFLUSH. |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1267 */ |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1268 if (idle_cpu_assert_cflush_monitor) { |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1269 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1270 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1271 } |
|
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1272 } |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1273 } |
|
7716
44c2ec1382be
6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system
Bill Holler <Bill.Holler@Sun.COM>
parents:
7656
diff
changeset
|
1274 #endif /* __xpv */ |
| 0 | 1275 |
|
13425
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1276 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) { |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1277 add_x86_feature(featureset, X86FSET_VMX); |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1278 } |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1279 |
|
7589
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1280 /* |
|
13425
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1281 * Only need it first time, rest of the cpus would follow suit. |
|
7589
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1282 * we only capture this for the bootcpu. |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1283 */ |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1284 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1285 add_x86_feature(featureset, X86FSET_CLFSH); |
|
7589
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1286 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); |
|
7de800909a06
PSARC 2008/560 Intel IOMMU
Vikram Hegde <Vikram.Hegde@Sun.COM>
parents:
7532
diff
changeset
|
1287 } |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1288 if (is_x86_feature(featureset, X86FSET_PAE)) |
| 0 | 1289 cpi->cpi_pabits = 36; |
| 1290 | |
| 1291 /* | |
| 1292 * Hyperthreading configuration is slightly tricky on Intel | |
| 1293 * and pure clones, and even trickier on AMD. | |
| 1294 * | |
| 1295 * (AMD chose to set the HTT bit on their CMP processors, | |
| 1296 * even though they're not actually hyperthreaded. Thus it | |
| 1297 * takes a bit more work to figure out what's really going | |
| 3446 | 1298 * on ... see the handling of the CMP_LGCY bit below) |
| 0 | 1299 */ |
| 1300 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { | |
| 1301 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); | |
| 1302 if (cpi->cpi_ncpu_per_chip > 1) | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1303 add_x86_feature(featureset, X86FSET_HTT); |
| 1228 | 1304 } else { |
| 1305 cpi->cpi_ncpu_per_chip = 1; | |
| 0 | 1306 } |
| 1307 | |
| 1308 /* | |
| 1309 * Work on the "extended" feature information, doing | |
| 1310 * some basic initialization for cpuid_pass2() | |
| 1311 */ | |
| 1312 xcpuid = 0; | |
| 1313 switch (cpi->cpi_vendor) { | |
| 1314 case X86_VENDOR_Intel: | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1315 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) |
| 0 | 1316 xcpuid++; |
| 1317 break; | |
| 1318 case X86_VENDOR_AMD: | |
| 1319 if (cpi->cpi_family > 5 || | |
| 1320 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 1321 xcpuid++; | |
| 1322 break; | |
| 1323 case X86_VENDOR_Cyrix: | |
| 1324 /* | |
| 1325 * Only these Cyrix CPUs are -known- to support | |
| 1326 * extended cpuid operations. | |
| 1327 */ | |
| 1328 if (x86_type == X86_TYPE_VIA_CYRIX_III || | |
| 1329 x86_type == X86_TYPE_CYRIX_GXm) | |
| 1330 xcpuid++; | |
| 1331 break; | |
| 1332 case X86_VENDOR_Centaur: | |
| 1333 case X86_VENDOR_TM: | |
| 1334 default: | |
| 1335 xcpuid++; | |
| 1336 break; | |
| 1337 } | |
| 1338 | |
| 1339 if (xcpuid) { | |
| 1340 cp = &cpi->cpi_extd[0]; | |
| 1228 | 1341 cp->cp_eax = 0x80000000; |
| 1342 cpi->cpi_xmaxeax = __cpuid_insn(cp); | |
| 0 | 1343 } |
| 1344 | |
| 1345 if (cpi->cpi_xmaxeax & 0x80000000) { | |
| 1346 | |
| 1347 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) | |
| 1348 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; | |
| 1349 | |
| 1350 switch (cpi->cpi_vendor) { | |
| 1351 case X86_VENDOR_Intel: | |
| 1352 case X86_VENDOR_AMD: | |
| 1353 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 1354 break; | |
| 1355 cp = &cpi->cpi_extd[1]; | |
| 1228 | 1356 cp->cp_eax = 0x80000001; |
| 1357 (void) __cpuid_insn(cp); | |
| 3446 | 1358 |
| 0 | 1359 if (cpi->cpi_vendor == X86_VENDOR_AMD && |
| 1360 cpi->cpi_family == 5 && | |
| 1361 cpi->cpi_model == 6 && | |
| 1362 cpi->cpi_step == 6) { | |
| 1363 /* | |
| 1364 * K6 model 6 uses bit 10 to indicate SYSC | |
| 1365 * Later models use bit 11. Fix it here. | |
| 1366 */ | |
| 1367 if (cp->cp_edx & 0x400) { | |
| 1368 cp->cp_edx &= ~0x400; | |
| 1369 cp->cp_edx |= CPUID_AMD_EDX_SYSC; | |
| 1370 } | |
| 1371 } | |
| 1372 | |
| 3446 | 1373 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); |
| 1374 | |
| 0 | 1375 /* |
| 1376 * Compute the additions to the kernel's feature word. | |
| 1377 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1378 if (cp->cp_edx & CPUID_AMD_EDX_NX) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1379 add_x86_feature(featureset, X86FSET_NX); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1380 } |
| 0 | 1381 |
|
7656
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1382 /* |
|
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1383 * Regardless whether or not we boot 64-bit, |
|
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1384 * we should have a way to identify whether |
|
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1385 * the CPU is capable of running 64-bit. |
|
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1386 */ |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1387 if (cp->cp_edx & CPUID_AMD_EDX_LM) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1388 add_x86_feature(featureset, X86FSET_64); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1389 } |
|
7656
2621e50fdf4a
PSARC 2008/382 Fast Reboot
Sherry Moore <Sherry.Moore@Sun.COM>
parents:
7589
diff
changeset
|
1390 |
|
5349
01422ec04372
6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages
kchow
parents:
5338
diff
changeset
|
1391 #if defined(__amd64) |
|
01422ec04372
6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages
kchow
parents:
5338
diff
changeset
|
1392 /* 1 GB large page - enable only for 64 bit kernel */ |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1393 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1394 add_x86_feature(featureset, X86FSET_1GPG); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1395 } |
|
5349
01422ec04372
6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages
kchow
parents:
5338
diff
changeset
|
1396 #endif |
|
01422ec04372
6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages
kchow
parents:
5338
diff
changeset
|
1397 |
|
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
1398 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
1399 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1400 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1401 add_x86_feature(featureset, X86FSET_SSE4A); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1402 } |
|
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
1403 |
| 0 | 1404 /* |
| 3446 | 1405 * If both the HTT and CMP_LGCY bits are set, |
| 1228 | 1406 * then we're not actually HyperThreaded. Read |
| 1407 * "AMD CPUID Specification" for more details. | |
| 0 | 1408 */ |
| 1409 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1410 is_x86_feature(featureset, X86FSET_HTT) && |
| 3446 | 1411 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1412 remove_x86_feature(featureset, X86FSET_HTT); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1413 add_x86_feature(featureset, X86FSET_CMP); |
| 1228 | 1414 } |
| 3446 | 1415 #if defined(__amd64) |
| 0 | 1416 /* |
| 1417 * It's really tricky to support syscall/sysret in | |
| 1418 * the i386 kernel; we rely on sysenter/sysexit | |
| 1419 * instead. In the amd64 kernel, things are -way- | |
| 1420 * better. | |
| 1421 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1422 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1423 add_x86_feature(featureset, X86FSET_ASYSC); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1424 } |
| 0 | 1425 |
| 1426 /* | |
| 1427 * While we're thinking about system calls, note | |
| 1428 * that AMD processors don't support sysenter | |
| 1429 * in long mode at all, so don't try to program them. | |
| 1430 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1431 if (x86_vendor == X86_VENDOR_AMD) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1432 remove_x86_feature(featureset, X86FSET_SEP); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1433 } |
| 0 | 1434 #endif |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1435 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1436 add_x86_feature(featureset, X86FSET_TSCP); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1437 } |
|
13425
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1438 |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1439 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) { |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1440 add_x86_feature(featureset, X86FSET_SVM); |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
1441 } |
| 0 | 1442 break; |
| 1443 default: | |
| 1444 break; | |
| 1445 } | |
| 1446 | |
| 1228 | 1447 /* |
| 1448 * Get CPUID data about processor cores and hyperthreads. | |
| 1449 */ | |
| 0 | 1450 switch (cpi->cpi_vendor) { |
| 1451 case X86_VENDOR_Intel: | |
| 1228 | 1452 if (cpi->cpi_maxeax >= 4) { |
| 1453 cp = &cpi->cpi_std[4]; | |
| 1454 cp->cp_eax = 4; | |
| 1455 cp->cp_ecx = 0; | |
| 1456 (void) __cpuid_insn(cp); | |
| 3446 | 1457 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); |
| 1228 | 1458 } |
| 1459 /*FALLTHROUGH*/ | |
| 0 | 1460 case X86_VENDOR_AMD: |
| 1461 if (cpi->cpi_xmaxeax < 0x80000008) | |
| 1462 break; | |
| 1463 cp = &cpi->cpi_extd[8]; | |
| 1228 | 1464 cp->cp_eax = 0x80000008; |
| 1465 (void) __cpuid_insn(cp); | |
| 3446 | 1466 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); |
| 1467 | |
| 0 | 1468 /* |
| 1469 * Virtual and physical address limits from | |
| 1470 * cpuid override previously guessed values. | |
| 1471 */ | |
| 1472 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); | |
| 1473 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); | |
| 1474 break; | |
| 1475 default: | |
| 1476 break; | |
| 1477 } | |
| 1228 | 1478 |
| 4606 | 1479 /* |
| 1480 * Derive the number of cores per chip | |
| 1481 */ | |
| 1228 | 1482 switch (cpi->cpi_vendor) { |
| 1483 case X86_VENDOR_Intel: | |
| 1484 if (cpi->cpi_maxeax < 4) { | |
| 1485 cpi->cpi_ncore_per_chip = 1; | |
| 1486 break; | |
| 1487 } else { | |
| 1488 cpi->cpi_ncore_per_chip = | |
| 1489 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; | |
| 1490 } | |
| 1491 break; | |
| 1492 case X86_VENDOR_AMD: | |
| 1493 if (cpi->cpi_xmaxeax < 0x80000008) { | |
| 1494 cpi->cpi_ncore_per_chip = 1; | |
| 1495 break; | |
| 1496 } else { | |
|
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1497 /* |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1498 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1499 * 1 less than the number of physical cores on |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1500 * the chip. In family 0x10 this value can |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1501 * be affected by "downcoring" - it reflects |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1502 * 1 less than the number of cores actually |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1503 * enabled on this node. |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1504 */ |
| 1228 | 1505 cpi->cpi_ncore_per_chip = |
| 1506 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; | |
| 1507 } | |
| 1508 break; | |
| 1509 default: | |
| 1510 cpi->cpi_ncore_per_chip = 1; | |
| 1511 break; | |
| 1512 } | |
|
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1513 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1514 /* |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1515 * Get CPUID data about TSC Invariance in Deep C-State. |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1516 */ |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1517 switch (cpi->cpi_vendor) { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1518 case X86_VENDOR_Intel: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1519 if (cpi->cpi_maxeax >= 7) { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1520 cp = &cpi->cpi_extd[7]; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1521 cp->cp_eax = 0x80000007; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1522 cp->cp_ecx = 0; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1523 (void) __cpuid_insn(cp); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1524 } |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1525 break; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1526 default: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1527 break; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
1528 } |
| 5284 | 1529 } else { |
| 1530 cpi->cpi_ncore_per_chip = 1; | |
| 0 | 1531 } |
| 1532 | |
| 1228 | 1533 /* |
| 1534 * If more than one core, then this processor is CMP. | |
| 1535 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1536 if (cpi->cpi_ncore_per_chip > 1) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1537 add_x86_feature(featureset, X86FSET_CMP); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1538 } |
| 3446 | 1539 |
| 1228 | 1540 /* |
| 1541 * If the number of cores is the same as the number | |
| 1542 * of CPUs, then we cannot have HyperThreading. | |
| 1543 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1544 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) { |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1545 remove_x86_feature(featureset, X86FSET_HTT); |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1546 } |
| 1228 | 1547 |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1548 cpi->cpi_apicid = CPI_APIC_ID(cpi); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1549 cpi->cpi_procnodes_per_pkg = 1; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1550 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE && |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1551 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) { |
| 1228 | 1552 /* |
| 1553 * Single-core single-threaded processors. | |
| 1554 */ | |
| 0 | 1555 cpi->cpi_chipid = -1; |
| 1556 cpi->cpi_clogid = 0; | |
| 1228 | 1557 cpi->cpi_coreid = cpu->cpu_id; |
|
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1558 cpi->cpi_pkgcoreid = 0; |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1559 if (cpi->cpi_vendor == X86_VENDOR_AMD) |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1560 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1561 else |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1562 cpi->cpi_procnodeid = cpi->cpi_chipid; |
| 0 | 1563 } else if (cpi->cpi_ncpu_per_chip > 1) { |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1564 if (cpi->cpi_vendor == X86_VENDOR_Intel) |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
1565 cpuid_intel_getids(cpu, featureset); |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1566 else if (cpi->cpi_vendor == X86_VENDOR_AMD) |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1567 cpuid_amd_getids(cpu); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1568 else { |
| 1228 | 1569 /* |
| 1570 * All other processors are currently | |
| 1571 * assumed to have single cores. | |
| 1572 */ | |
| 1573 cpi->cpi_coreid = cpi->cpi_chipid; | |
|
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
1574 cpi->cpi_pkgcoreid = 0; |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
1575 cpi->cpi_procnodeid = cpi->cpi_chipid; |
| 1228 | 1576 } |
| 0 | 1577 } |
| 1578 | |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1579 /* |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1580 * Synthesize chip "revision" and socket type |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1581 */ |
|
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1582 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1583 cpi->cpi_model, cpi->cpi_step); |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1584 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1585 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1586 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, |
|
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
1587 cpi->cpi_model, cpi->cpi_step); |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1588 |
| 0 | 1589 pass1_done: |
| 1590 cpi->cpi_pass = 1; | |
| 1591 } | |
| 1592 | |
| 1593 /* | |
| 1594 * Make copies of the cpuid table entries we depend on, in | |
| 1595 * part for ease of parsing now, in part so that we have only | |
| 1596 * one place to correct any of it, in part for ease of | |
| 1597 * later export to userland, and in part so we can look at | |
| 1598 * this stuff in a crash dump. | |
| 1599 */ | |
| 1600 | |
| 1601 /*ARGSUSED*/ | |
| 1602 void | |
| 1603 cpuid_pass2(cpu_t *cpu) | |
| 1604 { | |
| 1605 uint_t n, nmax; | |
| 1606 int i; | |
| 1228 | 1607 struct cpuid_regs *cp; |
| 0 | 1608 uint8_t *dp; |
| 1609 uint32_t *iptr; | |
| 1610 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1611 | |
| 1612 ASSERT(cpi->cpi_pass == 1); | |
| 1613 | |
| 1614 if (cpi->cpi_maxeax < 1) | |
| 1615 goto pass2_done; | |
| 1616 | |
| 1617 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) | |
| 1618 nmax = NMAX_CPI_STD; | |
| 1619 /* | |
| 1620 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1621 */ | |
| 1622 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { | |
| 1228 | 1623 cp->cp_eax = n; |
| 4606 | 1624 |
| 1625 /* | |
| 1626 * CPUID function 4 expects %ecx to be initialized | |
| 1627 * with an index which indicates which cache to return | |
| 1628 * information about. The OS is expected to call function 4 | |
| 1629 * with %ecx set to 0, 1, 2, ... until it returns with | |
| 1630 * EAX[4:0] set to 0, which indicates there are no more | |
| 1631 * caches. | |
| 1632 * | |
| 1633 * Here, populate cpi_std[4] with the information returned by | |
| 1634 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() | |
| 1635 * when dynamic memory allocation becomes available. | |
| 1636 * | |
| 1637 * Note: we need to explicitly initialize %ecx here, since | |
| 1638 * function 4 may have been previously invoked. | |
| 1639 */ | |
| 1640 if (n == 4) | |
| 1641 cp->cp_ecx = 0; | |
| 1642 | |
| 1228 | 1643 (void) __cpuid_insn(cp); |
| 3446 | 1644 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); |
| 0 | 1645 switch (n) { |
| 1646 case 2: | |
| 1647 /* | |
| 1648 * "the lower 8 bits of the %eax register | |
| 1649 * contain a value that identifies the number | |
| 1650 * of times the cpuid [instruction] has to be | |
| 1651 * executed to obtain a complete image of the | |
| 1652 * processor's caching systems." | |
| 1653 * | |
| 1654 * How *do* they make this stuff up? | |
| 1655 */ | |
| 1656 cpi->cpi_ncache = sizeof (*cp) * | |
| 1657 BITX(cp->cp_eax, 7, 0); | |
| 1658 if (cpi->cpi_ncache == 0) | |
| 1659 break; | |
| 1660 cpi->cpi_ncache--; /* skip count byte */ | |
| 1661 | |
| 1662 /* | |
| 1663 * Well, for now, rather than attempt to implement | |
| 1664 * this slightly dubious algorithm, we just look | |
| 1665 * at the first 15 .. | |
| 1666 */ | |
| 1667 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) | |
| 1668 cpi->cpi_ncache = sizeof (*cp) - 1; | |
| 1669 | |
| 1670 dp = cpi->cpi_cacheinfo; | |
| 1671 if (BITX(cp->cp_eax, 31, 31) == 0) { | |
| 1672 uint8_t *p = (void *)&cp->cp_eax; | |
|
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
1673 for (i = 1; i < 4; i++) |
| 0 | 1674 if (p[i] != 0) |
| 1675 *dp++ = p[i]; | |
| 1676 } | |
| 1677 if (BITX(cp->cp_ebx, 31, 31) == 0) { | |
| 1678 uint8_t *p = (void *)&cp->cp_ebx; | |
| 1679 for (i = 0; i < 4; i++) | |
| 1680 if (p[i] != 0) | |
| 1681 *dp++ = p[i]; | |
| 1682 } | |
| 1683 if (BITX(cp->cp_ecx, 31, 31) == 0) { | |
| 1684 uint8_t *p = (void *)&cp->cp_ecx; | |
| 1685 for (i = 0; i < 4; i++) | |
| 1686 if (p[i] != 0) | |
| 1687 *dp++ = p[i]; | |
| 1688 } | |
| 1689 if (BITX(cp->cp_edx, 31, 31) == 0) { | |
| 1690 uint8_t *p = (void *)&cp->cp_edx; | |
| 1691 for (i = 0; i < 4; i++) | |
| 1692 if (p[i] != 0) | |
| 1693 *dp++ = p[i]; | |
| 1694 } | |
| 1695 break; | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1696 |
| 0 | 1697 case 3: /* Processor serial number, if PSN supported */ |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1698 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1699 |
| 0 | 1700 case 4: /* Deterministic cache parameters */ |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1701 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1702 |
| 0 | 1703 case 5: /* Monitor/Mwait parameters */ |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1704 { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1705 size_t mwait_size; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1706 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1707 /* |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1708 * check cpi_mwait.support which was set in cpuid_pass1 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1709 */ |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1710 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1711 break; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1712 |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1713 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1714 * Protect ourself from insane mwait line size. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1715 * Workaround for incomplete hardware emulator(s). |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1716 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1717 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1718 if (mwait_size < sizeof (uint32_t) || |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1719 !ISP2(mwait_size)) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1720 #if DEBUG |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1721 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1722 "size %ld", cpu->cpu_id, (long)mwait_size); |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1723 #endif |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1724 break; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1725 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1726 |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1727 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1728 cpi->cpi_mwait.mon_max = mwait_size; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1729 if (MWAIT_EXTENSION(cpi)) { |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1730 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1731 if (MWAIT_INT_ENABLE(cpi)) |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1732 cpi->cpi_mwait.support |= |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1733 MWAIT_ECX_INT_ENABLE; |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1734 } |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1735 break; |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
1736 } |
| 0 | 1737 default: |
| 1738 break; | |
| 1739 } | |
| 1740 } | |
| 1741 | |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1742 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1743 struct cpuid_regs regs; |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1744 |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1745 cp = ®s; |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1746 cp->cp_eax = 0xB; |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1747 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1748 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1749 (void) __cpuid_insn(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1750 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1751 /* |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1752 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1753 * indicates that the extended topology enumeration leaf is |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1754 * available. |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1755 */ |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1756 if (cp->cp_ebx) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1757 uint32_t x2apic_id; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1758 uint_t coreid_shift = 0; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1759 uint_t ncpu_per_core = 1; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1760 uint_t chipid_shift = 0; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1761 uint_t ncpu_per_chip = 1; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1762 uint_t i; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1763 uint_t level; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1764 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1765 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1766 cp->cp_eax = 0xB; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1767 cp->cp_ecx = i; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1768 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1769 (void) __cpuid_insn(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1770 level = CPI_CPU_LEVEL_TYPE(cp); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1771 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1772 if (level == 1) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1773 x2apic_id = cp->cp_edx; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1774 coreid_shift = BITX(cp->cp_eax, 4, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1775 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1776 } else if (level == 2) { |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1777 x2apic_id = cp->cp_edx; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1778 chipid_shift = BITX(cp->cp_eax, 4, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1779 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1780 } |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1781 } |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1782 |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1783 cpi->cpi_apicid = x2apic_id; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1784 cpi->cpi_ncpu_per_chip = ncpu_per_chip; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1785 cpi->cpi_ncore_per_chip = ncpu_per_chip / |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1786 ncpu_per_core; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1787 cpi->cpi_chipid = x2apic_id >> chipid_shift; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1788 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1789 cpi->cpi_coreid = x2apic_id >> coreid_shift; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1790 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1791 } |
|
7798
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1792 |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1793 /* Make cp NULL so that we don't stumble on others */ |
|
2a682532f0ca
6749646 cpuid_pass2 stomps on cpi_xmaxeax
Saurabh Misra <Saurabh.Mishra@Sun.COM>
parents:
7716
diff
changeset
|
1794 cp = NULL; |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1795 } |
|
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
1796 |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
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1797 /* |
|
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1798 * XSAVE enumeration |
|
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|
1799 */ |
|
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1800 if (cpi->cpi_maxeax >= 0xD && cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
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|
1801 struct cpuid_regs regs; |
|
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|
1802 boolean_t cpuid_d_valid = B_TRUE; |
|
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1803 |
|
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1804 cp = ®s; |
|
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|
1805 cp->cp_eax = 0xD; |
|
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1806 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; |
|
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|
1807 |
|
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1808 (void) __cpuid_insn(cp); |
|
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|
1809 |
|
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|
1810 /* |
|
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1811 * Sanity checks for debug |
|
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1812 */ |
|
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1813 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 || |
|
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1814 (cp->cp_eax & XFEATURE_SSE) == 0) { |
|
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1815 cpuid_d_valid = B_FALSE; |
|
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1816 } |
|
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1817 |
|
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1818 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax; |
|
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1819 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx; |
|
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1820 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx; |
|
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1821 |
|
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1822 /* |
|
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1823 * If the hw supports AVX, get the size and offset in the save |
|
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1824 * area for the ymm state. |
|
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1825 */ |
|
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1826 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) { |
|
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1827 cp->cp_eax = 0xD; |
|
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1828 cp->cp_ecx = 2; |
|
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1829 cp->cp_edx = cp->cp_ebx = 0; |
|
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1830 |
|
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1831 (void) __cpuid_insn(cp); |
|
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1832 |
|
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1833 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET || |
|
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1834 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) { |
|
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1835 cpuid_d_valid = B_FALSE; |
|
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1836 } |
|
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|
1837 |
|
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1838 cpi->cpi_xsave.ymm_size = cp->cp_eax; |
|
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1839 cpi->cpi_xsave.ymm_offset = cp->cp_ebx; |
|
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|
1840 } |
|
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|
1841 |
|
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1842 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) { |
|
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1843 xsave_state_size = 0; |
|
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1844 } else if (cpuid_d_valid) { |
|
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1845 xsave_state_size = cpi->cpi_xsave.xsav_max_size; |
|
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1846 } else { |
|
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1847 /* Broken CPUID 0xD, probably in HVM */ |
|
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1848 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid " |
|
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1849 "value: hw_low = %d, hw_high = %d, xsave_size = %d" |
|
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1850 ", ymm_size = %d, ymm_offset = %d\n", |
|
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1851 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low, |
|
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1852 cpi->cpi_xsave.xsav_hw_features_high, |
|
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1853 (int)cpi->cpi_xsave.xsav_max_size, |
|
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1854 (int)cpi->cpi_xsave.ymm_size, |
|
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1855 (int)cpi->cpi_xsave.ymm_offset); |
|
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1856 |
|
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1857 if (xsave_state_size != 0) { |
|
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1858 /* |
|
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1859 * This must be a non-boot CPU. We cannot |
|
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1860 * continue, because boot cpu has already |
|
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1861 * enabled XSAVE. |
|
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1862 */ |
|
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1863 ASSERT(cpu->cpu_id != 0); |
|
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1864 cmn_err(CE_PANIC, "cpu%d: we have already " |
|
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|
1865 "enabled XSAVE on boot cpu, cannot " |
|
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|
1866 "continue.", cpu->cpu_id); |
|
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1867 } else { |
|
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1868 /* |
|
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1869 * Must be from boot CPU, OK to disable XSAVE. |
|
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1870 */ |
|
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1871 ASSERT(cpu->cpu_id == 0); |
|
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1872 remove_x86_feature(x86_featureset, |
|
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1873 X86FSET_XSAVE); |
|
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1874 remove_x86_feature(x86_featureset, X86FSET_AVX); |
|
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1875 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_XSAVE; |
|
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|
1876 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_AVX; |
|
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|
1877 xsave_force_disable = B_TRUE; |
|
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|
1878 } |
|
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|
1879 } |
|
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1880 } |
|
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|
1881 |
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1882 |
| 0 | 1883 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) |
| 1884 goto pass2_done; | |
| 1885 | |
| 1886 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) | |
| 1887 nmax = NMAX_CPI_EXTD; | |
| 1888 /* | |
| 1889 * Copy the extended properties, fixing them as we go. | |
| 1890 * (We already handled n == 0 and n == 1 in pass 1) | |
| 1891 */ | |
| 1892 iptr = (void *)cpi->cpi_brandstr; | |
| 1893 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { | |
| 1228 | 1894 cp->cp_eax = 0x80000000 + n; |
| 1895 (void) __cpuid_insn(cp); | |
| 3446 | 1896 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); |
| 0 | 1897 switch (n) { |
| 1898 case 2: | |
| 1899 case 3: | |
| 1900 case 4: | |
| 1901 /* | |
| 1902 * Extract the brand string | |
| 1903 */ | |
| 1904 *iptr++ = cp->cp_eax; | |
| 1905 *iptr++ = cp->cp_ebx; | |
| 1906 *iptr++ = cp->cp_ecx; | |
| 1907 *iptr++ = cp->cp_edx; | |
| 1908 break; | |
| 1909 case 5: | |
| 1910 switch (cpi->cpi_vendor) { | |
| 1911 case X86_VENDOR_AMD: | |
| 1912 /* | |
| 1913 * The Athlon and Duron were the first | |
| 1914 * parts to report the sizes of the | |
| 1915 * TLB for large pages. Before then, | |
| 1916 * we don't trust the data. | |
| 1917 */ | |
| 1918 if (cpi->cpi_family < 6 || | |
| 1919 (cpi->cpi_family == 6 && | |
| 1920 cpi->cpi_model < 1)) | |
| 1921 cp->cp_eax = 0; | |
| 1922 break; | |
| 1923 default: | |
| 1924 break; | |
| 1925 } | |
| 1926 break; | |
| 1927 case 6: | |
| 1928 switch (cpi->cpi_vendor) { | |
| 1929 case X86_VENDOR_AMD: | |
| 1930 /* | |
| 1931 * The Athlon and Duron were the first | |
| 1932 * AMD parts with L2 TLB's. | |
| 1933 * Before then, don't trust the data. | |
| 1934 */ | |
| 1935 if (cpi->cpi_family < 6 || | |
| 1936 cpi->cpi_family == 6 && | |
| 1937 cpi->cpi_model < 1) | |
| 1938 cp->cp_eax = cp->cp_ebx = 0; | |
| 1939 /* | |
| 1940 * AMD Duron rev A0 reports L2 | |
| 1941 * cache size incorrectly as 1K | |
| 1942 * when it is really 64K | |
| 1943 */ | |
| 1944 if (cpi->cpi_family == 6 && | |
| 1945 cpi->cpi_model == 3 && | |
| 1946 cpi->cpi_step == 0) { | |
| 1947 cp->cp_ecx &= 0xffff; | |
| 1948 cp->cp_ecx |= 0x400000; | |
| 1949 } | |
| 1950 break; | |
| 1951 case X86_VENDOR_Cyrix: /* VIA C3 */ | |
| 1952 /* | |
| 1953 * VIA C3 processors are a bit messed | |
| 1954 * up w.r.t. encoding cache sizes in %ecx | |
| 1955 */ | |
| 1956 if (cpi->cpi_family != 6) | |
| 1957 break; | |
| 1958 /* | |
| 1959 * model 7 and 8 were incorrectly encoded | |
| 1960 * | |
| 1961 * xxx is model 8 really broken? | |
| 1962 */ | |
| 1963 if (cpi->cpi_model == 7 || | |
| 1964 cpi->cpi_model == 8) | |
| 1965 cp->cp_ecx = | |
| 1966 BITX(cp->cp_ecx, 31, 24) << 16 | | |
| 1967 BITX(cp->cp_ecx, 23, 16) << 12 | | |
| 1968 BITX(cp->cp_ecx, 15, 8) << 8 | | |
| 1969 BITX(cp->cp_ecx, 7, 0); | |
| 1970 /* | |
| 1971 * model 9 stepping 1 has wrong associativity | |
| 1972 */ | |
| 1973 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) | |
| 1974 cp->cp_ecx |= 8 << 12; | |
| 1975 break; | |
| 1976 case X86_VENDOR_Intel: | |
| 1977 /* | |
| 1978 * Extended L2 Cache features function. | |
| 1979 * First appeared on Prescott. | |
| 1980 */ | |
| 1981 default: | |
| 1982 break; | |
| 1983 } | |
| 1984 break; | |
| 1985 default: | |
| 1986 break; | |
| 1987 } | |
| 1988 } | |
| 1989 | |
| 1990 pass2_done: | |
| 1991 cpi->cpi_pass = 2; | |
| 1992 } | |
| 1993 | |
| 1994 static const char * | |
| 1995 intel_cpubrand(const struct cpuid_info *cpi) | |
| 1996 { | |
| 1997 int i; | |
| 1998 | |
|
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|
1999 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || |
| 0 | 2000 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) |
| 2001 return ("i486"); | |
| 2002 | |
| 2003 switch (cpi->cpi_family) { | |
| 2004 case 5: | |
| 2005 return ("Intel Pentium(r)"); | |
| 2006 case 6: | |
| 2007 switch (cpi->cpi_model) { | |
| 2008 uint_t celeron, xeon; | |
| 1228 | 2009 const struct cpuid_regs *cp; |
| 0 | 2010 case 0: |
| 2011 case 1: | |
| 2012 case 2: | |
| 2013 return ("Intel Pentium(r) Pro"); | |
| 2014 case 3: | |
| 2015 case 4: | |
| 2016 return ("Intel Pentium(r) II"); | |
| 2017 case 6: | |
| 2018 return ("Intel Celeron(r)"); | |
| 2019 case 5: | |
| 2020 case 7: | |
| 2021 celeron = xeon = 0; | |
| 2022 cp = &cpi->cpi_std[2]; /* cache info */ | |
| 2023 | |
|
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|
2024 for (i = 1; i < 4; i++) { |
| 0 | 2025 uint_t tmp; |
| 2026 | |
| 2027 tmp = (cp->cp_eax >> (8 * i)) & 0xff; | |
| 2028 if (tmp == 0x40) | |
| 2029 celeron++; | |
| 2030 if (tmp >= 0x44 && tmp <= 0x45) | |
| 2031 xeon++; | |
| 2032 } | |
| 2033 | |
| 2034 for (i = 0; i < 2; i++) { | |
| 2035 uint_t tmp; | |
| 2036 | |
| 2037 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; | |
| 2038 if (tmp == 0x40) | |
| 2039 celeron++; | |
| 2040 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 2041 xeon++; | |
| 2042 } | |
| 2043 | |
| 2044 for (i = 0; i < 4; i++) { | |
| 2045 uint_t tmp; | |
| 2046 | |
| 2047 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; | |
| 2048 if (tmp == 0x40) | |
| 2049 celeron++; | |
| 2050 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 2051 xeon++; | |
| 2052 } | |
| 2053 | |
| 2054 for (i = 0; i < 4; i++) { | |
| 2055 uint_t tmp; | |
| 2056 | |
| 2057 tmp = (cp->cp_edx >> (8 * i)) & 0xff; | |
| 2058 if (tmp == 0x40) | |
| 2059 celeron++; | |
| 2060 else if (tmp >= 0x44 && tmp <= 0x45) | |
| 2061 xeon++; | |
| 2062 } | |
| 2063 | |
| 2064 if (celeron) | |
| 2065 return ("Intel Celeron(r)"); | |
| 2066 if (xeon) | |
| 2067 return (cpi->cpi_model == 5 ? | |
| 2068 "Intel Pentium(r) II Xeon(tm)" : | |
| 2069 "Intel Pentium(r) III Xeon(tm)"); | |
| 2070 return (cpi->cpi_model == 5 ? | |
| 2071 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : | |
| 2072 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); | |
| 2073 default: | |
| 2074 break; | |
| 2075 } | |
| 2076 default: | |
| 2077 break; | |
| 2078 } | |
| 2079 | |
|
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|
2080 /* BrandID is present if the field is nonzero */ |
|
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|
2081 if (cpi->cpi_brandid != 0) { |
| 0 | 2082 static const struct { |
| 2083 uint_t bt_bid; | |
| 2084 const char *bt_str; | |
| 2085 } brand_tbl[] = { | |
| 2086 { 0x1, "Intel(r) Celeron(r)" }, | |
| 2087 { 0x2, "Intel(r) Pentium(r) III" }, | |
| 2088 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, | |
| 2089 { 0x4, "Intel(r) Pentium(r) III" }, | |
| 2090 { 0x6, "Mobile Intel(r) Pentium(r) III" }, | |
| 2091 { 0x7, "Mobile Intel(r) Celeron(r)" }, | |
| 2092 { 0x8, "Intel(r) Pentium(r) 4" }, | |
| 2093 { 0x9, "Intel(r) Pentium(r) 4" }, | |
| 2094 { 0xa, "Intel(r) Celeron(r)" }, | |
| 2095 { 0xb, "Intel(r) Xeon(tm)" }, | |
| 2096 { 0xc, "Intel(r) Xeon(tm) MP" }, | |
| 2097 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, | |
|
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|
2098 { 0xf, "Mobile Intel(r) Celeron(r)" }, |
|
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|
2099 { 0x11, "Mobile Genuine Intel(r)" }, |
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|
2100 { 0x12, "Intel(r) Celeron(r) M" }, |
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|
2101 { 0x13, "Mobile Intel(r) Celeron(r)" }, |
|
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|
2102 { 0x14, "Intel(r) Celeron(r)" }, |
|
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|
2103 { 0x15, "Mobile Genuine Intel(r)" }, |
|
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|
2104 { 0x16, "Intel(r) Pentium(r) M" }, |
|
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diff
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|
2105 { 0x17, "Mobile Intel(r) Celeron(r)" } |
| 0 | 2106 }; |
| 2107 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); | |
| 2108 uint_t sgn; | |
| 2109 | |
| 2110 sgn = (cpi->cpi_family << 8) | | |
| 2111 (cpi->cpi_model << 4) | cpi->cpi_step; | |
| 2112 | |
| 2113 for (i = 0; i < btblmax; i++) | |
| 2114 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) | |
| 2115 break; | |
| 2116 if (i < btblmax) { | |
| 2117 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) | |
| 2118 return ("Intel(r) Celeron(r)"); | |
| 2119 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) | |
| 2120 return ("Intel(r) Xeon(tm) MP"); | |
| 2121 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) | |
| 2122 return ("Intel(r) Xeon(tm)"); | |
| 2123 return (brand_tbl[i].bt_str); | |
| 2124 } | |
| 2125 } | |
| 2126 | |
| 2127 return (NULL); | |
| 2128 } | |
| 2129 | |
| 2130 static const char * | |
| 2131 amd_cpubrand(const struct cpuid_info *cpi) | |
| 2132 { | |
|
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diff
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|
2133 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || |
| 0 | 2134 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) |
| 2135 return ("i486 compatible"); | |
| 2136 | |
| 2137 switch (cpi->cpi_family) { | |
| 2138 case 5: | |
| 2139 switch (cpi->cpi_model) { | |
| 2140 case 0: | |
| 2141 case 1: | |
| 2142 case 2: | |
| 2143 case 3: | |
| 2144 case 4: | |
| 2145 case 5: | |
| 2146 return ("AMD-K5(r)"); | |
| 2147 case 6: | |
| 2148 case 7: | |
| 2149 return ("AMD-K6(r)"); | |
| 2150 case 8: | |
| 2151 return ("AMD-K6(r)-2"); | |
| 2152 case 9: | |
| 2153 return ("AMD-K6(r)-III"); | |
| 2154 default: | |
| 2155 return ("AMD (family 5)"); | |
| 2156 } | |
| 2157 case 6: | |
| 2158 switch (cpi->cpi_model) { | |
| 2159 case 1: | |
| 2160 return ("AMD-K7(tm)"); | |
| 2161 case 0: | |
| 2162 case 2: | |
| 2163 case 4: | |
| 2164 return ("AMD Athlon(tm)"); | |
| 2165 case 3: | |
| 2166 case 7: | |
| 2167 return ("AMD Duron(tm)"); | |
| 2168 case 6: | |
| 2169 case 8: | |
| 2170 case 10: | |
| 2171 /* | |
| 2172 * Use the L2 cache size to distinguish | |
| 2173 */ | |
| 2174 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? | |
| 2175 "AMD Athlon(tm)" : "AMD Duron(tm)"); | |
| 2176 default: | |
| 2177 return ("AMD (family 6)"); | |
| 2178 } | |
| 2179 default: | |
| 2180 break; | |
| 2181 } | |
| 2182 | |
| 2183 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && | |
| 2184 cpi->cpi_brandid != 0) { | |
| 2185 switch (BITX(cpi->cpi_brandid, 7, 5)) { | |
| 2186 case 3: | |
| 2187 return ("AMD Opteron(tm) UP 1xx"); | |
| 2188 case 4: | |
| 2189 return ("AMD Opteron(tm) DP 2xx"); | |
| 2190 case 5: | |
| 2191 return ("AMD Opteron(tm) MP 8xx"); | |
| 2192 default: | |
| 2193 return ("AMD Opteron(tm)"); | |
| 2194 } | |
| 2195 } | |
| 2196 | |
| 2197 return (NULL); | |
| 2198 } | |
| 2199 | |
| 2200 static const char * | |
| 2201 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) | |
| 2202 { | |
|
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diff
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|
2203 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || |
| 0 | 2204 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || |
| 2205 type == X86_TYPE_CYRIX_486) | |
| 2206 return ("i486 compatible"); | |
| 2207 | |
| 2208 switch (type) { | |
| 2209 case X86_TYPE_CYRIX_6x86: | |
| 2210 return ("Cyrix 6x86"); | |
| 2211 case X86_TYPE_CYRIX_6x86L: | |
| 2212 return ("Cyrix 6x86L"); | |
| 2213 case X86_TYPE_CYRIX_6x86MX: | |
| 2214 return ("Cyrix 6x86MX"); | |
| 2215 case X86_TYPE_CYRIX_GXm: | |
| 2216 return ("Cyrix GXm"); | |
| 2217 case X86_TYPE_CYRIX_MediaGX: | |
| 2218 return ("Cyrix MediaGX"); | |
| 2219 case X86_TYPE_CYRIX_MII: | |
| 2220 return ("Cyrix M2"); | |
| 2221 case X86_TYPE_VIA_CYRIX_III: | |
| 2222 return ("VIA Cyrix M3"); | |
| 2223 default: | |
| 2224 /* | |
| 2225 * Have another wild guess .. | |
| 2226 */ | |
| 2227 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) | |
| 2228 return ("Cyrix 5x86"); | |
| 2229 else if (cpi->cpi_family == 5) { | |
| 2230 switch (cpi->cpi_model) { | |
| 2231 case 2: | |
| 2232 return ("Cyrix 6x86"); /* Cyrix M1 */ | |
| 2233 case 4: | |
| 2234 return ("Cyrix MediaGX"); | |
| 2235 default: | |
| 2236 break; | |
| 2237 } | |
| 2238 } else if (cpi->cpi_family == 6) { | |
| 2239 switch (cpi->cpi_model) { | |
| 2240 case 0: | |
| 2241 return ("Cyrix 6x86MX"); /* Cyrix M2? */ | |
| 2242 case 5: | |
| 2243 case 6: | |
| 2244 case 7: | |
| 2245 case 8: | |
| 2246 case 9: | |
| 2247 return ("VIA C3"); | |
| 2248 default: | |
| 2249 break; | |
| 2250 } | |
| 2251 } | |
| 2252 break; | |
| 2253 } | |
| 2254 return (NULL); | |
| 2255 } | |
| 2256 | |
| 2257 /* | |
| 2258 * This only gets called in the case that the CPU extended | |
| 2259 * feature brand string (0x80000002, 0x80000003, 0x80000004) | |
| 2260 * aren't available, or contain null bytes for some reason. | |
| 2261 */ | |
| 2262 static void | |
| 2263 fabricate_brandstr(struct cpuid_info *cpi) | |
| 2264 { | |
| 2265 const char *brand = NULL; | |
| 2266 | |
| 2267 switch (cpi->cpi_vendor) { | |
| 2268 case X86_VENDOR_Intel: | |
| 2269 brand = intel_cpubrand(cpi); | |
| 2270 break; | |
| 2271 case X86_VENDOR_AMD: | |
| 2272 brand = amd_cpubrand(cpi); | |
| 2273 break; | |
| 2274 case X86_VENDOR_Cyrix: | |
| 2275 brand = cyrix_cpubrand(cpi, x86_type); | |
| 2276 break; | |
| 2277 case X86_VENDOR_NexGen: | |
| 2278 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 2279 brand = "NexGen Nx586"; | |
| 2280 break; | |
| 2281 case X86_VENDOR_Centaur: | |
| 2282 if (cpi->cpi_family == 5) | |
| 2283 switch (cpi->cpi_model) { | |
| 2284 case 4: | |
| 2285 brand = "Centaur C6"; | |
| 2286 break; | |
| 2287 case 8: | |
| 2288 brand = "Centaur C2"; | |
| 2289 break; | |
| 2290 case 9: | |
| 2291 brand = "Centaur C3"; | |
| 2292 break; | |
| 2293 default: | |
| 2294 break; | |
| 2295 } | |
| 2296 break; | |
| 2297 case X86_VENDOR_Rise: | |
| 2298 if (cpi->cpi_family == 5 && | |
| 2299 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) | |
| 2300 brand = "Rise mP6"; | |
| 2301 break; | |
| 2302 case X86_VENDOR_SiS: | |
| 2303 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) | |
| 2304 brand = "SiS 55x"; | |
| 2305 break; | |
| 2306 case X86_VENDOR_TM: | |
| 2307 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) | |
| 2308 brand = "Transmeta Crusoe TM3x00 or TM5x00"; | |
| 2309 break; | |
| 2310 case X86_VENDOR_NSC: | |
| 2311 case X86_VENDOR_UMC: | |
| 2312 default: | |
| 2313 break; | |
| 2314 } | |
| 2315 if (brand) { | |
| 2316 (void) strcpy((char *)cpi->cpi_brandstr, brand); | |
| 2317 return; | |
| 2318 } | |
| 2319 | |
| 2320 /* | |
| 2321 * If all else fails ... | |
| 2322 */ | |
| 2323 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), | |
| 2324 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, | |
| 2325 cpi->cpi_model, cpi->cpi_step); | |
| 2326 } | |
| 2327 | |
| 2328 /* | |
| 2329 * This routine is called just after kernel memory allocation | |
| 2330 * becomes available on cpu0, and as part of mp_startup() on | |
| 2331 * the other cpus. | |
| 2332 * | |
| 4606 | 2333 * Fixup the brand string, and collect any information from cpuid |
| 2334 * that requires dynamicically allocated storage to represent. | |
| 0 | 2335 */ |
| 2336 /*ARGSUSED*/ | |
| 2337 void | |
| 2338 cpuid_pass3(cpu_t *cpu) | |
| 2339 { | |
| 4606 | 2340 int i, max, shft, level, size; |
| 2341 struct cpuid_regs regs; | |
| 2342 struct cpuid_regs *cp; | |
| 0 | 2343 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
| 2344 | |
| 2345 ASSERT(cpi->cpi_pass == 2); | |
| 2346 | |
| 4606 | 2347 /* |
| 2348 * Function 4: Deterministic cache parameters | |
| 2349 * | |
| 2350 * Take this opportunity to detect the number of threads | |
| 2351 * sharing the last level cache, and construct a corresponding | |
| 2352 * cache id. The respective cpuid_info members are initialized | |
| 2353 * to the default case of "no last level cache sharing". | |
| 2354 */ | |
| 2355 cpi->cpi_ncpu_shr_last_cache = 1; | |
| 2356 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; | |
| 2357 | |
| 2358 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { | |
| 2359 | |
| 2360 /* | |
| 2361 * Find the # of elements (size) returned by fn 4, and along | |
| 2362 * the way detect last level cache sharing details. | |
| 2363 */ | |
| 2364 bzero(®s, sizeof (regs)); | |
| 2365 cp = ®s; | |
| 2366 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { | |
| 2367 cp->cp_eax = 4; | |
| 2368 cp->cp_ecx = i; | |
| 2369 | |
| 2370 (void) __cpuid_insn(cp); | |
| 2371 | |
| 2372 if (CPI_CACHE_TYPE(cp) == 0) | |
| 2373 break; | |
| 2374 level = CPI_CACHE_LVL(cp); | |
| 2375 if (level > max) { | |
| 2376 max = level; | |
| 2377 cpi->cpi_ncpu_shr_last_cache = | |
| 2378 CPI_NTHR_SHR_CACHE(cp) + 1; | |
| 2379 } | |
| 2380 } | |
| 2381 cpi->cpi_std_4_size = size = i; | |
| 2382 | |
| 2383 /* | |
| 2384 * Allocate the cpi_std_4 array. The first element | |
| 2385 * references the regs for fn 4, %ecx == 0, which | |
| 2386 * cpuid_pass2() stashed in cpi->cpi_std[4]. | |
| 2387 */ | |
| 2388 if (size > 0) { | |
| 2389 cpi->cpi_std_4 = | |
| 2390 kmem_alloc(size * sizeof (cp), KM_SLEEP); | |
| 2391 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; | |
| 2392 | |
| 2393 /* | |
| 2394 * Allocate storage to hold the additional regs | |
| 2395 * for function 4, %ecx == 1 .. cpi_std_4_size. | |
| 2396 * | |
| 2397 * The regs for fn 4, %ecx == 0 has already | |
| 2398 * been allocated as indicated above. | |
| 2399 */ | |
| 2400 for (i = 1; i < size; i++) { | |
| 2401 cp = cpi->cpi_std_4[i] = | |
| 2402 kmem_zalloc(sizeof (regs), KM_SLEEP); | |
| 2403 cp->cp_eax = 4; | |
| 2404 cp->cp_ecx = i; | |
| 2405 | |
| 2406 (void) __cpuid_insn(cp); | |
| 2407 } | |
| 2408 } | |
| 2409 /* | |
| 2410 * Determine the number of bits needed to represent | |
| 2411 * the number of CPUs sharing the last level cache. | |
| 2412 * | |
| 2413 * Shift off that number of bits from the APIC id to | |
| 2414 * derive the cache id. | |
| 2415 */ | |
| 2416 shft = 0; | |
| 2417 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) | |
| 2418 shft++; | |
|
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6964
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changeset
|
2419 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; |
| 0 | 2420 } |
| 2421 | |
| 2422 /* | |
| 4606 | 2423 * Now fixup the brand string |
| 0 | 2424 */ |
| 4606 | 2425 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { |
| 2426 fabricate_brandstr(cpi); | |
| 2427 } else { | |
| 0 | 2428 |
| 2429 /* | |
| 4606 | 2430 * If we successfully extracted a brand string from the cpuid |
| 2431 * instruction, clean it up by removing leading spaces and | |
| 2432 * similar junk. | |
| 0 | 2433 */ |
| 4606 | 2434 if (cpi->cpi_brandstr[0]) { |
| 2435 size_t maxlen = sizeof (cpi->cpi_brandstr); | |
| 2436 char *src, *dst; | |
| 2437 | |
| 2438 dst = src = (char *)cpi->cpi_brandstr; | |
| 2439 src[maxlen - 1] = '\0'; | |
| 2440 /* | |
| 2441 * strip leading spaces | |
| 2442 */ | |
| 2443 while (*src == ' ') | |
| 2444 src++; | |
| 2445 /* | |
| 2446 * Remove any 'Genuine' or "Authentic" prefixes | |
| 2447 */ | |
| 2448 if (strncmp(src, "Genuine ", 8) == 0) | |
| 2449 src += 8; | |
| 2450 if (strncmp(src, "Authentic ", 10) == 0) | |
| 2451 src += 10; | |
| 2452 | |
| 2453 /* | |
| 2454 * Now do an in-place copy. | |
| 2455 * Map (R) to (r) and (TM) to (tm). | |
| 2456 * The era of teletypes is long gone, and there's | |
| 2457 * -really- no need to shout. | |
| 2458 */ | |
| 2459 while (*src != '\0') { | |
| 2460 if (src[0] == '(') { | |
| 2461 if (strncmp(src + 1, "R)", 2) == 0) { | |
| 2462 (void) strncpy(dst, "(r)", 3); | |
| 2463 src += 3; | |
| 2464 dst += 3; | |
| 2465 continue; | |
| 2466 } | |
| 2467 if (strncmp(src + 1, "TM)", 3) == 0) { | |
| 2468 (void) strncpy(dst, "(tm)", 4); | |
| 2469 src += 4; | |
| 2470 dst += 4; | |
| 2471 continue; | |
| 2472 } | |
| 0 | 2473 } |
| 4606 | 2474 *dst++ = *src++; |
| 0 | 2475 } |
| 4606 | 2476 *dst = '\0'; |
| 2477 | |
| 2478 /* | |
| 2479 * Finally, remove any trailing spaces | |
| 2480 */ | |
| 2481 while (--dst > cpi->cpi_brandstr) | |
| 2482 if (*dst == ' ') | |
| 2483 *dst = '\0'; | |
| 2484 else | |
| 2485 break; | |
| 2486 } else | |
| 2487 fabricate_brandstr(cpi); | |
| 2488 } | |
| 0 | 2489 cpi->cpi_pass = 3; |
| 2490 } | |
| 2491 | |
| 2492 /* | |
| 2493 * This routine is called out of bind_hwcap() much later in the life | |
| 2494 * of the kernel (post_startup()). The job of this routine is to resolve | |
| 2495 * the hardware feature support and kernel support for those features into | |
| 2496 * what we're actually going to tell applications via the aux vector. | |
| 2497 */ | |
| 2498 uint_t | |
| 2499 cpuid_pass4(cpu_t *cpu) | |
| 2500 { | |
| 2501 struct cpuid_info *cpi; | |
| 2502 uint_t hwcap_flags = 0; | |
| 2503 | |
| 2504 if (cpu == NULL) | |
| 2505 cpu = CPU; | |
| 2506 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2507 | |
| 2508 ASSERT(cpi->cpi_pass == 3); | |
| 2509 | |
| 2510 if (cpi->cpi_maxeax >= 1) { | |
| 2511 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; | |
| 2512 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; | |
| 2513 | |
| 2514 *edx = CPI_FEATURES_EDX(cpi); | |
| 2515 *ecx = CPI_FEATURES_ECX(cpi); | |
| 2516 | |
| 2517 /* | |
| 2518 * [these require explicit kernel support] | |
| 2519 */ | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2520 if (!is_x86_feature(x86_featureset, X86FSET_SEP)) |
| 0 | 2521 *edx &= ~CPUID_INTC_EDX_SEP; |
| 2522 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2523 if (!is_x86_feature(x86_featureset, X86FSET_SSE)) |
| 0 | 2524 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2525 if (!is_x86_feature(x86_featureset, X86FSET_SSE2)) |
| 0 | 2526 *edx &= ~CPUID_INTC_EDX_SSE2; |
| 2527 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2528 if (!is_x86_feature(x86_featureset, X86FSET_HTT)) |
| 0 | 2529 *edx &= ~CPUID_INTC_EDX_HTT; |
| 2530 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2531 if (!is_x86_feature(x86_featureset, X86FSET_SSE3)) |
| 0 | 2532 *ecx &= ~CPUID_INTC_ECX_SSE3; |
| 2533 | |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2534 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2535 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3)) |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2536 *ecx &= ~CPUID_INTC_ECX_SSSE3; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2537 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1)) |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2538 *ecx &= ~CPUID_INTC_ECX_SSE4_1; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2539 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2)) |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2540 *ecx &= ~CPUID_INTC_ECX_SSE4_2; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2541 if (!is_x86_feature(x86_featureset, X86FSET_AES)) |
|
9370
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2542 *ecx &= ~CPUID_INTC_ECX_AES; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2543 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ)) |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2544 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ; |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2545 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE)) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2546 *ecx &= ~(CPUID_INTC_ECX_XSAVE | |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2547 CPUID_INTC_ECX_OSXSAVE); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2548 if (!is_x86_feature(x86_featureset, X86FSET_AVX)) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2549 *ecx &= ~CPUID_INTC_ECX_AVX; |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2550 } |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2551 |
| 0 | 2552 /* |
| 2553 * [no explicit support required beyond x87 fp context] | |
| 2554 */ | |
| 2555 if (!fpu_exists) | |
| 2556 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); | |
| 2557 | |
| 2558 /* | |
| 2559 * Now map the supported feature vector to things that we | |
| 2560 * think userland will care about. | |
| 2561 */ | |
| 2562 if (*edx & CPUID_INTC_EDX_SEP) | |
| 2563 hwcap_flags |= AV_386_SEP; | |
| 2564 if (*edx & CPUID_INTC_EDX_SSE) | |
| 2565 hwcap_flags |= AV_386_FXSR | AV_386_SSE; | |
| 2566 if (*edx & CPUID_INTC_EDX_SSE2) | |
| 2567 hwcap_flags |= AV_386_SSE2; | |
| 2568 if (*ecx & CPUID_INTC_ECX_SSE3) | |
| 2569 hwcap_flags |= AV_386_SSE3; | |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2570 if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2571 if (*ecx & CPUID_INTC_ECX_SSSE3) |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2572 hwcap_flags |= AV_386_SSSE3; |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2573 if (*ecx & CPUID_INTC_ECX_SSE4_1) |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2574 hwcap_flags |= AV_386_SSE4_1; |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2575 if (*ecx & CPUID_INTC_ECX_SSE4_2) |
|
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2576 hwcap_flags |= AV_386_SSE4_2; |
|
8418
a4853cd72a21
6719310 Expose availability of MOVBE instruction
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
8377
diff
changeset
|
2577 if (*ecx & CPUID_INTC_ECX_MOVBE) |
|
a4853cd72a21
6719310 Expose availability of MOVBE instruction
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
8377
diff
changeset
|
2578 hwcap_flags |= AV_386_MOVBE; |
|
9370
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2579 if (*ecx & CPUID_INTC_ECX_AES) |
|
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2580 hwcap_flags |= AV_386_AES; |
|
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2581 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) |
|
5f964d9a7826
6750666 getisax(2) needs to detect Intel AES instruction set extension and PCLMULQDQ instruction
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9283
diff
changeset
|
2582 hwcap_flags |= AV_386_PCLMULQDQ; |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2583 if ((*ecx & CPUID_INTC_ECX_XSAVE) && |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2584 (*ecx & CPUID_INTC_ECX_OSXSAVE)) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
2585 hwcap_flags |= AV_386_XSAVE; |
|
5269
395a95dbfd17
6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors
kk208521
parents:
5254
diff
changeset
|
2586 } |
|
13425
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
2587 if (*ecx & CPUID_INTC_ECX_VMX) |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
2588 hwcap_flags |= AV_386_VMX; |
|
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2589 if (*ecx & CPUID_INTC_ECX_POPCNT) |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2590 hwcap_flags |= AV_386_POPCNT; |
| 0 | 2591 if (*edx & CPUID_INTC_EDX_FPU) |
| 2592 hwcap_flags |= AV_386_FPU; | |
| 2593 if (*edx & CPUID_INTC_EDX_MMX) | |
| 2594 hwcap_flags |= AV_386_MMX; | |
| 2595 | |
| 2596 if (*edx & CPUID_INTC_EDX_TSC) | |
| 2597 hwcap_flags |= AV_386_TSC; | |
| 2598 if (*edx & CPUID_INTC_EDX_CX8) | |
| 2599 hwcap_flags |= AV_386_CX8; | |
| 2600 if (*edx & CPUID_INTC_EDX_CMOV) | |
| 2601 hwcap_flags |= AV_386_CMOV; | |
| 2602 if (*ecx & CPUID_INTC_ECX_CX16) | |
| 2603 hwcap_flags |= AV_386_CX16; | |
| 2604 } | |
| 2605 | |
| 2606 if (cpi->cpi_xmaxeax < 0x80000001) | |
| 2607 goto pass4_done; | |
| 2608 | |
| 2609 switch (cpi->cpi_vendor) { | |
| 1228 | 2610 struct cpuid_regs cp; |
| 3446 | 2611 uint32_t *edx, *ecx; |
| 0 | 2612 |
| 3446 | 2613 case X86_VENDOR_Intel: |
| 2614 /* | |
| 2615 * Seems like Intel duplicated what we necessary | |
| 2616 * here to make the initial crop of 64-bit OS's work. | |
| 2617 * Hopefully, those are the only "extended" bits | |
| 2618 * they'll add. | |
| 2619 */ | |
| 2620 /*FALLTHROUGH*/ | |
| 2621 | |
| 0 | 2622 case X86_VENDOR_AMD: |
| 2623 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; | |
| 3446 | 2624 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; |
| 0 | 2625 |
| 2626 *edx = CPI_FEATURES_XTD_EDX(cpi); | |
| 3446 | 2627 *ecx = CPI_FEATURES_XTD_ECX(cpi); |
| 2628 | |
| 2629 /* | |
| 2630 * [these features require explicit kernel support] | |
| 2631 */ | |
| 2632 switch (cpi->cpi_vendor) { | |
| 2633 case X86_VENDOR_Intel: | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2634 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) |
| 6657 | 2635 *edx &= ~CPUID_AMD_EDX_TSCP; |
| 3446 | 2636 break; |
| 2637 | |
| 2638 case X86_VENDOR_AMD: | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2639 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) |
| 3446 | 2640 *edx &= ~CPUID_AMD_EDX_TSCP; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2641 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A)) |
|
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2642 *ecx &= ~CPUID_AMD_ECX_SSE4A; |
| 3446 | 2643 break; |
| 2644 | |
| 2645 default: | |
| 2646 break; | |
| 2647 } | |
| 0 | 2648 |
| 2649 /* | |
| 2650 * [no explicit support required beyond | |
| 2651 * x87 fp context and exception handlers] | |
| 2652 */ | |
| 2653 if (!fpu_exists) | |
| 2654 *edx &= ~(CPUID_AMD_EDX_MMXamd | | |
| 2655 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); | |
| 2656 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
2657 if (!is_x86_feature(x86_featureset, X86FSET_NX)) |
| 0 | 2658 *edx &= ~CPUID_AMD_EDX_NX; |
| 3446 | 2659 #if !defined(__amd64) |
| 0 | 2660 *edx &= ~CPUID_AMD_EDX_LM; |
| 2661 #endif | |
| 2662 /* | |
| 2663 * Now map the supported feature vector to | |
| 2664 * things that we think userland will care about. | |
| 2665 */ | |
| 3446 | 2666 #if defined(__amd64) |
| 0 | 2667 if (*edx & CPUID_AMD_EDX_SYSC) |
| 2668 hwcap_flags |= AV_386_AMD_SYSC; | |
| 3446 | 2669 #endif |
| 0 | 2670 if (*edx & CPUID_AMD_EDX_MMXamd) |
| 2671 hwcap_flags |= AV_386_AMD_MMX; | |
| 2672 if (*edx & CPUID_AMD_EDX_3DNow) | |
| 2673 hwcap_flags |= AV_386_AMD_3DNow; | |
| 2674 if (*edx & CPUID_AMD_EDX_3DNowx) | |
| 2675 hwcap_flags |= AV_386_AMD_3DNowx; | |
|
13425
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
2676 if (*ecx & CPUID_AMD_ECX_SVM) |
|
8640246a3548
1347 isainfo should indicate presence of vmx/svm support
Bryan Cantrill <bryan@joyent.com>
parents:
13148
diff
changeset
|
2677 hwcap_flags |= AV_386_AMD_SVM; |
| 3446 | 2678 |
| 2679 switch (cpi->cpi_vendor) { | |
| 2680 case X86_VENDOR_AMD: | |
| 2681 if (*edx & CPUID_AMD_EDX_TSCP) | |
| 2682 hwcap_flags |= AV_386_TSCP; | |
| 2683 if (*ecx & CPUID_AMD_ECX_AHF64) | |
| 2684 hwcap_flags |= AV_386_AHF; | |
|
4628
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2685 if (*ecx & CPUID_AMD_ECX_SSE4A) |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2686 hwcap_flags |= AV_386_AMD_SSE4A; |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2687 if (*ecx & CPUID_AMD_ECX_LZCNT) |
|
f90cf8fd4710
6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor
kk208521
parents:
4606
diff
changeset
|
2688 hwcap_flags |= AV_386_AMD_LZCNT; |
| 3446 | 2689 break; |
| 2690 | |
| 2691 case X86_VENDOR_Intel: | |
| 6657 | 2692 if (*edx & CPUID_AMD_EDX_TSCP) |
| 2693 hwcap_flags |= AV_386_TSCP; | |
| 3446 | 2694 /* |
| 2695 * Aarrgh. | |
| 2696 * Intel uses a different bit in the same word. | |
| 2697 */ | |
| 2698 if (*ecx & CPUID_INTC_ECX_AHF64) | |
| 2699 hwcap_flags |= AV_386_AHF; | |
| 2700 break; | |
| 2701 | |
| 2702 default: | |
| 2703 break; | |
| 2704 } | |
| 0 | 2705 break; |
| 2706 | |
| 2707 case X86_VENDOR_TM: | |
| 1228 | 2708 cp.cp_eax = 0x80860001; |
| 2709 (void) __cpuid_insn(&cp); | |
| 2710 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; | |
| 0 | 2711 break; |
| 2712 | |
| 2713 default: | |
| 2714 break; | |
| 2715 } | |
| 2716 | |
| 2717 pass4_done: | |
| 2718 cpi->cpi_pass = 4; | |
| 2719 return (hwcap_flags); | |
| 2720 } | |
| 2721 | |
| 2722 | |
| 2723 /* | |
| 2724 * Simulate the cpuid instruction using the data we previously | |
| 2725 * captured about this CPU. We try our best to return the truth | |
| 2726 * about the hardware, independently of kernel support. | |
| 2727 */ | |
| 2728 uint32_t | |
| 1228 | 2729 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) |
| 0 | 2730 { |
| 2731 struct cpuid_info *cpi; | |
| 1228 | 2732 struct cpuid_regs *xcp; |
| 0 | 2733 |
| 2734 if (cpu == NULL) | |
| 2735 cpu = CPU; | |
| 2736 cpi = cpu->cpu_m.mcpu_cpi; | |
| 2737 | |
| 2738 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2739 | |
| 2740 /* | |
| 2741 * CPUID data is cached in two separate places: cpi_std for standard | |
| 2742 * CPUID functions, and cpi_extd for extended CPUID functions. | |
| 2743 */ | |
| 1228 | 2744 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) |
| 2745 xcp = &cpi->cpi_std[cp->cp_eax]; | |
| 2746 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && | |
| 2747 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) | |
| 2748 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; | |
| 0 | 2749 else |
| 2750 /* | |
| 2751 * The caller is asking for data from an input parameter which | |
| 2752 * the kernel has not cached. In this case we go fetch from | |
| 2753 * the hardware and return the data directly to the user. | |
| 2754 */ | |
| 1228 | 2755 return (__cpuid_insn(cp)); |
| 2756 | |
| 2757 cp->cp_eax = xcp->cp_eax; | |
| 2758 cp->cp_ebx = xcp->cp_ebx; | |
| 2759 cp->cp_ecx = xcp->cp_ecx; | |
| 2760 cp->cp_edx = xcp->cp_edx; | |
| 0 | 2761 return (cp->cp_eax); |
| 2762 } | |
| 2763 | |
| 2764 int | |
| 2765 cpuid_checkpass(cpu_t *cpu, int pass) | |
| 2766 { | |
| 2767 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && | |
| 2768 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); | |
| 2769 } | |
| 2770 | |
| 2771 int | |
| 2772 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) | |
| 2773 { | |
| 2774 ASSERT(cpuid_checkpass(cpu, 3)); | |
| 2775 | |
| 2776 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); | |
| 2777 } | |
| 2778 | |
| 2779 int | |
| 1228 | 2780 cpuid_is_cmt(cpu_t *cpu) |
| 0 | 2781 { |
| 2782 if (cpu == NULL) | |
| 2783 cpu = CPU; | |
| 2784 | |
| 2785 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2786 | |
| 2787 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); | |
| 2788 } | |
| 2789 | |
| 2790 /* | |
| 2791 * AMD and Intel both implement the 64-bit variant of the syscall | |
| 2792 * instruction (syscallq), so if there's -any- support for syscall, | |
| 2793 * cpuid currently says "yes, we support this". | |
| 2794 * | |
| 2795 * However, Intel decided to -not- implement the 32-bit variant of the | |
| 2796 * syscall instruction, so we provide a predicate to allow our caller | |
| 2797 * to test that subtlety here. | |
| 5084 | 2798 * |
| 2799 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, | |
| 2800 * even in the case where the hardware would in fact support it. | |
| 0 | 2801 */ |
| 2802 /*ARGSUSED*/ | |
| 2803 int | |
| 2804 cpuid_syscall32_insn(cpu_t *cpu) | |
| 2805 { | |
| 2806 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); | |
| 2807 | |
| 5084 | 2808 #if !defined(__xpv) |
| 3446 | 2809 if (cpu == NULL) |
| 2810 cpu = CPU; | |
| 2811 | |
| 2812 /*CSTYLED*/ | |
| 2813 { | |
| 2814 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2815 | |
| 2816 if (cpi->cpi_vendor == X86_VENDOR_AMD && | |
| 2817 cpi->cpi_xmaxeax >= 0x80000001 && | |
| 2818 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) | |
| 2819 return (1); | |
| 2820 } | |
| 5084 | 2821 #endif |
| 0 | 2822 return (0); |
| 2823 } | |
| 2824 | |
| 2825 int | |
| 2826 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) | |
| 2827 { | |
| 2828 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 2829 | |
| 2830 static const char fmt[] = | |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2831 "x86 (%s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2832 static const char fmt_ht[] = |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2833 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; |
| 0 | 2834 |
| 2835 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2836 | |
| 1228 | 2837 if (cpuid_is_cmt(cpu)) |
| 0 | 2838 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2839 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
|
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2840 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2841 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2842 return (snprintf(s, n, fmt, | |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2843 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
|
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
2844 cpi->cpi_family, cpi->cpi_model, |
| 0 | 2845 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
| 2846 } | |
| 2847 | |
| 2848 const char * | |
| 2849 cpuid_getvendorstr(cpu_t *cpu) | |
| 2850 { | |
| 2851 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2852 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); | |
| 2853 } | |
| 2854 | |
| 2855 uint_t | |
| 2856 cpuid_getvendor(cpu_t *cpu) | |
| 2857 { | |
| 2858 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2859 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); | |
| 2860 } | |
| 2861 | |
| 2862 uint_t | |
| 2863 cpuid_getfamily(cpu_t *cpu) | |
| 2864 { | |
| 2865 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2866 return (cpu->cpu_m.mcpu_cpi->cpi_family); | |
| 2867 } | |
| 2868 | |
| 2869 uint_t | |
| 2870 cpuid_getmodel(cpu_t *cpu) | |
| 2871 { | |
| 2872 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2873 return (cpu->cpu_m.mcpu_cpi->cpi_model); | |
| 2874 } | |
| 2875 | |
| 2876 uint_t | |
| 2877 cpuid_get_ncpu_per_chip(cpu_t *cpu) | |
| 2878 { | |
| 2879 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2880 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); | |
| 2881 } | |
| 2882 | |
| 2883 uint_t | |
| 1228 | 2884 cpuid_get_ncore_per_chip(cpu_t *cpu) |
| 2885 { | |
| 2886 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2887 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); | |
| 2888 } | |
| 2889 | |
| 2890 uint_t | |
| 4606 | 2891 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) |
| 2892 { | |
| 2893 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2894 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); | |
| 2895 } | |
| 2896 | |
| 2897 id_t | |
| 2898 cpuid_get_last_lvl_cacheid(cpu_t *cpu) | |
| 2899 { | |
| 2900 ASSERT(cpuid_checkpass(cpu, 2)); | |
| 2901 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); | |
| 2902 } | |
| 2903 | |
| 2904 uint_t | |
| 0 | 2905 cpuid_getstep(cpu_t *cpu) |
| 2906 { | |
| 2907 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2908 return (cpu->cpu_m.mcpu_cpi->cpi_step); | |
| 2909 } | |
| 2910 | |
| 4581 | 2911 uint_t |
| 2912 cpuid_getsig(struct cpu *cpu) | |
| 2913 { | |
| 2914 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2915 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); | |
| 2916 } | |
| 2917 | |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2918 uint32_t |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2919 cpuid_getchiprev(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2920 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2921 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2922 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2923 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2924 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2925 const char * |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2926 cpuid_getchiprevstr(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2927 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2928 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2929 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2930 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2931 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2932 uint32_t |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2933 cpuid_getsockettype(struct cpu *cpu) |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2934 { |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2935 ASSERT(cpuid_checkpass(cpu, 1)); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2936 return (cpu->cpu_m.mcpu_cpi->cpi_socket); |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2937 } |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2938 |
|
9482
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2939 const char * |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2940 cpuid_getsocketstr(cpu_t *cpu) |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2941 { |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2942 static const char *socketstr = NULL; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2943 struct cpuid_info *cpi; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2944 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2945 ASSERT(cpuid_checkpass(cpu, 1)); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2946 cpi = cpu->cpu_m.mcpu_cpi; |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2947 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2948 /* Assume that socket types are the same across the system */ |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2949 if (socketstr == NULL) |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2950 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2951 cpi->cpi_model, cpi->cpi_step); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2952 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2953 |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2954 return (socketstr); |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2955 } |
|
42f3d60af7ca
6770233 New model ID for Istanbul processor
Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM>
parents:
9370
diff
changeset
|
2956 |
| 3434 | 2957 int |
| 2958 cpuid_get_chipid(cpu_t *cpu) | |
| 0 | 2959 { |
| 2960 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2961 | |
| 1228 | 2962 if (cpuid_is_cmt(cpu)) |
| 0 | 2963 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); |
| 2964 return (cpu->cpu_id); | |
| 2965 } | |
| 2966 | |
| 1228 | 2967 id_t |
| 3434 | 2968 cpuid_get_coreid(cpu_t *cpu) |
| 1228 | 2969 { |
| 2970 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2971 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); | |
| 2972 } | |
| 2973 | |
| 0 | 2974 int |
|
5870
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2975 cpuid_get_pkgcoreid(cpu_t *cpu) |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2976 { |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2977 ASSERT(cpuid_checkpass(cpu, 1)); |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2978 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2979 } |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2980 |
|
2513339ac53a
6642169 cpu.generic panic during install of snv_76 and later builds
gavinm
parents:
5741
diff
changeset
|
2981 int |
| 3434 | 2982 cpuid_get_clogid(cpu_t *cpu) |
| 0 | 2983 { |
| 2984 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 2985 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); | |
| 2986 } | |
| 2987 | |
|
11389
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2988 int |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2989 cpuid_get_cacheid(cpu_t *cpu) |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2990 { |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2991 ASSERT(cpuid_checkpass(cpu, 1)); |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2992 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2993 } |
|
dd00b884e84f
6764832 Provide user-level processor groups observability
Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>
parents:
11013
diff
changeset
|
2994 |
|
10947
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2995 uint_t |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2996 cpuid_get_procnodeid(cpu_t *cpu) |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2997 { |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2998 ASSERT(cpuid_checkpass(cpu, 1)); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
2999 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3000 } |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3001 |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3002 uint_t |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3003 cpuid_get_procnodes_per_pkg(cpu_t *cpu) |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3004 { |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3005 ASSERT(cpuid_checkpass(cpu, 1)); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3006 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg); |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3007 } |
|
2ecbb0a4d189
6843035 Need support for Magny-Cours processors
Srihari Venkatesan <Srihari.Venkatesan@Sun.COM>
parents:
10175
diff
changeset
|
3008 |
|
10080
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3009 /*ARGSUSED*/ |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3010 int |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3011 cpuid_have_cr8access(cpu_t *cpu) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3012 { |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3013 #if defined(__amd64) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3014 return (1); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3015 #else |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3016 struct cpuid_info *cpi; |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3017 |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3018 ASSERT(cpu != NULL); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3019 cpi = cpu->cpu_m.mcpu_cpi; |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3020 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3021 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3022 return (1); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3023 return (0); |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3024 #endif |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3025 } |
|
29a4a1bb9f3f
6848982 32 bit kernel should use %cr8 to access the TPR when possible
Joe Bonasera <Joe.Bonasera@sun.com>
parents:
9652
diff
changeset
|
3026 |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3027 uint32_t |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3028 cpuid_get_apicid(cpu_t *cpu) |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3029 { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3030 ASSERT(cpuid_checkpass(cpu, 1)); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3031 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3032 return (UINT32_MAX); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3033 } else { |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3034 return (cpu->cpu_m.mcpu_cpi->cpi_apicid); |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3035 } |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3036 } |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3037 |
| 0 | 3038 void |
| 3039 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) | |
| 3040 { | |
| 3041 struct cpuid_info *cpi; | |
| 3042 | |
| 3043 if (cpu == NULL) | |
| 3044 cpu = CPU; | |
| 3045 cpi = cpu->cpu_m.mcpu_cpi; | |
| 3046 | |
| 3047 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 3048 | |
| 3049 if (pabits) | |
| 3050 *pabits = cpi->cpi_pabits; | |
| 3051 if (vabits) | |
| 3052 *vabits = cpi->cpi_vabits; | |
| 3053 } | |
| 3054 | |
| 3055 /* | |
| 3056 * Returns the number of data TLB entries for a corresponding | |
| 3057 * pagesize. If it can't be computed, or isn't known, the | |
| 3058 * routine returns zero. If you ask about an architecturally | |
| 3059 * impossible pagesize, the routine will panic (so that the | |
| 3060 * hat implementor knows that things are inconsistent.) | |
| 3061 */ | |
| 3062 uint_t | |
| 3063 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) | |
| 3064 { | |
| 3065 struct cpuid_info *cpi; | |
| 3066 uint_t dtlb_nent = 0; | |
| 3067 | |
| 3068 if (cpu == NULL) | |
| 3069 cpu = CPU; | |
| 3070 cpi = cpu->cpu_m.mcpu_cpi; | |
| 3071 | |
| 3072 ASSERT(cpuid_checkpass(cpu, 1)); | |
| 3073 | |
| 3074 /* | |
| 3075 * Check the L2 TLB info | |
| 3076 */ | |
| 3077 if (cpi->cpi_xmaxeax >= 0x80000006) { | |
| 1228 | 3078 struct cpuid_regs *cp = &cpi->cpi_extd[6]; |
| 0 | 3079 |
| 3080 switch (pagesize) { | |
| 3081 | |
| 3082 case 4 * 1024: | |
| 3083 /* | |
| 3084 * All zero in the top 16 bits of the register | |
| 3085 * indicates a unified TLB. Size is in low 16 bits. | |
| 3086 */ | |
| 3087 if ((cp->cp_ebx & 0xffff0000) == 0) | |
| 3088 dtlb_nent = cp->cp_ebx & 0x0000ffff; | |
| 3089 else | |
| 3090 dtlb_nent = BITX(cp->cp_ebx, 27, 16); | |
| 3091 break; | |
| 3092 | |
| 3093 case 2 * 1024 * 1024: | |
| 3094 if ((cp->cp_eax & 0xffff0000) == 0) | |
| 3095 dtlb_nent = cp->cp_eax & 0x0000ffff; | |
| 3096 else | |
| 3097 dtlb_nent = BITX(cp->cp_eax, 27, 16); | |
| 3098 break; | |
| 3099 | |
| 3100 default: | |
| 3101 panic("unknown L2 pagesize"); | |
| 3102 /*NOTREACHED*/ | |
| 3103 } | |
| 3104 } | |
| 3105 | |
| 3106 if (dtlb_nent != 0) | |
| 3107 return (dtlb_nent); | |
| 3108 | |
| 3109 /* | |
| 3110 * No L2 TLB support for this size, try L1. | |
| 3111 */ | |
| 3112 if (cpi->cpi_xmaxeax >= 0x80000005) { | |
| 1228 | 3113 struct cpuid_regs *cp = &cpi->cpi_extd[5]; |
| 0 | 3114 |
| 3115 switch (pagesize) { | |
| 3116 case 4 * 1024: | |
| 3117 dtlb_nent = BITX(cp->cp_ebx, 23, 16); | |
| 3118 break; | |
| 3119 case 2 * 1024 * 1024: | |
| 3120 dtlb_nent = BITX(cp->cp_eax, 23, 16); | |
| 3121 break; | |
| 3122 default: | |
| 3123 panic("unknown L1 d-TLB pagesize"); | |
| 3124 /*NOTREACHED*/ | |
| 3125 } | |
| 3126 } | |
| 3127 | |
| 3128 return (dtlb_nent); | |
| 3129 } | |
| 3130 | |
| 3131 /* | |
| 3132 * Return 0 if the erratum is not present or not applicable, positive | |
| 3133 * if it is, and negative if the status of the erratum is unknown. | |
| 3134 * | |
| 3135 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) | |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
3136 * Processors" #25759, Rev 3.57, August 2005 |
| 0 | 3137 */ |
| 3138 int | |
| 3139 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) | |
| 3140 { | |
| 3141 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 1228 | 3142 uint_t eax; |
| 0 | 3143 |
|
2584
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
3144 /* |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
3145 * Bail out if this CPU isn't an AMD CPU, or if it's |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
3146 * a legacy (32-bit) AMD CPU. |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
3147 */ |
|
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
3148 if (cpi->cpi_vendor != X86_VENDOR_AMD || |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3149 cpi->cpi_family == 4 || cpi->cpi_family == 5 || |
|
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3150 cpi->cpi_family == 6) |
|
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
3151 |
| 0 | 3152 return (0); |
| 3153 | |
| 3154 eax = cpi->cpi_std[1].cp_eax; | |
| 3155 | |
| 3156 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) | |
| 3157 #define SH_B3(eax) (eax == 0xf51) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3158 #define B(eax) (SH_B0(eax) || SH_B3(eax)) |
| 0 | 3159 |
| 3160 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) | |
| 3161 | |
| 3162 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) | |
| 3163 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) | |
| 3164 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3165 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) |
| 0 | 3166 |
| 3167 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) | |
| 3168 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) | |
| 3169 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3170 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) |
| 0 | 3171 |
| 3172 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) | |
| 3173 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ | |
| 3174 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) | |
| 3175 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) | |
| 3176 #define BH_E4(eax) (eax == 0x20fb1) | |
| 3177 #define SH_E5(eax) (eax == 0x20f42) | |
| 3178 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) | |
| 3179 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) | |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3180 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3181 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3182 DH_E6(eax) || JH_E6(eax)) |
| 0 | 3183 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3184 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3185 #define DR_B0(eax) (eax == 0x100f20) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3186 #define DR_B1(eax) (eax == 0x100f21) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3187 #define DR_BA(eax) (eax == 0x100f2a) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3188 #define DR_B2(eax) (eax == 0x100f22) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3189 #define DR_B3(eax) (eax == 0x100f23) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3190 #define RB_C0(eax) (eax == 0x100f40) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3191 |
| 0 | 3192 switch (erratum) { |
| 3193 case 1: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3194 return (cpi->cpi_family < 0x10); |
| 0 | 3195 case 51: /* what does the asterisk mean? */ |
| 3196 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 3197 case 52: | |
| 3198 return (B(eax)); | |
| 3199 case 57: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3200 return (cpi->cpi_family <= 0x11); |
| 0 | 3201 case 58: |
| 3202 return (B(eax)); | |
| 3203 case 60: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3204 return (cpi->cpi_family <= 0x11); |
| 0 | 3205 case 61: |
| 3206 case 62: | |
| 3207 case 63: | |
| 3208 case 64: | |
| 3209 case 65: | |
| 3210 case 66: | |
| 3211 case 68: | |
| 3212 case 69: | |
| 3213 case 70: | |
| 3214 case 71: | |
| 3215 return (B(eax)); | |
| 3216 case 72: | |
| 3217 return (SH_B0(eax)); | |
| 3218 case 74: | |
| 3219 return (B(eax)); | |
| 3220 case 75: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3221 return (cpi->cpi_family < 0x10); |
| 0 | 3222 case 76: |
| 3223 return (B(eax)); | |
| 3224 case 77: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3225 return (cpi->cpi_family <= 0x11); |
| 0 | 3226 case 78: |
| 3227 return (B(eax) || SH_C0(eax)); | |
| 3228 case 79: | |
| 3229 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 3230 case 80: | |
| 3231 case 81: | |
| 3232 case 82: | |
| 3233 return (B(eax)); | |
| 3234 case 83: | |
| 3235 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 3236 case 85: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3237 return (cpi->cpi_family < 0x10); |
| 0 | 3238 case 86: |
| 3239 return (SH_C0(eax) || CG(eax)); | |
| 3240 case 88: | |
| 3241 #if !defined(__amd64) | |
| 3242 return (0); | |
| 3243 #else | |
| 3244 return (B(eax) || SH_C0(eax)); | |
| 3245 #endif | |
| 3246 case 89: | |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3247 return (cpi->cpi_family < 0x10); |
| 0 | 3248 case 90: |
| 3249 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 3250 case 91: | |
| 3251 case 92: | |
| 3252 return (B(eax) || SH_C0(eax)); | |
| 3253 case 93: | |
| 3254 return (SH_C0(eax)); | |
| 3255 case 94: | |
| 3256 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 3257 case 95: | |
| 3258 #if !defined(__amd64) | |
| 3259 return (0); | |
| 3260 #else | |
| 3261 return (B(eax) || SH_C0(eax)); | |
| 3262 #endif | |
| 3263 case 96: | |
| 3264 return (B(eax) || SH_C0(eax) || CG(eax)); | |
| 3265 case 97: | |
| 3266 case 98: | |
| 3267 return (SH_C0(eax) || CG(eax)); | |
| 3268 case 99: | |
| 3269 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3270 case 100: | |
| 3271 return (B(eax) || SH_C0(eax)); | |
| 3272 case 101: | |
| 3273 case 103: | |
| 3274 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3275 case 104: | |
| 3276 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3277 case 105: | |
| 3278 case 106: | |
| 3279 case 107: | |
| 3280 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3281 case 108: | |
| 3282 return (DH_CG(eax)); | |
| 3283 case 109: | |
| 3284 return (SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3285 case 110: | |
| 3286 return (D0(eax) || EX(eax)); | |
| 3287 case 111: | |
| 3288 return (CG(eax)); | |
| 3289 case 112: | |
| 3290 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 3291 case 113: | |
| 3292 return (eax == 0x20fc0); | |
| 3293 case 114: | |
| 3294 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 3295 case 115: | |
| 3296 return (SH_E0(eax) || JH_E1(eax)); | |
| 3297 case 116: | |
| 3298 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); | |
| 3299 case 117: | |
| 3300 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); | |
| 3301 case 118: | |
| 3302 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || | |
| 3303 JH_E6(eax)); | |
| 3304 case 121: | |
| 3305 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); | |
| 3306 case 122: | |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3307 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); |
| 0 | 3308 case 123: |
| 3309 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); | |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
3310 case 131: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3311 return (cpi->cpi_family < 0x10); |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3312 case 6336786: |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3313 /* |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3314 * Test for AdvPowerMgmtInfo.TscPStateInvariant |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
3315 * if this is a K8 family or newer processor |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3316 */ |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3317 if (CPI_FAMILY(cpi) == 0xf) { |
| 1228 | 3318 struct cpuid_regs regs; |
| 3319 regs.cp_eax = 0x80000007; | |
| 3320 (void) __cpuid_insn(®s); | |
| 3321 return (!(regs.cp_edx & 0x100)); | |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3322 } |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
3323 return (0); |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3324 case 6323525: |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3325 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3326 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
3327 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3328 case 6671130: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3329 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3330 * check for processors (pre-Shanghai) that do not provide |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3331 * optimal management of 1gb ptes in its tlb. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3332 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3333 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3334 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3335 case 298: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3336 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3337 DR_B2(eax) || RB_C0(eax)); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3338 |
|
13651
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3339 case 721: |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3340 #if defined(__amd64) |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3341 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12); |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3342 #else |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3343 return (0); |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3344 #endif |
|
af464d8d3a31
2449 Add workaround for AMD K10 CPU erratum 721
Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
parents:
13498
diff
changeset
|
3345 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3346 default: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3347 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3348 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3349 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3350 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3351 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3352 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3353 * Determine if specified erratum is present via OSVW (OS Visible Workaround). |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3354 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3355 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3356 int |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3357 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3358 { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3359 struct cpuid_info *cpi; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3360 uint_t osvwid; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3361 static int osvwfeature = -1; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3362 uint64_t osvwlength; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3363 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3364 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3365 cpi = cpu->cpu_m.mcpu_cpi; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3366 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3367 /* confirm OSVW supported */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3368 if (osvwfeature == -1) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3369 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3370 } else { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3371 /* assert that osvw feature setting is consistent on all cpus */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3372 ASSERT(osvwfeature == |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3373 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3374 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3375 if (!osvwfeature) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3376 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3377 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3378 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3379 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3380 switch (erratum) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3381 case 298: /* osvwid is 0 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3382 osvwid = 0; |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3383 if (osvwlength <= (uint64_t)osvwid) { |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3384 /* osvwid 0 is unknown */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3385 return (-1); |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3386 } |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3387 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3388 /* |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3389 * Check the OSVW STATUS MSR to determine the state |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3390 * of the erratum where: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3391 * 0 - fixed by HW |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3392 * 1 - BIOS has applied the workaround when BIOS |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3393 * workaround is available. (Or for other errata, |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3394 * OS workaround is required.) |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3395 * For a value of 1, caller will confirm that the |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3396 * erratum 298 workaround has indeed been applied by BIOS. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3397 * |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3398 * A 1 may be set in cpus that have a HW fix |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3399 * in a mixed cpu system. Regarding erratum 298: |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3400 * In a multiprocessor platform, the workaround above |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3401 * should be applied to all processors regardless of |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3402 * silicon revision when an affected processor is |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3403 * present. |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3404 */ |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3405 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3406 return (rdmsr(MSR_AMD_OSVW_STATUS + |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3407 (osvwid / OSVW_ID_CNT_PER_MSR)) & |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6671
diff
changeset
|
3408 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); |
|
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|
3409 |
| 0 | 3410 default: |
| 3411 return (-1); | |
| 3412 } | |
| 3413 } | |
| 3414 | |
| 3415 static const char assoc_str[] = "associativity"; | |
| 3416 static const char line_str[] = "line-size"; | |
| 3417 static const char size_str[] = "size"; | |
| 3418 | |
| 3419 static void | |
| 3420 add_cache_prop(dev_info_t *devi, const char *label, const char *type, | |
| 3421 uint32_t val) | |
| 3422 { | |
| 3423 char buf[128]; | |
| 3424 | |
| 3425 /* | |
| 3426 * ndi_prop_update_int() is used because it is desirable for | |
| 3427 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. | |
| 3428 */ | |
| 3429 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) | |
| 3430 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); | |
| 3431 } | |
| 3432 | |
| 3433 /* | |
| 3434 * Intel-style cache/tlb description | |
| 3435 * | |
| 3436 * Standard cpuid level 2 gives a randomly ordered | |
| 3437 * selection of tags that index into a table that describes | |
| 3438 * cache and tlb properties. | |
| 3439 */ | |
| 3440 | |
| 3441 static const char l1_icache_str[] = "l1-icache"; | |
| 3442 static const char l1_dcache_str[] = "l1-dcache"; | |
| 3443 static const char l2_cache_str[] = "l2-cache"; | |
| 3446 | 3444 static const char l3_cache_str[] = "l3-cache"; |
| 0 | 3445 static const char itlb4k_str[] = "itlb-4K"; |
| 3446 static const char dtlb4k_str[] = "dtlb-4K"; | |
|
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|
3447 static const char itlb2M_str[] = "itlb-2M"; |
| 0 | 3448 static const char itlb4M_str[] = "itlb-4M"; |
| 3449 static const char dtlb4M_str[] = "dtlb-4M"; | |
|
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|
3450 static const char dtlb24_str[] = "dtlb0-2M-4M"; |
| 0 | 3451 static const char itlb424_str[] = "itlb-4K-2M-4M"; |
|
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|
3452 static const char itlb24_str[] = "itlb-2M-4M"; |
| 0 | 3453 static const char dtlb44_str[] = "dtlb-4K-4M"; |
| 3454 static const char sl1_dcache_str[] = "sectored-l1-dcache"; | |
| 3455 static const char sl2_cache_str[] = "sectored-l2-cache"; | |
| 3456 static const char itrace_str[] = "itrace-cache"; | |
| 3457 static const char sl3_cache_str[] = "sectored-l3-cache"; | |
|
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|
3458 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; |
| 0 | 3459 |
| 3460 static const struct cachetab { | |
| 3461 uint8_t ct_code; | |
| 3462 uint8_t ct_assoc; | |
| 3463 uint16_t ct_line_size; | |
| 3464 size_t ct_size; | |
| 3465 const char *ct_label; | |
| 3466 } intel_ctab[] = { | |
|
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|
3467 /* |
|
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|
3468 * maintain descending order! |
|
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|
3469 * |
|
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|
3470 * Codes ignored - Reason |
|
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|
3471 * ---------------------- |
|
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|
3472 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache |
|
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|
3473 * f0H/f1H - Currently we do not interpret prefetch size by design |
|
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|
3474 */ |
|
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|
3475 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, |
|
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|
3476 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, |
|
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|
3477 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, |
|
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|
3478 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, |
|
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|
3479 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, |
|
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|
3480 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, |
|
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|
3481 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, |
|
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|
3482 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, |
|
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|
3483 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, |
|
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|
3484 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, |
|
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|
3485 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, |
|
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|
3486 { 0xd0, 4, 64, 512*1024, l3_cache_str}, |
|
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|
3487 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, |
|
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|
3488 { 0xc0, 4, 0, 8, dtlb44_str }, |
|
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|
3489 { 0xba, 4, 0, 64, dtlb4k_str }, |
| 3446 | 3490 { 0xb4, 4, 0, 256, dtlb4k_str }, |
| 0 | 3491 { 0xb3, 4, 0, 128, dtlb4k_str }, |
|
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|
3492 { 0xb2, 4, 0, 64, itlb4k_str }, |
| 0 | 3493 { 0xb0, 4, 0, 128, itlb4k_str }, |
| 3494 { 0x87, 8, 64, 1024*1024, l2_cache_str}, | |
| 3495 { 0x86, 4, 64, 512*1024, l2_cache_str}, | |
| 3496 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, | |
| 3497 { 0x84, 8, 32, 1024*1024, l2_cache_str}, | |
| 3498 { 0x83, 8, 32, 512*1024, l2_cache_str}, | |
| 3499 { 0x82, 8, 32, 256*1024, l2_cache_str}, | |
|
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|
3500 { 0x80, 8, 64, 512*1024, l2_cache_str}, |
| 0 | 3501 { 0x7f, 2, 64, 512*1024, l2_cache_str}, |
| 3502 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, | |
| 3503 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, | |
| 3504 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, | |
| 3505 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, | |
| 3506 { 0x79, 8, 64, 128*1024, sl2_cache_str}, | |
| 3507 { 0x78, 8, 64, 1024*1024, l2_cache_str}, | |
| 3446 | 3508 { 0x73, 8, 0, 64*1024, itrace_str}, |
| 0 | 3509 { 0x72, 8, 0, 32*1024, itrace_str}, |
| 3510 { 0x71, 8, 0, 16*1024, itrace_str}, | |
| 3511 { 0x70, 8, 0, 12*1024, itrace_str}, | |
| 3512 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, | |
| 3513 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, | |
| 3514 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, | |
| 3515 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, | |
| 3516 { 0x5d, 0, 0, 256, dtlb44_str}, | |
| 3517 { 0x5c, 0, 0, 128, dtlb44_str}, | |
| 3518 { 0x5b, 0, 0, 64, dtlb44_str}, | |
|
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|
3519 { 0x5a, 4, 0, 32, dtlb24_str}, |
|
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|
3520 { 0x59, 0, 0, 16, dtlb4k_str}, |
|
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|
3521 { 0x57, 4, 0, 16, dtlb4k_str}, |
|
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|
3522 { 0x56, 4, 0, 16, dtlb4M_str}, |
|
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|
3523 { 0x55, 0, 0, 7, itlb24_str}, |
| 0 | 3524 { 0x52, 0, 0, 256, itlb424_str}, |
| 3525 { 0x51, 0, 0, 128, itlb424_str}, | |
| 3526 { 0x50, 0, 0, 64, itlb424_str}, | |
|
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|
3527 { 0x4f, 0, 0, 32, itlb4k_str}, |
|
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|
3528 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, |
| 3446 | 3529 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, |
| 3530 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, | |
| 3531 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, | |
| 3532 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, | |
| 3533 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, | |
|
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|
3534 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, |
| 3446 | 3535 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, |
| 3536 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, | |
| 0 | 3537 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, |
| 3538 { 0x44, 4, 32, 1024*1024, l2_cache_str}, | |
| 3539 { 0x43, 4, 32, 512*1024, l2_cache_str}, | |
| 3540 { 0x42, 4, 32, 256*1024, l2_cache_str}, | |
| 3541 { 0x41, 4, 32, 128*1024, l2_cache_str}, | |
| 3446 | 3542 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, |
| 3543 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, | |
| 0 | 3544 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, |
| 3545 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, | |
| 3446 | 3546 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, |
| 0 | 3547 { 0x39, 4, 64, 128*1024, sl2_cache_str}, |
| 3548 { 0x30, 8, 64, 32*1024, l1_icache_str}, | |
| 3549 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, | |
| 3550 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, | |
| 3551 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, | |
| 3552 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, | |
| 3553 { 0x22, 4, 64, 512*1024, sl3_cache_str}, | |
|
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|
3554 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, |
|
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|
3555 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, |
| 0 | 3556 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, |
| 3446 | 3557 { 0x0b, 4, 0, 4, itlb4M_str}, |
| 0 | 3558 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, |
| 3559 { 0x08, 4, 32, 16*1024, l1_icache_str}, | |
| 3560 { 0x06, 4, 32, 8*1024, l1_icache_str}, | |
|
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|
3561 { 0x05, 4, 0, 32, dtlb4M_str}, |
| 0 | 3562 { 0x04, 4, 0, 8, dtlb4M_str}, |
| 3563 { 0x03, 4, 0, 64, dtlb4k_str}, | |
| 3564 { 0x02, 4, 0, 2, itlb4M_str}, | |
| 3565 { 0x01, 4, 0, 32, itlb4k_str}, | |
| 3566 { 0 } | |
| 3567 }; | |
| 3568 | |
| 3569 static const struct cachetab cyrix_ctab[] = { | |
| 3570 { 0x70, 4, 0, 32, "tlb-4K" }, | |
| 3571 { 0x80, 4, 16, 16*1024, "l1-cache" }, | |
| 3572 { 0 } | |
| 3573 }; | |
| 3574 | |
| 3575 /* | |
| 3576 * Search a cache table for a matching entry | |
| 3577 */ | |
| 3578 static const struct cachetab * | |
| 3579 find_cacheent(const struct cachetab *ct, uint_t code) | |
| 3580 { | |
| 3581 if (code != 0) { | |
| 3582 for (; ct->ct_code != 0; ct++) | |
| 3583 if (ct->ct_code <= code) | |
| 3584 break; | |
| 3585 if (ct->ct_code == code) | |
| 3586 return (ct); | |
| 3587 } | |
| 3588 return (NULL); | |
| 3589 } | |
| 3590 | |
| 3591 /* | |
|
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3592 * Populate cachetab entry with L2 or L3 cache-information using |
|
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3593 * cpuid function 4. This function is called from intel_walk_cacheinfo() |
|
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3594 * when descriptor 0x49 is encountered. It returns 0 if no such cache |
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3595 * information is found. |
|
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3596 */ |
|
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3597 static int |
|
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|
3598 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) |
|
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3599 { |
|
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3600 uint32_t level, i; |
|
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3601 int ret = 0; |
|
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|
3602 |
|
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3603 for (i = 0; i < cpi->cpi_std_4_size; i++) { |
|
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3604 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); |
|
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3605 |
|
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3606 if (level == 2 || level == 3) { |
|
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|
3607 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; |
|
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3608 ct->ct_line_size = |
|
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3609 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; |
|
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3610 ct->ct_size = ct->ct_assoc * |
|
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3611 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * |
|
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3612 ct->ct_line_size * |
|
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3613 (cpi->cpi_std_4[i]->cp_ecx + 1); |
|
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|
3614 |
|
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3615 if (level == 2) { |
|
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|
3616 ct->ct_label = l2_cache_str; |
|
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3617 } else if (level == 3) { |
|
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6603986 Installing a Linux zone on an Intel blade causes a panic
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5349
diff
changeset
|
3618 ct->ct_label = l3_cache_str; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3619 } |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3620 ret = 1; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3621 } |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3622 } |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
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|
3623 |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3624 return (ret); |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3625 } |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3626 |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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5349
diff
changeset
|
3627 /* |
| 0 | 3628 * Walk the cacheinfo descriptor, applying 'func' to every valid element |
| 3629 * The walk is terminated if the walker returns non-zero. | |
| 3630 */ | |
| 3631 static void | |
| 3632 intel_walk_cacheinfo(struct cpuid_info *cpi, | |
| 3633 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 3634 { | |
| 3635 const struct cachetab *ct; | |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3636 struct cachetab des_49_ct, des_b1_ct; |
| 0 | 3637 uint8_t *dp; |
| 3638 int i; | |
| 3639 | |
| 3640 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 3641 return; | |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3642 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { |
|
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
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parents:
4636
diff
changeset
|
3643 /* |
|
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3644 * For overloaded descriptor 0x49 we use cpuid function 4 |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3645 * if supported by the current processor, to create |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3646 * cache information. |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3647 * For overloaded descriptor 0xb1 we use X86_PAE flag |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3648 * to disambiguate the cache information. |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3649 */ |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3650 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3651 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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5349
diff
changeset
|
3652 ct = &des_49_ct; |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3653 } else if (*dp == 0xb1) { |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3654 des_b1_ct.ct_code = 0xb1; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3655 des_b1_ct.ct_assoc = 4; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3656 des_b1_ct.ct_line_size = 0; |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
3657 if (is_x86_feature(x86_featureset, X86FSET_PAE)) { |
|
6964
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3658 des_b1_ct.ct_size = 8; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3659 des_b1_ct.ct_label = itlb2M_str; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3660 } else { |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3661 des_b1_ct.ct_size = 4; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3662 des_b1_ct.ct_label = itlb4M_str; |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3663 } |
|
3eb8a0c8b90a
6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors
vd224797
parents:
6691
diff
changeset
|
3664 ct = &des_b1_ct; |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3665 } else { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3666 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3667 continue; |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
parents:
5349
diff
changeset
|
3668 } |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3669 } |
|
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3670 |
|
5438
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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5349
diff
changeset
|
3671 if (func(arg, ct) != 0) { |
|
41d8edfa90d7
6603986 Installing a Linux zone on an Intel blade causes a panic
ksadhukh
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5349
diff
changeset
|
3672 break; |
| 0 | 3673 } |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
parents:
4636
diff
changeset
|
3674 } |
| 0 | 3675 } |
| 3676 | |
| 3677 /* | |
| 3678 * (Like the Intel one, except for Cyrix CPUs) | |
| 3679 */ | |
| 3680 static void | |
| 3681 cyrix_walk_cacheinfo(struct cpuid_info *cpi, | |
| 3682 void *arg, int (*func)(void *, const struct cachetab *)) | |
| 3683 { | |
| 3684 const struct cachetab *ct; | |
| 3685 uint8_t *dp; | |
| 3686 int i; | |
| 3687 | |
| 3688 if ((dp = cpi->cpi_cacheinfo) == NULL) | |
| 3689 return; | |
| 3690 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { | |
| 3691 /* | |
| 3692 * Search Cyrix-specific descriptor table first .. | |
| 3693 */ | |
| 3694 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { | |
| 3695 if (func(arg, ct) != 0) | |
| 3696 break; | |
| 3697 continue; | |
| 3698 } | |
| 3699 /* | |
| 3700 * .. else fall back to the Intel one | |
| 3701 */ | |
| 3702 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { | |
| 3703 if (func(arg, ct) != 0) | |
| 3704 break; | |
| 3705 continue; | |
| 3706 } | |
| 3707 } | |
| 3708 } | |
| 3709 | |
| 3710 /* | |
| 3711 * A cacheinfo walker that adds associativity, line-size, and size properties | |
| 3712 * to the devinfo node it is passed as an argument. | |
| 3713 */ | |
| 3714 static int | |
| 3715 add_cacheent_props(void *arg, const struct cachetab *ct) | |
| 3716 { | |
| 3717 dev_info_t *devi = arg; | |
| 3718 | |
| 3719 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); | |
| 3720 if (ct->ct_line_size != 0) | |
| 3721 add_cache_prop(devi, ct->ct_label, line_str, | |
| 3722 ct->ct_line_size); | |
| 3723 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); | |
| 3724 return (0); | |
| 3725 } | |
| 3726 | |
|
4797
2ebe22df4dfc
6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache
ksadhukh
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4636
diff
changeset
|
3727 |
| 0 | 3728 static const char fully_assoc[] = "fully-associative?"; |
| 3729 | |
| 3730 /* | |
| 3731 * AMD style cache/tlb description | |
| 3732 * | |
| 3733 * Extended functions 5 and 6 directly describe properties of | |
| 3734 * tlbs and various cache levels. | |
| 3735 */ | |
| 3736 static void | |
| 3737 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 3738 { | |
| 3739 switch (assoc) { | |
| 3740 case 0: /* reserved; ignore */ | |
| 3741 break; | |
| 3742 default: | |
| 3743 add_cache_prop(devi, label, assoc_str, assoc); | |
| 3744 break; | |
| 3745 case 0xff: | |
| 3746 add_cache_prop(devi, label, fully_assoc, 1); | |
| 3747 break; | |
| 3748 } | |
| 3749 } | |
| 3750 | |
| 3751 static void | |
| 3752 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 3753 { | |
| 3754 if (size == 0) | |
| 3755 return; | |
| 3756 add_cache_prop(devi, label, size_str, size); | |
| 3757 add_amd_assoc(devi, label, assoc); | |
| 3758 } | |
| 3759 | |
| 3760 static void | |
| 3761 add_amd_cache(dev_info_t *devi, const char *label, | |
| 3762 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 3763 { | |
| 3764 if (size == 0 || line_size == 0) | |
| 3765 return; | |
| 3766 add_amd_assoc(devi, label, assoc); | |
| 3767 /* | |
| 3768 * Most AMD parts have a sectored cache. Multiple cache lines are | |
| 3769 * associated with each tag. A sector consists of all cache lines | |
| 3770 * associated with a tag. For example, the AMD K6-III has a sector | |
| 3771 * size of 2 cache lines per tag. | |
| 3772 */ | |
| 3773 if (lines_per_tag != 0) | |
| 3774 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 3775 add_cache_prop(devi, label, line_str, line_size); | |
| 3776 add_cache_prop(devi, label, size_str, size * 1024); | |
| 3777 } | |
| 3778 | |
| 3779 static void | |
| 3780 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) | |
| 3781 { | |
| 3782 switch (assoc) { | |
| 3783 case 0: /* off */ | |
| 3784 break; | |
| 3785 case 1: | |
| 3786 case 2: | |
| 3787 case 4: | |
| 3788 add_cache_prop(devi, label, assoc_str, assoc); | |
| 3789 break; | |
| 3790 case 6: | |
| 3791 add_cache_prop(devi, label, assoc_str, 8); | |
| 3792 break; | |
| 3793 case 8: | |
| 3794 add_cache_prop(devi, label, assoc_str, 16); | |
| 3795 break; | |
| 3796 case 0xf: | |
| 3797 add_cache_prop(devi, label, fully_assoc, 1); | |
| 3798 break; | |
| 3799 default: /* reserved; ignore */ | |
| 3800 break; | |
| 3801 } | |
| 3802 } | |
| 3803 | |
| 3804 static void | |
| 3805 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) | |
| 3806 { | |
| 3807 if (size == 0 || assoc == 0) | |
| 3808 return; | |
| 3809 add_amd_l2_assoc(devi, label, assoc); | |
| 3810 add_cache_prop(devi, label, size_str, size); | |
| 3811 } | |
| 3812 | |
| 3813 static void | |
| 3814 add_amd_l2_cache(dev_info_t *devi, const char *label, | |
| 3815 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) | |
| 3816 { | |
| 3817 if (size == 0 || assoc == 0 || line_size == 0) | |
| 3818 return; | |
| 3819 add_amd_l2_assoc(devi, label, assoc); | |
| 3820 if (lines_per_tag != 0) | |
| 3821 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); | |
| 3822 add_cache_prop(devi, label, line_str, line_size); | |
| 3823 add_cache_prop(devi, label, size_str, size * 1024); | |
| 3824 } | |
| 3825 | |
| 3826 static void | |
| 3827 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) | |
| 3828 { | |
| 1228 | 3829 struct cpuid_regs *cp; |
| 0 | 3830 |
| 3831 if (cpi->cpi_xmaxeax < 0x80000005) | |
| 3832 return; | |
| 3833 cp = &cpi->cpi_extd[5]; | |
| 3834 | |
| 3835 /* | |
| 3836 * 4M/2M L1 TLB configuration | |
| 3837 * | |
| 3838 * We report the size for 2M pages because AMD uses two | |
| 3839 * TLB entries for one 4M page. | |
| 3840 */ | |
| 3841 add_amd_tlb(devi, "dtlb-2M", | |
| 3842 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); | |
| 3843 add_amd_tlb(devi, "itlb-2M", | |
| 3844 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); | |
| 3845 | |
| 3846 /* | |
| 3847 * 4K L1 TLB configuration | |
| 3848 */ | |
| 3849 | |
| 3850 switch (cpi->cpi_vendor) { | |
| 3851 uint_t nentries; | |
| 3852 case X86_VENDOR_TM: | |
| 3853 if (cpi->cpi_family >= 5) { | |
| 3854 /* | |
| 3855 * Crusoe processors have 256 TLB entries, but | |
| 3856 * cpuid data format constrains them to only | |
| 3857 * reporting 255 of them. | |
| 3858 */ | |
| 3859 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) | |
| 3860 nentries = 256; | |
| 3861 /* | |
| 3862 * Crusoe processors also have a unified TLB | |
| 3863 */ | |
| 3864 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), | |
| 3865 nentries); | |
| 3866 break; | |
| 3867 } | |
| 3868 /*FALLTHROUGH*/ | |
| 3869 default: | |
| 3870 add_amd_tlb(devi, itlb4k_str, | |
| 3871 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); | |
| 3872 add_amd_tlb(devi, dtlb4k_str, | |
| 3873 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); | |
| 3874 break; | |
| 3875 } | |
| 3876 | |
| 3877 /* | |
| 3878 * data L1 cache configuration | |
| 3879 */ | |
| 3880 | |
| 3881 add_amd_cache(devi, l1_dcache_str, | |
| 3882 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), | |
| 3883 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 3884 | |
| 3885 /* | |
| 3886 * code L1 cache configuration | |
| 3887 */ | |
| 3888 | |
| 3889 add_amd_cache(devi, l1_icache_str, | |
| 3890 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), | |
| 3891 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); | |
| 3892 | |
| 3893 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 3894 return; | |
| 3895 cp = &cpi->cpi_extd[6]; | |
| 3896 | |
| 3897 /* Check for a unified L2 TLB for large pages */ | |
| 3898 | |
| 3899 if (BITX(cp->cp_eax, 31, 16) == 0) | |
| 3900 add_amd_l2_tlb(devi, "l2-tlb-2M", | |
| 3901 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3902 else { | |
| 3903 add_amd_l2_tlb(devi, "l2-dtlb-2M", | |
| 3904 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 3905 add_amd_l2_tlb(devi, "l2-itlb-2M", | |
| 3906 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3907 } | |
| 3908 | |
| 3909 /* Check for a unified L2 TLB for 4K pages */ | |
| 3910 | |
| 3911 if (BITX(cp->cp_ebx, 31, 16) == 0) { | |
| 3912 add_amd_l2_tlb(devi, "l2-tlb-4K", | |
| 3913 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3914 } else { | |
| 3915 add_amd_l2_tlb(devi, "l2-dtlb-4K", | |
| 3916 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); | |
| 3917 add_amd_l2_tlb(devi, "l2-itlb-4K", | |
| 3918 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); | |
| 3919 } | |
| 3920 | |
| 3921 add_amd_l2_cache(devi, l2_cache_str, | |
| 3922 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), | |
| 3923 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); | |
| 3924 } | |
| 3925 | |
| 3926 /* | |
| 3927 * There are two basic ways that the x86 world describes it cache | |
| 3928 * and tlb architecture - Intel's way and AMD's way. | |
| 3929 * | |
| 3930 * Return which flavor of cache architecture we should use | |
| 3931 */ | |
| 3932 static int | |
| 3933 x86_which_cacheinfo(struct cpuid_info *cpi) | |
| 3934 { | |
| 3935 switch (cpi->cpi_vendor) { | |
| 3936 case X86_VENDOR_Intel: | |
| 3937 if (cpi->cpi_maxeax >= 2) | |
| 3938 return (X86_VENDOR_Intel); | |
| 3939 break; | |
| 3940 case X86_VENDOR_AMD: | |
| 3941 /* | |
| 3942 * The K5 model 1 was the first part from AMD that reported | |
| 3943 * cache sizes via extended cpuid functions. | |
| 3944 */ | |
| 3945 if (cpi->cpi_family > 5 || | |
| 3946 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) | |
| 3947 return (X86_VENDOR_AMD); | |
| 3948 break; | |
| 3949 case X86_VENDOR_TM: | |
| 3950 if (cpi->cpi_family >= 5) | |
| 3951 return (X86_VENDOR_AMD); | |
| 3952 /*FALLTHROUGH*/ | |
| 3953 default: | |
| 3954 /* | |
| 3955 * If they have extended CPU data for 0x80000005 | |
| 3956 * then we assume they have AMD-format cache | |
| 3957 * information. | |
| 3958 * | |
| 3959 * If not, and the vendor happens to be Cyrix, | |
| 3960 * then try our-Cyrix specific handler. | |
| 3961 * | |
| 3962 * If we're not Cyrix, then assume we're using Intel's | |
| 3963 * table-driven format instead. | |
| 3964 */ | |
| 3965 if (cpi->cpi_xmaxeax >= 0x80000005) | |
| 3966 return (X86_VENDOR_AMD); | |
| 3967 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) | |
| 3968 return (X86_VENDOR_Cyrix); | |
| 3969 else if (cpi->cpi_maxeax >= 2) | |
| 3970 return (X86_VENDOR_Intel); | |
| 3971 break; | |
| 3972 } | |
| 3973 return (-1); | |
| 3974 } | |
| 3975 | |
| 3976 void | |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3977 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, |
|
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3978 struct cpuid_info *cpi) |
| 0 | 3979 { |
| 3980 dev_info_t *cpu_devi; | |
| 3981 int create; | |
| 3982 | |
|
9652
6b40e106879c
6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot
Michael Corcoran <Michael.Corcoran@Sun.COM>
parents:
9482
diff
changeset
|
3983 cpu_devi = (dev_info_t *)dip; |
| 0 | 3984 |
| 3985 /* device_type */ | |
| 3986 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 3987 "device_type", "cpu"); | |
| 3988 | |
| 3989 /* reg */ | |
| 3990 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3991 "reg", cpu_id); | |
| 3992 | |
| 3993 /* cpu-mhz, and clock-frequency */ | |
| 3994 if (cpu_freq > 0) { | |
| 3995 long long mul; | |
| 3996 | |
| 3997 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 3998 "cpu-mhz", cpu_freq); | |
| 3999 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) | |
| 4000 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4001 "clock-frequency", (int)mul); | |
| 4002 } | |
| 4003 | |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4004 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) { |
| 0 | 4005 return; |
| 4006 } | |
| 4007 | |
| 4008 /* vendor-id */ | |
| 4009 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4010 "vendor-id", cpi->cpi_vendorstr); |
| 0 | 4011 |
| 4012 if (cpi->cpi_maxeax == 0) { | |
| 4013 return; | |
| 4014 } | |
| 4015 | |
| 4016 /* | |
| 4017 * family, model, and step | |
| 4018 */ | |
| 4019 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4020 "family", CPI_FAMILY(cpi)); |
| 0 | 4021 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4022 "cpu-model", CPI_MODEL(cpi)); |
| 0 | 4023 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4024 "stepping-id", CPI_STEP(cpi)); |
| 0 | 4025 |
| 4026 /* type */ | |
| 4027 switch (cpi->cpi_vendor) { | |
| 4028 case X86_VENDOR_Intel: | |
| 4029 create = 1; | |
| 4030 break; | |
| 4031 default: | |
| 4032 create = 0; | |
| 4033 break; | |
| 4034 } | |
| 4035 if (create) | |
| 4036 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4037 "type", CPI_TYPE(cpi)); |
| 0 | 4038 |
| 4039 /* ext-family */ | |
| 4040 switch (cpi->cpi_vendor) { | |
| 4041 case X86_VENDOR_Intel: | |
| 4042 case X86_VENDOR_AMD: | |
| 4043 create = cpi->cpi_family >= 0xf; | |
| 4044 break; | |
| 4045 default: | |
| 4046 create = 0; | |
| 4047 break; | |
| 4048 } | |
| 4049 if (create) | |
| 4050 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4051 "ext-family", CPI_FAMILY_XTD(cpi)); | |
| 4052 | |
| 4053 /* ext-model */ | |
| 4054 switch (cpi->cpi_vendor) { | |
| 4055 case X86_VENDOR_Intel: | |
|
6317
8afb524fc268
6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info
kk208521
parents:
5870
diff
changeset
|
4056 create = IS_EXTENDED_MODEL_INTEL(cpi); |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
4057 break; |
| 0 | 4058 case X86_VENDOR_AMD: |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
4059 create = CPI_FAMILY(cpi) == 0xf; |
| 0 | 4060 break; |
| 4061 default: | |
| 4062 create = 0; | |
| 4063 break; | |
| 4064 } | |
| 4065 if (create) | |
| 4066 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4067 "ext-model", CPI_MODEL_XTD(cpi)); |
| 0 | 4068 |
| 4069 /* generation */ | |
| 4070 switch (cpi->cpi_vendor) { | |
| 4071 case X86_VENDOR_AMD: | |
| 4072 /* | |
| 4073 * AMD K5 model 1 was the first part to support this | |
| 4074 */ | |
| 4075 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 4076 break; | |
| 4077 default: | |
| 4078 create = 0; | |
| 4079 break; | |
| 4080 } | |
| 4081 if (create) | |
| 4082 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4083 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); | |
| 4084 | |
| 4085 /* brand-id */ | |
| 4086 switch (cpi->cpi_vendor) { | |
| 4087 case X86_VENDOR_Intel: | |
| 4088 /* | |
| 4089 * brand id first appeared on Pentium III Xeon model 8, | |
| 4090 * and Celeron model 8 processors and Opteron | |
| 4091 */ | |
| 4092 create = cpi->cpi_family > 6 || | |
| 4093 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); | |
| 4094 break; | |
| 4095 case X86_VENDOR_AMD: | |
| 4096 create = cpi->cpi_family >= 0xf; | |
| 4097 break; | |
| 4098 default: | |
| 4099 create = 0; | |
| 4100 break; | |
| 4101 } | |
| 4102 if (create && cpi->cpi_brandid != 0) { | |
| 4103 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4104 "brand-id", cpi->cpi_brandid); | |
| 4105 } | |
| 4106 | |
| 4107 /* chunks, and apic-id */ | |
| 4108 switch (cpi->cpi_vendor) { | |
| 4109 /* | |
| 4110 * first available on Pentium IV and Opteron (K8) | |
| 4111 */ | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4112 case X86_VENDOR_Intel: |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4113 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4114 break; |
|
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4115 case X86_VENDOR_AMD: |
| 0 | 4116 create = cpi->cpi_family >= 0xf; |
| 4117 break; | |
| 4118 default: | |
| 4119 create = 0; | |
| 4120 break; | |
| 4121 } | |
| 4122 if (create) { | |
| 4123 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4124 "chunks", CPI_CHUNKS(cpi)); |
| 0 | 4125 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
7282
5b3b6674ac91
6528768 apic_navail_vector() fails when IPL equals 8 or 9
mishra
parents:
6964
diff
changeset
|
4126 "apic-id", cpi->cpi_apicid); |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
4127 if (cpi->cpi_chipid >= 0) { |
| 0 | 4128 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
| 4129 "chip#", cpi->cpi_chipid); | |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
4130 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
4131 "clog#", cpi->cpi_clogid); |
|
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
4132 } |
| 0 | 4133 } |
| 4134 | |
| 4135 /* cpuid-features */ | |
| 4136 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4137 "cpuid-features", CPI_FEATURES_EDX(cpi)); | |
| 4138 | |
| 4139 | |
| 4140 /* cpuid-features-ecx */ | |
| 4141 switch (cpi->cpi_vendor) { | |
| 4142 case X86_VENDOR_Intel: | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4143 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
| 0 | 4144 break; |
| 4145 default: | |
| 4146 create = 0; | |
| 4147 break; | |
| 4148 } | |
| 4149 if (create) | |
| 4150 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, | |
| 4151 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); | |
| 4152 | |
| 4153 /* ext-cpuid-features */ | |
| 4154 switch (cpi->cpi_vendor) { | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4155 case X86_VENDOR_Intel: |
| 0 | 4156 case X86_VENDOR_AMD: |
| 4157 case X86_VENDOR_Cyrix: | |
| 4158 case X86_VENDOR_TM: | |
| 4159 case X86_VENDOR_Centaur: | |
| 4160 create = cpi->cpi_xmaxeax >= 0x80000001; | |
| 4161 break; | |
| 4162 default: | |
| 4163 create = 0; | |
| 4164 break; | |
| 4165 } | |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4166 if (create) { |
| 0 | 4167 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4168 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4169 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4170 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
4171 } |
| 0 | 4172 |
| 4173 /* | |
| 4174 * Brand String first appeared in Intel Pentium IV, AMD K5 | |
| 4175 * model 1, and Cyrix GXm. On earlier models we try and | |
| 4176 * simulate something similar .. so this string should always | |
| 4177 * same -something- about the processor, however lame. | |
| 4178 */ | |
| 4179 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, | |
| 4180 "brand-string", cpi->cpi_brandstr); | |
| 4181 | |
| 4182 /* | |
| 4183 * Finally, cache and tlb information | |
| 4184 */ | |
| 4185 switch (x86_which_cacheinfo(cpi)) { | |
| 4186 case X86_VENDOR_Intel: | |
| 4187 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 4188 break; | |
| 4189 case X86_VENDOR_Cyrix: | |
| 4190 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); | |
| 4191 break; | |
| 4192 case X86_VENDOR_AMD: | |
| 4193 amd_cache_info(cpi, cpu_devi); | |
| 4194 break; | |
| 4195 default: | |
| 4196 break; | |
| 4197 } | |
| 4198 } | |
| 4199 | |
| 4200 struct l2info { | |
| 4201 int *l2i_csz; | |
| 4202 int *l2i_lsz; | |
| 4203 int *l2i_assoc; | |
| 4204 int l2i_ret; | |
| 4205 }; | |
| 4206 | |
| 4207 /* | |
| 4208 * A cacheinfo walker that fetches the size, line-size and associativity | |
| 4209 * of the L2 cache | |
| 4210 */ | |
| 4211 static int | |
| 4212 intel_l2cinfo(void *arg, const struct cachetab *ct) | |
| 4213 { | |
| 4214 struct l2info *l2i = arg; | |
| 4215 int *ip; | |
| 4216 | |
| 4217 if (ct->ct_label != l2_cache_str && | |
| 4218 ct->ct_label != sl2_cache_str) | |
| 4219 return (0); /* not an L2 -- keep walking */ | |
| 4220 | |
| 4221 if ((ip = l2i->l2i_csz) != NULL) | |
| 4222 *ip = ct->ct_size; | |
| 4223 if ((ip = l2i->l2i_lsz) != NULL) | |
| 4224 *ip = ct->ct_line_size; | |
| 4225 if ((ip = l2i->l2i_assoc) != NULL) | |
| 4226 *ip = ct->ct_assoc; | |
| 4227 l2i->l2i_ret = ct->ct_size; | |
| 4228 return (1); /* was an L2 -- terminate walk */ | |
| 4229 } | |
| 4230 | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4231 /* |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4232 * AMD L2/L3 Cache and TLB Associativity Field Definition: |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4233 * |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4234 * Unlike the associativity for the L1 cache and tlb where the 8 bit |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4235 * value is the associativity, the associativity for the L2 cache and |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4236 * tlb is encoded in the following table. The 4 bit L2 value serves as |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4237 * an index into the amd_afd[] array to determine the associativity. |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4238 * -1 is undefined. 0 is fully associative. |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4239 */ |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4240 |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4241 static int amd_afd[] = |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4242 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4243 |
| 0 | 4244 static void |
| 4245 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) | |
| 4246 { | |
| 1228 | 4247 struct cpuid_regs *cp; |
| 0 | 4248 uint_t size, assoc; |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4249 int i; |
| 0 | 4250 int *ip; |
| 4251 | |
| 4252 if (cpi->cpi_xmaxeax < 0x80000006) | |
| 4253 return; | |
| 4254 cp = &cpi->cpi_extd[6]; | |
| 4255 | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4256 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && |
| 0 | 4257 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { |
| 4258 uint_t cachesz = size * 1024; | |
|
5070
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4259 assoc = amd_afd[i]; |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4260 |
|
f1c8fa0cbaca
6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system
kchow
parents:
5045
diff
changeset
|
4261 ASSERT(assoc != -1); |
| 0 | 4262 |
| 4263 if ((ip = l2i->l2i_csz) != NULL) | |
| 4264 *ip = cachesz; | |
| 4265 if ((ip = l2i->l2i_lsz) != NULL) | |
| 4266 *ip = BITX(cp->cp_ecx, 7, 0); | |
| 4267 if ((ip = l2i->l2i_assoc) != NULL) | |
| 4268 *ip = assoc; | |
| 4269 l2i->l2i_ret = cachesz; | |
| 4270 } | |
| 4271 } | |
| 4272 | |
| 4273 int | |
| 4274 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) | |
| 4275 { | |
| 4276 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; | |
| 4277 struct l2info __l2info, *l2i = &__l2info; | |
| 4278 | |
| 4279 l2i->l2i_csz = csz; | |
| 4280 l2i->l2i_lsz = lsz; | |
| 4281 l2i->l2i_assoc = assoc; | |
| 4282 l2i->l2i_ret = -1; | |
| 4283 | |
| 4284 switch (x86_which_cacheinfo(cpi)) { | |
| 4285 case X86_VENDOR_Intel: | |
| 4286 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 4287 break; | |
| 4288 case X86_VENDOR_Cyrix: | |
| 4289 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); | |
| 4290 break; | |
| 4291 case X86_VENDOR_AMD: | |
| 4292 amd_l2cacheinfo(cpi, l2i); | |
| 4293 break; | |
| 4294 default: | |
| 4295 break; | |
| 4296 } | |
| 4297 return (l2i->l2i_ret); | |
| 4298 } | |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4299 |
| 5084 | 4300 #if !defined(__xpv) |
| 4301 | |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4302 uint32_t * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4303 cpuid_mwait_alloc(cpu_t *cpu) |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4304 { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4305 uint32_t *ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4306 size_t mwait_size; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4307 |
|
12004
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4308 ASSERT(cpuid_checkpass(CPU, 2)); |
|
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4309 |
|
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4310 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max; |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4311 if (mwait_size == 0) |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4312 return (NULL); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4313 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4314 /* |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4315 * kmem_alloc() returns cache line size aligned data for mwait_size |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4316 * allocations. mwait_size is currently cache line sized. Neither |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4317 * of these implementation details are guarantied to be true in the |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4318 * future. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4319 * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4320 * First try allocating mwait_size as kmem_alloc() currently returns |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4321 * correctly aligned memory. If kmem_alloc() does not return |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4322 * mwait_size aligned memory, then use mwait_size ROUNDUP. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4323 * |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4324 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4325 * decide to free this memory. |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4326 */ |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4327 ret = kmem_zalloc(mwait_size, KM_SLEEP); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4328 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4329 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4330 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4331 *ret = MWAIT_RUNNING; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4332 return (ret); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4333 } else { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4334 kmem_free(ret, mwait_size); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4335 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4336 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4337 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4338 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4339 *ret = MWAIT_RUNNING; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4340 return (ret); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4341 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4342 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4343 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4344 void |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4345 cpuid_mwait_free(cpu_t *cpu) |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4346 { |
|
12004
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4347 if (cpu->cpu_m.mcpu_cpi == NULL) { |
|
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4348 return; |
|
93f274d4a367
PSARC/2009/104 Hot-Plug Support for ACPI-based Systems
Gerry Liu <jiang.liu@intel.com>
parents:
11919
diff
changeset
|
4349 } |
|
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4350 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4351 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4352 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4353 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4354 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4355 } |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4356 |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4357 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; |
|
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4858
diff
changeset
|
4358 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
4359 } |
| 5084 | 4360 |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4361 void |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4362 patch_tsc_read(int flag) |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4363 { |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4364 size_t cnt; |
|
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7282
diff
changeset
|
4365 |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4366 switch (flag) { |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4367 case X86_NO_TSC: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4368 cnt = &_no_rdtsc_end - &_no_rdtsc_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4369 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4370 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4371 case X86_HAVE_TSCP: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4372 cnt = &_tscp_end - &_tscp_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4373 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4374 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4375 case X86_TSC_MFENCE: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4376 cnt = &_tsc_mfence_end - &_tsc_mfence_start; |
|
5338
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4377 (void) memcpy((void *)tsc_read, |
|
fd7cad8433cf
6600939 gethrtime sometimes return a large time value into the future (fix lint)
sudheer
parents:
5322
diff
changeset
|
4378 (void *)&_tsc_mfence_start, cnt); |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4379 break; |
|
6642
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4380 case X86_TSC_LFENCE: |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4381 cnt = &_tsc_lfence_end - &_tsc_lfence_start; |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4382 (void) memcpy((void *)tsc_read, |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4383 (void *)&_tsc_lfence_start, cnt); |
|
c41a8f6eba0e
6671782 rdtsc synchronization change for Intel processors
sudheer
parents:
6445
diff
changeset
|
4384 break; |
|
5322
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4385 default: |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4386 break; |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4387 } |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4388 } |
|
010e79fdab36
6600939 gethrtime sometimes return a large time value into the future
sudheer
parents:
5284
diff
changeset
|
4389 |
|
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4390 int |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4391 cpuid_deep_cstates_supported(void) |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4392 { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4393 struct cpuid_info *cpi; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4394 struct cpuid_regs regs; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4395 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4396 ASSERT(cpuid_checkpass(CPU, 1)); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4397 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4398 cpi = CPU->cpu_m.mcpu_cpi; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4399 |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4400 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) |
|
8906
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4401 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4402 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4403 switch (cpi->cpi_vendor) { |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4404 case X86_VENDOR_Intel: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4405 if (cpi->cpi_xmaxeax < 0x80000007) |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4406 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4407 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4408 /* |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4409 * TSC run at a constant rate in all ACPI C-states? |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4410 */ |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4411 regs.cp_eax = 0x80000007; |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4412 (void) __cpuid_insn(®s); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4413 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4414 |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4415 default: |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4416 return (0); |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4417 } |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4418 } |
|
e559381f1e2b
PSARC 2008/777 cpupm keyword mode extensions
Eric Saxe <Eric.Saxe@Sun.COM>
parents:
8418
diff
changeset
|
4419 |
|
8930
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4420 #endif /* !__xpv */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4421 |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4422 void |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4423 post_startup_cpu_fixups(void) |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4424 { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4425 #ifndef __xpv |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4426 /* |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4427 * Some AMD processors support C1E state. Entering this state will |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4428 * cause the local APIC timer to stop, which we can't deal with at |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4429 * this time. |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4430 */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4431 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4432 on_trap_data_t otd; |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4433 uint64_t reg; |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4434 |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4435 if (!on_trap(&otd, OT_DATA_ACCESS)) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4436 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4437 /* Disable C1E state if it is enabled by BIOS */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4438 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4439 AMD_ACTONCMPHALT_MASK) { |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4440 reg &= ~(AMD_ACTONCMPHALT_MASK << |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4441 AMD_ACTONCMPHALT_SHIFT); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4442 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4443 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4444 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4445 no_trap(); |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4446 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4447 #endif /* !__xpv */ |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4448 } |
|
02055889c73a
6786943 AMD-based systems with C1E state enabled hang at boot
Bill Holler <Bill.Holler@Sun.COM>
parents:
8906
diff
changeset
|
4449 |
|
9283
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4450 /* |
|
13146
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4451 * Setup necessary registers to enable XSAVE feature on this processor. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4452 * This function needs to be called early enough, so that no xsave/xrstor |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4453 * ops will execute on the processor before the MSRs are properly set up. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4454 * |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4455 * Current implementation has the following assumption: |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4456 * - cpuid_pass1() is done, so that X86 features are known. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4457 * - fpu_probe() is done, so that fp_save_mech is chosen. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4458 */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4459 void |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4460 xsave_setup_msr(cpu_t *cpu) |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4461 { |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4462 ASSERT(fp_save_mech == FP_XSAVE); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4463 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4464 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4465 /* Enable OSXSAVE in CR4. */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4466 setcr4(getcr4() | CR4_OSXSAVE); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4467 /* |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4468 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4469 * correct value. |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4470 */ |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4471 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE; |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4472 setup_xfem(); |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4473 } |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4474 |
|
8315ff49e22e
6958308 XSAVE/XRSTOR mechanism to save and restore processor state
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
13041
diff
changeset
|
4475 /* |
|
9283
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4476 * Starting with the Westmere processor the local |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4477 * APIC timer will continue running in all C-states, |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4478 * including the deepest C-states. |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4479 */ |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4480 int |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4481 cpuid_arat_supported(void) |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4482 { |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4483 struct cpuid_info *cpi; |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4484 struct cpuid_regs regs; |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4485 |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4486 ASSERT(cpuid_checkpass(CPU, 1)); |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4487 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); |
|
9283
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4488 |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4489 cpi = CPU->cpu_m.mcpu_cpi; |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4490 |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4491 switch (cpi->cpi_vendor) { |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4492 case X86_VENDOR_Intel: |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4493 /* |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4494 * Always-running Local APIC Timer is |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4495 * indicated by CPUID.6.EAX[2]. |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4496 */ |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4497 if (cpi->cpi_maxeax >= 6) { |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4498 regs.cp_eax = 6; |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4499 (void) cpuid_insn(NULL, ®s); |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4500 return (regs.cp_eax & CPUID_CSTATE_ARAT); |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4501 } else { |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4502 return (0); |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4503 } |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4504 default: |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4505 return (0); |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4506 } |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4507 } |
|
2ee48b3d20ef
6821708 deeper C-state support required for processors with ARAT
Bill Holler <Bill.Holler@Sun.COM>
parents:
9000
diff
changeset
|
4508 |
|
10992
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4509 /* |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4510 * Check support for Intel ENERGY_PERF_BIAS feature |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4511 */ |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4512 int |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4513 cpuid_iepb_supported(struct cpu *cp) |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4514 { |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4515 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi; |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4516 struct cpuid_regs regs; |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4517 |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4518 ASSERT(cpuid_checkpass(cp, 1)); |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4519 |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4520 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) || |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4521 !(is_x86_feature(x86_featureset, X86FSET_MSR))) { |
|
10992
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4522 return (0); |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4523 } |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4524 |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4525 /* |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4526 * Intel ENERGY_PERF_BIAS MSR is indicated by |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4527 * capability bit CPUID.6.ECX.3 |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4528 */ |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4529 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6)) |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4530 return (0); |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4531 |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4532 regs.cp_eax = 0x6; |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4533 (void) cpuid_insn(NULL, ®s); |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4534 return (regs.cp_ecx & CPUID_EPB_SUPPORT); |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4535 } |
|
54a1c1cbd683
6887944 support for IA32_ENERGY_PERF_BIAS MSR
aubrey.li@intel.com
parents:
10947
diff
changeset
|
4536 |
|
13041
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4537 /* |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4538 * Check support for TSC deadline timer |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4539 * |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4540 * TSC deadline timer provides a superior software programming |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4541 * model over local APIC timer that eliminates "time drifts". |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4542 * Instead of specifying a relative time, software specifies an |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4543 * absolute time as the target at which the processor should |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4544 * generate a timer event. |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4545 */ |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4546 int |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4547 cpuid_deadline_tsc_supported(void) |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4548 { |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4549 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi; |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4550 struct cpuid_regs regs; |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4551 |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4552 ASSERT(cpuid_checkpass(CPU, 1)); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4553 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4554 |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4555 switch (cpi->cpi_vendor) { |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4556 case X86_VENDOR_Intel: |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4557 if (cpi->cpi_maxeax >= 1) { |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4558 regs.cp_eax = 1; |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4559 (void) cpuid_insn(NULL, ®s); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4560 return (regs.cp_ecx & CPUID_DEADLINE_TSC); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4561 } else { |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4562 return (0); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4563 } |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4564 default: |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4565 return (0); |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4566 } |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4567 } |
|
2ba2eec82e2a
6932990 Support for TSC deadline timer
Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM>
parents:
12838
diff
changeset
|
4568 |
|
8377
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4569 #if defined(__amd64) && !defined(__xpv) |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4570 /* |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4571 * Patch in versions of bcopy for high performance Intel Nhm processors |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4572 * and later... |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4573 */ |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4574 void |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4575 patch_memops(uint_t vendor) |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4576 { |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4577 size_t cnt, i; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4578 caddr_t to, from; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4579 |
|
12838
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4580 if ((vendor == X86_VENDOR_Intel) && |
|
fca99d9e3f2f
6812663 Running out of bits in x86_feature
Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com>
parents:
12726
diff
changeset
|
4581 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) { |
|
8377
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4582 cnt = &bcopy_patch_end - &bcopy_patch_start; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4583 to = &bcopy_ck_size; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4584 from = &bcopy_patch_start; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4585 for (i = 0; i < cnt; i++) { |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4586 *to++ = *from++; |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4587 } |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4588 } |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4589 } |
|
e4fb59d35f38
6292199 bcopy and kcopy should'nt use rep, smov
Bill Holler <Bill.Holler@Sun.COM>
parents:
7798
diff
changeset
|
4590 #endif /* __amd64 && !__xpv */ |
|
12261
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4591 |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4592 /* |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4593 * This function finds the number of bits to represent the number of cores per |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4594 * chip and the number of strands per core for the Intel platforms. |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4595 * It re-uses the x2APIC cpuid code of the cpuid_pass2(). |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4596 */ |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4597 void |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4598 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits) |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4599 { |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4600 struct cpuid_regs regs; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4601 struct cpuid_regs *cp = ®s; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4602 |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4603 if (vendor != X86_VENDOR_Intel) { |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4604 return; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4605 } |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4606 |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4607 /* if the cpuid level is 0xB, extended topo is available. */ |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4608 cp->cp_eax = 0; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4609 if (__cpuid_insn(cp) >= 0xB) { |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4610 |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4611 cp->cp_eax = 0xB; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4612 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4613 (void) __cpuid_insn(cp); |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4614 |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4615 /* |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4616 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4617 * indicates that the extended topology enumeration leaf is |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4618 * available. |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4619 */ |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4620 if (cp->cp_ebx) { |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4621 uint_t coreid_shift = 0; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4622 uint_t chipid_shift = 0; |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
|
4623 uint_t i; |
|
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
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parents:
12090
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4624 uint_t level; |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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4625 |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
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4626 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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4627 cp->cp_eax = 0xB; |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
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4628 cp->cp_ecx = i; |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4629 |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
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4630 (void) __cpuid_insn(cp); |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
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4631 level = CPI_CPU_LEVEL_TYPE(cp); |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4632 |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4633 if (level == 1) { |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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diff
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4634 /* |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
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parents:
12090
diff
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4635 * Thread level processor topology |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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diff
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4636 * Number of bits shift right APIC ID |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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diff
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4637 * to get the coreid. |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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diff
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4638 */ |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4639 coreid_shift = BITX(cp->cp_eax, 4, 0); |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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4640 } else if (level == 2) { |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
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diff
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4641 /* |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4642 * Core level processor topology |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4643 * Number of bits shift right APIC ID |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
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4644 * to get the chipid. |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4645 */ |
|
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4646 chipid_shift = BITX(cp->cp_eax, 4, 0); |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4647 } |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4648 } |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4649 |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4650 if (coreid_shift > 0 && chipid_shift > coreid_shift) { |
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4651 *strand_nbits = coreid_shift; |
|
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4652 *core_nbits = chipid_shift - coreid_shift; |
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52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
changeset
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4653 } |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4654 } |
|
52117d41c06e
6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4655 } |
|
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6930914 Need enhancement of the cmi handle table for Intel EX chip family
Vuong Nguyen <Vuong.Nguyen@Sun.COM>
parents:
12090
diff
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4656 } |